drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "vega20_baco.h"
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53 #include "nbio/nbio_7_4_sh_mask.h"
  54
  55 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  56 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  57
  58 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  59 {
  60         struct vega20_hwmgr *data =
  61                         (struct vega20_hwmgr *)(hwmgr->backend);
  62
  63         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  64         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  65         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  66         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  67         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  68
  69         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  70         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  78         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  81         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  82
  83         /*
  84          * Disable the following features for now:
  85          *   GFXCLK DS
  86          *   SOCLK DS
  87          *   LCLK DS
  88          *   DCEFCLK DS
  89          *   FCLK DS
  90          *   MP1CLK DS
  91          *   MP0CLK DS
  92          */
  93         data->registry_data.disallowed_features = 0xE0041C00;
  94         /* ECC feature should be disabled on old SMUs */
  95         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
  96         if (hwmgr->smu_version < 0x282100)
  97                 data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
  98
  99         if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
 100                 data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK;
 101
 102         if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
 103                 data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK;
 104
 105         if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
 106                 data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK;
 107
 108         if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
 109                 data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK;
 110
 111         if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
 112                 data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK;
 113
 114         if (!(hwmgr->feature_mask & PP_ULV_MASK))
 115                 data->registry_data.disallowed_features |= FEATURE_ULV_MASK;
 116
 117         if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
 118                 data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK;
 119
 120         data->registry_data.od_state_in_dc_support = 0;
 121         data->registry_data.thermal_support = 1;
 122         data->registry_data.skip_baco_hardware = 0;
 123
 124         data->registry_data.log_avfs_param = 0;
 125         data->registry_data.sclk_throttle_low_notification = 1;
 126         data->registry_data.force_dpm_high = 0;
 127         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
 128
 129         data->registry_data.didt_support = 0;
 130         if (data->registry_data.didt_support) {
 131                 data->registry_data.didt_mode = 6;
 132                 data->registry_data.sq_ramping_support = 1;
 133                 data->registry_data.db_ramping_support = 0;
 134                 data->registry_data.td_ramping_support = 0;
 135                 data->registry_data.tcp_ramping_support = 0;
 136                 data->registry_data.dbr_ramping_support = 0;
 137                 data->registry_data.edc_didt_support = 1;
 138                 data->registry_data.gc_didt_support = 0;
 139                 data->registry_data.psm_didt_support = 0;
 140         }
 141
 142         data->registry_data.pcie_lane_override = 0xff;
 143         data->registry_data.pcie_speed_override = 0xff;
 144         data->registry_data.pcie_clock_override = 0xffffffff;
 145         data->registry_data.regulator_hot_gpio_support = 1;
 146         data->registry_data.ac_dc_switch_gpio_support = 0;
 147         data->registry_data.quick_transition_support = 0;
 148         data->registry_data.zrpm_start_temp = 0xffff;
 149         data->registry_data.zrpm_stop_temp = 0xffff;
 150         data->registry_data.od8_feature_enable = 1;
 151         data->registry_data.disable_water_mark = 0;
 152         data->registry_data.disable_pp_tuning = 0;
 153         data->registry_data.disable_xlpp_tuning = 0;
 154         data->registry_data.disable_workload_policy = 0;
 155         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 156         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 157         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 158         data->registry_data.force_workload_policy_mask = 0;
 159         data->registry_data.disable_3d_fs_detection = 0;
 160         data->registry_data.fps_support = 1;
 161         data->registry_data.disable_auto_wattman = 1;
 162         data->registry_data.auto_wattman_debug = 0;
 163         data->registry_data.auto_wattman_sample_period = 100;
 164         data->registry_data.fclk_gfxclk_ratio = 0;
 165         data->registry_data.auto_wattman_threshold = 50;
 166         data->registry_data.gfxoff_controlled_by_driver = 1;
 167         data->gfxoff_allowed = false;
 168         data->counter_gfxoff = 0;
 169 }
 170
 171 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 172 {
 173         struct vega20_hwmgr *data =
 174                         (struct vega20_hwmgr *)(hwmgr->backend);
 175         struct amdgpu_device *adev = hwmgr->adev;
 176
 177         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 178                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 179                                 PHM_PlatformCaps_ControlVDDCI);
 180
 181         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 182                         PHM_PlatformCaps_TablelessHardwareInterface);
 183
 184         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 185                         PHM_PlatformCaps_BACO);
 186
 187         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 188                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 189
 190         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 191                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 192                                 PHM_PlatformCaps_UVDPowerGating);
 193
 194         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 195                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                                 PHM_PlatformCaps_VCEPowerGating);
 197
 198         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 199                         PHM_PlatformCaps_UnTabledHardwareInterface);
 200
 201         if (data->registry_data.od8_feature_enable)
 202                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 203                                 PHM_PlatformCaps_OD8inACSupport);
 204
 205         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 206                         PHM_PlatformCaps_ActivityReporting);
 207         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 208                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 209
 210         if (data->registry_data.od_state_in_dc_support) {
 211                 if (data->registry_data.od8_feature_enable)
 212                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 213                                         PHM_PlatformCaps_OD8inDCSupport);
 214         }
 215
 216         if (data->registry_data.thermal_support &&
 217             data->registry_data.fuzzy_fan_control_support &&
 218             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 219                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 220                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 221
 222         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_DynamicPowerManagement);
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_SMC);
 226         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_ThermalPolicyDelay);
 228
 229         if (data->registry_data.force_dpm_high)
 230                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 231                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_DynamicUVDState);
 235
 236         if (data->registry_data.sclk_throttle_low_notification)
 237                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 238                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 239
 240         /* power tune caps */
 241         /* assume disabled */
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_PowerContainment);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_DiDtSupport);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_SQRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_DBRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_TDRamping);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_TCPRamping);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_DBRRamping);
 256         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 257                         PHM_PlatformCaps_DiDtEDCEnable);
 258         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 259                         PHM_PlatformCaps_GCEDC);
 260         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 261                         PHM_PlatformCaps_PSM);
 262
 263         if (data->registry_data.didt_support) {
 264                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 265                                 PHM_PlatformCaps_DiDtSupport);
 266                 if (data->registry_data.sq_ramping_support)
 267                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                         PHM_PlatformCaps_SQRamping);
 269                 if (data->registry_data.db_ramping_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 271                                         PHM_PlatformCaps_DBRamping);
 272                 if (data->registry_data.td_ramping_support)
 273                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 274                                         PHM_PlatformCaps_TDRamping);
 275                 if (data->registry_data.tcp_ramping_support)
 276                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 277                                         PHM_PlatformCaps_TCPRamping);
 278                 if (data->registry_data.dbr_ramping_support)
 279                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 280                                         PHM_PlatformCaps_DBRRamping);
 281                 if (data->registry_data.edc_didt_support)
 282                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                                         PHM_PlatformCaps_DiDtEDCEnable);
 284                 if (data->registry_data.gc_didt_support)
 285                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 286                                         PHM_PlatformCaps_GCEDC);
 287                 if (data->registry_data.psm_didt_support)
 288                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 289                                         PHM_PlatformCaps_PSM);
 290         }
 291
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                         PHM_PlatformCaps_RegulatorHot);
 294
 295         if (data->registry_data.ac_dc_switch_gpio_support) {
 296                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 297                                 PHM_PlatformCaps_AutomaticDCTransition);
 298                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 299                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 300         }
 301
 302         if (data->registry_data.quick_transition_support) {
 303                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 304                                 PHM_PlatformCaps_AutomaticDCTransition);
 305                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 306                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 307                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 308                                 PHM_PlatformCaps_Falcon_QuickTransition);
 309         }
 310
 311         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 312                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 313                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 314                 if (data->lowest_uclk_reserved_for_ulv == 1)
 315                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 316                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 317         }
 318
 319         if (data->registry_data.custom_fan_support)
 320                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 321                                 PHM_PlatformCaps_CustomFanControlSupport);
 322
 323         return 0;
 324 }
 325
 326 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 327 {
 328         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 329         struct amdgpu_device *adev = hwmgr->adev;
 330         uint32_t top32, bottom32;
 331         int i;
 332
 333         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 334                         FEATURE_DPM_PREFETCHER_BIT;
 335         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 336                         FEATURE_DPM_GFXCLK_BIT;
 337         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 338                         FEATURE_DPM_UCLK_BIT;
 339         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 340                         FEATURE_DPM_SOCCLK_BIT;
 341         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 342                         FEATURE_DPM_UVD_BIT;
 343         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 344                         FEATURE_DPM_VCE_BIT;
 345         data->smu_features[GNLD_ULV].smu_feature_id =
 346                         FEATURE_ULV_BIT;
 347         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 348                         FEATURE_DPM_MP0CLK_BIT;
 349         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 350                         FEATURE_DPM_LINK_BIT;
 351         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 352                         FEATURE_DPM_DCEFCLK_BIT;
 353         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 354                         FEATURE_DS_GFXCLK_BIT;
 355         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 356                         FEATURE_DS_SOCCLK_BIT;
 357         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 358                         FEATURE_DS_LCLK_BIT;
 359         data->smu_features[GNLD_PPT].smu_feature_id =
 360                         FEATURE_PPT_BIT;
 361         data->smu_features[GNLD_TDC].smu_feature_id =
 362                         FEATURE_TDC_BIT;
 363         data->smu_features[GNLD_THERMAL].smu_feature_id =
 364                         FEATURE_THERMAL_BIT;
 365         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 366                         FEATURE_GFX_PER_CU_CG_BIT;
 367         data->smu_features[GNLD_RM].smu_feature_id =
 368                         FEATURE_RM_BIT;
 369         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 370                         FEATURE_DS_DCEFCLK_BIT;
 371         data->smu_features[GNLD_ACDC].smu_feature_id =
 372                         FEATURE_ACDC_BIT;
 373         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 374                         FEATURE_VR0HOT_BIT;
 375         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 376                         FEATURE_VR1HOT_BIT;
 377         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 378                         FEATURE_FW_CTF_BIT;
 379         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 380                         FEATURE_LED_DISPLAY_BIT;
 381         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 382                         FEATURE_FAN_CONTROL_BIT;
 383         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 384         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 385         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 386         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 387         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 388         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 389         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 390         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 391         data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
 392
 393         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 394                 data->smu_features[i].smu_feature_bitmap =
 395                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 396                 data->smu_features[i].allowed =
 397                         ((data->registry_data.disallowed_features >> i) & 1) ?
 398                         false : true;
 399         }
 400
 401         /* Get the SN to turn into a Unique ID */
 402         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 403         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 404
 405         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 406 }
 407
 408 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 409 {
 410         return 0;
 411 }
 412
 413 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 414 {
 415         kfree(hwmgr->backend);
 416         hwmgr->backend = NULL;
 417
 418         return 0;
 419 }
 420
 421 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 422 {
 423         struct vega20_hwmgr *data;
 424         struct amdgpu_device *adev = hwmgr->adev;
 425
 426         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 427         if (data == NULL)
 428                 return -ENOMEM;
 429
 430         hwmgr->backend = data;
 431
 432         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 433         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 434         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 435
 436         vega20_set_default_registry_data(hwmgr);
 437
 438         data->disable_dpm_mask = 0xff;
 439
 440         /* need to set voltage control types before EVV patching */
 441         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 442         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 443         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 444
 445         data->water_marks_bitmap = 0;
 446         data->avfs_exist = false;
 447
 448         vega20_set_features_platform_caps(hwmgr);
 449
 450         vega20_init_dpm_defaults(hwmgr);
 451
 452         /* Parse pptable data read from VBIOS */
 453         vega20_set_private_data_based_on_pptable(hwmgr);
 454
 455         data->is_tlu_enabled = false;
 456
 457         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 458                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 459         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 460         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 461
 462         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 463         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 464         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 465         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 466
 467         data->total_active_cus = adev->gfx.cu_info.number;
 468         data->is_custom_profile_set = false;
 469
 470         return 0;
 471 }
 472
 473 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 474 {
 475         struct vega20_hwmgr *data =
 476                         (struct vega20_hwmgr *)(hwmgr->backend);
 477
 478         data->low_sclk_interrupt_threshold = 0;
 479
 480         return 0;
 481 }
 482
 483 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 484 {
 485         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 486         int ret = 0;
 487         bool use_baco = (adev->in_gpu_reset &&
 488                          (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
 489                 (adev->in_runpm && amdgpu_asic_supports_baco(adev));
 490
 491         ret = vega20_init_sclk_threshold(hwmgr);
 492         PP_ASSERT_WITH_CODE(!ret,
 493                         "Failed to init sclk threshold!",
 494                         return ret);
 495
 496         if (use_baco) {
 497                 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
 498                 if (ret)
 499                         pr_err("Failed to apply vega20 baco workaround!\n");
 500         }
 501
 502         return ret;
 503 }
 504
 505 /*
 506  * @fn vega20_init_dpm_state
 507  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 508  *
 509  * @param    dpm_state - the address of the DPM Table to initiailize.
 510  * @return   None.
 511  */
 512 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 513 {
 514         dpm_state->soft_min_level = 0x0;
 515         dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
 516         dpm_state->hard_min_level = 0x0;
 517         dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
 518 }
 519
 520 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 521                 PPCLK_e clk_id, uint32_t *num_of_levels)
 522 {
 523         int ret = 0;
 524
 525         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 526                         PPSMC_MSG_GetDpmFreqByIndex,
 527                         (clk_id << 16 | 0xFF),
 528                         num_of_levels);
 529         PP_ASSERT_WITH_CODE(!ret,
 530                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 531                         return ret);
 532
 533         return ret;
 534 }
 535
 536 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 537                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 538 {
 539         int ret = 0;
 540
 541         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 542                         PPSMC_MSG_GetDpmFreqByIndex,
 543                         (clk_id << 16 | index),
 544                         clk);
 545         PP_ASSERT_WITH_CODE(!ret,
 546                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 547                         return ret);
 548
 549         return ret;
 550 }
 551
 552 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 553                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 554 {
 555         int ret = 0;
 556         uint32_t i, num_of_levels, clk;
 557
 558         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 559         PP_ASSERT_WITH_CODE(!ret,
 560                         "[SetupSingleDpmTable] failed to get clk levels!",
 561                         return ret);
 562
 563         dpm_table->count = num_of_levels;
 564
 565         for (i = 0; i < num_of_levels; i++) {
 566                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 567                 PP_ASSERT_WITH_CODE(!ret,
 568                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 569                         return ret);
 570                 dpm_table->dpm_levels[i].value = clk;
 571                 dpm_table->dpm_levels[i].enabled = true;
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 578 {
 579         struct vega20_hwmgr *data =
 580                         (struct vega20_hwmgr *)(hwmgr->backend);
 581         struct vega20_single_dpm_table *dpm_table;
 582         int ret = 0;
 583
 584         dpm_table = &(data->dpm_table.gfx_table);
 585         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 586                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 587                 PP_ASSERT_WITH_CODE(!ret,
 588                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 589                                 return ret);
 590         } else {
 591                 dpm_table->count = 1;
 592                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 599 {
 600         struct vega20_hwmgr *data =
 601                         (struct vega20_hwmgr *)(hwmgr->backend);
 602         struct vega20_single_dpm_table *dpm_table;
 603         int ret = 0;
 604
 605         dpm_table = &(data->dpm_table.mem_table);
 606         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 607                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 608                 PP_ASSERT_WITH_CODE(!ret,
 609                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 610                                 return ret);
 611         } else {
 612                 dpm_table->count = 1;
 613                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 614         }
 615
 616         return ret;
 617 }
 618
 619 /*
 620  * This function is to initialize all DPM state tables
 621  * for SMU based on the dependency table.
 622  * Dynamic state patching function will then trim these
 623  * state tables to the allowed range based
 624  * on the power policy or external client requests,
 625  * such as UVD request, etc.
 626  */
 627 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 628 {
 629         struct vega20_hwmgr *data =
 630                         (struct vega20_hwmgr *)(hwmgr->backend);
 631         struct vega20_single_dpm_table *dpm_table;
 632         int ret = 0;
 633
 634         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 635
 636         /* socclk */
 637         dpm_table = &(data->dpm_table.soc_table);
 638         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 639                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 640                 PP_ASSERT_WITH_CODE(!ret,
 641                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 642                                 return ret);
 643         } else {
 644                 dpm_table->count = 1;
 645                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 646         }
 647         vega20_init_dpm_state(&(dpm_table->dpm_state));
 648
 649         /* gfxclk */
 650         dpm_table = &(data->dpm_table.gfx_table);
 651         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 652         if (ret)
 653                 return ret;
 654         vega20_init_dpm_state(&(dpm_table->dpm_state));
 655
 656         /* memclk */
 657         dpm_table = &(data->dpm_table.mem_table);
 658         ret = vega20_setup_memclk_dpm_table(hwmgr);
 659         if (ret)
 660                 return ret;
 661         vega20_init_dpm_state(&(dpm_table->dpm_state));
 662
 663         /* eclk */
 664         dpm_table = &(data->dpm_table.eclk_table);
 665         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 666                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 667                 PP_ASSERT_WITH_CODE(!ret,
 668                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 669                                 return ret);
 670         } else {
 671                 dpm_table->count = 1;
 672                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 673         }
 674         vega20_init_dpm_state(&(dpm_table->dpm_state));
 675
 676         /* vclk */
 677         dpm_table = &(data->dpm_table.vclk_table);
 678         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 679                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 680                 PP_ASSERT_WITH_CODE(!ret,
 681                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 682                                 return ret);
 683         } else {
 684                 dpm_table->count = 1;
 685                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 686         }
 687         vega20_init_dpm_state(&(dpm_table->dpm_state));
 688
 689         /* dclk */
 690         dpm_table = &(data->dpm_table.dclk_table);
 691         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 692                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 693                 PP_ASSERT_WITH_CODE(!ret,
 694                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 695                                 return ret);
 696         } else {
 697                 dpm_table->count = 1;
 698                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 699         }
 700         vega20_init_dpm_state(&(dpm_table->dpm_state));
 701
 702         /* dcefclk */
 703         dpm_table = &(data->dpm_table.dcef_table);
 704         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 705                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 706                 PP_ASSERT_WITH_CODE(!ret,
 707                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 708                                 return ret);
 709         } else {
 710                 dpm_table->count = 1;
 711                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 712         }
 713         vega20_init_dpm_state(&(dpm_table->dpm_state));
 714
 715         /* pixclk */
 716         dpm_table = &(data->dpm_table.pixel_table);
 717         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 718                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 719                 PP_ASSERT_WITH_CODE(!ret,
 720                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 721                                 return ret);
 722         } else
 723                 dpm_table->count = 0;
 724         vega20_init_dpm_state(&(dpm_table->dpm_state));
 725
 726         /* dispclk */
 727         dpm_table = &(data->dpm_table.display_table);
 728         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 729                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 730                 PP_ASSERT_WITH_CODE(!ret,
 731                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 732                                 return ret);
 733         } else
 734                 dpm_table->count = 0;
 735         vega20_init_dpm_state(&(dpm_table->dpm_state));
 736
 737         /* phyclk */
 738         dpm_table = &(data->dpm_table.phy_table);
 739         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 740                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 741                 PP_ASSERT_WITH_CODE(!ret,
 742                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 743                                 return ret);
 744         } else
 745                 dpm_table->count = 0;
 746         vega20_init_dpm_state(&(dpm_table->dpm_state));
 747
 748         /* fclk */
 749         dpm_table = &(data->dpm_table.fclk_table);
 750         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 751                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 752                 PP_ASSERT_WITH_CODE(!ret,
 753                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 754                                 return ret);
 755         } else {
 756                 dpm_table->count = 1;
 757                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
 758         }
 759         vega20_init_dpm_state(&(dpm_table->dpm_state));
 760
 761         /* save a copy of the default DPM table */
 762         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 763                         sizeof(struct vega20_dpm_table));
 764
 765         return 0;
 766 }
 767
 768 /**
 769 * Initializes the SMC table and uploads it
 770 *
 771 * @param    hwmgr  the address of the powerplay hardware manager.
 772 * @param    pInput  the pointer to input data (PowerState)
 773 * @return   always 0
 774 */
 775 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 776 {
 777         int result;
 778         struct vega20_hwmgr *data =
 779                         (struct vega20_hwmgr *)(hwmgr->backend);
 780         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 781         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 782         struct phm_ppt_v3_information *pptable_information =
 783                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 784
 785         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 786         PP_ASSERT_WITH_CODE(!result,
 787                         "[InitSMCTable] Failed to get vbios bootup values!",
 788                         return result);
 789
 790         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 791         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 792         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 793         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 794         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 795         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 796         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 797         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 798         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 799         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 800         data->vbios_boot_state.fclock = boot_up_values.ulFClk;
 801         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 802
 803         smum_send_msg_to_smc_with_parameter(hwmgr,
 804                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 805                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
 806                         NULL);
 807
 808         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 809
 810         result = smum_smc_table_manager(hwmgr,
 811                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 812         PP_ASSERT_WITH_CODE(!result,
 813                         "[InitSMCTable] Failed to upload PPtable!",
 814                         return result);
 815
 816         return 0;
 817 }
 818
 819 /*
 820  * Override PCIe link speed and link width for DPM Level 1. PPTable entries
 821  * reflect the ASIC capabilities and not the system capabilities. For e.g.
 822  * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
 823  * to DPM1, it fails as system doesn't support Gen4.
 824  */
 825 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 826 {
 827         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 828         struct vega20_hwmgr *data =
 829                         (struct vega20_hwmgr *)(hwmgr->backend);
 830         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 831         int ret;
 832
 833         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 834                 pcie_gen = 3;
 835         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 836                 pcie_gen = 2;
 837         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 838                 pcie_gen = 1;
 839         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 840                 pcie_gen = 0;
 841
 842         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 843                 pcie_width = 6;
 844         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 845                 pcie_width = 5;
 846         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 847                 pcie_width = 4;
 848         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 849                 pcie_width = 3;
 850         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 851                 pcie_width = 2;
 852         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 853                 pcie_width = 1;
 854
 855         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 856          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 857          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 858          */
 859         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 860         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 861                         PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
 862                         NULL);
 863         PP_ASSERT_WITH_CODE(!ret,
 864                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 865                 return ret);
 866
 867         data->pcie_parameters_override = true;
 868         data->pcie_gen_level1 = pcie_gen;
 869         data->pcie_width_level1 = pcie_width;
 870
 871         return 0;
 872 }
 873
 874 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 875 {
 876         struct vega20_hwmgr *data =
 877                         (struct vega20_hwmgr *)(hwmgr->backend);
 878         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 879         int i;
 880         int ret = 0;
 881
 882         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 883                 if (data->smu_features[i].allowed)
 884                         data->smu_features[i].smu_feature_id > 31 ?
 885                                 (allowed_features_high |=
 886                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 887                                   & 0xFFFFFFFF)) :
 888                                 (allowed_features_low |=
 889                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 890                                   & 0xFFFFFFFF));
 891
 892         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 893                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL);
 894         PP_ASSERT_WITH_CODE(!ret,
 895                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 896                 return ret);
 897
 898         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 899                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL);
 900         PP_ASSERT_WITH_CODE(!ret,
 901                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 902                 return ret);
 903
 904         return 0;
 905 }
 906
 907 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
 908 {
 909         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL);
 910 }
 911
 912 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 913 {
 914         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL);
 915 }
 916
 917 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 918 {
 919         struct vega20_hwmgr *data =
 920                         (struct vega20_hwmgr *)(hwmgr->backend);
 921         uint64_t features_enabled;
 922         int i;
 923         bool enabled;
 924         int ret = 0;
 925
 926         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 927                         PPSMC_MSG_EnableAllSmuFeatures,
 928                         NULL)) == 0,
 929                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 930                         return ret);
 931
 932         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 933         PP_ASSERT_WITH_CODE(!ret,
 934                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 935                         return ret);
 936
 937         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 938                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 939                         true : false;
 940                 data->smu_features[i].enabled = enabled;
 941                 data->smu_features[i].supported = enabled;
 942
 943 #if 0
 944                 if (data->smu_features[i].allowed && !enabled)
 945                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 946                 else if (!data->smu_features[i].allowed && enabled)
 947                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 948 #endif
 949         }
 950
 951         return 0;
 952 }
 953
 954 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
 955 {
 956         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 957
 958         if (data->smu_features[GNLD_DPM_UCLK].enabled)
 959                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 960                         PPSMC_MSG_SetUclkFastSwitch,
 961                         1,
 962                         NULL);
 963
 964         return 0;
 965 }
 966
 967 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 968 {
 969         struct vega20_hwmgr *data =
 970                         (struct vega20_hwmgr *)(hwmgr->backend);
 971
 972         return smum_send_msg_to_smc_with_parameter(hwmgr,
 973                         PPSMC_MSG_SetFclkGfxClkRatio,
 974                         data->registry_data.fclk_gfxclk_ratio,
 975                         NULL);
 976 }
 977
 978 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 979 {
 980         struct vega20_hwmgr *data =
 981                         (struct vega20_hwmgr *)(hwmgr->backend);
 982         uint64_t features_enabled;
 983         int i;
 984         bool enabled;
 985         int ret = 0;
 986
 987         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 988                         PPSMC_MSG_DisableAllSmuFeatures,
 989                         NULL)) == 0,
 990                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 991                         return ret);
 992
 993         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 994         PP_ASSERT_WITH_CODE(!ret,
 995                         "[DisableAllSMUFeatures] Failed to get enabled smc features!",
 996                         return ret);
 997
 998         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 999                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
1000                         true : false;
1001                 data->smu_features[i].enabled = enabled;
1002                 data->smu_features[i].supported = enabled;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int vega20_od8_set_feature_capabilities(
1009                 struct pp_hwmgr *hwmgr)
1010 {
1011         struct phm_ppt_v3_information *pptable_information =
1012                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1013         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1014         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1015         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1016
1017         od_settings->overdrive8_capabilities = 0;
1018
1019         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1020                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1021                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1022                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1023                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1024                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
1025                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
1026
1027                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1028                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1029                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
1030                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1031                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
1032                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
1033                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
1034                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
1035         }
1036
1037         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1038                 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1039                         data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1040                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1041                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1042                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1043                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1044                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1045                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1046         }
1047
1048         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1049             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1050             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1051             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1052             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1053                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1054
1055         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1056                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1057                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1058                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1059                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1060                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1061                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1062
1063                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1064                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1065                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1066                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1067                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1068                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1069                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1070         }
1071
1072         if (data->smu_features[GNLD_THERMAL].enabled) {
1073                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1074                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1075                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1076                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1077                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1078                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1079
1080                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1081                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1082                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1083                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1084                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1085                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1086         }
1087
1088         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1089                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1090
1091         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1092             pp_table->FanZeroRpmEnable)
1093                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1094
1095         if (!od_settings->overdrive8_capabilities)
1096                 hwmgr->od_enabled = false;
1097
1098         return 0;
1099 }
1100
1101 static int vega20_od8_set_feature_id(
1102                 struct pp_hwmgr *hwmgr)
1103 {
1104         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1105         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1106
1107         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1108                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1109                         OD8_GFXCLK_LIMITS;
1110                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1111                         OD8_GFXCLK_LIMITS;
1112         } else {
1113                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1114                         0;
1115                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1116                         0;
1117         }
1118
1119         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1120                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1121                         OD8_GFXCLK_CURVE;
1122                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1123                         OD8_GFXCLK_CURVE;
1124                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1125                         OD8_GFXCLK_CURVE;
1126                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1127                         OD8_GFXCLK_CURVE;
1128                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1129                         OD8_GFXCLK_CURVE;
1130                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1131                         OD8_GFXCLK_CURVE;
1132         } else {
1133                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1134                         0;
1135                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1136                         0;
1137                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1138                         0;
1139                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1140                         0;
1141                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1142                         0;
1143                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1144                         0;
1145         }
1146
1147         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1148                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1149         else
1150                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1151
1152         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1153                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1154         else
1155                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1156
1157         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1158                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1159                         OD8_ACOUSTIC_LIMIT_SCLK;
1160         else
1161                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1162                         0;
1163
1164         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1165                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1166                         OD8_FAN_SPEED_MIN;
1167         else
1168                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1169                         0;
1170
1171         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1172                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1173                         OD8_TEMPERATURE_FAN;
1174         else
1175                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1176                         0;
1177
1178         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1179                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1180                         OD8_TEMPERATURE_SYSTEM;
1181         else
1182                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1183                         0;
1184
1185         return 0;
1186 }
1187
1188 static int vega20_od8_get_gfx_clock_base_voltage(
1189                 struct pp_hwmgr *hwmgr,
1190                 uint32_t *voltage,
1191                 uint32_t freq)
1192 {
1193         int ret = 0;
1194
1195         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1196                         PPSMC_MSG_GetAVFSVoltageByDpm,
1197                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq),
1198                         voltage);
1199         PP_ASSERT_WITH_CODE(!ret,
1200                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1201                         return ret);
1202
1203         *voltage = *voltage / VOLTAGE_SCALE;
1204
1205         return 0;
1206 }
1207
1208 static int vega20_od8_initialize_default_settings(
1209                 struct pp_hwmgr *hwmgr)
1210 {
1211         struct phm_ppt_v3_information *pptable_information =
1212                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1213         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1214         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1215         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1216         int i, ret = 0;
1217
1218         /* Set Feature Capabilities */
1219         vega20_od8_set_feature_capabilities(hwmgr);
1220
1221         /* Map FeatureID to individual settings */
1222         vega20_od8_set_feature_id(hwmgr);
1223
1224         /* Set default values */
1225         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1226         PP_ASSERT_WITH_CODE(!ret,
1227                         "Failed to export over drive table!",
1228                         return ret);
1229
1230         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1231                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1232                         od_table->GfxclkFmin;
1233                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1234                         od_table->GfxclkFmax;
1235         } else {
1236                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1237                         0;
1238                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1239                         0;
1240         }
1241
1242         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1243                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1244                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1245                         od_table->GfxclkFreq1;
1246
1247                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1248                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1249                         od_table->GfxclkFreq3;
1250
1251                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1252                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1253                         od_table->GfxclkFreq2;
1254
1255                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1256                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1257                                      od_table->GfxclkFreq1),
1258                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1259                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1260                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1261                         * VOLTAGE_SCALE;
1262
1263                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1264                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1265                                      od_table->GfxclkFreq2),
1266                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1267                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1268                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1269                         * VOLTAGE_SCALE;
1270
1271                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1272                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1273                                      od_table->GfxclkFreq3),
1274                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1275                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1276                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1277                         * VOLTAGE_SCALE;
1278         } else {
1279                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1280                         0;
1281                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1282                         0;
1283                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1284                         0;
1285                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1286                         0;
1287                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1288                         0;
1289                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1290                         0;
1291         }
1292
1293         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1294                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1295                         od_table->UclkFmax;
1296         else
1297                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1298                         0;
1299
1300         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1301                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1302                         od_table->OverDrivePct;
1303         else
1304                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1305                         0;
1306
1307         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1308                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1309                         od_table->FanMaximumRpm;
1310         else
1311                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1312                         0;
1313
1314         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1315                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1316                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1317         else
1318                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1319                         0;
1320
1321         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1322                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1323                         od_table->FanTargetTemperature;
1324         else
1325                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1326                         0;
1327
1328         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1329                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1330                         od_table->MaxOpTemp;
1331         else
1332                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1333                         0;
1334
1335         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1336                 if (od8_settings->od8_settings_array[i].feature_id) {
1337                         od8_settings->od8_settings_array[i].min_value =
1338                                 pptable_information->od_settings_min[i];
1339                         od8_settings->od8_settings_array[i].max_value =
1340                                 pptable_information->od_settings_max[i];
1341                         od8_settings->od8_settings_array[i].current_value =
1342                                 od8_settings->od8_settings_array[i].default_value;
1343                 } else {
1344                         od8_settings->od8_settings_array[i].min_value =
1345                                 0;
1346                         od8_settings->od8_settings_array[i].max_value =
1347                                 0;
1348                         od8_settings->od8_settings_array[i].current_value =
1349                                 0;
1350                 }
1351         }
1352
1353         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1354         PP_ASSERT_WITH_CODE(!ret,
1355                         "Failed to import over drive table!",
1356                         return ret);
1357
1358         return 0;
1359 }
1360
1361 static int vega20_od8_set_settings(
1362                 struct pp_hwmgr *hwmgr,
1363                 uint32_t index,
1364                 uint32_t value)
1365 {
1366         OverDriveTable_t od_table;
1367         int ret = 0;
1368         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1369         struct vega20_od8_single_setting *od8_settings =
1370                         data->od8_settings.od8_settings_array;
1371
1372         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1373         PP_ASSERT_WITH_CODE(!ret,
1374                         "Failed to export over drive table!",
1375                         return ret);
1376
1377         switch(index) {
1378         case OD8_SETTING_GFXCLK_FMIN:
1379                 od_table.GfxclkFmin = (uint16_t)value;
1380                 break;
1381         case OD8_SETTING_GFXCLK_FMAX:
1382                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1383                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1384                         return -EINVAL;
1385
1386                 od_table.GfxclkFmax = (uint16_t)value;
1387                 break;
1388         case OD8_SETTING_GFXCLK_FREQ1:
1389                 od_table.GfxclkFreq1 = (uint16_t)value;
1390                 break;
1391         case OD8_SETTING_GFXCLK_VOLTAGE1:
1392                 od_table.GfxclkVolt1 = (uint16_t)value;
1393                 break;
1394         case OD8_SETTING_GFXCLK_FREQ2:
1395                 od_table.GfxclkFreq2 = (uint16_t)value;
1396                 break;
1397         case OD8_SETTING_GFXCLK_VOLTAGE2:
1398                 od_table.GfxclkVolt2 = (uint16_t)value;
1399                 break;
1400         case OD8_SETTING_GFXCLK_FREQ3:
1401                 od_table.GfxclkFreq3 = (uint16_t)value;
1402                 break;
1403         case OD8_SETTING_GFXCLK_VOLTAGE3:
1404                 od_table.GfxclkVolt3 = (uint16_t)value;
1405                 break;
1406         case OD8_SETTING_UCLK_FMAX:
1407                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1408                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1409                         return -EINVAL;
1410                 od_table.UclkFmax = (uint16_t)value;
1411                 break;
1412         case OD8_SETTING_POWER_PERCENTAGE:
1413                 od_table.OverDrivePct = (int16_t)value;
1414                 break;
1415         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1416                 od_table.FanMaximumRpm = (uint16_t)value;
1417                 break;
1418         case OD8_SETTING_FAN_MIN_SPEED:
1419                 od_table.FanMinimumPwm = (uint16_t)value;
1420                 break;
1421         case OD8_SETTING_FAN_TARGET_TEMP:
1422                 od_table.FanTargetTemperature = (uint16_t)value;
1423                 break;
1424         case OD8_SETTING_OPERATING_TEMP_MAX:
1425                 od_table.MaxOpTemp = (uint16_t)value;
1426                 break;
1427         }
1428
1429         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1430         PP_ASSERT_WITH_CODE(!ret,
1431                         "Failed to import over drive table!",
1432                         return ret);
1433
1434         return 0;
1435 }
1436
1437 static int vega20_get_sclk_od(
1438                 struct pp_hwmgr *hwmgr)
1439 {
1440         struct vega20_hwmgr *data = hwmgr->backend;
1441         struct vega20_single_dpm_table *sclk_table =
1442                         &(data->dpm_table.gfx_table);
1443         struct vega20_single_dpm_table *golden_sclk_table =
1444                         &(data->golden_dpm_table.gfx_table);
1445         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1446         int golden_value = golden_sclk_table->dpm_levels
1447                         [golden_sclk_table->count - 1].value;
1448
1449         /* od percentage */
1450         value -= golden_value;
1451         value = DIV_ROUND_UP(value * 100, golden_value);
1452
1453         return value;
1454 }
1455
1456 static int vega20_set_sclk_od(
1457                 struct pp_hwmgr *hwmgr, uint32_t value)
1458 {
1459         struct vega20_hwmgr *data = hwmgr->backend;
1460         struct vega20_single_dpm_table *golden_sclk_table =
1461                         &(data->golden_dpm_table.gfx_table);
1462         uint32_t od_sclk;
1463         int ret = 0;
1464
1465         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1466         od_sclk /= 100;
1467         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1468
1469         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1470         PP_ASSERT_WITH_CODE(!ret,
1471                         "[SetSclkOD] failed to set od gfxclk!",
1472                         return ret);
1473
1474         /* retrieve updated gfxclk table */
1475         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1476         PP_ASSERT_WITH_CODE(!ret,
1477                         "[SetSclkOD] failed to refresh gfxclk table!",
1478                         return ret);
1479
1480         return 0;
1481 }
1482
1483 static int vega20_get_mclk_od(
1484                 struct pp_hwmgr *hwmgr)
1485 {
1486         struct vega20_hwmgr *data = hwmgr->backend;
1487         struct vega20_single_dpm_table *mclk_table =
1488                         &(data->dpm_table.mem_table);
1489         struct vega20_single_dpm_table *golden_mclk_table =
1490                         &(data->golden_dpm_table.mem_table);
1491         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1492         int golden_value = golden_mclk_table->dpm_levels
1493                         [golden_mclk_table->count - 1].value;
1494
1495         /* od percentage */
1496         value -= golden_value;
1497         value = DIV_ROUND_UP(value * 100, golden_value);
1498
1499         return value;
1500 }
1501
1502 static int vega20_set_mclk_od(
1503                 struct pp_hwmgr *hwmgr, uint32_t value)
1504 {
1505         struct vega20_hwmgr *data = hwmgr->backend;
1506         struct vega20_single_dpm_table *golden_mclk_table =
1507                         &(data->golden_dpm_table.mem_table);
1508         uint32_t od_mclk;
1509         int ret = 0;
1510
1511         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1512         od_mclk /= 100;
1513         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1514
1515         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1516         PP_ASSERT_WITH_CODE(!ret,
1517                         "[SetMclkOD] failed to set od memclk!",
1518                         return ret);
1519
1520         /* retrieve updated memclk table */
1521         ret = vega20_setup_memclk_dpm_table(hwmgr);
1522         PP_ASSERT_WITH_CODE(!ret,
1523                         "[SetMclkOD] failed to refresh memclk table!",
1524                         return ret);
1525
1526         return 0;
1527 }
1528
1529 static int vega20_populate_umdpstate_clocks(
1530                 struct pp_hwmgr *hwmgr)
1531 {
1532         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1533         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1534         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1535
1536         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1537         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1538
1539         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1540             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1541                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1542                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1543         }
1544
1545         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1546         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1547
1548         return 0;
1549 }
1550
1551 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1552                 PP_Clock *clock, PPCLK_e clock_select)
1553 {
1554         int ret = 0;
1555
1556         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1557                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1558                         (clock_select << 16),
1559                         clock)) == 0,
1560                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1561                         return ret);
1562
1563         /* if DC limit is zero, return AC limit */
1564         if (*clock == 0) {
1565                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1566                         PPSMC_MSG_GetMaxDpmFreq,
1567                         (clock_select << 16),
1568                         clock)) == 0,
1569                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1570                         return ret);
1571         }
1572
1573         return 0;
1574 }
1575
1576 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1577 {
1578         struct vega20_hwmgr *data =
1579                 (struct vega20_hwmgr *)(hwmgr->backend);
1580         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1581                 &(data->max_sustainable_clocks);
1582         int ret = 0;
1583
1584         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1585         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1586         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1587         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1588         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1589         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1590
1591         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1592                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1593                                 &(max_sustainable_clocks->uclock),
1594                                 PPCLK_UCLK)) == 0,
1595                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1596                                 return ret);
1597
1598         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1599                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1600                                 &(max_sustainable_clocks->soc_clock),
1601                                 PPCLK_SOCCLK)) == 0,
1602                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1603                                 return ret);
1604
1605         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1606                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1607                                 &(max_sustainable_clocks->dcef_clock),
1608                                 PPCLK_DCEFCLK)) == 0,
1609                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1610                                 return ret);
1611                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1612                                 &(max_sustainable_clocks->display_clock),
1613                                 PPCLK_DISPCLK)) == 0,
1614                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1615                                 return ret);
1616                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1617                                 &(max_sustainable_clocks->phy_clock),
1618                                 PPCLK_PHYCLK)) == 0,
1619                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1620                                 return ret);
1621                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1622                                 &(max_sustainable_clocks->pixel_clock),
1623                                 PPCLK_PIXCLK)) == 0,
1624                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1625                                 return ret);
1626         }
1627
1628         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1629                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1630
1631         return 0;
1632 }
1633
1634 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1635 {
1636         int result;
1637
1638         result = smum_send_msg_to_smc(hwmgr,
1639                 PPSMC_MSG_SetMGpuFanBoostLimitRpm,
1640                 NULL);
1641         PP_ASSERT_WITH_CODE(!result,
1642                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1643                         return result);
1644
1645         return 0;
1646 }
1647
1648 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1649 {
1650         struct vega20_hwmgr *data =
1651                 (struct vega20_hwmgr *)(hwmgr->backend);
1652
1653         data->uvd_power_gated = true;
1654         data->vce_power_gated = true;
1655
1656         if (data->smu_features[GNLD_DPM_UVD].enabled)
1657                 data->uvd_power_gated = false;
1658
1659         if (data->smu_features[GNLD_DPM_VCE].enabled)
1660                 data->vce_power_gated = false;
1661 }
1662
1663 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1664 {
1665         int result = 0;
1666
1667         smum_send_msg_to_smc_with_parameter(hwmgr,
1668                         PPSMC_MSG_NumOfDisplays, 0, NULL);
1669
1670         result = vega20_set_allowed_featuresmask(hwmgr);
1671         PP_ASSERT_WITH_CODE(!result,
1672                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1673                         return result);
1674
1675         result = vega20_init_smc_table(hwmgr);
1676         PP_ASSERT_WITH_CODE(!result,
1677                         "[EnableDPMTasks] Failed to initialize SMC table!",
1678                         return result);
1679
1680         result = vega20_run_btc(hwmgr);
1681         PP_ASSERT_WITH_CODE(!result,
1682                         "[EnableDPMTasks] Failed to run btc!",
1683                         return result);
1684
1685         result = vega20_run_btc_afll(hwmgr);
1686         PP_ASSERT_WITH_CODE(!result,
1687                         "[EnableDPMTasks] Failed to run btc afll!",
1688                         return result);
1689
1690         result = vega20_enable_all_smu_features(hwmgr);
1691         PP_ASSERT_WITH_CODE(!result,
1692                         "[EnableDPMTasks] Failed to enable all smu features!",
1693                         return result);
1694
1695         result = vega20_override_pcie_parameters(hwmgr);
1696         PP_ASSERT_WITH_CODE(!result,
1697                         "[EnableDPMTasks] Failed to override pcie parameters!",
1698                         return result);
1699
1700         result = vega20_notify_smc_display_change(hwmgr);
1701         PP_ASSERT_WITH_CODE(!result,
1702                         "[EnableDPMTasks] Failed to notify smc display change!",
1703                         return result);
1704
1705         result = vega20_send_clock_ratio(hwmgr);
1706         PP_ASSERT_WITH_CODE(!result,
1707                         "[EnableDPMTasks] Failed to send clock ratio!",
1708                         return result);
1709
1710         /* Initialize UVD/VCE powergating state */
1711         vega20_init_powergate_state(hwmgr);
1712
1713         result = vega20_setup_default_dpm_tables(hwmgr);
1714         PP_ASSERT_WITH_CODE(!result,
1715                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1716                         return result);
1717
1718         result = vega20_init_max_sustainable_clocks(hwmgr);
1719         PP_ASSERT_WITH_CODE(!result,
1720                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1721                         return result);
1722
1723         result = vega20_power_control_set_level(hwmgr);
1724         PP_ASSERT_WITH_CODE(!result,
1725                         "[EnableDPMTasks] Failed to power control set level!",
1726                         return result);
1727
1728         result = vega20_od8_initialize_default_settings(hwmgr);
1729         PP_ASSERT_WITH_CODE(!result,
1730                         "[EnableDPMTasks] Failed to initialize odn settings!",
1731                         return result);
1732
1733         result = vega20_populate_umdpstate_clocks(hwmgr);
1734         PP_ASSERT_WITH_CODE(!result,
1735                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1736                         return result);
1737
1738         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1739                         POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);
1740         PP_ASSERT_WITH_CODE(!result,
1741                         "[GetPptLimit] get default PPT limit failed!",
1742                         return result);
1743         hwmgr->power_limit =
1744                 hwmgr->default_power_limit;
1745
1746         return 0;
1747 }
1748
1749 static uint32_t vega20_find_lowest_dpm_level(
1750                 struct vega20_single_dpm_table *table)
1751 {
1752         uint32_t i;
1753
1754         for (i = 0; i < table->count; i++) {
1755                 if (table->dpm_levels[i].enabled)
1756                         break;
1757         }
1758         if (i >= table->count) {
1759                 i = 0;
1760                 table->dpm_levels[i].enabled = true;
1761         }
1762
1763         return i;
1764 }
1765
1766 static uint32_t vega20_find_highest_dpm_level(
1767                 struct vega20_single_dpm_table *table)
1768 {
1769         int i = 0;
1770
1771         PP_ASSERT_WITH_CODE(table != NULL,
1772                         "[FindHighestDPMLevel] DPM Table does not exist!",
1773                         return 0);
1774         PP_ASSERT_WITH_CODE(table->count > 0,
1775                         "[FindHighestDPMLevel] DPM Table has no entry!",
1776                         return 0);
1777         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1778                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1779                         return MAX_REGULAR_DPM_NUMBER - 1);
1780
1781         for (i = table->count - 1; i >= 0; i--) {
1782                 if (table->dpm_levels[i].enabled)
1783                         break;
1784         }
1785         if (i < 0) {
1786                 i = 0;
1787                 table->dpm_levels[i].enabled = true;
1788         }
1789
1790         return i;
1791 }
1792
1793 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1794 {
1795         struct vega20_hwmgr *data =
1796                         (struct vega20_hwmgr *)(hwmgr->backend);
1797         uint32_t min_freq;
1798         int ret = 0;
1799
1800         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1801            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1802                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1803                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1804                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1805                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1806                                         NULL)),
1807                                         "Failed to set soft min gfxclk !",
1808                                         return ret);
1809         }
1810
1811         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1812            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1813                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1814                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1815                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1816                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1817                                         NULL)),
1818                                         "Failed to set soft min memclk !",
1819                                         return ret);
1820         }
1821
1822         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1823            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1824                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1825
1826                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1827                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1828                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1829                                         NULL)),
1830                                         "Failed to set soft min vclk!",
1831                                         return ret);
1832
1833                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1834
1835                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1836                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1837                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1838                                         NULL)),
1839                                         "Failed to set soft min dclk!",
1840                                         return ret);
1841         }
1842
1843         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1844            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1845                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1846
1847                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1848                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1849                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1850                                         NULL)),
1851                                         "Failed to set soft min eclk!",
1852                                         return ret);
1853         }
1854
1855         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1856            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1857                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1858
1859                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1860                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1861                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1862                                         NULL)),
1863                                         "Failed to set soft min socclk!",
1864                                         return ret);
1865         }
1866
1867         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1868            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1869                 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1870
1871                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1872                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1873                                         (PPCLK_FCLK << 16) | (min_freq & 0xffff),
1874                                         NULL)),
1875                                         "Failed to set soft min fclk!",
1876                                         return ret);
1877         }
1878
1879         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1880            (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1881                 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1882
1883                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1884                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1885                                         (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1886                                         NULL)),
1887                                         "Failed to set hard min dcefclk!",
1888                                         return ret);
1889         }
1890
1891         return ret;
1892 }
1893
1894 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1895 {
1896         struct vega20_hwmgr *data =
1897                         (struct vega20_hwmgr *)(hwmgr->backend);
1898         uint32_t max_freq;
1899         int ret = 0;
1900
1901         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1902            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1903                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1904
1905                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1906                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1907                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1908                                         NULL)),
1909                                         "Failed to set soft max gfxclk!",
1910                                         return ret);
1911         }
1912
1913         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1914            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1915                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1916
1917                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1918                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1919                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1920                                         NULL)),
1921                                         "Failed to set soft max memclk!",
1922                                         return ret);
1923         }
1924
1925         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1926            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1927                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1928
1929                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1930                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1931                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1932                                         NULL)),
1933                                         "Failed to set soft max vclk!",
1934                                         return ret);
1935
1936                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1937                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1938                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1939                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1940                                         NULL)),
1941                                         "Failed to set soft max dclk!",
1942                                         return ret);
1943         }
1944
1945         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1946            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1947                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1948
1949                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1950                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1951                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1952                                         NULL)),
1953                                         "Failed to set soft max eclk!",
1954                                         return ret);
1955         }
1956
1957         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1958            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1959                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1960
1961                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1962                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1963                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1964                                         NULL)),
1965                                         "Failed to set soft max socclk!",
1966                                         return ret);
1967         }
1968
1969         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1970            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1971                 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1972
1973                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1974                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1975                                         (PPCLK_FCLK << 16) | (max_freq & 0xffff),
1976                                         NULL)),
1977                                         "Failed to set soft max fclk!",
1978                                         return ret);
1979         }
1980
1981         return ret;
1982 }
1983
1984 static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1985 {
1986         struct vega20_hwmgr *data =
1987                         (struct vega20_hwmgr *)(hwmgr->backend);
1988         int ret = 0;
1989
1990         if (data->smu_features[GNLD_DPM_VCE].supported) {
1991                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1992                         if (enable)
1993                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1994                         else
1995                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1996                 }
1997
1998                 ret = vega20_enable_smc_features(hwmgr,
1999                                 enable,
2000                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
2001                 PP_ASSERT_WITH_CODE(!ret,
2002                                 "Attempt to Enable/Disable DPM VCE Failed!",
2003                                 return ret);
2004                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
2005         }
2006
2007         return 0;
2008 }
2009
2010 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
2011                 uint32_t *clock,
2012                 PPCLK_e clock_select,
2013                 bool max)
2014 {
2015         int ret;
2016         *clock = 0;
2017
2018         if (max) {
2019                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2020                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16),
2021                                 clock)) == 0,
2022                                 "[GetClockRanges] Failed to get max clock from SMC!",
2023                                 return ret);
2024         } else {
2025                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2026                                 PPSMC_MSG_GetMinDpmFreq,
2027                                 (clock_select << 16),
2028                                 clock)) == 0,
2029                                 "[GetClockRanges] Failed to get min clock from SMC!",
2030                                 return ret);
2031         }
2032
2033         return 0;
2034 }
2035
2036 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2037 {
2038         struct vega20_hwmgr *data =
2039                         (struct vega20_hwmgr *)(hwmgr->backend);
2040         uint32_t gfx_clk;
2041         int ret = 0;
2042
2043         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2044                         "[GetSclks]: gfxclk dpm not enabled!\n",
2045                         return -EPERM);
2046
2047         if (low) {
2048                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
2049                 PP_ASSERT_WITH_CODE(!ret,
2050                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
2051                         return ret);
2052         } else {
2053                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2054                 PP_ASSERT_WITH_CODE(!ret,
2055                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2056                         return ret);
2057         }
2058
2059         return (gfx_clk * 100);
2060 }
2061
2062 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2063 {
2064         struct vega20_hwmgr *data =
2065                         (struct vega20_hwmgr *)(hwmgr->backend);
2066         uint32_t mem_clk;
2067         int ret = 0;
2068
2069         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2070                         "[MemMclks]: memclk dpm not enabled!\n",
2071                         return -EPERM);
2072
2073         if (low) {
2074                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2075                 PP_ASSERT_WITH_CODE(!ret,
2076                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
2077                         return ret);
2078         } else {
2079                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2080                 PP_ASSERT_WITH_CODE(!ret,
2081                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
2082                         return ret);
2083         }
2084
2085         return (mem_clk * 100);
2086 }
2087
2088 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
2089 {
2090         struct vega20_hwmgr *data =
2091                         (struct vega20_hwmgr *)(hwmgr->backend);
2092         int ret = 0;
2093
2094         if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
2095                 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
2096                                 TABLE_SMU_METRICS, true);
2097                 if (ret) {
2098                         pr_info("Failed to export SMU metrics table!\n");
2099                         return ret;
2100                 }
2101                 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
2102                 data->metrics_time = jiffies;
2103         } else
2104                 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2105
2106         return ret;
2107 }
2108
2109 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
2110                 uint32_t *query)
2111 {
2112         int ret = 0;
2113         SmuMetrics_t metrics_table;
2114
2115         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2116         if (ret)
2117                 return ret;
2118
2119         /* For the 40.46 release, they changed the value name */
2120         if (hwmgr->smu_version == 0x282e00)
2121                 *query = metrics_table.AverageSocketPower << 8;
2122         else
2123                 *query = metrics_table.CurrSocketPower << 8;
2124
2125         return ret;
2126 }
2127
2128 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2129                 PPCLK_e clk_id, uint32_t *clk_freq)
2130 {
2131         int ret = 0;
2132
2133         *clk_freq = 0;
2134
2135         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2136                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16),
2137                         clk_freq)) == 0,
2138                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2139                         return ret);
2140
2141         *clk_freq = *clk_freq * 100;
2142
2143         return 0;
2144 }
2145
2146 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2147                 int idx,
2148                 uint32_t *activity_percent)
2149 {
2150         int ret = 0;
2151         SmuMetrics_t metrics_table;
2152
2153         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2154         if (ret)
2155                 return ret;
2156
2157         switch (idx) {
2158         case AMDGPU_PP_SENSOR_GPU_LOAD:
2159                 *activity_percent = metrics_table.AverageGfxActivity;
2160                 break;
2161         case AMDGPU_PP_SENSOR_MEM_LOAD:
2162                 *activity_percent = metrics_table.AverageUclkActivity;
2163                 break;
2164         default:
2165                 pr_err("Invalid index for retrieving clock activity\n");
2166                 return -EINVAL;
2167         }
2168
2169         return ret;
2170 }
2171
2172 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2173                               void *value, int *size)
2174 {
2175         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2176         struct amdgpu_device *adev = hwmgr->adev;
2177         SmuMetrics_t metrics_table;
2178         uint32_t val_vid;
2179         int ret = 0;
2180
2181         switch (idx) {
2182         case AMDGPU_PP_SENSOR_GFX_SCLK:
2183                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2184                 if (ret)
2185                         return ret;
2186
2187                 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2188                 *size = 4;
2189                 break;
2190         case AMDGPU_PP_SENSOR_GFX_MCLK:
2191                 ret = vega20_get_current_clk_freq(hwmgr,
2192                                 PPCLK_UCLK,
2193                                 (uint32_t *)value);
2194                 if (!ret)
2195                         *size = 4;
2196                 break;
2197         case AMDGPU_PP_SENSOR_GPU_LOAD:
2198         case AMDGPU_PP_SENSOR_MEM_LOAD:
2199                 ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
2200                 if (!ret)
2201                         *size = 4;
2202                 break;
2203         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2204                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2205                 *size = 4;
2206                 break;
2207         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2208                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2209                 if (ret)
2210                         return ret;
2211
2212                 *((uint32_t *)value) = metrics_table.TemperatureEdge *
2213                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2214                 *size = 4;
2215                 break;
2216         case AMDGPU_PP_SENSOR_MEM_TEMP:
2217                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2218                 if (ret)
2219                         return ret;
2220
2221                 *((uint32_t *)value) = metrics_table.TemperatureHBM *
2222                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2223                 *size = 4;
2224                 break;
2225         case AMDGPU_PP_SENSOR_UVD_POWER:
2226                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2227                 *size = 4;
2228                 break;
2229         case AMDGPU_PP_SENSOR_VCE_POWER:
2230                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2231                 *size = 4;
2232                 break;
2233         case AMDGPU_PP_SENSOR_GPU_POWER:
2234                 *size = 16;
2235                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2236                 break;
2237         case AMDGPU_PP_SENSOR_VDDGFX:
2238                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2239                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2240                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2241                 *((uint32_t *)value) =
2242                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
2243                 break;
2244         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2245                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2246                 if (!ret)
2247                         *size = 8;
2248                 break;
2249         default:
2250                 ret = -EINVAL;
2251                 break;
2252         }
2253         return ret;
2254 }
2255
2256 static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2257                 struct pp_display_clock_request *clock_req)
2258 {
2259         int result = 0;
2260         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2261         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2262         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2263         PPCLK_e clk_select = 0;
2264         uint32_t clk_request = 0;
2265
2266         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2267                 switch (clk_type) {
2268                 case amd_pp_dcef_clock:
2269                         clk_select = PPCLK_DCEFCLK;
2270                         break;
2271                 case amd_pp_disp_clock:
2272                         clk_select = PPCLK_DISPCLK;
2273                         break;
2274                 case amd_pp_pixel_clock:
2275                         clk_select = PPCLK_PIXCLK;
2276                         break;
2277                 case amd_pp_phy_clock:
2278                         clk_select = PPCLK_PHYCLK;
2279                         break;
2280                 default:
2281                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2282                         result = -EINVAL;
2283                         break;
2284                 }
2285
2286                 if (!result) {
2287                         clk_request = (clk_select << 16) | clk_freq;
2288                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2289                                         PPSMC_MSG_SetHardMinByFreq,
2290                                         clk_request,
2291                                         NULL);
2292                 }
2293         }
2294
2295         return result;
2296 }
2297
2298 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2299                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2300                                 PHM_PerformanceLevel *level)
2301 {
2302         return 0;
2303 }
2304
2305 static int vega20_notify_smc_display_config_after_ps_adjustment(
2306                 struct pp_hwmgr *hwmgr)
2307 {
2308         struct vega20_hwmgr *data =
2309                         (struct vega20_hwmgr *)(hwmgr->backend);
2310         struct vega20_single_dpm_table *dpm_table =
2311                         &data->dpm_table.mem_table;
2312         struct PP_Clocks min_clocks = {0};
2313         struct pp_display_clock_request clock_req;
2314         int ret = 0;
2315
2316         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2317         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2318         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2319
2320         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2321                 clock_req.clock_type = amd_pp_dcef_clock;
2322                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2323                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2324                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2325                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2326                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2327                                         min_clocks.dcefClockInSR / 100,
2328                                         NULL)) == 0,
2329                                         "Attempt to set divider for DCEFCLK Failed!",
2330                                         return ret);
2331                 } else {
2332                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2333                 }
2334         }
2335
2336         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2337                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2338                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2339                                 PPSMC_MSG_SetHardMinByFreq,
2340                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2341                                 NULL)),
2342                                 "[SetHardMinFreq] Set hard min uclk failed!",
2343                                 return ret);
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2350 {
2351         struct vega20_hwmgr *data =
2352                         (struct vega20_hwmgr *)(hwmgr->backend);
2353         uint32_t soft_level;
2354         int ret = 0;
2355
2356         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2357
2358         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2359                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2360                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2361
2362         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2363
2364         data->dpm_table.mem_table.dpm_state.soft_min_level =
2365                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2366                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2367
2368         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2369
2370         data->dpm_table.soc_table.dpm_state.soft_min_level =
2371                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2372                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2373
2374         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2375                                                  FEATURE_DPM_UCLK_MASK |
2376                                                  FEATURE_DPM_SOCCLK_MASK);
2377         PP_ASSERT_WITH_CODE(!ret,
2378                         "Failed to upload boot level to highest!",
2379                         return ret);
2380
2381         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2382                                                  FEATURE_DPM_UCLK_MASK |
2383                                                  FEATURE_DPM_SOCCLK_MASK);
2384         PP_ASSERT_WITH_CODE(!ret,
2385                         "Failed to upload dpm max level to highest!",
2386                         return ret);
2387
2388         return 0;
2389 }
2390
2391 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2392 {
2393         struct vega20_hwmgr *data =
2394                         (struct vega20_hwmgr *)(hwmgr->backend);
2395         uint32_t soft_level;
2396         int ret = 0;
2397
2398         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2399
2400         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2401                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2402                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2403
2404         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2405
2406         data->dpm_table.mem_table.dpm_state.soft_min_level =
2407                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2408                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2409
2410         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2411
2412         data->dpm_table.soc_table.dpm_state.soft_min_level =
2413                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2414                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2415
2416         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2417                                                  FEATURE_DPM_UCLK_MASK |
2418                                                  FEATURE_DPM_SOCCLK_MASK);
2419         PP_ASSERT_WITH_CODE(!ret,
2420                         "Failed to upload boot level to highest!",
2421                         return ret);
2422
2423         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2424                                                  FEATURE_DPM_UCLK_MASK |
2425                                                  FEATURE_DPM_SOCCLK_MASK);
2426         PP_ASSERT_WITH_CODE(!ret,
2427                         "Failed to upload dpm max level to highest!",
2428                         return ret);
2429
2430         return 0;
2431
2432 }
2433
2434 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2435 {
2436         struct vega20_hwmgr *data =
2437                         (struct vega20_hwmgr *)(hwmgr->backend);
2438         uint32_t soft_min_level, soft_max_level;
2439         int ret = 0;
2440
2441         /* gfxclk soft min/max settings */
2442         soft_min_level =
2443                 vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2444         soft_max_level =
2445                 vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2446
2447         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2448                 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2449         data->dpm_table.gfx_table.dpm_state.soft_max_level =
2450                 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2451
2452         /* uclk soft min/max settings */
2453         soft_min_level =
2454                 vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2455         soft_max_level =
2456                 vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2457
2458         data->dpm_table.mem_table.dpm_state.soft_min_level =
2459                 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2460         data->dpm_table.mem_table.dpm_state.soft_max_level =
2461                 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2462
2463         /* socclk soft min/max settings */
2464         soft_min_level =
2465                 vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2466         soft_max_level =
2467                 vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2468
2469         data->dpm_table.soc_table.dpm_state.soft_min_level =
2470                 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2471         data->dpm_table.soc_table.dpm_state.soft_max_level =
2472                 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2473
2474         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2475                                                  FEATURE_DPM_UCLK_MASK |
2476                                                  FEATURE_DPM_SOCCLK_MASK);
2477         PP_ASSERT_WITH_CODE(!ret,
2478                         "Failed to upload DPM Bootup Levels!",
2479                         return ret);
2480
2481         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2482                                                  FEATURE_DPM_UCLK_MASK |
2483                                                  FEATURE_DPM_SOCCLK_MASK);
2484         PP_ASSERT_WITH_CODE(!ret,
2485                         "Failed to upload DPM Max Levels!",
2486                         return ret);
2487
2488         return 0;
2489 }
2490
2491 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2492                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2493 {
2494         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2495         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2496         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2497         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2498
2499         *sclk_mask = 0;
2500         *mclk_mask = 0;
2501         *soc_mask  = 0;
2502
2503         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2504             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2505             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2506                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2507                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2508                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2509         }
2510
2511         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2512                 *sclk_mask = 0;
2513         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2514                 *mclk_mask = 0;
2515         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2516                 *sclk_mask = gfx_dpm_table->count - 1;
2517                 *mclk_mask = mem_dpm_table->count - 1;
2518                 *soc_mask  = soc_dpm_table->count - 1;
2519         }
2520
2521         return 0;
2522 }
2523
2524 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2525                 enum pp_clock_type type, uint32_t mask)
2526 {
2527         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2528         uint32_t soft_min_level, soft_max_level, hard_min_level;
2529         int ret = 0;
2530
2531         switch (type) {
2532         case PP_SCLK:
2533                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2534                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2535
2536                 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2537                         pr_err("Clock level specified %d is over max allowed %d\n",
2538                                         soft_max_level,
2539                                         data->dpm_table.gfx_table.count - 1);
2540                         return -EINVAL;
2541                 }
2542
2543                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2544                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2545                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2546                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2547
2548                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2549                 PP_ASSERT_WITH_CODE(!ret,
2550                         "Failed to upload boot level to lowest!",
2551                         return ret);
2552
2553                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2554                 PP_ASSERT_WITH_CODE(!ret,
2555                         "Failed to upload dpm max level to highest!",
2556                         return ret);
2557                 break;
2558
2559         case PP_MCLK:
2560                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2561                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2562
2563                 if (soft_max_level >= data->dpm_table.mem_table.count) {
2564                         pr_err("Clock level specified %d is over max allowed %d\n",
2565                                         soft_max_level,
2566                                         data->dpm_table.mem_table.count - 1);
2567                         return -EINVAL;
2568                 }
2569
2570                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2571                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2572                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2573                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2574
2575                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2576                 PP_ASSERT_WITH_CODE(!ret,
2577                         "Failed to upload boot level to lowest!",
2578                         return ret);
2579
2580                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2581                 PP_ASSERT_WITH_CODE(!ret,
2582                         "Failed to upload dpm max level to highest!",
2583                         return ret);
2584
2585                 break;
2586
2587         case PP_SOCCLK:
2588                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2589                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2590
2591                 if (soft_max_level >= data->dpm_table.soc_table.count) {
2592                         pr_err("Clock level specified %d is over max allowed %d\n",
2593                                         soft_max_level,
2594                                         data->dpm_table.soc_table.count - 1);
2595                         return -EINVAL;
2596                 }
2597
2598                 data->dpm_table.soc_table.dpm_state.soft_min_level =
2599                         data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2600                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2601                         data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2602
2603                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2604                 PP_ASSERT_WITH_CODE(!ret,
2605                         "Failed to upload boot level to lowest!",
2606                         return ret);
2607
2608                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2609                 PP_ASSERT_WITH_CODE(!ret,
2610                         "Failed to upload dpm max level to highest!",
2611                         return ret);
2612
2613                 break;
2614
2615         case PP_FCLK:
2616                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2617                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2618
2619                 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2620                         pr_err("Clock level specified %d is over max allowed %d\n",
2621                                         soft_max_level,
2622                                         data->dpm_table.fclk_table.count - 1);
2623                         return -EINVAL;
2624                 }
2625
2626                 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2627                         data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2628                 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2629                         data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2630
2631                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2632                 PP_ASSERT_WITH_CODE(!ret,
2633                         "Failed to upload boot level to lowest!",
2634                         return ret);
2635
2636                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2637                 PP_ASSERT_WITH_CODE(!ret,
2638                         "Failed to upload dpm max level to highest!",
2639                         return ret);
2640
2641                 break;
2642
2643         case PP_DCEFCLK:
2644                 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2645
2646                 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2647                         pr_err("Clock level specified %d is over max allowed %d\n",
2648                                         hard_min_level,
2649                                         data->dpm_table.dcef_table.count - 1);
2650                         return -EINVAL;
2651                 }
2652
2653                 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2654                         data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2655
2656                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2657                 PP_ASSERT_WITH_CODE(!ret,
2658                         "Failed to upload boot level to lowest!",
2659                         return ret);
2660
2661                 //TODO: Setting DCEFCLK max dpm level is not supported
2662
2663                 break;
2664
2665         case PP_PCIE:
2666                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2667                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2668                 if (soft_min_level >= NUM_LINK_LEVELS ||
2669                     soft_max_level >= NUM_LINK_LEVELS)
2670                         return -EINVAL;
2671
2672                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2673                         PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level,
2674                         NULL);
2675                 PP_ASSERT_WITH_CODE(!ret,
2676                         "Failed to set min link dpm level!",
2677                         return ret);
2678
2679                 break;
2680
2681         default:
2682                 break;
2683         }
2684
2685         return 0;
2686 }
2687
2688 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2689                                 enum amd_dpm_forced_level level)
2690 {
2691         int ret = 0;
2692         uint32_t sclk_mask, mclk_mask, soc_mask;
2693
2694         switch (level) {
2695         case AMD_DPM_FORCED_LEVEL_HIGH:
2696                 ret = vega20_force_dpm_highest(hwmgr);
2697                 break;
2698
2699         case AMD_DPM_FORCED_LEVEL_LOW:
2700                 ret = vega20_force_dpm_lowest(hwmgr);
2701                 break;
2702
2703         case AMD_DPM_FORCED_LEVEL_AUTO:
2704                 ret = vega20_unforce_dpm_levels(hwmgr);
2705                 break;
2706
2707         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2708         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2709         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2710         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2711                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2712                 if (ret)
2713                         return ret;
2714                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2715                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2716                 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2717                 break;
2718
2719         case AMD_DPM_FORCED_LEVEL_MANUAL:
2720         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2721         default:
2722                 break;
2723         }
2724
2725         return ret;
2726 }
2727
2728 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2729 {
2730         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2731
2732         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2733                 return AMD_FAN_CTRL_MANUAL;
2734         else
2735                 return AMD_FAN_CTRL_AUTO;
2736 }
2737
2738 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2739 {
2740         switch (mode) {
2741         case AMD_FAN_CTRL_NONE:
2742                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2743                 break;
2744         case AMD_FAN_CTRL_MANUAL:
2745                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2746                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2747                 break;
2748         case AMD_FAN_CTRL_AUTO:
2749                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2750                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2751                 break;
2752         default:
2753                 break;
2754         }
2755 }
2756
2757 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2758                 struct amd_pp_simple_clock_info *info)
2759 {
2760 #if 0
2761         struct phm_ppt_v2_information *table_info =
2762                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2763         struct phm_clock_and_voltage_limits *max_limits =
2764                         &table_info->max_clock_voltage_on_ac;
2765
2766         info->engine_max_clock = max_limits->sclk;
2767         info->memory_max_clock = max_limits->mclk;
2768 #endif
2769         return 0;
2770 }
2771
2772
2773 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2774                 struct pp_clock_levels_with_latency *clocks)
2775 {
2776         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2777         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2778         int i, count;
2779
2780         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2781                 return -1;
2782
2783         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2784         clocks->num_levels = count;
2785
2786         for (i = 0; i < count; i++) {
2787                 clocks->data[i].clocks_in_khz =
2788                         dpm_table->dpm_levels[i].value * 1000;
2789                 clocks->data[i].latency_in_us = 0;
2790         }
2791
2792         return 0;
2793 }
2794
2795 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2796                 uint32_t clock)
2797 {
2798         return 25;
2799 }
2800
2801 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2802                 struct pp_clock_levels_with_latency *clocks)
2803 {
2804         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2805         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2806         int i, count;
2807
2808         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2809                 return -1;
2810
2811         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2812         clocks->num_levels = data->mclk_latency_table.count = count;
2813
2814         for (i = 0; i < count; i++) {
2815                 clocks->data[i].clocks_in_khz =
2816                         data->mclk_latency_table.entries[i].frequency =
2817                         dpm_table->dpm_levels[i].value * 1000;
2818                 clocks->data[i].latency_in_us =
2819                         data->mclk_latency_table.entries[i].latency =
2820                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2821         }
2822
2823         return 0;
2824 }
2825
2826 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2827                 struct pp_clock_levels_with_latency *clocks)
2828 {
2829         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2830         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2831         int i, count;
2832
2833         if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2834                 return -1;
2835
2836         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2837         clocks->num_levels = count;
2838
2839         for (i = 0; i < count; i++) {
2840                 clocks->data[i].clocks_in_khz =
2841                         dpm_table->dpm_levels[i].value * 1000;
2842                 clocks->data[i].latency_in_us = 0;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2849                 struct pp_clock_levels_with_latency *clocks)
2850 {
2851         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2852         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2853         int i, count;
2854
2855         if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2856                 return -1;
2857
2858         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2859         clocks->num_levels = count;
2860
2861         for (i = 0; i < count; i++) {
2862                 clocks->data[i].clocks_in_khz =
2863                         dpm_table->dpm_levels[i].value * 1000;
2864                 clocks->data[i].latency_in_us = 0;
2865         }
2866
2867         return 0;
2868
2869 }
2870
2871 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2872                 enum amd_pp_clock_type type,
2873                 struct pp_clock_levels_with_latency *clocks)
2874 {
2875         int ret;
2876
2877         switch (type) {
2878         case amd_pp_sys_clock:
2879                 ret = vega20_get_sclks(hwmgr, clocks);
2880                 break;
2881         case amd_pp_mem_clock:
2882                 ret = vega20_get_memclocks(hwmgr, clocks);
2883                 break;
2884         case amd_pp_dcef_clock:
2885                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2886                 break;
2887         case amd_pp_soc_clock:
2888                 ret = vega20_get_socclocks(hwmgr, clocks);
2889                 break;
2890         default:
2891                 return -EINVAL;
2892         }
2893
2894         return ret;
2895 }
2896
2897 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2898                 enum amd_pp_clock_type type,
2899                 struct pp_clock_levels_with_voltage *clocks)
2900 {
2901         clocks->num_levels = 0;
2902
2903         return 0;
2904 }
2905
2906 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2907                                                    void *clock_ranges)
2908 {
2909         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2910         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2911         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2912
2913         if (!data->registry_data.disable_water_mark &&
2914             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2915             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2916                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2917                 data->water_marks_bitmap |= WaterMarksExist;
2918                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2919         }
2920
2921         return 0;
2922 }
2923
2924 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2925                                         enum PP_OD_DPM_TABLE_COMMAND type,
2926                                         long *input, uint32_t size)
2927 {
2928         struct vega20_hwmgr *data =
2929                         (struct vega20_hwmgr *)(hwmgr->backend);
2930         struct vega20_od8_single_setting *od8_settings =
2931                         data->od8_settings.od8_settings_array;
2932         OverDriveTable_t *od_table =
2933                         &(data->smc_state_table.overdrive_table);
2934         int32_t input_index, input_clk, input_vol, i;
2935         int od8_id;
2936         int ret;
2937
2938         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2939                                 return -EINVAL);
2940
2941         switch (type) {
2942         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2943                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2944                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2945                         pr_info("Sclk min/max frequency overdrive not supported\n");
2946                         return -EOPNOTSUPP;
2947                 }
2948
2949                 for (i = 0; i < size; i += 2) {
2950                         if (i + 2 > size) {
2951                                 pr_info("invalid number of input parameters %d\n",
2952                                         size);
2953                                 return -EINVAL;
2954                         }
2955
2956                         input_index = input[i];
2957                         input_clk = input[i + 1];
2958
2959                         if (input_index != 0 && input_index != 1) {
2960                                 pr_info("Invalid index %d\n", input_index);
2961                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2962                                 return -EINVAL;
2963                         }
2964
2965                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2966                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2967                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2968                                         input_clk,
2969                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2970                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2971                                 return -EINVAL;
2972                         }
2973
2974                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2975                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2976                                 data->gfxclk_overdrive = true;
2977
2978                         if (input_index == 0)
2979                                 od_table->GfxclkFmin = input_clk;
2980                         else
2981                                 od_table->GfxclkFmax = input_clk;
2982                 }
2983
2984                 break;
2985
2986         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2987                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2988                         pr_info("Mclk max frequency overdrive not supported\n");
2989                         return -EOPNOTSUPP;
2990                 }
2991
2992                 for (i = 0; i < size; i += 2) {
2993                         if (i + 2 > size) {
2994                                 pr_info("invalid number of input parameters %d\n",
2995                                         size);
2996                                 return -EINVAL;
2997                         }
2998
2999                         input_index = input[i];
3000                         input_clk = input[i + 1];
3001
3002                         if (input_index != 1) {
3003                                 pr_info("Invalid index %d\n", input_index);
3004                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
3005                                 return -EINVAL;
3006                         }
3007
3008                         if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
3009                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
3010                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3011                                         input_clk,
3012                                         od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3013                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3014                                 return -EINVAL;
3015                         }
3016
3017                         if (input_index == 1 && od_table->UclkFmax != input_clk)
3018                                 data->memclk_overdrive = true;
3019
3020                         od_table->UclkFmax = input_clk;
3021                 }
3022
3023                 break;
3024
3025         case PP_OD_EDIT_VDDC_CURVE:
3026                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3027                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3028                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3029                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3030                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3031                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
3032                         pr_info("Voltage curve calibrate not supported\n");
3033                         return -EOPNOTSUPP;
3034                 }
3035
3036                 for (i = 0; i < size; i += 3) {
3037                         if (i + 3 > size) {
3038                                 pr_info("invalid number of input parameters %d\n",
3039                                         size);
3040                                 return -EINVAL;
3041                         }
3042
3043                         input_index = input[i];
3044                         input_clk = input[i + 1];
3045                         input_vol = input[i + 2];
3046
3047                         if (input_index > 2) {
3048                                 pr_info("Setting for point %d is not supported\n",
3049                                                 input_index + 1);
3050                                 pr_info("Three supported points index by 0, 1, 2\n");
3051                                 return -EINVAL;
3052                         }
3053
3054                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
3055                         if (input_clk < od8_settings[od8_id].min_value ||
3056                             input_clk > od8_settings[od8_id].max_value) {
3057                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3058                                         input_clk,
3059                                         od8_settings[od8_id].min_value,
3060                                         od8_settings[od8_id].max_value);
3061                                 return -EINVAL;
3062                         }
3063
3064                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
3065                         if (input_vol < od8_settings[od8_id].min_value ||
3066                             input_vol > od8_settings[od8_id].max_value) {
3067                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
3068                                         input_vol,
3069                                         od8_settings[od8_id].min_value,
3070                                         od8_settings[od8_id].max_value);
3071                                 return -EINVAL;
3072                         }
3073
3074                         switch (input_index) {
3075                         case 0:
3076                                 od_table->GfxclkFreq1 = input_clk;
3077                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
3078                                 break;
3079                         case 1:
3080                                 od_table->GfxclkFreq2 = input_clk;
3081                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
3082                                 break;
3083                         case 2:
3084                                 od_table->GfxclkFreq3 = input_clk;
3085                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
3086                                 break;
3087                         }
3088                 }
3089                 break;
3090
3091         case PP_OD_RESTORE_DEFAULT_TABLE:
3092                 data->gfxclk_overdrive = false;
3093                 data->memclk_overdrive = false;
3094
3095                 ret = smum_smc_table_manager(hwmgr,
3096                                              (uint8_t *)od_table,
3097                                              TABLE_OVERDRIVE, true);
3098                 PP_ASSERT_WITH_CODE(!ret,
3099                                 "Failed to export overdrive table!",
3100                                 return ret);
3101                 break;
3102
3103         case PP_OD_COMMIT_DPM_TABLE:
3104                 ret = smum_smc_table_manager(hwmgr,
3105                                              (uint8_t *)od_table,
3106                                              TABLE_OVERDRIVE, false);
3107                 PP_ASSERT_WITH_CODE(!ret,
3108                                 "Failed to import overdrive table!",
3109                                 return ret);
3110
3111                 /* retrieve updated gfxclk table */
3112                 if (data->gfxclk_overdrive) {
3113                         data->gfxclk_overdrive = false;
3114
3115                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
3116                         if (ret)
3117                                 return ret;
3118                 }
3119
3120                 /* retrieve updated memclk table */
3121                 if (data->memclk_overdrive) {
3122                         data->memclk_overdrive = false;
3123
3124                         ret = vega20_setup_memclk_dpm_table(hwmgr);
3125                         if (ret)
3126                                 return ret;
3127                 }
3128                 break;
3129
3130         default:
3131                 return -EINVAL;
3132         }
3133
3134         return 0;
3135 }
3136
3137 static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
3138                                 enum pp_mp1_state mp1_state)
3139 {
3140         uint16_t msg;
3141         int ret;
3142
3143         switch (mp1_state) {
3144         case PP_MP1_STATE_SHUTDOWN:
3145                 msg = PPSMC_MSG_PrepareMp1ForShutdown;
3146                 break;
3147         case PP_MP1_STATE_UNLOAD:
3148                 msg = PPSMC_MSG_PrepareMp1ForUnload;
3149                 break;
3150         case PP_MP1_STATE_RESET:
3151                 msg = PPSMC_MSG_PrepareMp1ForReset;
3152                 break;
3153         case PP_MP1_STATE_NONE:
3154         default:
3155                 return 0;
3156         }
3157
3158         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
3159                             "[PrepareMp1] Failed!",
3160                             return ret);
3161
3162         return 0;
3163 }
3164
3165 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
3166 {
3167         static const char *ppfeature_name[] = {
3168                                 "DPM_PREFETCHER",
3169                                 "GFXCLK_DPM",
3170                                 "UCLK_DPM",
3171                                 "SOCCLK_DPM",
3172                                 "UVD_DPM",
3173                                 "VCE_DPM",
3174                                 "ULV",
3175                                 "MP0CLK_DPM",
3176                                 "LINK_DPM",
3177                                 "DCEFCLK_DPM",
3178                                 "GFXCLK_DS",
3179                                 "SOCCLK_DS",
3180                                 "LCLK_DS",
3181                                 "PPT",
3182                                 "TDC",
3183                                 "THERMAL",
3184                                 "GFX_PER_CU_CG",
3185                                 "RM",
3186                                 "DCEFCLK_DS",
3187                                 "ACDC",
3188                                 "VR0HOT",
3189                                 "VR1HOT",
3190                                 "FW_CTF",
3191                                 "LED_DISPLAY",
3192                                 "FAN_CONTROL",
3193                                 "GFX_EDC",
3194                                 "GFXOFF",
3195                                 "CG",
3196                                 "FCLK_DPM",
3197                                 "FCLK_DS",
3198                                 "MP1CLK_DS",
3199                                 "MP0CLK_DS",
3200                                 "XGMI",
3201                                 "ECC"};
3202         static const char *output_title[] = {
3203                                 "FEATURES",
3204                                 "BITMASK",
3205                                 "ENABLEMENT"};
3206         uint64_t features_enabled;
3207         int i;
3208         int ret = 0;
3209         int size = 0;
3210
3211         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3212         PP_ASSERT_WITH_CODE(!ret,
3213                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3214                         return ret);
3215
3216         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3217         size += sprintf(buf + size, "%-19s %-22s %s\n",
3218                                 output_title[0],
3219                                 output_title[1],
3220                                 output_title[2]);
3221         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3222                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
3223                                         ppfeature_name[i],
3224                                         1ULL << i,
3225                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
3226         }
3227
3228         return size;
3229 }
3230
3231 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3232 {
3233         uint64_t features_enabled;
3234         uint64_t features_to_enable;
3235         uint64_t features_to_disable;
3236         int ret = 0;
3237
3238         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3239                 return -EINVAL;
3240
3241         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3242         if (ret)
3243                 return ret;
3244
3245         features_to_disable =
3246                 features_enabled & ~new_ppfeature_masks;
3247         features_to_enable =
3248                 ~features_enabled & new_ppfeature_masks;
3249
3250         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3251         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3252
3253         if (features_to_disable) {
3254                 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3255                 if (ret)
3256                         return ret;
3257         }
3258
3259         if (features_to_enable) {
3260                 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3261                 if (ret)
3262                         return ret;
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3269                 enum pp_clock_type type, char *buf)
3270 {
3271         struct vega20_hwmgr *data =
3272                         (struct vega20_hwmgr *)(hwmgr->backend);
3273         struct vega20_od8_single_setting *od8_settings =
3274                         data->od8_settings.od8_settings_array;
3275         OverDriveTable_t *od_table =
3276                         &(data->smc_state_table.overdrive_table);
3277         struct phm_ppt_v3_information *pptable_information =
3278                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3279         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
3280         struct amdgpu_device *adev = hwmgr->adev;
3281         struct pp_clock_levels_with_latency clocks;
3282         struct vega20_single_dpm_table *fclk_dpm_table =
3283                         &(data->dpm_table.fclk_table);
3284         int i, now, size = 0;
3285         int ret = 0;
3286         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3287
3288         switch (type) {
3289         case PP_SCLK:
3290                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3291                 PP_ASSERT_WITH_CODE(!ret,
3292                                 "Attempt to get current gfx clk Failed!",
3293                                 return ret);
3294
3295                 if (vega20_get_sclks(hwmgr, &clocks)) {
3296                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3297                                 now / 100);
3298                         break;
3299                 }
3300
3301                 for (i = 0; i < clocks.num_levels; i++)
3302                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3303                                 i, clocks.data[i].clocks_in_khz / 1000,
3304                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3305                 break;
3306
3307         case PP_MCLK:
3308                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3309                 PP_ASSERT_WITH_CODE(!ret,
3310                                 "Attempt to get current mclk freq Failed!",
3311                                 return ret);
3312
3313                 if (vega20_get_memclocks(hwmgr, &clocks)) {
3314                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3315                                 now / 100);
3316                         break;
3317                 }
3318
3319                 for (i = 0; i < clocks.num_levels; i++)
3320                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3321                                 i, clocks.data[i].clocks_in_khz / 1000,
3322                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3323                 break;
3324
3325         case PP_SOCCLK:
3326                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3327                 PP_ASSERT_WITH_CODE(!ret,
3328                                 "Attempt to get current socclk freq Failed!",
3329                                 return ret);
3330
3331                 if (vega20_get_socclocks(hwmgr, &clocks)) {
3332                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3333                                 now / 100);
3334                         break;
3335                 }
3336
3337                 for (i = 0; i < clocks.num_levels; i++)
3338                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3339                                 i, clocks.data[i].clocks_in_khz / 1000,
3340                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3341                 break;
3342
3343         case PP_FCLK:
3344                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3345                 PP_ASSERT_WITH_CODE(!ret,
3346                                 "Attempt to get current fclk freq Failed!",
3347                                 return ret);
3348
3349                 for (i = 0; i < fclk_dpm_table->count; i++)
3350                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3351                                 i, fclk_dpm_table->dpm_levels[i].value,
3352                                 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3353                 break;
3354
3355         case PP_DCEFCLK:
3356                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3357                 PP_ASSERT_WITH_CODE(!ret,
3358                                 "Attempt to get current dcefclk freq Failed!",
3359                                 return ret);
3360
3361                 if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3362                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3363                                 now / 100);
3364                         break;
3365                 }
3366
3367                 for (i = 0; i < clocks.num_levels; i++)
3368                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3369                                 i, clocks.data[i].clocks_in_khz / 1000,
3370                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3371                 break;
3372
3373         case PP_PCIE:
3374                 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3375                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3376                             >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3377                 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3378                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3379                             >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3380                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3381                         if (i == 1 && data->pcie_parameters_override) {
3382                                 gen_speed = data->pcie_gen_level1;
3383                                 lane_width = data->pcie_width_level1;
3384                         } else {
3385                                 gen_speed = pptable->PcieGenSpeed[i];
3386                                 lane_width = pptable->PcieLaneCount[i];
3387                         }
3388                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3389                                         (gen_speed == 0) ? "2.5GT/s," :
3390                                         (gen_speed == 1) ? "5.0GT/s," :
3391                                         (gen_speed == 2) ? "8.0GT/s," :
3392                                         (gen_speed == 3) ? "16.0GT/s," : "",
3393                                         (lane_width == 1) ? "x1" :
3394                                         (lane_width == 2) ? "x2" :
3395                                         (lane_width == 3) ? "x4" :
3396                                         (lane_width == 4) ? "x8" :
3397                                         (lane_width == 5) ? "x12" :
3398                                         (lane_width == 6) ? "x16" : "",
3399                                         pptable->LclkFreq[i],
3400                                         (current_gen_speed == gen_speed) &&
3401                                         (current_lane_width == lane_width) ?
3402                                         "*" : "");
3403                 }
3404                 break;
3405
3406         case OD_SCLK:
3407                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3408                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3409                         size = sprintf(buf, "%s:\n", "OD_SCLK");
3410                         size += sprintf(buf + size, "0: %10uMhz\n",
3411                                 od_table->GfxclkFmin);
3412                         size += sprintf(buf + size, "1: %10uMhz\n",
3413                                 od_table->GfxclkFmax);
3414                 }
3415                 break;
3416
3417         case OD_MCLK:
3418                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3419                         size = sprintf(buf, "%s:\n", "OD_MCLK");
3420                         size += sprintf(buf + size, "1: %10uMhz\n",
3421                                 od_table->UclkFmax);
3422                 }
3423
3424                 break;
3425
3426         case OD_VDDC_CURVE:
3427                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3428                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3429                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3430                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3431                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3432                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3433                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
3434                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3435                                 od_table->GfxclkFreq1,
3436                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3437                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3438                                 od_table->GfxclkFreq2,
3439                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3440                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3441                                 od_table->GfxclkFreq3,
3442                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3443                 }
3444
3445                 break;
3446
3447         case OD_RANGE:
3448                 size = sprintf(buf, "%s:\n", "OD_RANGE");
3449
3450                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3451                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3452                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3453                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3454                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3455                 }
3456
3457                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3458                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3459                                 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3460                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3461                 }
3462
3463                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3464                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3465                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3466                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3467                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3468                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3469                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3470                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3471                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3472                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3473                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3474                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3475                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3476                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3477                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3478                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3479                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3480                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3481                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3482                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3483                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3484                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3485                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3486                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3487                 }
3488
3489                 break;
3490         default:
3491                 break;
3492         }
3493         return size;
3494 }
3495
3496 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3497                 struct vega20_single_dpm_table *dpm_table)
3498 {
3499         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3500         int ret = 0;
3501
3502         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3503                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3504                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3505                                 return -EINVAL);
3506                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3507                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3508                                 return -EINVAL);
3509
3510                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3511                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3512                                 PPSMC_MSG_SetHardMinByFreq,
3513                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
3514                                 NULL)),
3515                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3516                                 return ret);
3517         }
3518
3519         return ret;
3520 }
3521
3522 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3523 {
3524         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3525         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3526         int ret = 0;
3527
3528         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3529                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3530                                 "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3531                                 return -EINVAL);
3532                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3533                                 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3534                                 return -EINVAL);
3535
3536                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3537                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3538                                 PPSMC_MSG_SetSoftMinByFreq,
3539                                 (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level,
3540                                 NULL)),
3541                                 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3542                                 return ret);
3543         }
3544
3545         return ret;
3546 }
3547
3548 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3549 {
3550         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3551         int ret = 0;
3552
3553         smum_send_msg_to_smc_with_parameter(hwmgr,
3554                         PPSMC_MSG_NumOfDisplays, 0, NULL);
3555
3556         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3557                         &data->dpm_table.mem_table);
3558         if (ret)
3559                 return ret;
3560
3561         return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3562 }
3563
3564 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3565 {
3566         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3567         int result = 0;
3568         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3569
3570         if ((data->water_marks_bitmap & WaterMarksExist) &&
3571             !(data->water_marks_bitmap & WaterMarksLoaded)) {
3572                 result = smum_smc_table_manager(hwmgr,
3573                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3574                 PP_ASSERT_WITH_CODE(!result,
3575                                 "Failed to update WMTABLE!",
3576                                 return result);
3577                 data->water_marks_bitmap |= WaterMarksLoaded;
3578         }
3579
3580         if ((data->water_marks_bitmap & WaterMarksExist) &&
3581             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3582             data->smu_features[GNLD_DPM_SOCCLK].supported) {
3583                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3584                         PPSMC_MSG_NumOfDisplays,
3585                         hwmgr->display_config->num_display,
3586                         NULL);
3587         }
3588
3589         return result;
3590 }
3591
3592 static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3593 {
3594         struct vega20_hwmgr *data =
3595                         (struct vega20_hwmgr *)(hwmgr->backend);
3596         int ret = 0;
3597
3598         if (data->smu_features[GNLD_DPM_UVD].supported) {
3599                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3600                         if (enable)
3601                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3602                         else
3603                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3604                 }
3605
3606                 ret = vega20_enable_smc_features(hwmgr,
3607                                 enable,
3608                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3609                 PP_ASSERT_WITH_CODE(!ret,
3610                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3611                                 return ret);
3612                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3613         }
3614
3615         return 0;
3616 }
3617
3618 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3619 {
3620         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3621
3622         if (data->vce_power_gated == bgate)
3623                 return ;
3624
3625         data->vce_power_gated = bgate;
3626         if (bgate) {
3627                 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3628                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3629                                                 AMD_IP_BLOCK_TYPE_VCE,
3630                                                 AMD_PG_STATE_GATE);
3631         } else {
3632                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3633                                                 AMD_IP_BLOCK_TYPE_VCE,
3634                                                 AMD_PG_STATE_UNGATE);
3635                 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3636         }
3637
3638 }
3639
3640 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3641 {
3642         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3643
3644         if (data->uvd_power_gated == bgate)
3645                 return ;
3646
3647         data->uvd_power_gated = bgate;
3648         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3649 }
3650
3651 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3652 {
3653         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3654         struct vega20_single_dpm_table *dpm_table;
3655         bool vblank_too_short = false;
3656         bool disable_mclk_switching;
3657         bool disable_fclk_switching;
3658         uint32_t i, latency;
3659
3660         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3661                            !hwmgr->display_config->multi_monitor_in_sync) ||
3662                             vblank_too_short;
3663         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3664
3665         /* gfxclk */
3666         dpm_table = &(data->dpm_table.gfx_table);
3667         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3668         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3669         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3670         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3671
3672         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3673                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3674                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3675                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3676                 }
3677
3678                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3679                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3680                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3681                 }
3682
3683                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3684                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3685                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3686                 }
3687         }
3688
3689         /* memclk */
3690         dpm_table = &(data->dpm_table.mem_table);
3691         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3692         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3693         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3694         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3695
3696         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3697                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3698                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3699                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3700                 }
3701
3702                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3703                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3704                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3705                 }
3706
3707                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3708                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3709                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3710                 }
3711         }
3712
3713         /* honour DAL's UCLK Hardmin */
3714         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3715                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3716
3717         /* Hardmin is dependent on displayconfig */
3718         if (disable_mclk_switching) {
3719                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3720                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3721                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3722                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3723                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3724                                         break;
3725                                 }
3726                         }
3727                 }
3728         }
3729
3730         if (hwmgr->display_config->nb_pstate_switch_disable)
3731                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3732
3733         if ((disable_mclk_switching &&
3734             (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
3735              hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
3736                 disable_fclk_switching = true;
3737         else
3738                 disable_fclk_switching = false;
3739
3740         /* fclk */
3741         dpm_table = &(data->dpm_table.fclk_table);
3742         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3743         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3744         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3745         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3746         if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
3747                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3748
3749         /* vclk */
3750         dpm_table = &(data->dpm_table.vclk_table);
3751         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3752         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3753         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3754         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3755
3756         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3757                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3758                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3759                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3760                 }
3761
3762                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3763                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3764                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3765                 }
3766         }
3767
3768         /* dclk */
3769         dpm_table = &(data->dpm_table.dclk_table);
3770         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3771         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3772         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3773         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3774
3775         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3776                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3777                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3778                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3779                 }
3780
3781                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3782                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3783                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3784                 }
3785         }
3786
3787         /* socclk */
3788         dpm_table = &(data->dpm_table.soc_table);
3789         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3790         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3791         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3792         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3793
3794         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3795                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3796                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3797                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3798                 }
3799
3800                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3801                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3802                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3803                 }
3804         }
3805
3806         /* eclk */
3807         dpm_table = &(data->dpm_table.eclk_table);
3808         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3809         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3810         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3811         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3812
3813         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3814                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3815                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3816                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3817                 }
3818
3819                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3820                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3821                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3822                 }
3823         }
3824
3825         return 0;
3826 }
3827
3828 static bool
3829 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3830 {
3831         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3832         bool is_update_required = false;
3833
3834         if (data->display_timing.num_existing_displays !=
3835                         hwmgr->display_config->num_display)
3836                 is_update_required = true;
3837
3838         if (data->registry_data.gfx_clk_deep_sleep_support &&
3839            (data->display_timing.min_clock_in_sr !=
3840             hwmgr->display_config->min_core_set_clock_in_sr))
3841                 is_update_required = true;
3842
3843         return is_update_required;
3844 }
3845
3846 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3847 {
3848         int ret = 0;
3849
3850         ret = vega20_disable_all_smu_features(hwmgr);
3851         PP_ASSERT_WITH_CODE(!ret,
3852                         "[DisableDpmTasks] Failed to disable all smu features!",
3853                         return ret);
3854
3855         return 0;
3856 }
3857
3858 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3859 {
3860         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3861         int result;
3862
3863         result = vega20_disable_dpm_tasks(hwmgr);
3864         PP_ASSERT_WITH_CODE((0 == result),
3865                         "[PowerOffAsic] Failed to disable DPM!",
3866                         );
3867         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3868
3869         return result;
3870 }
3871
3872 static int conv_power_profile_to_pplib_workload(int power_profile)
3873 {
3874         int pplib_workload = 0;
3875
3876         switch (power_profile) {
3877         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3878                 pplib_workload = WORKLOAD_DEFAULT_BIT;
3879                 break;
3880         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3881                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3882                 break;
3883         case PP_SMC_POWER_PROFILE_POWERSAVING:
3884                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3885                 break;
3886         case PP_SMC_POWER_PROFILE_VIDEO:
3887                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3888                 break;
3889         case PP_SMC_POWER_PROFILE_VR:
3890                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3891                 break;
3892         case PP_SMC_POWER_PROFILE_COMPUTE:
3893                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3894                 break;
3895         case PP_SMC_POWER_PROFILE_CUSTOM:
3896                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3897                 break;
3898         }
3899
3900         return pplib_workload;
3901 }
3902
3903 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3904 {
3905         DpmActivityMonitorCoeffInt_t activity_monitor;
3906         uint32_t i, size = 0;
3907         uint16_t workload_type = 0;
3908         static const char *profile_name[] = {
3909                                         "BOOTUP_DEFAULT",
3910                                         "3D_FULL_SCREEN",
3911                                         "POWER_SAVING",
3912                                         "VIDEO",
3913                                         "VR",
3914                                         "COMPUTE",
3915                                         "CUSTOM"};
3916         static const char *title[] = {
3917                         "PROFILE_INDEX(NAME)",
3918                         "CLOCK_TYPE(NAME)",
3919                         "FPS",
3920                         "UseRlcBusy",
3921                         "MinActiveFreqType",
3922                         "MinActiveFreq",
3923                         "BoosterFreqType",
3924                         "BoosterFreq",
3925                         "PD_Data_limit_c",
3926                         "PD_Data_error_coeff",
3927                         "PD_Data_error_rate_coeff"};
3928         int result = 0;
3929
3930         if (!buf)
3931                 return -EINVAL;
3932
3933         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3934                         title[0], title[1], title[2], title[3], title[4], title[5],
3935                         title[6], title[7], title[8], title[9], title[10]);
3936
3937         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3938                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3939                 workload_type = conv_power_profile_to_pplib_workload(i);
3940                 result = vega20_get_activity_monitor_coeff(hwmgr,
3941                                 (uint8_t *)(&activity_monitor), workload_type);
3942                 PP_ASSERT_WITH_CODE(!result,
3943                                 "[GetPowerProfile] Failed to get activity monitor!",
3944                                 return result);
3945
3946                 size += sprintf(buf + size, "%2d %14s%s:\n",
3947                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3948
3949                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3950                         " ",
3951                         0,
3952                         "GFXCLK",
3953                         activity_monitor.Gfx_FPS,
3954                         activity_monitor.Gfx_UseRlcBusy,
3955                         activity_monitor.Gfx_MinActiveFreqType,
3956                         activity_monitor.Gfx_MinActiveFreq,
3957                         activity_monitor.Gfx_BoosterFreqType,
3958                         activity_monitor.Gfx_BoosterFreq,
3959                         activity_monitor.Gfx_PD_Data_limit_c,
3960                         activity_monitor.Gfx_PD_Data_error_coeff,
3961                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3962
3963                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3964                         " ",
3965                         1,
3966                         "SOCCLK",
3967                         activity_monitor.Soc_FPS,
3968                         activity_monitor.Soc_UseRlcBusy,
3969                         activity_monitor.Soc_MinActiveFreqType,
3970                         activity_monitor.Soc_MinActiveFreq,
3971                         activity_monitor.Soc_BoosterFreqType,
3972                         activity_monitor.Soc_BoosterFreq,
3973                         activity_monitor.Soc_PD_Data_limit_c,
3974                         activity_monitor.Soc_PD_Data_error_coeff,
3975                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3976
3977                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3978                         " ",
3979                         2,
3980                         "UCLK",
3981                         activity_monitor.Mem_FPS,
3982                         activity_monitor.Mem_UseRlcBusy,
3983                         activity_monitor.Mem_MinActiveFreqType,
3984                         activity_monitor.Mem_MinActiveFreq,
3985                         activity_monitor.Mem_BoosterFreqType,
3986                         activity_monitor.Mem_BoosterFreq,
3987                         activity_monitor.Mem_PD_Data_limit_c,
3988                         activity_monitor.Mem_PD_Data_error_coeff,
3989                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3990
3991                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3992                         " ",
3993                         3,
3994                         "FCLK",
3995                         activity_monitor.Fclk_FPS,
3996                         activity_monitor.Fclk_UseRlcBusy,
3997                         activity_monitor.Fclk_MinActiveFreqType,
3998                         activity_monitor.Fclk_MinActiveFreq,
3999                         activity_monitor.Fclk_BoosterFreqType,
4000                         activity_monitor.Fclk_BoosterFreq,
4001                         activity_monitor.Fclk_PD_Data_limit_c,
4002                         activity_monitor.Fclk_PD_Data_error_coeff,
4003                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
4004         }
4005
4006         return size;
4007 }
4008
4009 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4010 {
4011         DpmActivityMonitorCoeffInt_t activity_monitor;
4012         int workload_type, result = 0;
4013         uint32_t power_profile_mode = input[size];
4014
4015         if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
4016                 pr_err("Invalid power profile mode %d\n", power_profile_mode);
4017                 return -EINVAL;
4018         }
4019
4020         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4021                 struct vega20_hwmgr *data =
4022                         (struct vega20_hwmgr *)(hwmgr->backend);
4023                 if (size == 0 && !data->is_custom_profile_set)
4024                         return -EINVAL;
4025                 if (size < 10 && size != 0)
4026                         return -EINVAL;
4027
4028                 result = vega20_get_activity_monitor_coeff(hwmgr,
4029                                 (uint8_t *)(&activity_monitor),
4030                                 WORKLOAD_PPLIB_CUSTOM_BIT);
4031                 PP_ASSERT_WITH_CODE(!result,
4032                                 "[SetPowerProfile] Failed to get activity monitor!",
4033                                 return result);
4034
4035                 /* If size==0, then we want to apply the already-configured
4036                  * CUSTOM profile again. Just apply it, since we checked its
4037                  * validity above
4038                  */
4039                 if (size == 0)
4040                         goto out;
4041
4042                 switch (input[0]) {
4043                 case 0: /* Gfxclk */
4044                         activity_monitor.Gfx_FPS = input[1];
4045                         activity_monitor.Gfx_UseRlcBusy = input[2];
4046                         activity_monitor.Gfx_MinActiveFreqType = input[3];
4047                         activity_monitor.Gfx_MinActiveFreq = input[4];
4048                         activity_monitor.Gfx_BoosterFreqType = input[5];
4049                         activity_monitor.Gfx_BoosterFreq = input[6];
4050                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
4051                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
4052                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
4053                         break;
4054                 case 1: /* Socclk */
4055                         activity_monitor.Soc_FPS = input[1];
4056                         activity_monitor.Soc_UseRlcBusy = input[2];
4057                         activity_monitor.Soc_MinActiveFreqType = input[3];
4058                         activity_monitor.Soc_MinActiveFreq = input[4];
4059                         activity_monitor.Soc_BoosterFreqType = input[5];
4060                         activity_monitor.Soc_BoosterFreq = input[6];
4061                         activity_monitor.Soc_PD_Data_limit_c = input[7];
4062                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
4063                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
4064                         break;
4065                 case 2: /* Uclk */
4066                         activity_monitor.Mem_FPS = input[1];
4067                         activity_monitor.Mem_UseRlcBusy = input[2];
4068                         activity_monitor.Mem_MinActiveFreqType = input[3];
4069                         activity_monitor.Mem_MinActiveFreq = input[4];
4070                         activity_monitor.Mem_BoosterFreqType = input[5];
4071                         activity_monitor.Mem_BoosterFreq = input[6];
4072                         activity_monitor.Mem_PD_Data_limit_c = input[7];
4073                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
4074                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
4075                         break;
4076                 case 3: /* Fclk */
4077                         activity_monitor.Fclk_FPS = input[1];
4078                         activity_monitor.Fclk_UseRlcBusy = input[2];
4079                         activity_monitor.Fclk_MinActiveFreqType = input[3];
4080                         activity_monitor.Fclk_MinActiveFreq = input[4];
4081                         activity_monitor.Fclk_BoosterFreqType = input[5];
4082                         activity_monitor.Fclk_BoosterFreq = input[6];
4083                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
4084                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
4085                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
4086                         break;
4087                 }
4088
4089                 result = vega20_set_activity_monitor_coeff(hwmgr,
4090                                 (uint8_t *)(&activity_monitor),
4091                                 WORKLOAD_PPLIB_CUSTOM_BIT);
4092                 data->is_custom_profile_set = true;
4093                 PP_ASSERT_WITH_CODE(!result,
4094                                 "[SetPowerProfile] Failed to set activity monitor!",
4095                                 return result);
4096         }
4097
4098 out:
4099         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4100         workload_type =
4101                 conv_power_profile_to_pplib_workload(power_profile_mode);
4102         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4103                                                 1 << workload_type,
4104                                                 NULL);
4105
4106         hwmgr->power_profile_mode = power_profile_mode;
4107
4108         return 0;
4109 }
4110
4111 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4112                                         uint32_t virtual_addr_low,
4113                                         uint32_t virtual_addr_hi,
4114                                         uint32_t mc_addr_low,
4115                                         uint32_t mc_addr_hi,
4116                                         uint32_t size)
4117 {
4118         smum_send_msg_to_smc_with_parameter(hwmgr,
4119                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4120                                         virtual_addr_hi,
4121                                         NULL);
4122         smum_send_msg_to_smc_with_parameter(hwmgr,
4123                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4124                                         virtual_addr_low,
4125                                         NULL);
4126         smum_send_msg_to_smc_with_parameter(hwmgr,
4127                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4128                                         mc_addr_hi,
4129                                         NULL);
4130
4131         smum_send_msg_to_smc_with_parameter(hwmgr,
4132                                         PPSMC_MSG_DramLogSetDramAddrLow,
4133                                         mc_addr_low,
4134                                         NULL);
4135
4136         smum_send_msg_to_smc_with_parameter(hwmgr,
4137                                         PPSMC_MSG_DramLogSetDramSize,
4138                                         size,
4139                                         NULL);
4140         return 0;
4141 }
4142
4143 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4144                 struct PP_TemperatureRange *thermal_data)
4145 {
4146         struct vega20_hwmgr *data =
4147                         (struct vega20_hwmgr *)(hwmgr->backend);
4148         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
4149
4150         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4151
4152         thermal_data->max = pp_table->TedgeLimit *
4153                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4154         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
4155                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4156         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
4157                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4158         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
4159                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4160         thermal_data->mem_crit_max = pp_table->ThbmLimit *
4161                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4162         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
4163                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4164
4165         return 0;
4166 }
4167
4168 static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
4169 {
4170         int res;
4171
4172         /* I2C bus access can happen very early, when SMU not loaded yet */
4173         if (!vega20_is_smc_ram_running(hwmgr))
4174                 return 0;
4175
4176         res = smum_send_msg_to_smc_with_parameter(hwmgr,
4177                                                   (acquire ?
4178                                                   PPSMC_MSG_RequestI2CBus :
4179                                                   PPSMC_MSG_ReleaseI2CBus),
4180                                                   0,
4181                                                   NULL);
4182
4183         PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
4184         return res;
4185 }
4186
4187 static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
4188                                 enum pp_df_cstate state)
4189 {
4190         int ret;
4191
4192         /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
4193         if (hwmgr->smu_version < 0x283200) {
4194                 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
4195                 return -EINVAL;
4196         }
4197
4198         ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state,
4199                                 NULL);
4200         if (ret)
4201                 pr_err("SetDfCstate failed!\n");
4202
4203         return ret;
4204 }
4205
4206 static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
4207                                   uint32_t pstate)
4208 {
4209         int ret;
4210
4211         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4212                                                   PPSMC_MSG_SetXgmiMode,
4213                                                   pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
4214                                                   NULL);
4215         if (ret)
4216                 pr_err("SetXgmiPstate failed!\n");
4217
4218         return ret;
4219 }
4220
4221 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
4222         /* init/fini related */
4223         .backend_init = vega20_hwmgr_backend_init,
4224         .backend_fini = vega20_hwmgr_backend_fini,
4225         .asic_setup = vega20_setup_asic_task,
4226         .power_off_asic = vega20_power_off_asic,
4227         .dynamic_state_management_enable = vega20_enable_dpm_tasks,
4228         .dynamic_state_management_disable = vega20_disable_dpm_tasks,
4229         /* power state related */
4230         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
4231         .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
4232         .display_config_changed = vega20_display_configuration_changed_task,
4233         .check_smc_update_required_for_display_configuration =
4234                 vega20_check_smc_update_required_for_display_configuration,
4235         .notify_smc_display_config_after_ps_adjustment =
4236                 vega20_notify_smc_display_config_after_ps_adjustment,
4237         /* export to DAL */
4238         .get_sclk = vega20_dpm_get_sclk,
4239         .get_mclk = vega20_dpm_get_mclk,
4240         .get_dal_power_level = vega20_get_dal_power_level,
4241         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
4242         .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
4243         .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
4244         .display_clock_voltage_request = vega20_display_clock_voltage_request,
4245         .get_performance_level = vega20_get_performance_level,
4246         /* UMD pstate, profile related */
4247         .force_dpm_level = vega20_dpm_force_dpm_level,
4248         .get_power_profile_mode = vega20_get_power_profile_mode,
4249         .set_power_profile_mode = vega20_set_power_profile_mode,
4250         /* od related */
4251         .set_power_limit = vega20_set_power_limit,
4252         .get_sclk_od = vega20_get_sclk_od,
4253         .set_sclk_od = vega20_set_sclk_od,
4254         .get_mclk_od = vega20_get_mclk_od,
4255         .set_mclk_od = vega20_set_mclk_od,
4256         .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
4257         /* for sysfs to retrive/set gfxclk/memclk */
4258         .force_clock_level = vega20_force_clock_level,
4259         .print_clock_levels = vega20_print_clock_levels,
4260         .read_sensor = vega20_read_sensor,
4261         .get_ppfeature_status = vega20_get_ppfeature_status,
4262         .set_ppfeature_status = vega20_set_ppfeature_status,
4263         /* powergate related */
4264         .powergate_uvd = vega20_power_gate_uvd,
4265         .powergate_vce = vega20_power_gate_vce,
4266         /* thermal related */
4267         .start_thermal_controller = vega20_start_thermal_controller,
4268         .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
4269         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
4270         .register_irq_handlers = smu9_register_irq_handlers,
4271         .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
4272         /* fan control related */
4273         .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
4274         .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
4275         .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4276         .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4277         .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4278         .get_fan_control_mode = vega20_get_fan_control_mode,
4279         .set_fan_control_mode = vega20_set_fan_control_mode,
4280         /* smu memory related */
4281         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4282         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4283         /* BACO related */
4284         .get_asic_baco_capability = vega20_baco_get_capability,
4285         .get_asic_baco_state = vega20_baco_get_state,
4286         .set_asic_baco_state = vega20_baco_set_state,
4287         .set_mp1_state = vega20_set_mp1_state,
4288         .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
4289         .set_df_cstate = vega20_set_df_cstate,
4290         .set_xgmi_pstate = vega20_set_xgmi_pstate,
4291 };
4292
4293 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4294 {
4295         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4296         hwmgr->pptable_func = &vega20_pptable_funcs;
4297
4298         return 0;
4299 }