drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_processpptables.h"
  43 #include "vega10_pptable.h"
  44 #include "vega10_thermal.h"
  45 #include "pp_debug.h"
  46 #include "amd_pcie_helpers.h"
  47 #include "ppinterrupt.h"
  48 #include "pp_overdriver.h"
  49 #include "pp_thermal.h"
  50
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53
  54 #define HBM_MEMORY_CHANNEL_WIDTH    128
  55
  56 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  57
  58 #define MEM_FREQ_LOW_LATENCY        25000
  59 #define MEM_FREQ_HIGH_LATENCY       80000
  60 #define MEM_LATENCY_HIGH            245
  61 #define MEM_LATENCY_LOW             35
  62 #define MEM_LATENCY_ERR             0xFFFF
  63
  64 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  65 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  66
  67 //DF_CS_AON0_DramBaseAddress0
  68 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  69 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  71 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  72 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  73 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  74 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  75 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  76 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  77 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  78
  79 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  80
  81 struct vega10_power_state *cast_phw_vega10_power_state(
  82                                   struct pp_hw_power_state *hw_ps)
  83 {
  84         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  85                                 "Invalid Powerstate Type!",
  86                                  return NULL;);
  87
  88         return (struct vega10_power_state *)hw_ps;
  89 }
  90
  91 const struct vega10_power_state *cast_const_phw_vega10_power_state(
  92                                  const struct pp_hw_power_state *hw_ps)
  93 {
  94         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  95                                 "Invalid Powerstate Type!",
  96                                  return NULL;);
  97
  98         return (const struct vega10_power_state *)hw_ps;
  99 }
 100
 101 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 102 {
 103         struct vega10_hwmgr *data = hwmgr->backend;
 104
 105         data->registry_data.sclk_dpm_key_disabled =
 106                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 107         data->registry_data.socclk_dpm_key_disabled =
 108                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 109         data->registry_data.mclk_dpm_key_disabled =
 110                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 111         data->registry_data.pcie_dpm_key_disabled =
 112                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 113
 114         data->registry_data.dcefclk_dpm_key_disabled =
 115                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 116
 117         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 118                 data->registry_data.power_containment_support = 1;
 119                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 120                 data->registry_data.enable_tdc_limit_feature = 1;
 121         }
 122
 123         data->registry_data.clock_stretcher_support =
 124                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 125
 126         data->registry_data.ulv_support =
 127                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 128
 129         data->registry_data.sclk_deep_sleep_support =
 130                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 131
 132         data->registry_data.disable_water_mark = 0;
 133
 134         data->registry_data.fan_control_support = 1;
 135         data->registry_data.thermal_support = 1;
 136         data->registry_data.fw_ctf_enabled = 1;
 137
 138         data->registry_data.avfs_support = 1;
 139         data->registry_data.led_dpm_enabled = 1;
 140
 141         data->registry_data.vr0hot_enabled = 1;
 142         data->registry_data.vr1hot_enabled = 1;
 143         data->registry_data.regulator_hot_gpio_support = 1;
 144
 145         data->registry_data.didt_support = 1;
 146         if (data->registry_data.didt_support) {
 147                 data->registry_data.didt_mode = 6;
 148                 data->registry_data.sq_ramping_support = 1;
 149                 data->registry_data.db_ramping_support = 0;
 150                 data->registry_data.td_ramping_support = 0;
 151                 data->registry_data.tcp_ramping_support = 0;
 152                 data->registry_data.dbr_ramping_support = 0;
 153                 data->registry_data.edc_didt_support = 1;
 154                 data->registry_data.gc_didt_support = 0;
 155                 data->registry_data.psm_didt_support = 0;
 156         }
 157
 158         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 159         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 160         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 161         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 162         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 163         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 164         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 165         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 166         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 167         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 168         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 169         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 170         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 171
 172         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 173         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 174         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 175         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 176 }
 177
 178 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 179 {
 180         struct vega10_hwmgr *data = hwmgr->backend;
 181         struct phm_ppt_v2_information *table_info =
 182                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 183         struct amdgpu_device *adev = hwmgr->adev;
 184
 185         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 186                         PHM_PlatformCaps_SclkDeepSleep);
 187
 188         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 189                         PHM_PlatformCaps_DynamicPatchPowerState);
 190
 191         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 192                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 193                                 PHM_PlatformCaps_ControlVDDCI);
 194
 195         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 197
 198         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 199                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 200                                 PHM_PlatformCaps_UVDPowerGating);
 201
 202         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 203                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 204                                 PHM_PlatformCaps_VCEPowerGating);
 205
 206         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 207                         PHM_PlatformCaps_UnTabledHardwareInterface);
 208
 209         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 210                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 211
 212         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 213                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 214
 215         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 216                                 PHM_PlatformCaps_DynamicPowerManagement);
 217
 218         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 219                         PHM_PlatformCaps_SMC);
 220
 221         /* power tune caps */
 222         /* assume disabled */
 223         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_PowerContainment);
 225         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_DiDtSupport);
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_SQRamping);
 229         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 230                         PHM_PlatformCaps_DBRamping);
 231         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_TDRamping);
 233         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_TCPRamping);
 235         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 236                         PHM_PlatformCaps_DBRRamping);
 237         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 238                         PHM_PlatformCaps_DiDtEDCEnable);
 239         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 240                         PHM_PlatformCaps_GCEDC);
 241         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 242                         PHM_PlatformCaps_PSM);
 243
 244         if (data->registry_data.didt_support) {
 245                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 246                 if (data->registry_data.sq_ramping_support)
 247                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 248                 if (data->registry_data.db_ramping_support)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 250                 if (data->registry_data.td_ramping_support)
 251                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 252                 if (data->registry_data.tcp_ramping_support)
 253                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 254                 if (data->registry_data.dbr_ramping_support)
 255                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 256                 if (data->registry_data.edc_didt_support)
 257                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 258                 if (data->registry_data.gc_didt_support)
 259                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 260                 if (data->registry_data.psm_didt_support)
 261                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 262         }
 263
 264         if (data->registry_data.power_containment_support)
 265                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 266                                 PHM_PlatformCaps_PowerContainment);
 267         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                         PHM_PlatformCaps_CAC);
 269
 270         if (table_info->tdp_table->usClockStretchAmount &&
 271                         data->registry_data.clock_stretcher_support)
 272                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 273                                 PHM_PlatformCaps_ClockStretcher);
 274
 275         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 276                         PHM_PlatformCaps_RegulatorHot);
 277         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 278                         PHM_PlatformCaps_AutomaticDCTransition);
 279
 280         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 281                         PHM_PlatformCaps_UVDDPM);
 282         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_VCEDPM);
 284
 285         return 0;
 286 }
 287
 288 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 289 {
 290         struct vega10_hwmgr *data = hwmgr->backend;
 291         struct phm_ppt_v2_information *table_info =
 292                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 293         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 294         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 295         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 296         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 297         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 298         uint32_t i;
 299
 300         od_lookup_table = &odn_table->vddc_lookup_table;
 301         vddc_lookup_table = table_info->vddc_lookup_table;
 302
 303         for (i = 0; i < vddc_lookup_table->count; i++)
 304                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 305
 306         od_lookup_table->count = vddc_lookup_table->count;
 307
 308         dep_table[0] = table_info->vdd_dep_on_sclk;
 309         dep_table[1] = table_info->vdd_dep_on_mclk;
 310         dep_table[2] = table_info->vdd_dep_on_socclk;
 311         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 312         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 313         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 314
 315         for (i = 0; i < 3; i++)
 316                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 317
 318         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 319                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 320         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 321                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 322
 323         i = od_table[2]->count - 1;
 324         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock;
 325         od_table[2]->entries[i].vddc = odn_table->max_vddc;
 326
 327         return 0;
 328 }
 329
 330 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 331 {
 332         struct vega10_hwmgr *data = hwmgr->backend;
 333         int i;
 334         uint32_t sub_vendor_id, hw_revision;
 335         struct amdgpu_device *adev = hwmgr->adev;
 336
 337         vega10_initialize_power_tune_defaults(hwmgr);
 338
 339         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 340                 data->smu_features[i].smu_feature_id = 0xffff;
 341                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 342                 data->smu_features[i].enabled = false;
 343                 data->smu_features[i].supported = false;
 344         }
 345
 346         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 347                         FEATURE_DPM_PREFETCHER_BIT;
 348         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 349                         FEATURE_DPM_GFXCLK_BIT;
 350         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 351                         FEATURE_DPM_UCLK_BIT;
 352         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 353                         FEATURE_DPM_SOCCLK_BIT;
 354         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 355                         FEATURE_DPM_UVD_BIT;
 356         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 357                         FEATURE_DPM_VCE_BIT;
 358         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 359                         FEATURE_DPM_MP0CLK_BIT;
 360         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 361                         FEATURE_DPM_LINK_BIT;
 362         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 363                         FEATURE_DPM_DCEFCLK_BIT;
 364         data->smu_features[GNLD_ULV].smu_feature_id =
 365                         FEATURE_ULV_BIT;
 366         data->smu_features[GNLD_AVFS].smu_feature_id =
 367                         FEATURE_AVFS_BIT;
 368         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 369                         FEATURE_DS_GFXCLK_BIT;
 370         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 371                         FEATURE_DS_SOCCLK_BIT;
 372         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 373                         FEATURE_DS_LCLK_BIT;
 374         data->smu_features[GNLD_PPT].smu_feature_id =
 375                         FEATURE_PPT_BIT;
 376         data->smu_features[GNLD_TDC].smu_feature_id =
 377                         FEATURE_TDC_BIT;
 378         data->smu_features[GNLD_THERMAL].smu_feature_id =
 379                         FEATURE_THERMAL_BIT;
 380         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 381                         FEATURE_GFX_PER_CU_CG_BIT;
 382         data->smu_features[GNLD_RM].smu_feature_id =
 383                         FEATURE_RM_BIT;
 384         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 385                         FEATURE_DS_DCEFCLK_BIT;
 386         data->smu_features[GNLD_ACDC].smu_feature_id =
 387                         FEATURE_ACDC_BIT;
 388         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 389                         FEATURE_VR0HOT_BIT;
 390         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 391                         FEATURE_VR1HOT_BIT;
 392         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 393                         FEATURE_FW_CTF_BIT;
 394         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 395                         FEATURE_LED_DISPLAY_BIT;
 396         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 397                         FEATURE_FAN_CONTROL_BIT;
 398         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 399         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 400         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 401
 402         if (!data->registry_data.prefetcher_dpm_key_disabled)
 403                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 404
 405         if (!data->registry_data.sclk_dpm_key_disabled)
 406                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 407
 408         if (!data->registry_data.mclk_dpm_key_disabled)
 409                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 410
 411         if (!data->registry_data.socclk_dpm_key_disabled)
 412                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 413
 414         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 415                 data->smu_features[GNLD_DPM_UVD].supported = true;
 416
 417         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 418                 data->smu_features[GNLD_DPM_VCE].supported = true;
 419
 420         if (!data->registry_data.pcie_dpm_key_disabled)
 421                 data->smu_features[GNLD_DPM_LINK].supported = true;
 422
 423         if (!data->registry_data.dcefclk_dpm_key_disabled)
 424                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 425
 426         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 427             data->registry_data.sclk_deep_sleep_support) {
 428                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 429                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 430                 data->smu_features[GNLD_DS_LCLK].supported = true;
 431                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 432         }
 433
 434         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 435                 data->smu_features[GNLD_PPT].supported = true;
 436
 437         if (data->registry_data.enable_tdc_limit_feature)
 438                 data->smu_features[GNLD_TDC].supported = true;
 439
 440         if (data->registry_data.thermal_support)
 441                 data->smu_features[GNLD_THERMAL].supported = true;
 442
 443         if (data->registry_data.fan_control_support)
 444                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 445
 446         if (data->registry_data.fw_ctf_enabled)
 447                 data->smu_features[GNLD_FW_CTF].supported = true;
 448
 449         if (data->registry_data.avfs_support)
 450                 data->smu_features[GNLD_AVFS].supported = true;
 451
 452         if (data->registry_data.led_dpm_enabled)
 453                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 454
 455         if (data->registry_data.vr1hot_enabled)
 456                 data->smu_features[GNLD_VR1HOT].supported = true;
 457
 458         if (data->registry_data.vr0hot_enabled)
 459                 data->smu_features[GNLD_VR0HOT].supported = true;
 460
 461         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 462         hwmgr->smu_version = smum_get_argument(hwmgr);
 463                 /* ACG firmware has major version 5 */
 464         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 465                 data->smu_features[GNLD_ACG].supported = true;
 466         if (data->registry_data.didt_support)
 467                 data->smu_features[GNLD_DIDT].supported = true;
 468
 469         hw_revision = adev->pdev->revision;
 470         sub_vendor_id = adev->pdev->subsystem_vendor;
 471
 472         if ((hwmgr->chip_id == 0x6862 ||
 473                 hwmgr->chip_id == 0x6861 ||
 474                 hwmgr->chip_id == 0x6868) &&
 475                 (hw_revision == 0) &&
 476                 (sub_vendor_id != 0x1002))
 477                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 478 }
 479
 480 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 481 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 482         phm_ppt_v1_voltage_lookup_table *lookup_table,
 483         uint16_t virtual_voltage_id, int32_t *socclk)
 484 {
 485         uint8_t entry_id;
 486         uint8_t voltage_id;
 487         struct phm_ppt_v2_information *table_info =
 488                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 489
 490         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 491                         "Lookup table is empty",
 492                         return -EINVAL);
 493
 494         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 495         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 496                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 497                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 498                         break;
 499         }
 500
 501         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 502                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 503                         return -EINVAL);
 504
 505         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 506
 507         return 0;
 508 }
 509
 510 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 511 /**
 512 * Get Leakage VDDC based on leakage ID.
 513 *
 514 * @param    hwmgr  the address of the powerplay hardware manager.
 515 * @return   always 0.
 516 */
 517 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 518 {
 519         struct vega10_hwmgr *data = hwmgr->backend;
 520         uint16_t vv_id;
 521         uint32_t vddc = 0;
 522         uint16_t i, j;
 523         uint32_t sclk = 0;
 524         struct phm_ppt_v2_information *table_info =
 525                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 526         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 527                         table_info->vdd_dep_on_socclk;
 528         int result;
 529
 530         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 531                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 532
 533                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 534                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 535                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 536                                 for (j = 1; j < socclk_table->count; j++) {
 537                                         if (socclk_table->entries[j].clk == sclk &&
 538                                                         socclk_table->entries[j].cks_enable == 0) {
 539                                                 sclk += 5000;
 540                                                 break;
 541                                         }
 542                                 }
 543                         }
 544
 545                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 546                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 547                                         "Error retrieving EVV voltage value!",
 548                                         continue);
 549
 550
 551                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 552                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 553                                         "Invalid VDDC value", result = -EINVAL;);
 554
 555                         /* the voltage should not be zero nor equal to leakage ID */
 556                         if (vddc != 0 && vddc != vv_id) {
 557                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 558                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 559                                 data->vddc_leakage.count++;
 560                         }
 561                 }
 562         }
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * Change virtual leakage voltage to actual value.
 569  *
 570  * @param     hwmgr  the address of the powerplay hardware manager.
 571  * @param     pointer to changing voltage
 572  * @param     pointer to leakage table
 573  */
 574 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 575                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 576 {
 577         uint32_t index;
 578
 579         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 580         for (index = 0; index < leakage_table->count; index++) {
 581                 /* if this voltage matches a leakage voltage ID */
 582                 /* patch with actual leakage voltage */
 583                 if (leakage_table->leakage_id[index] == *voltage) {
 584                         *voltage = leakage_table->actual_voltage[index];
 585                         break;
 586                 }
 587         }
 588
 589         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 590                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 591 }
 592
 593 /**
 594 * Patch voltage lookup table by EVV leakages.
 595 *
 596 * @param     hwmgr  the address of the powerplay hardware manager.
 597 * @param     pointer to voltage lookup table
 598 * @param     pointer to leakage table
 599 * @return     always 0
 600 */
 601 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 602                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 603                 struct vega10_leakage_voltage *leakage_table)
 604 {
 605         uint32_t i;
 606
 607         for (i = 0; i < lookup_table->count; i++)
 608                 vega10_patch_with_vdd_leakage(hwmgr,
 609                                 &lookup_table->entries[i].us_vdd, leakage_table);
 610
 611         return 0;
 612 }
 613
 614 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 615                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 616                 uint16_t *vddc)
 617 {
 618         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 619
 620         return 0;
 621 }
 622 #endif
 623
 624 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 625                 struct pp_hwmgr *hwmgr)
 626 {
 627         uint8_t entry_id, voltage_id;
 628         unsigned i;
 629         struct phm_ppt_v2_information *table_info =
 630                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 631         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 632                         table_info->mm_dep_table;
 633         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 634                         table_info->vdd_dep_on_mclk;
 635
 636         for (i = 0; i < 6; i++) {
 637                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 638                 switch (i) {
 639                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 640                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 641                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 642                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 643                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 644                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 645                 }
 646
 647                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 648                         voltage_id = vdt->entries[entry_id].vddInd;
 649                         vdt->entries[entry_id].vddc =
 650                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 651                 }
 652         }
 653
 654         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 655                 voltage_id = mm_table->entries[entry_id].vddcInd;
 656                 mm_table->entries[entry_id].vddc =
 657                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 658         }
 659
 660         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 661                 voltage_id = mclk_table->entries[entry_id].vddInd;
 662                 mclk_table->entries[entry_id].vddc =
 663                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 664                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 665                 mclk_table->entries[entry_id].vddci =
 666                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 667                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 668                 mclk_table->entries[entry_id].mvdd =
 669                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 670         }
 671
 672
 673         return 0;
 674
 675 }
 676
 677 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 678                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 679 {
 680         uint32_t table_size, i, j;
 681         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 682
 683         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 684                 "Lookup table is empty", return -EINVAL);
 685
 686         table_size = lookup_table->count;
 687
 688         /* Sorting voltages */
 689         for (i = 0; i < table_size - 1; i++) {
 690                 for (j = i + 1; j > 0; j--) {
 691                         if (lookup_table->entries[j].us_vdd <
 692                                         lookup_table->entries[j - 1].us_vdd) {
 693                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 694                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 695                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 696                         }
 697                 }
 698         }
 699
 700         return 0;
 701 }
 702
 703 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 704 {
 705         int result = 0;
 706         int tmp_result;
 707         struct phm_ppt_v2_information *table_info =
 708                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 709 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 710         struct vega10_hwmgr *data = hwmgr->backend;
 711
 712         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 713                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 714         if (tmp_result)
 715                 result = tmp_result;
 716
 717         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 718                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 719         if (tmp_result)
 720                 result = tmp_result;
 721 #endif
 722
 723         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 724         if (tmp_result)
 725                 result = tmp_result;
 726
 727         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 728         if (tmp_result)
 729                 result = tmp_result;
 730
 731         return result;
 732 }
 733
 734 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 735 {
 736         struct phm_ppt_v2_information *table_info =
 737                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 738         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 739                         table_info->vdd_dep_on_socclk;
 740         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 741                         table_info->vdd_dep_on_mclk;
 742
 743         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 744                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 745         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 746                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 747
 748         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 749                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 750         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 751                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 752
 753         table_info->max_clock_voltage_on_ac.sclk =
 754                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 755         table_info->max_clock_voltage_on_ac.mclk =
 756                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 757         table_info->max_clock_voltage_on_ac.vddc =
 758                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 759         table_info->max_clock_voltage_on_ac.vddci =
 760                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 761
 762         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 763                 table_info->max_clock_voltage_on_ac.sclk;
 764         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 765                 table_info->max_clock_voltage_on_ac.mclk;
 766         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 767                 table_info->max_clock_voltage_on_ac.vddc;
 768         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 769                 table_info->max_clock_voltage_on_ac.vddci;
 770
 771         return 0;
 772 }
 773
 774 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 775 {
 776         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 777         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 778
 779         kfree(hwmgr->backend);
 780         hwmgr->backend = NULL;
 781
 782         return 0;
 783 }
 784
 785 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 786 {
 787         int result = 0;
 788         struct vega10_hwmgr *data;
 789         uint32_t config_telemetry = 0;
 790         struct pp_atomfwctrl_voltage_table vol_table;
 791         struct amdgpu_device *adev = hwmgr->adev;
 792
 793         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 794         if (data == NULL)
 795                 return -ENOMEM;
 796
 797         hwmgr->backend = data;
 798
 799         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
 800         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 801         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 802
 803         vega10_set_default_registry_data(hwmgr);
 804         data->disable_dpm_mask = 0xff;
 805
 806         /* need to set voltage control types before EVV patching */
 807         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 808         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 809         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 810
 811         /* VDDCR_SOC */
 812         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 813                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 814                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 815                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 816                                 &vol_table)) {
 817                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 818                                         (vol_table.telemetry_offset & 0xff);
 819                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 820                 }
 821         } else {
 822                 kfree(hwmgr->backend);
 823                 hwmgr->backend = NULL;
 824                 PP_ASSERT_WITH_CODE(false,
 825                                 "VDDCR_SOC is not SVID2!",
 826                                 return -1);
 827         }
 828
 829         /* MVDDC */
 830         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 831                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 832                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 833                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 834                                 &vol_table)) {
 835                         config_telemetry |=
 836                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 837                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 838                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 839                 }
 840         }
 841
 842          /* VDDCI_MEM */
 843         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 844                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 845                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 846                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 847         }
 848
 849         data->config_telemetry = config_telemetry;
 850
 851         vega10_set_features_platform_caps(hwmgr);
 852
 853         vega10_init_dpm_defaults(hwmgr);
 854
 855 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 856         /* Get leakage voltage based on leakage ID. */
 857         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 858                         "Get EVV Voltage Failed.  Abort Driver loading!",
 859                         return -1);
 860 #endif
 861
 862         /* Patch our voltage dependency table with actual leakage voltage
 863          * We need to perform leakage translation before it's used by other functions
 864          */
 865         vega10_complete_dependency_tables(hwmgr);
 866
 867         /* Parse pptable data read from VBIOS */
 868         vega10_set_private_data_based_on_pptable(hwmgr);
 869
 870         data->is_tlu_enabled = false;
 871
 872         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 873                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 874         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 875         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 876
 877         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 878         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 879         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 880         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 881
 882         data->total_active_cus = adev->gfx.cu_info.number;
 883         /* Setup default Overdrive Fan control settings */
 884         data->odn_fan_table.target_fan_speed =
 885                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 886         data->odn_fan_table.target_temperature =
 887                         hwmgr->thermal_controller.
 888                         advanceFanControlParameters.ucTargetTemperature;
 889         data->odn_fan_table.min_performance_clock =
 890                         hwmgr->thermal_controller.advanceFanControlParameters.
 891                         ulMinFanSCLKAcousticLimit;
 892         data->odn_fan_table.min_fan_limit =
 893                         hwmgr->thermal_controller.
 894                         advanceFanControlParameters.usFanPWMMinLimit *
 895                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 896
 897         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 898                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 899                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 900         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 901                         "Mem Channel Index Exceeded maximum!",
 902                         return -EINVAL);
 903
 904         return result;
 905 }
 906
 907 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 908 {
 909         struct vega10_hwmgr *data = hwmgr->backend;
 910
 911         data->low_sclk_interrupt_threshold = 0;
 912
 913         return 0;
 914 }
 915
 916 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 917 {
 918         struct vega10_hwmgr *data = hwmgr->backend;
 919         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 920
 921         struct pp_atomfwctrl_voltage_table table;
 922         uint8_t i, j;
 923         uint32_t mask = 0;
 924         uint32_t tmp;
 925         int32_t ret = 0;
 926
 927         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 928                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 929
 930         if (!ret) {
 931                 tmp = table.mask_low;
 932                 for (i = 0, j = 0; i < 32; i++) {
 933                         if (tmp & 1) {
 934                                 mask |= (uint32_t)(i << (8 * j));
 935                                 if (++j >= 3)
 936                                         break;
 937                         }
 938                         tmp >>= 1;
 939                 }
 940         }
 941
 942         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 943         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 944         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 945         return 0;
 946 }
 947
 948 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 949 {
 950         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 951                         "Failed to init sclk threshold!",
 952                         return -EINVAL);
 953
 954         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 955                         "Failed to set up led dpm config!",
 956                         return -EINVAL);
 957
 958         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
 959
 960         return 0;
 961 }
 962
 963 /**
 964 * Remove repeated voltage values and create table with unique values.
 965 *
 966 * @param    hwmgr  the address of the powerplay hardware manager.
 967 * @param    vol_table  the pointer to changing voltage table
 968 * @return    0 in success
 969 */
 970
 971 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
 972                 struct pp_atomfwctrl_voltage_table *vol_table)
 973 {
 974         uint32_t i, j;
 975         uint16_t vvalue;
 976         bool found = false;
 977         struct pp_atomfwctrl_voltage_table *table;
 978
 979         PP_ASSERT_WITH_CODE(vol_table,
 980                         "Voltage Table empty.", return -EINVAL);
 981         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
 982                         GFP_KERNEL);
 983
 984         if (!table)
 985                 return -ENOMEM;
 986
 987         table->mask_low = vol_table->mask_low;
 988         table->phase_delay = vol_table->phase_delay;
 989
 990         for (i = 0; i < vol_table->count; i++) {
 991                 vvalue = vol_table->entries[i].value;
 992                 found = false;
 993
 994                 for (j = 0; j < table->count; j++) {
 995                         if (vvalue == table->entries[j].value) {
 996                                 found = true;
 997                                 break;
 998                         }
 999                 }
1000
1001                 if (!found) {
1002                         table->entries[table->count].value = vvalue;
1003                         table->entries[table->count].smio_low =
1004                                         vol_table->entries[i].smio_low;
1005                         table->count++;
1006                 }
1007         }
1008
1009         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1010         kfree(table);
1011
1012         return 0;
1013 }
1014
1015 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1016                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1017                 struct pp_atomfwctrl_voltage_table *vol_table)
1018 {
1019         int i;
1020
1021         PP_ASSERT_WITH_CODE(dep_table->count,
1022                         "Voltage Dependency Table empty.",
1023                         return -EINVAL);
1024
1025         vol_table->mask_low = 0;
1026         vol_table->phase_delay = 0;
1027         vol_table->count = dep_table->count;
1028
1029         for (i = 0; i < vol_table->count; i++) {
1030                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1031                 vol_table->entries[i].smio_low = 0;
1032         }
1033
1034         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1035                         vol_table),
1036                         "Failed to trim MVDD Table!",
1037                         return -1);
1038
1039         return 0;
1040 }
1041
1042 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1043                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1044                 struct pp_atomfwctrl_voltage_table *vol_table)
1045 {
1046         uint32_t i;
1047
1048         PP_ASSERT_WITH_CODE(dep_table->count,
1049                         "Voltage Dependency Table empty.",
1050                         return -EINVAL);
1051
1052         vol_table->mask_low = 0;
1053         vol_table->phase_delay = 0;
1054         vol_table->count = dep_table->count;
1055
1056         for (i = 0; i < dep_table->count; i++) {
1057                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1058                 vol_table->entries[i].smio_low = 0;
1059         }
1060
1061         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1062                         "Failed to trim VDDCI table.",
1063                         return -1);
1064
1065         return 0;
1066 }
1067
1068 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1069                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1070                 struct pp_atomfwctrl_voltage_table *vol_table)
1071 {
1072         int i;
1073
1074         PP_ASSERT_WITH_CODE(dep_table->count,
1075                         "Voltage Dependency Table empty.",
1076                         return -EINVAL);
1077
1078         vol_table->mask_low = 0;
1079         vol_table->phase_delay = 0;
1080         vol_table->count = dep_table->count;
1081
1082         for (i = 0; i < vol_table->count; i++) {
1083                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1084                 vol_table->entries[i].smio_low = 0;
1085         }
1086
1087         return 0;
1088 }
1089
1090 /* ---- Voltage Tables ----
1091  * If the voltage table would be bigger than
1092  * what will fit into the state table on
1093  * the SMC keep only the higher entries.
1094  */
1095 static void vega10_trim_voltage_table_to_fit_state_table(
1096                 struct pp_hwmgr *hwmgr,
1097                 uint32_t max_vol_steps,
1098                 struct pp_atomfwctrl_voltage_table *vol_table)
1099 {
1100         unsigned int i, diff;
1101
1102         if (vol_table->count <= max_vol_steps)
1103                 return;
1104
1105         diff = vol_table->count - max_vol_steps;
1106
1107         for (i = 0; i < max_vol_steps; i++)
1108                 vol_table->entries[i] = vol_table->entries[i + diff];
1109
1110         vol_table->count = max_vol_steps;
1111 }
1112
1113 /**
1114 * Create Voltage Tables.
1115 *
1116 * @param    hwmgr  the address of the powerplay hardware manager.
1117 * @return   always 0
1118 */
1119 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1120 {
1121         struct vega10_hwmgr *data = hwmgr->backend;
1122         struct phm_ppt_v2_information *table_info =
1123                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1124         int result;
1125
1126         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1127                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1128                 result = vega10_get_mvdd_voltage_table(hwmgr,
1129                                 table_info->vdd_dep_on_mclk,
1130                                 &(data->mvdd_voltage_table));
1131                 PP_ASSERT_WITH_CODE(!result,
1132                                 "Failed to retrieve MVDDC table!",
1133                                 return result);
1134         }
1135
1136         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1137                 result = vega10_get_vddci_voltage_table(hwmgr,
1138                                 table_info->vdd_dep_on_mclk,
1139                                 &(data->vddci_voltage_table));
1140                 PP_ASSERT_WITH_CODE(!result,
1141                                 "Failed to retrieve VDDCI_MEM table!",
1142                                 return result);
1143         }
1144
1145         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1146                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1147                 result = vega10_get_vdd_voltage_table(hwmgr,
1148                                 table_info->vdd_dep_on_sclk,
1149                                 &(data->vddc_voltage_table));
1150                 PP_ASSERT_WITH_CODE(!result,
1151                                 "Failed to retrieve VDDCR_SOC table!",
1152                                 return result);
1153         }
1154
1155         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1156                         "Too many voltage values for VDDC. Trimming to fit state table.",
1157                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1158                                         16, &(data->vddc_voltage_table)));
1159
1160         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1161                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1162                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1163                                         16, &(data->vddci_voltage_table)));
1164
1165         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1166                         "Too many voltage values for MVDD. Trimming to fit state table.",
1167                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1168                                         16, &(data->mvdd_voltage_table)));
1169
1170
1171         return 0;
1172 }
1173
1174 /*
1175  * @fn vega10_init_dpm_state
1176  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1177  *
1178  * @param    dpm_state - the address of the DPM Table to initiailize.
1179  * @return   None.
1180  */
1181 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1182 {
1183         dpm_state->soft_min_level = 0xff;
1184         dpm_state->soft_max_level = 0xff;
1185         dpm_state->hard_min_level = 0xff;
1186         dpm_state->hard_max_level = 0xff;
1187 }
1188
1189 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1190                 struct vega10_single_dpm_table *dpm_table,
1191                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1192 {
1193         int i;
1194
1195         dpm_table->count = 0;
1196
1197         for (i = 0; i < dep_table->count; i++) {
1198                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1199                                 dep_table->entries[i].clk) {
1200                         dpm_table->dpm_levels[dpm_table->count].value =
1201                                         dep_table->entries[i].clk;
1202                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1203                         dpm_table->count++;
1204                 }
1205         }
1206 }
1207 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1208 {
1209         struct vega10_hwmgr *data = hwmgr->backend;
1210         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1211         struct phm_ppt_v2_information *table_info =
1212                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1213         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1214                         table_info->pcie_table;
1215         uint32_t i;
1216
1217         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1218                         "Incorrect number of PCIE States from VBIOS!",
1219                         return -1);
1220
1221         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1222                 if (data->registry_data.pcieSpeedOverride)
1223                         pcie_table->pcie_gen[i] =
1224                                         data->registry_data.pcieSpeedOverride;
1225                 else
1226                         pcie_table->pcie_gen[i] =
1227                                         bios_pcie_table->entries[i].gen_speed;
1228
1229                 if (data->registry_data.pcieLaneOverride)
1230                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1231                                         data->registry_data.pcieLaneOverride);
1232                 else
1233                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1234                                                         bios_pcie_table->entries[i].lane_width);
1235                 if (data->registry_data.pcieClockOverride)
1236                         pcie_table->lclk[i] =
1237                                         data->registry_data.pcieClockOverride;
1238                 else
1239                         pcie_table->lclk[i] =
1240                                         bios_pcie_table->entries[i].pcie_sclk;
1241         }
1242
1243         pcie_table->count = NUM_LINK_LEVELS;
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * This function is to initialize all DPM state tables
1250  * for SMU based on the dependency table.
1251  * Dynamic state patching function will then trim these
1252  * state tables to the allowed range based
1253  * on the power policy or external client requests,
1254  * such as UVD request, etc.
1255  */
1256 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1257 {
1258         struct vega10_hwmgr *data = hwmgr->backend;
1259         struct phm_ppt_v2_information *table_info =
1260                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1261         struct vega10_single_dpm_table *dpm_table;
1262         uint32_t i;
1263
1264         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1265                         table_info->vdd_dep_on_socclk;
1266         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1267                         table_info->vdd_dep_on_sclk;
1268         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1269                         table_info->vdd_dep_on_mclk;
1270         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1271                         table_info->mm_dep_table;
1272         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1273                         table_info->vdd_dep_on_dcefclk;
1274         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1275                         table_info->vdd_dep_on_pixclk;
1276         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1277                         table_info->vdd_dep_on_dispclk;
1278         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1279                         table_info->vdd_dep_on_phyclk;
1280
1281         PP_ASSERT_WITH_CODE(dep_soc_table,
1282                         "SOCCLK dependency table is missing. This table is mandatory",
1283                         return -EINVAL);
1284         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1285                         "SOCCLK dependency table is empty. This table is mandatory",
1286                         return -EINVAL);
1287
1288         PP_ASSERT_WITH_CODE(dep_gfx_table,
1289                         "GFXCLK dependency table is missing. This table is mandatory",
1290                         return -EINVAL);
1291         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1292                         "GFXCLK dependency table is empty. This table is mandatory",
1293                         return -EINVAL);
1294
1295         PP_ASSERT_WITH_CODE(dep_mclk_table,
1296                         "MCLK dependency table is missing. This table is mandatory",
1297                         return -EINVAL);
1298         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1299                         "MCLK dependency table has to have is missing. This table is mandatory",
1300                         return -EINVAL);
1301
1302         /* Initialize Sclk DPM table based on allow Sclk values */
1303         dpm_table = &(data->dpm_table.soc_table);
1304         vega10_setup_default_single_dpm_table(hwmgr,
1305                         dpm_table,
1306                         dep_soc_table);
1307
1308         vega10_init_dpm_state(&(dpm_table->dpm_state));
1309
1310         dpm_table = &(data->dpm_table.gfx_table);
1311         vega10_setup_default_single_dpm_table(hwmgr,
1312                         dpm_table,
1313                         dep_gfx_table);
1314         vega10_init_dpm_state(&(dpm_table->dpm_state));
1315
1316         /* Initialize Mclk DPM table based on allow Mclk values */
1317         data->dpm_table.mem_table.count = 0;
1318         dpm_table = &(data->dpm_table.mem_table);
1319         vega10_setup_default_single_dpm_table(hwmgr,
1320                         dpm_table,
1321                         dep_mclk_table);
1322         vega10_init_dpm_state(&(dpm_table->dpm_state));
1323
1324         data->dpm_table.eclk_table.count = 0;
1325         dpm_table = &(data->dpm_table.eclk_table);
1326         for (i = 0; i < dep_mm_table->count; i++) {
1327                 if (i == 0 || dpm_table->dpm_levels
1328                                 [dpm_table->count - 1].value <=
1329                                                 dep_mm_table->entries[i].eclk) {
1330                         dpm_table->dpm_levels[dpm_table->count].value =
1331                                         dep_mm_table->entries[i].eclk;
1332                         dpm_table->dpm_levels[dpm_table->count].enabled =
1333                                         (i == 0) ? true : false;
1334                         dpm_table->count++;
1335                 }
1336         }
1337         vega10_init_dpm_state(&(dpm_table->dpm_state));
1338
1339         data->dpm_table.vclk_table.count = 0;
1340         data->dpm_table.dclk_table.count = 0;
1341         dpm_table = &(data->dpm_table.vclk_table);
1342         for (i = 0; i < dep_mm_table->count; i++) {
1343                 if (i == 0 || dpm_table->dpm_levels
1344                                 [dpm_table->count - 1].value <=
1345                                                 dep_mm_table->entries[i].vclk) {
1346                         dpm_table->dpm_levels[dpm_table->count].value =
1347                                         dep_mm_table->entries[i].vclk;
1348                         dpm_table->dpm_levels[dpm_table->count].enabled =
1349                                         (i == 0) ? true : false;
1350                         dpm_table->count++;
1351                 }
1352         }
1353         vega10_init_dpm_state(&(dpm_table->dpm_state));
1354
1355         dpm_table = &(data->dpm_table.dclk_table);
1356         for (i = 0; i < dep_mm_table->count; i++) {
1357                 if (i == 0 || dpm_table->dpm_levels
1358                                 [dpm_table->count - 1].value <=
1359                                                 dep_mm_table->entries[i].dclk) {
1360                         dpm_table->dpm_levels[dpm_table->count].value =
1361                                         dep_mm_table->entries[i].dclk;
1362                         dpm_table->dpm_levels[dpm_table->count].enabled =
1363                                         (i == 0) ? true : false;
1364                         dpm_table->count++;
1365                 }
1366         }
1367         vega10_init_dpm_state(&(dpm_table->dpm_state));
1368
1369         /* Assume there is no headless Vega10 for now */
1370         dpm_table = &(data->dpm_table.dcef_table);
1371         vega10_setup_default_single_dpm_table(hwmgr,
1372                         dpm_table,
1373                         dep_dcef_table);
1374
1375         vega10_init_dpm_state(&(dpm_table->dpm_state));
1376
1377         dpm_table = &(data->dpm_table.pixel_table);
1378         vega10_setup_default_single_dpm_table(hwmgr,
1379                         dpm_table,
1380                         dep_pix_table);
1381
1382         vega10_init_dpm_state(&(dpm_table->dpm_state));
1383
1384         dpm_table = &(data->dpm_table.display_table);
1385         vega10_setup_default_single_dpm_table(hwmgr,
1386                         dpm_table,
1387                         dep_disp_table);
1388
1389         vega10_init_dpm_state(&(dpm_table->dpm_state));
1390
1391         dpm_table = &(data->dpm_table.phy_table);
1392         vega10_setup_default_single_dpm_table(hwmgr,
1393                         dpm_table,
1394                         dep_phy_table);
1395
1396         vega10_init_dpm_state(&(dpm_table->dpm_state));
1397
1398         vega10_setup_default_pcie_table(hwmgr);
1399
1400         /* save a copy of the default DPM table */
1401         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1402                         sizeof(struct vega10_dpm_table));
1403
1404         return 0;
1405 }
1406
1407 /*
1408  * @fn vega10_populate_ulv_state
1409  * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1410  *
1411  * @param    hwmgr - the address of the hardware manager.
1412  * @return   Always 0.
1413  */
1414 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1415 {
1416         struct vega10_hwmgr *data = hwmgr->backend;
1417         struct phm_ppt_v2_information *table_info =
1418                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1419
1420         data->smc_state_table.pp_table.UlvOffsetVid =
1421                         (uint8_t)table_info->us_ulv_voltage_offset;
1422
1423         data->smc_state_table.pp_table.UlvSmnclkDid =
1424                         (uint8_t)(table_info->us_ulv_smnclk_did);
1425         data->smc_state_table.pp_table.UlvMp1clkDid =
1426                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1427         data->smc_state_table.pp_table.UlvGfxclkBypass =
1428                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1429         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1430                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1431         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1432                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1433
1434         return 0;
1435 }
1436
1437 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1438                 uint32_t lclock, uint8_t *curr_lclk_did)
1439 {
1440         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1441
1442         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1443                         hwmgr,
1444                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1445                         lclock, &dividers),
1446                         "Failed to get LCLK clock settings from VBIOS!",
1447                         return -1);
1448
1449         *curr_lclk_did = dividers.ulDid;
1450
1451         return 0;
1452 }
1453
1454 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1455 {
1456         int result = -1;
1457         struct vega10_hwmgr *data = hwmgr->backend;
1458         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1459         struct vega10_pcie_table *pcie_table =
1460                         &(data->dpm_table.pcie_table);
1461         uint32_t i, j;
1462
1463         for (i = 0; i < pcie_table->count; i++) {
1464                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1465                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1466
1467                 result = vega10_populate_single_lclk_level(hwmgr,
1468                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1469                 if (result) {
1470                         pr_info("Populate LClock Level %d Failed!\n", i);
1471                         return result;
1472                 }
1473         }
1474
1475         j = i - 1;
1476         while (i < NUM_LINK_LEVELS) {
1477                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1478                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1479
1480                 result = vega10_populate_single_lclk_level(hwmgr,
1481                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1482                 if (result) {
1483                         pr_info("Populate LClock Level %d Failed!\n", i);
1484                         return result;
1485                 }
1486                 i++;
1487         }
1488
1489         return result;
1490 }
1491
1492 /**
1493 * Populates single SMC GFXSCLK structure using the provided engine clock
1494 *
1495 * @param    hwmgr      the address of the hardware manager
1496 * @param    gfx_clock  the GFX clock to use to populate the structure.
1497 * @param    current_gfxclk_level  location in PPTable for the SMC GFXCLK structure.
1498 */
1499
1500 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1501                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1502                 uint32_t *acg_freq)
1503 {
1504         struct phm_ppt_v2_information *table_info =
1505                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1506         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1507         struct vega10_hwmgr *data = hwmgr->backend;
1508         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1509         uint32_t gfx_max_clock =
1510                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1511         uint32_t i = 0;
1512
1513         if (hwmgr->od_enabled)
1514                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1515                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1516         else
1517                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1518
1519         PP_ASSERT_WITH_CODE(dep_on_sclk,
1520                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1521                         return -EINVAL);
1522
1523         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1524                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1525         else {
1526                 for (i = 0; i < dep_on_sclk->count; i++) {
1527                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1528                                 break;
1529                 }
1530                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1531                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1532                                 return -EINVAL);
1533         }
1534
1535         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1536                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1537                         gfx_clock, &dividers),
1538                         "Failed to get GFX Clock settings from VBIOS!",
1539                         return -EINVAL);
1540
1541         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1542         current_gfxclk_level->FbMult =
1543                         cpu_to_le32(dividers.ulPll_fb_mult);
1544         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1545         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1546         current_gfxclk_level->SsFbMult =
1547                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1548         current_gfxclk_level->SsSlewFrac =
1549                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1550         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1551
1552         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1553
1554         return 0;
1555 }
1556
1557 /**
1558  * @brief Populates single SMC SOCCLK structure using the provided clock.
1559  *
1560  * @param    hwmgr - the address of the hardware manager.
1561  * @param    soc_clock - the SOC clock to use to populate the structure.
1562  * @param    current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1563  * @return   0 on success..
1564  */
1565 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1566                 uint32_t soc_clock, uint8_t *current_soc_did,
1567                 uint8_t *current_vol_index)
1568 {
1569         struct vega10_hwmgr *data = hwmgr->backend;
1570         struct phm_ppt_v2_information *table_info =
1571                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1572         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1573         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1574         uint32_t i;
1575
1576         if (hwmgr->od_enabled) {
1577                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1578                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1579                 for (i = 0; i < dep_on_soc->count; i++) {
1580                         if (dep_on_soc->entries[i].clk >= soc_clock)
1581                                 break;
1582                 }
1583         } else {
1584                 dep_on_soc = table_info->vdd_dep_on_socclk;
1585                 for (i = 0; i < dep_on_soc->count; i++) {
1586                         if (dep_on_soc->entries[i].clk == soc_clock)
1587                                 break;
1588                 }
1589         }
1590
1591         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1592                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1593                         return -EINVAL);
1594
1595         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1596                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1597                         soc_clock, &dividers),
1598                         "Failed to get SOC Clock settings from VBIOS!",
1599                         return -EINVAL);
1600
1601         *current_soc_did = (uint8_t)dividers.ulDid;
1602         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1603         return 0;
1604 }
1605
1606 /**
1607 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1608 *
1609 * @param    hwmgr      the address of the hardware manager
1610 */
1611 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1612 {
1613         struct vega10_hwmgr *data = hwmgr->backend;
1614         struct phm_ppt_v2_information *table_info =
1615                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1616         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1617         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1618         int result = 0;
1619         uint32_t i, j;
1620
1621         for (i = 0; i < dpm_table->count; i++) {
1622                 result = vega10_populate_single_gfx_level(hwmgr,
1623                                 dpm_table->dpm_levels[i].value,
1624                                 &(pp_table->GfxclkLevel[i]),
1625                                 &(pp_table->AcgFreqTable[i]));
1626                 if (result)
1627                         return result;
1628         }
1629
1630         j = i - 1;
1631         while (i < NUM_GFXCLK_DPM_LEVELS) {
1632                 result = vega10_populate_single_gfx_level(hwmgr,
1633                                 dpm_table->dpm_levels[j].value,
1634                                 &(pp_table->GfxclkLevel[i]),
1635                                 &(pp_table->AcgFreqTable[i]));
1636                 if (result)
1637                         return result;
1638                 i++;
1639         }
1640
1641         pp_table->GfxclkSlewRate =
1642                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1643
1644         dpm_table = &(data->dpm_table.soc_table);
1645         for (i = 0; i < dpm_table->count; i++) {
1646                 result = vega10_populate_single_soc_level(hwmgr,
1647                                 dpm_table->dpm_levels[i].value,
1648                                 &(pp_table->SocclkDid[i]),
1649                                 &(pp_table->SocDpmVoltageIndex[i]));
1650                 if (result)
1651                         return result;
1652         }
1653
1654         j = i - 1;
1655         while (i < NUM_SOCCLK_DPM_LEVELS) {
1656                 result = vega10_populate_single_soc_level(hwmgr,
1657                                 dpm_table->dpm_levels[j].value,
1658                                 &(pp_table->SocclkDid[i]),
1659                                 &(pp_table->SocDpmVoltageIndex[i]));
1660                 if (result)
1661                         return result;
1662                 i++;
1663         }
1664
1665         return result;
1666 }
1667
1668 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1669 {
1670         struct vega10_hwmgr *data = hwmgr->backend;
1671         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1672         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1673         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1674
1675         uint8_t soc_vid = 0;
1676         uint32_t i, max_vddc_level;
1677
1678         if (hwmgr->od_enabled)
1679                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1680         else
1681                 vddc_lookup_table = table_info->vddc_lookup_table;
1682
1683         max_vddc_level = vddc_lookup_table->count;
1684         for (i = 0; i < max_vddc_level; i++) {
1685                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1686                 pp_table->SocVid[i] = soc_vid;
1687         }
1688         while (i < MAX_REGULAR_DPM_NUMBER) {
1689                 pp_table->SocVid[i] = soc_vid;
1690                 i++;
1691         }
1692 }
1693
1694 /**
1695  * @brief Populates single SMC GFXCLK structure using the provided clock.
1696  *
1697  * @param    hwmgr - the address of the hardware manager.
1698  * @param    mem_clock - the memory clock to use to populate the structure.
1699  * @return   0 on success..
1700  */
1701 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1702                 uint32_t mem_clock, uint8_t *current_mem_vid,
1703                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1704 {
1705         struct vega10_hwmgr *data = hwmgr->backend;
1706         struct phm_ppt_v2_information *table_info =
1707                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1708         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1709         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1710         uint32_t mem_max_clock =
1711                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1712         uint32_t i = 0;
1713
1714         if (hwmgr->od_enabled)
1715                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1716                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1717         else
1718                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1719
1720         PP_ASSERT_WITH_CODE(dep_on_mclk,
1721                         "Invalid SOC_VDD-UCLK Dependency Table!",
1722                         return -EINVAL);
1723
1724         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1725                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1726         } else {
1727                 for (i = 0; i < dep_on_mclk->count; i++) {
1728                         if (dep_on_mclk->entries[i].clk == mem_clock)
1729                                 break;
1730                 }
1731                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1732                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1733                                 return -EINVAL);
1734         }
1735
1736         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1737                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1738                         "Failed to get UCLK settings from VBIOS!",
1739                         return -1);
1740
1741         *current_mem_vid =
1742                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1743         *current_mem_soc_vind =
1744                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1745         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1746         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1747
1748         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1749                         "Invalid Divider ID!",
1750                         return -EINVAL);
1751
1752         return 0;
1753 }
1754
1755 /**
1756  * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1757  *
1758  * @param    pHwMgr - the address of the hardware manager.
1759  * @return   PP_Result_OK on success.
1760  */
1761 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1762 {
1763         struct vega10_hwmgr *data = hwmgr->backend;
1764         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1765         struct vega10_single_dpm_table *dpm_table =
1766                         &(data->dpm_table.mem_table);
1767         int result = 0;
1768         uint32_t i, j;
1769
1770         for (i = 0; i < dpm_table->count; i++) {
1771                 result = vega10_populate_single_memory_level(hwmgr,
1772                                 dpm_table->dpm_levels[i].value,
1773                                 &(pp_table->MemVid[i]),
1774                                 &(pp_table->UclkLevel[i]),
1775                                 &(pp_table->MemSocVoltageIndex[i]));
1776                 if (result)
1777                         return result;
1778         }
1779
1780         j = i - 1;
1781         while (i < NUM_UCLK_DPM_LEVELS) {
1782                 result = vega10_populate_single_memory_level(hwmgr,
1783                                 dpm_table->dpm_levels[j].value,
1784                                 &(pp_table->MemVid[i]),
1785                                 &(pp_table->UclkLevel[i]),
1786                                 &(pp_table->MemSocVoltageIndex[i]));
1787                 if (result)
1788                         return result;
1789                 i++;
1790         }
1791
1792         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1793         pp_table->MemoryChannelWidth =
1794                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1795                                         channel_number[data->mem_channels]);
1796
1797         pp_table->LowestUclkReservedForUlv =
1798                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1799
1800         return result;
1801 }
1802
1803 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1804                 DSPCLK_e disp_clock)
1805 {
1806         struct vega10_hwmgr *data = hwmgr->backend;
1807         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1808         struct phm_ppt_v2_information *table_info =
1809                         (struct phm_ppt_v2_information *)
1810                         (hwmgr->pptable);
1811         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1812         uint32_t i;
1813         uint16_t clk = 0, vddc = 0;
1814         uint8_t vid = 0;
1815
1816         switch (disp_clock) {
1817         case DSPCLK_DCEFCLK:
1818                 dep_table = table_info->vdd_dep_on_dcefclk;
1819                 break;
1820         case DSPCLK_DISPCLK:
1821                 dep_table = table_info->vdd_dep_on_dispclk;
1822                 break;
1823         case DSPCLK_PIXCLK:
1824                 dep_table = table_info->vdd_dep_on_pixclk;
1825                 break;
1826         case DSPCLK_PHYCLK:
1827                 dep_table = table_info->vdd_dep_on_phyclk;
1828                 break;
1829         default:
1830                 return -1;
1831         }
1832
1833         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1834                         "Number Of Entries Exceeded maximum!",
1835                         return -1);
1836
1837         for (i = 0; i < dep_table->count; i++) {
1838                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1839                 vddc = table_info->vddc_lookup_table->
1840                                 entries[dep_table->entries[i].vddInd].us_vdd;
1841                 vid = (uint8_t)convert_to_vid(vddc);
1842                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1843                                 cpu_to_le16(clk);
1844                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1845                                 cpu_to_le16(vid);
1846         }
1847
1848         while (i < NUM_DSPCLK_LEVELS) {
1849                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1850                                 cpu_to_le16(clk);
1851                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1852                                 cpu_to_le16(vid);
1853                 i++;
1854         }
1855
1856         return 0;
1857 }
1858
1859 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1860 {
1861         uint32_t i;
1862
1863         for (i = 0; i < DSPCLK_COUNT; i++) {
1864                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1865                                 "Failed to populate Clock in DisplayClockTable!",
1866                                 return -1);
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1873                 uint32_t eclock, uint8_t *current_eclk_did,
1874                 uint8_t *current_soc_vol)
1875 {
1876         struct phm_ppt_v2_information *table_info =
1877                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1878         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1879                         table_info->mm_dep_table;
1880         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1881         uint32_t i;
1882
1883         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1884                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1885                         eclock, &dividers),
1886                         "Failed to get ECLK clock settings from VBIOS!",
1887                         return -1);
1888
1889         *current_eclk_did = (uint8_t)dividers.ulDid;
1890
1891         for (i = 0; i < dep_table->count; i++) {
1892                 if (dep_table->entries[i].eclk == eclock)
1893                         *current_soc_vol = dep_table->entries[i].vddcInd;
1894         }
1895
1896         return 0;
1897 }
1898
1899 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1900 {
1901         struct vega10_hwmgr *data = hwmgr->backend;
1902         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1903         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1904         int result = -EINVAL;
1905         uint32_t i, j;
1906
1907         for (i = 0; i < dpm_table->count; i++) {
1908                 result = vega10_populate_single_eclock_level(hwmgr,
1909                                 dpm_table->dpm_levels[i].value,
1910                                 &(pp_table->EclkDid[i]),
1911                                 &(pp_table->VceDpmVoltageIndex[i]));
1912                 if (result)
1913                         return result;
1914         }
1915
1916         j = i - 1;
1917         while (i < NUM_VCE_DPM_LEVELS) {
1918                 result = vega10_populate_single_eclock_level(hwmgr,
1919                                 dpm_table->dpm_levels[j].value,
1920                                 &(pp_table->EclkDid[i]),
1921                                 &(pp_table->VceDpmVoltageIndex[i]));
1922                 if (result)
1923                         return result;
1924                 i++;
1925         }
1926
1927         return result;
1928 }
1929
1930 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
1931                 uint32_t vclock, uint8_t *current_vclk_did)
1932 {
1933         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1934
1935         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1936                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1937                         vclock, &dividers),
1938                         "Failed to get VCLK clock settings from VBIOS!",
1939                         return -EINVAL);
1940
1941         *current_vclk_did = (uint8_t)dividers.ulDid;
1942
1943         return 0;
1944 }
1945
1946 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
1947                 uint32_t dclock, uint8_t *current_dclk_did)
1948 {
1949         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1950
1951         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1952                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1953                         dclock, &dividers),
1954                         "Failed to get DCLK clock settings from VBIOS!",
1955                         return -EINVAL);
1956
1957         *current_dclk_did = (uint8_t)dividers.ulDid;
1958
1959         return 0;
1960 }
1961
1962 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
1963 {
1964         struct vega10_hwmgr *data = hwmgr->backend;
1965         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1966         struct vega10_single_dpm_table *vclk_dpm_table =
1967                         &(data->dpm_table.vclk_table);
1968         struct vega10_single_dpm_table *dclk_dpm_table =
1969                         &(data->dpm_table.dclk_table);
1970         struct phm_ppt_v2_information *table_info =
1971                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1972         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1973                         table_info->mm_dep_table;
1974         int result = -EINVAL;
1975         uint32_t i, j;
1976
1977         for (i = 0; i < vclk_dpm_table->count; i++) {
1978                 result = vega10_populate_single_vclock_level(hwmgr,
1979                                 vclk_dpm_table->dpm_levels[i].value,
1980                                 &(pp_table->VclkDid[i]));
1981                 if (result)
1982                         return result;
1983         }
1984
1985         j = i - 1;
1986         while (i < NUM_UVD_DPM_LEVELS) {
1987                 result = vega10_populate_single_vclock_level(hwmgr,
1988                                 vclk_dpm_table->dpm_levels[j].value,
1989                                 &(pp_table->VclkDid[i]));
1990                 if (result)
1991                         return result;
1992                 i++;
1993         }
1994
1995         for (i = 0; i < dclk_dpm_table->count; i++) {
1996                 result = vega10_populate_single_dclock_level(hwmgr,
1997                                 dclk_dpm_table->dpm_levels[i].value,
1998                                 &(pp_table->DclkDid[i]));
1999                 if (result)
2000                         return result;
2001         }
2002
2003         j = i - 1;
2004         while (i < NUM_UVD_DPM_LEVELS) {
2005                 result = vega10_populate_single_dclock_level(hwmgr,
2006                                 dclk_dpm_table->dpm_levels[j].value,
2007                                 &(pp_table->DclkDid[i]));
2008                 if (result)
2009                         return result;
2010                 i++;
2011         }
2012
2013         for (i = 0; i < dep_table->count; i++) {
2014                 if (dep_table->entries[i].vclk ==
2015                                 vclk_dpm_table->dpm_levels[i].value &&
2016                         dep_table->entries[i].dclk ==
2017                                 dclk_dpm_table->dpm_levels[i].value)
2018                         pp_table->UvdDpmVoltageIndex[i] =
2019                                         dep_table->entries[i].vddcInd;
2020                 else
2021                         return -1;
2022         }
2023
2024         j = i - 1;
2025         while (i < NUM_UVD_DPM_LEVELS) {
2026                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2027                 i++;
2028         }
2029
2030         return 0;
2031 }
2032
2033 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2034 {
2035         struct vega10_hwmgr *data = hwmgr->backend;
2036         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2037         struct phm_ppt_v2_information *table_info =
2038                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2039         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2040                         table_info->vdd_dep_on_sclk;
2041         uint32_t i;
2042
2043         for (i = 0; i < dep_table->count; i++) {
2044                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2045                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2046                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2047         }
2048
2049         return 0;
2050 }
2051
2052 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2053 {
2054         struct vega10_hwmgr *data = hwmgr->backend;
2055         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2056         struct phm_ppt_v2_information *table_info =
2057                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2058         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2059                         table_info->vdd_dep_on_sclk;
2060         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2061         int result = 0;
2062         uint32_t i;
2063
2064         pp_table->MinVoltageVid = (uint8_t)0xff;
2065         pp_table->MaxVoltageVid = (uint8_t)0;
2066
2067         if (data->smu_features[GNLD_AVFS].supported) {
2068                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2069                 if (!result) {
2070                         data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
2071                         data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
2072
2073                         pp_table->MinVoltageVid = (uint8_t)
2074                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2075                         pp_table->MaxVoltageVid = (uint8_t)
2076                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2077
2078                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2079                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2080                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2081                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2082                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2083                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2084                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2085
2086                         pp_table->BtcGbVdroopTableCksOff.a0 =
2087                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2088                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2089                         pp_table->BtcGbVdroopTableCksOff.a1 =
2090                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2091                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2092                         pp_table->BtcGbVdroopTableCksOff.a2 =
2093                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2094                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2095
2096                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2097                         pp_table->BtcGbVdroopTableCksOn.a0 =
2098                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2099                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2100                         pp_table->BtcGbVdroopTableCksOn.a1 =
2101                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2102                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2103                         pp_table->BtcGbVdroopTableCksOn.a2 =
2104                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2105                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2106
2107                         pp_table->AvfsGbCksOn.m1 =
2108                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2109                         pp_table->AvfsGbCksOn.m2 =
2110                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2111                         pp_table->AvfsGbCksOn.b =
2112                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2113                         pp_table->AvfsGbCksOn.m1_shift = 24;
2114                         pp_table->AvfsGbCksOn.m2_shift = 12;
2115                         pp_table->AvfsGbCksOn.b_shift = 0;
2116
2117                         pp_table->OverrideAvfsGbCksOn =
2118                                         avfs_params.ucEnableGbFuseTableCkson;
2119                         pp_table->AvfsGbCksOff.m1 =
2120                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2121                         pp_table->AvfsGbCksOff.m2 =
2122                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2123                         pp_table->AvfsGbCksOff.b =
2124                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2125                         pp_table->AvfsGbCksOff.m1_shift = 24;
2126                         pp_table->AvfsGbCksOff.m2_shift = 12;
2127                         pp_table->AvfsGbCksOff.b_shift = 0;
2128
2129                         for (i = 0; i < dep_table->count; i++)
2130                                 pp_table->StaticVoltageOffsetVid[i] =
2131                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2132
2133                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2134                                         data->disp_clk_quad_eqn_a) &&
2135                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2136                                         data->disp_clk_quad_eqn_b)) {
2137                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2138                                                 (int32_t)data->disp_clk_quad_eqn_a;
2139                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2140                                                 (int32_t)data->disp_clk_quad_eqn_b;
2141                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2142                                                 (int32_t)data->disp_clk_quad_eqn_c;
2143                         } else {
2144                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2145                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2146                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2147                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2148                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2149                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2150                         }
2151
2152                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2153                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2154                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2155
2156                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2157                                         data->dcef_clk_quad_eqn_a) &&
2158                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2159                                         data->dcef_clk_quad_eqn_b)) {
2160                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2161                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2162                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2163                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2164                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2165                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2166                         } else {
2167                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2168                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2169                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2170                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2171                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2172                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2173                         }
2174
2175                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2176                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2177                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2178
2179                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2180                                         data->pixel_clk_quad_eqn_a) &&
2181                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2182                                         data->pixel_clk_quad_eqn_b)) {
2183                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2184                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2185                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2186                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2187                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2188                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2189                         } else {
2190                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2191                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2192                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2193                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2194                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2195                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2196                         }
2197
2198                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2199                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2200                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2201                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2202                                         data->phy_clk_quad_eqn_a) &&
2203                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2204                                         data->phy_clk_quad_eqn_b)) {
2205                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2206                                                 (int32_t)data->phy_clk_quad_eqn_a;
2207                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2208                                                 (int32_t)data->phy_clk_quad_eqn_b;
2209                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2210                                                 (int32_t)data->phy_clk_quad_eqn_c;
2211                         } else {
2212                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2213                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2214                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2215                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2216                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2217                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2218                         }
2219
2220                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2221                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2222                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2223
2224                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2225                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2226                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2227                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2228                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2229                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2230
2231                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2232                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2233                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2234                         pp_table->AcgAvfsGb.m1_shift             = 0;
2235                         pp_table->AcgAvfsGb.m2_shift             = 0;
2236                         pp_table->AcgAvfsGb.b_shift              = 0;
2237
2238                 } else {
2239                         data->smu_features[GNLD_AVFS].supported = false;
2240                 }
2241         }
2242
2243         return 0;
2244 }
2245
2246 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2247 {
2248         struct vega10_hwmgr *data = hwmgr->backend;
2249         uint32_t agc_btc_response;
2250
2251         if (data->smu_features[GNLD_ACG].supported) {
2252                 if (0 == vega10_enable_smc_features(hwmgr, true,
2253                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2254                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2255
2256                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
2257
2258                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
2259                 agc_btc_response = smum_get_argument(hwmgr);
2260
2261                 if (1 == agc_btc_response) {
2262                         if (1 == data->acg_loop_state)
2263                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
2264                         else if (2 == data->acg_loop_state)
2265                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
2266                         if (0 == vega10_enable_smc_features(hwmgr, true,
2267                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2268                                         data->smu_features[GNLD_ACG].enabled = true;
2269                 } else {
2270                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2271                         data->smu_features[GNLD_ACG].enabled = false;
2272                 }
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2279 {
2280         struct vega10_hwmgr *data = hwmgr->backend;
2281
2282         if (data->smu_features[GNLD_ACG].supported &&
2283             data->smu_features[GNLD_ACG].enabled)
2284                 if (!vega10_enable_smc_features(hwmgr, false,
2285                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2286                         data->smu_features[GNLD_ACG].enabled = false;
2287
2288         return 0;
2289 }
2290
2291 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2292 {
2293         struct vega10_hwmgr *data = hwmgr->backend;
2294         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2295         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2296         int result;
2297
2298         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2299         if (!result) {
2300                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2301                     data->registry_data.regulator_hot_gpio_support) {
2302                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2303                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2304                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2305                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2306                 } else {
2307                         pp_table->VR0HotGpio = 0;
2308                         pp_table->VR0HotPolarity = 0;
2309                         pp_table->VR1HotGpio = 0;
2310                         pp_table->VR1HotPolarity = 0;
2311                 }
2312
2313                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2314                     data->registry_data.ac_dc_switch_gpio_support) {
2315                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2316                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2317                 } else {
2318                         pp_table->AcDcGpio = 0;
2319                         pp_table->AcDcPolarity = 0;
2320                 }
2321         }
2322
2323         return result;
2324 }
2325
2326 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2327 {
2328         struct vega10_hwmgr *data = hwmgr->backend;
2329
2330         if (data->smu_features[GNLD_AVFS].supported) {
2331                 if (enable) {
2332                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2333                                         true,
2334                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2335                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2336                                         return -1);
2337                         data->smu_features[GNLD_AVFS].enabled = true;
2338                 } else {
2339                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2340                                         false,
2341                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2342                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2343                                         return -1);
2344                         data->smu_features[GNLD_AVFS].enabled = false;
2345                 }
2346         }
2347
2348         return 0;
2349 }
2350
2351 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2352 {
2353         struct vega10_hwmgr *data = hwmgr->backend;
2354
2355         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2356                 vega10_avfs_enable(hwmgr, false);
2357         } else if (data->need_update_dpm_table) {
2358                 vega10_avfs_enable(hwmgr, false);
2359                 vega10_avfs_enable(hwmgr, true);
2360         } else {
2361                 vega10_avfs_enable(hwmgr, true);
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2368 {
2369         int result = 0;
2370
2371         uint64_t serial_number = 0;
2372         uint32_t top32, bottom32;
2373         struct phm_fuses_default fuse;
2374
2375         struct vega10_hwmgr *data = hwmgr->backend;
2376         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2377
2378         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
2379         top32 = smum_get_argument(hwmgr);
2380
2381         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
2382         bottom32 = smum_get_argument(hwmgr);
2383
2384         serial_number = ((uint64_t)bottom32 << 32) | top32;
2385
2386         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2387                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2388                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2389                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2390                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2391                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2392                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2393                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2394                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2395                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2396                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2397                                                 AVFSFUSETABLE, false);
2398                 PP_ASSERT_WITH_CODE(!result,
2399                         "Failed to upload FuseOVerride!",
2400                         );
2401         }
2402
2403         return result;
2404 }
2405
2406 /**
2407 * Initializes the SMC table and uploads it
2408 *
2409 * @param    hwmgr  the address of the powerplay hardware manager.
2410 * @param    pInput  the pointer to input data (PowerState)
2411 * @return   always 0
2412 */
2413 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2414 {
2415         int result;
2416         struct vega10_hwmgr *data = hwmgr->backend;
2417         struct phm_ppt_v2_information *table_info =
2418                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2419         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2420         struct pp_atomfwctrl_voltage_table voltage_table;
2421         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2422
2423         result = vega10_setup_default_dpm_tables(hwmgr);
2424         PP_ASSERT_WITH_CODE(!result,
2425                         "Failed to setup default DPM tables!",
2426                         return result);
2427
2428         /* initialize ODN table */
2429         if (hwmgr->od_enabled)
2430                 vega10_odn_initial_default_setting(hwmgr);
2431
2432         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2433                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2434         pp_table->MaxVidStep = voltage_table.max_vid_step;
2435
2436         pp_table->GfxDpmVoltageMode =
2437                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2438         pp_table->SocDpmVoltageMode =
2439                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2440         pp_table->UclkDpmVoltageMode =
2441                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2442         pp_table->UvdDpmVoltageMode =
2443                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2444         pp_table->VceDpmVoltageMode =
2445                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2446         pp_table->Mp0DpmVoltageMode =
2447                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2448
2449         pp_table->DisplayDpmVoltageMode =
2450                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2451
2452         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2453         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2454
2455         if (data->registry_data.ulv_support &&
2456                         table_info->us_ulv_voltage_offset) {
2457                 result = vega10_populate_ulv_state(hwmgr);
2458                 PP_ASSERT_WITH_CODE(!result,
2459                                 "Failed to initialize ULV state!",
2460                                 return result);
2461         }
2462
2463         result = vega10_populate_smc_link_levels(hwmgr);
2464         PP_ASSERT_WITH_CODE(!result,
2465                         "Failed to initialize Link Level!",
2466                         return result);
2467
2468         result = vega10_populate_all_graphic_levels(hwmgr);
2469         PP_ASSERT_WITH_CODE(!result,
2470                         "Failed to initialize Graphics Level!",
2471                         return result);
2472
2473         result = vega10_populate_all_memory_levels(hwmgr);
2474         PP_ASSERT_WITH_CODE(!result,
2475                         "Failed to initialize Memory Level!",
2476                         return result);
2477
2478         vega10_populate_vddc_soc_levels(hwmgr);
2479
2480         result = vega10_populate_all_display_clock_levels(hwmgr);
2481         PP_ASSERT_WITH_CODE(!result,
2482                         "Failed to initialize Display Level!",
2483                         return result);
2484
2485         result = vega10_populate_smc_vce_levels(hwmgr);
2486         PP_ASSERT_WITH_CODE(!result,
2487                         "Failed to initialize VCE Level!",
2488                         return result);
2489
2490         result = vega10_populate_smc_uvd_levels(hwmgr);
2491         PP_ASSERT_WITH_CODE(!result,
2492                         "Failed to initialize UVD Level!",
2493                         return result);
2494
2495         if (data->registry_data.clock_stretcher_support) {
2496                 result = vega10_populate_clock_stretcher_table(hwmgr);
2497                 PP_ASSERT_WITH_CODE(!result,
2498                                 "Failed to populate Clock Stretcher Table!",
2499                                 return result);
2500         }
2501
2502         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2503         if (!result) {
2504                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2505                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2506                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2507                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2508                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2509                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2510                                 SMU9_SYSPLL0_SOCCLK_ID, &boot_up_values.ulSocClk);
2511
2512                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2513                                 SMU9_SYSPLL0_DCEFCLK_ID, &boot_up_values.ulDCEFClk);
2514
2515                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2516                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2517                 if (0 != boot_up_values.usVddc) {
2518                         smum_send_msg_to_smc_with_parameter(hwmgr,
2519                                                 PPSMC_MSG_SetFloorSocVoltage,
2520                                                 (boot_up_values.usVddc * 4));
2521                         data->vbios_boot_state.bsoc_vddc_lock = true;
2522                 } else {
2523                         data->vbios_boot_state.bsoc_vddc_lock = false;
2524                 }
2525                 smum_send_msg_to_smc_with_parameter(hwmgr,
2526                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2527                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
2528         }
2529
2530         result = vega10_populate_avfs_parameters(hwmgr);
2531         PP_ASSERT_WITH_CODE(!result,
2532                         "Failed to initialize AVFS Parameters!",
2533                         return result);
2534
2535         result = vega10_populate_gpio_parameters(hwmgr);
2536         PP_ASSERT_WITH_CODE(!result,
2537                         "Failed to initialize GPIO Parameters!",
2538                         return result);
2539
2540         pp_table->GfxclkAverageAlpha = (uint8_t)
2541                         (data->gfxclk_average_alpha);
2542         pp_table->SocclkAverageAlpha = (uint8_t)
2543                         (data->socclk_average_alpha);
2544         pp_table->UclkAverageAlpha = (uint8_t)
2545                         (data->uclk_average_alpha);
2546         pp_table->GfxActivityAverageAlpha = (uint8_t)
2547                         (data->gfx_activity_average_alpha);
2548
2549         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2550
2551         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2552
2553         PP_ASSERT_WITH_CODE(!result,
2554                         "Failed to upload PPtable!", return result);
2555
2556         result = vega10_avfs_enable(hwmgr, true);
2557         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2558                                         return result);
2559         vega10_acg_enable(hwmgr);
2560
2561         return 0;
2562 }
2563
2564 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2565 {
2566         struct vega10_hwmgr *data = hwmgr->backend;
2567
2568         if (data->smu_features[GNLD_THERMAL].supported) {
2569                 if (data->smu_features[GNLD_THERMAL].enabled)
2570                         pr_info("THERMAL Feature Already enabled!");
2571
2572                 PP_ASSERT_WITH_CODE(
2573                                 !vega10_enable_smc_features(hwmgr,
2574                                 true,
2575                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2576                                 "Enable THERMAL Feature Failed!",
2577                                 return -1);
2578                 data->smu_features[GNLD_THERMAL].enabled = true;
2579         }
2580
2581         return 0;
2582 }
2583
2584 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2585 {
2586         struct vega10_hwmgr *data = hwmgr->backend;
2587
2588         if (data->smu_features[GNLD_THERMAL].supported) {
2589                 if (!data->smu_features[GNLD_THERMAL].enabled)
2590                         pr_info("THERMAL Feature Already disabled!");
2591
2592                 PP_ASSERT_WITH_CODE(
2593                                 !vega10_enable_smc_features(hwmgr,
2594                                 false,
2595                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2596                                 "disable THERMAL Feature Failed!",
2597                                 return -1);
2598                 data->smu_features[GNLD_THERMAL].enabled = false;
2599         }
2600
2601         return 0;
2602 }
2603
2604 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2605 {
2606         struct vega10_hwmgr *data = hwmgr->backend;
2607
2608         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2609                 if (data->smu_features[GNLD_VR0HOT].supported) {
2610                         PP_ASSERT_WITH_CODE(
2611                                         !vega10_enable_smc_features(hwmgr,
2612                                         true,
2613                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2614                                         "Attempt to Enable VR0 Hot feature Failed!",
2615                                         return -1);
2616                         data->smu_features[GNLD_VR0HOT].enabled = true;
2617                 } else {
2618                         if (data->smu_features[GNLD_VR1HOT].supported) {
2619                                 PP_ASSERT_WITH_CODE(
2620                                                 !vega10_enable_smc_features(hwmgr,
2621                                                 true,
2622                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2623                                                 "Attempt to Enable VR0 Hot feature Failed!",
2624                                                 return -1);
2625                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2626                         }
2627                 }
2628         }
2629         return 0;
2630 }
2631
2632 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2633 {
2634         struct vega10_hwmgr *data = hwmgr->backend;
2635
2636         if (data->registry_data.ulv_support) {
2637                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2638                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2639                                 "Enable ULV Feature Failed!",
2640                                 return -1);
2641                 data->smu_features[GNLD_ULV].enabled = true;
2642         }
2643
2644         return 0;
2645 }
2646
2647 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2648 {
2649         struct vega10_hwmgr *data = hwmgr->backend;
2650
2651         if (data->registry_data.ulv_support) {
2652                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2653                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2654                                 "disable ULV Feature Failed!",
2655                                 return -EINVAL);
2656                 data->smu_features[GNLD_ULV].enabled = false;
2657         }
2658
2659         return 0;
2660 }
2661
2662 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2663 {
2664         struct vega10_hwmgr *data = hwmgr->backend;
2665
2666         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2667                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2668                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2669                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2670                                 return -EINVAL);
2671                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2672         }
2673
2674         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2675                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2676                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2677                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2678                                 return -EINVAL);
2679                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2680         }
2681
2682         if (data->smu_features[GNLD_DS_LCLK].supported) {
2683                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2684                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2685                                 "Attempt to Enable DS_LCLK Feature Failed!",
2686                                 return -EINVAL);
2687                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2688         }
2689
2690         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2691                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2692                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2693                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2694                                 return -EINVAL);
2695                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2696         }
2697
2698         return 0;
2699 }
2700
2701 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2702 {
2703         struct vega10_hwmgr *data = hwmgr->backend;
2704
2705         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2706                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2707                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2708                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2709                                 return -EINVAL);
2710                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2711         }
2712
2713         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2714                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2715                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2716                                 "Attempt to disable DS_ Feature Failed!",
2717                                 return -EINVAL);
2718                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2719         }
2720
2721         if (data->smu_features[GNLD_DS_LCLK].supported) {
2722                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2723                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2724                                 "Attempt to disable DS_LCLK Feature Failed!",
2725                                 return -EINVAL);
2726                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2727         }
2728
2729         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2730                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2731                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2732                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2733                                 return -EINVAL);
2734                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2735         }
2736
2737         return 0;
2738 }
2739
2740 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2741 {
2742         struct vega10_hwmgr *data = hwmgr->backend;
2743         uint32_t i, feature_mask = 0;
2744
2745
2746         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2747                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2748                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2749                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2750                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2751         }
2752
2753         for (i = 0; i < GNLD_DPM_MAX; i++) {
2754                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2755                         if (data->smu_features[i].supported) {
2756                                 if (data->smu_features[i].enabled) {
2757                                         feature_mask |= data->smu_features[i].
2758                                                         smu_feature_bitmap;
2759                                         data->smu_features[i].enabled = false;
2760                                 }
2761                         }
2762                 }
2763         }
2764
2765         vega10_enable_smc_features(hwmgr, false, feature_mask);
2766
2767         return 0;
2768 }
2769
2770 /**
2771  * @brief Tell SMC to enabled the supported DPMs.
2772  *
2773  * @param    hwmgr - the address of the powerplay hardware manager.
2774  * @Param    bitmap - bitmap for the features to enabled.
2775  * @return   0 on at least one DPM is successfully enabled.
2776  */
2777 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2778 {
2779         struct vega10_hwmgr *data = hwmgr->backend;
2780         uint32_t i, feature_mask = 0;
2781
2782         for (i = 0; i < GNLD_DPM_MAX; i++) {
2783                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2784                         if (data->smu_features[i].supported) {
2785                                 if (!data->smu_features[i].enabled) {
2786                                         feature_mask |= data->smu_features[i].
2787                                                         smu_feature_bitmap;
2788                                         data->smu_features[i].enabled = true;
2789                                 }
2790                         }
2791                 }
2792         }
2793
2794         if (vega10_enable_smc_features(hwmgr,
2795                         true, feature_mask)) {
2796                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2797                         if (data->smu_features[i].smu_feature_bitmap &
2798                                         feature_mask)
2799                                 data->smu_features[i].enabled = false;
2800                 }
2801         }
2802
2803         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2804                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2805                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2806                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2807                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2808         }
2809
2810         if (data->vbios_boot_state.bsoc_vddc_lock) {
2811                 smum_send_msg_to_smc_with_parameter(hwmgr,
2812                                                 PPSMC_MSG_SetFloorSocVoltage, 0);
2813                 data->vbios_boot_state.bsoc_vddc_lock = false;
2814         }
2815
2816         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2817                 if (data->smu_features[GNLD_ACDC].supported) {
2818                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2819                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2820                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2821                                         return -1);
2822                         data->smu_features[GNLD_ACDC].enabled = true;
2823                 }
2824         }
2825
2826         return 0;
2827 }
2828
2829 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2830 {
2831         struct vega10_hwmgr *data = hwmgr->backend;
2832
2833         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2834                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2835                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2836                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2837                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2838                                 "Attempt to Enable PCC Limit feature Failed!",
2839                                 return -EINVAL);
2840                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
2841         }
2842
2843         return 0;
2844 }
2845
2846 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2847 {
2848         struct vega10_hwmgr *data = hwmgr->backend;
2849         int tmp_result, result = 0;
2850
2851         vega10_enable_disable_PCC_limit_feature(hwmgr, true);
2852
2853         if ((hwmgr->smu_version == 0x001c2c00) ||
2854                         (hwmgr->smu_version == 0x001c2d00))
2855                 smum_send_msg_to_smc_with_parameter(hwmgr,
2856                                 PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
2857
2858         smum_send_msg_to_smc_with_parameter(hwmgr,
2859                 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2860
2861         tmp_result = vega10_construct_voltage_tables(hwmgr);
2862         PP_ASSERT_WITH_CODE(!tmp_result,
2863                         "Failed to contruct voltage tables!",
2864                         result = tmp_result);
2865
2866         tmp_result = vega10_init_smc_table(hwmgr);
2867         PP_ASSERT_WITH_CODE(!tmp_result,
2868                         "Failed to initialize SMC table!",
2869                         result = tmp_result);
2870
2871         if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
2872                 tmp_result = vega10_enable_thermal_protection(hwmgr);
2873                 PP_ASSERT_WITH_CODE(!tmp_result,
2874                                 "Failed to enable thermal protection!",
2875                                 result = tmp_result);
2876         }
2877
2878         tmp_result = vega10_enable_vrhot_feature(hwmgr);
2879         PP_ASSERT_WITH_CODE(!tmp_result,
2880                         "Failed to enable VR hot feature!",
2881                         result = tmp_result);
2882
2883         tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
2884         PP_ASSERT_WITH_CODE(!tmp_result,
2885                         "Failed to enable deep sleep master switch!",
2886                         result = tmp_result);
2887
2888         tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
2889         PP_ASSERT_WITH_CODE(!tmp_result,
2890                         "Failed to start DPM!", result = tmp_result);
2891
2892         /* enable didt, do not abort if failed didt */
2893         tmp_result = vega10_enable_didt_config(hwmgr);
2894         PP_ASSERT(!tmp_result,
2895                         "Failed to enable didt config!");
2896
2897         tmp_result = vega10_enable_power_containment(hwmgr);
2898         PP_ASSERT_WITH_CODE(!tmp_result,
2899                         "Failed to enable power containment!",
2900                         result = tmp_result);
2901
2902         tmp_result = vega10_power_control_set_level(hwmgr);
2903         PP_ASSERT_WITH_CODE(!tmp_result,
2904                         "Failed to power control set level!",
2905                         result = tmp_result);
2906
2907         tmp_result = vega10_enable_ulv(hwmgr);
2908         PP_ASSERT_WITH_CODE(!tmp_result,
2909                         "Failed to enable ULV!",
2910                         result = tmp_result);
2911
2912         return result;
2913 }
2914
2915 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
2916 {
2917         return sizeof(struct vega10_power_state);
2918 }
2919
2920 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
2921                 void *state, struct pp_power_state *power_state,
2922                 void *pp_table, uint32_t classification_flag)
2923 {
2924         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
2925         struct vega10_power_state *vega10_power_state =
2926                         cast_phw_vega10_power_state(&(power_state->hardware));
2927         struct vega10_performance_level *performance_level;
2928         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
2929         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
2930                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
2931         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
2932                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
2933                         (((unsigned long)powerplay_table) +
2934                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
2935         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
2936                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
2937                         (((unsigned long)powerplay_table) +
2938                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
2939         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
2940                         (ATOM_Vega10_MCLK_Dependency_Table *)
2941                         (((unsigned long)powerplay_table) +
2942                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2943
2944
2945         /* The following fields are not initialized here:
2946          * id orderedList allStatesList
2947          */
2948         power_state->classification.ui_label =
2949                         (le16_to_cpu(state_entry->usClassification) &
2950                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2951                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2952         power_state->classification.flags = classification_flag;
2953         /* NOTE: There is a classification2 flag in BIOS
2954          * that is not being used right now
2955          */
2956         power_state->classification.temporary_state = false;
2957         power_state->classification.to_be_deleted = false;
2958
2959         power_state->validation.disallowOnDC =
2960                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
2961                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
2962
2963         power_state->display.disableFrameModulation = false;
2964         power_state->display.limitRefreshrate = false;
2965         power_state->display.enableVariBright =
2966                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
2967                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
2968
2969         power_state->validation.supportedPowerLevels = 0;
2970         power_state->uvd_clocks.VCLK = 0;
2971         power_state->uvd_clocks.DCLK = 0;
2972         power_state->temperatures.min = 0;
2973         power_state->temperatures.max = 0;
2974
2975         performance_level = &(vega10_power_state->performance_levels
2976                         [vega10_power_state->performance_level_count++]);
2977
2978         PP_ASSERT_WITH_CODE(
2979                         (vega10_power_state->performance_level_count <
2980                                         NUM_GFXCLK_DPM_LEVELS),
2981                         "Performance levels exceeds SMC limit!",
2982                         return -1);
2983
2984         PP_ASSERT_WITH_CODE(
2985                         (vega10_power_state->performance_level_count <=
2986                                         hwmgr->platform_descriptor.
2987                                         hardwareActivityPerformanceLevels),
2988                         "Performance levels exceeds Driver limit!",
2989                         return -1);
2990
2991         /* Performance levels are arranged from low to high. */
2992         performance_level->soc_clock = socclk_dep_table->entries
2993                         [state_entry->ucSocClockIndexLow].ulClk;
2994         performance_level->gfx_clock = gfxclk_dep_table->entries
2995                         [state_entry->ucGfxClockIndexLow].ulClk;
2996         performance_level->mem_clock = mclk_dep_table->entries
2997                         [state_entry->ucMemClockIndexLow].ulMemClk;
2998
2999         performance_level = &(vega10_power_state->performance_levels
3000                                 [vega10_power_state->performance_level_count++]);
3001         performance_level->soc_clock = socclk_dep_table->entries
3002                                 [state_entry->ucSocClockIndexHigh].ulClk;
3003         if (gfxclk_dep_table->ucRevId == 0) {
3004                 performance_level->gfx_clock = gfxclk_dep_table->entries
3005                         [state_entry->ucGfxClockIndexHigh].ulClk;
3006         } else if (gfxclk_dep_table->ucRevId == 1) {
3007                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3008                 performance_level->gfx_clock = patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3009         }
3010
3011         performance_level->mem_clock = mclk_dep_table->entries
3012                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3013         return 0;
3014 }
3015
3016 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3017                 unsigned long entry_index, struct pp_power_state *state)
3018 {
3019         int result;
3020         struct vega10_power_state *ps;
3021
3022         state->hardware.magic = PhwVega10_Magic;
3023
3024         ps = cast_phw_vega10_power_state(&state->hardware);
3025
3026         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3027                         vega10_get_pp_table_entry_callback_func);
3028
3029         /*
3030          * This is the earliest time we have all the dependency table
3031          * and the VBIOS boot state
3032          */
3033         /* set DC compatible flag if this state supports DC */
3034         if (!state->validation.disallowOnDC)
3035                 ps->dc_compatible = true;
3036
3037         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3038         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3039
3040         return 0;
3041 }
3042
3043 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3044              struct pp_hw_power_state *hw_ps)
3045 {
3046         return 0;
3047 }
3048
3049 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3050                                 struct pp_power_state  *request_ps,
3051                         const struct pp_power_state *current_ps)
3052 {
3053         struct vega10_power_state *vega10_ps =
3054                                 cast_phw_vega10_power_state(&request_ps->hardware);
3055         uint32_t sclk;
3056         uint32_t mclk;
3057         struct PP_Clocks minimum_clocks = {0};
3058         bool disable_mclk_switching;
3059         bool disable_mclk_switching_for_frame_lock;
3060         bool disable_mclk_switching_for_vr;
3061         bool force_mclk_high;
3062         const struct phm_clock_and_voltage_limits *max_limits;
3063         uint32_t i;
3064         struct vega10_hwmgr *data = hwmgr->backend;
3065         struct phm_ppt_v2_information *table_info =
3066                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3067         int32_t count;
3068         uint32_t stable_pstate_sclk_dpm_percentage;
3069         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3070         uint32_t latency;
3071
3072         data->battery_state = (PP_StateUILabel_Battery ==
3073                         request_ps->classification.ui_label);
3074
3075         if (vega10_ps->performance_level_count != 2)
3076                 pr_info("VI should always have 2 performance levels");
3077
3078         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3079                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3080                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3081
3082         /* Cap clock DPM tables at DC MAX if it is in DC. */
3083         if (PP_PowerSource_DC == hwmgr->power_source) {
3084                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3085                         if (vega10_ps->performance_levels[i].mem_clock >
3086                                 max_limits->mclk)
3087                                 vega10_ps->performance_levels[i].mem_clock =
3088                                                 max_limits->mclk;
3089                         if (vega10_ps->performance_levels[i].gfx_clock >
3090                                 max_limits->sclk)
3091                                 vega10_ps->performance_levels[i].gfx_clock =
3092                                                 max_limits->sclk;
3093                 }
3094         }
3095
3096         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3097         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3098         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3099
3100         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3101                 stable_pstate_sclk_dpm_percentage =
3102                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3103                 PP_ASSERT_WITH_CODE(
3104                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3105                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3106                         "percent sclk value must range from 1% to 100%, setting default value",
3107                         stable_pstate_sclk_dpm_percentage = 75);
3108
3109                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3110                 stable_pstate_sclk = (max_limits->sclk *
3111                                 stable_pstate_sclk_dpm_percentage) / 100;
3112
3113                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3114                                 count >= 0; count--) {
3115                         if (stable_pstate_sclk >=
3116                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3117                                 stable_pstate_sclk =
3118                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3119                                 break;
3120                         }
3121                 }
3122
3123                 if (count < 0)
3124                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3125
3126                 stable_pstate_mclk = max_limits->mclk;
3127
3128                 minimum_clocks.engineClock = stable_pstate_sclk;
3129                 minimum_clocks.memoryClock = stable_pstate_mclk;
3130         }
3131
3132         disable_mclk_switching_for_frame_lock =
3133                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3134         disable_mclk_switching_for_vr =
3135                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3136         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3137
3138         if (hwmgr->display_config->num_display == 0)
3139                 disable_mclk_switching = false;
3140         else
3141                 disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
3142                         disable_mclk_switching_for_frame_lock ||
3143                         disable_mclk_switching_for_vr ||
3144                         force_mclk_high;
3145
3146         sclk = vega10_ps->performance_levels[0].gfx_clock;
3147         mclk = vega10_ps->performance_levels[0].mem_clock;
3148
3149         if (sclk < minimum_clocks.engineClock)
3150                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3151                                 max_limits->sclk : minimum_clocks.engineClock;
3152
3153         if (mclk < minimum_clocks.memoryClock)
3154                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3155                                 max_limits->mclk : minimum_clocks.memoryClock;
3156
3157         vega10_ps->performance_levels[0].gfx_clock = sclk;
3158         vega10_ps->performance_levels[0].mem_clock = mclk;
3159
3160         if (vega10_ps->performance_levels[1].gfx_clock <
3161                         vega10_ps->performance_levels[0].gfx_clock)
3162                 vega10_ps->performance_levels[0].gfx_clock =
3163                                 vega10_ps->performance_levels[1].gfx_clock;
3164
3165         if (disable_mclk_switching) {
3166                 /* Set Mclk the max of level 0 and level 1 */
3167                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3168                         mclk = vega10_ps->performance_levels[1].mem_clock;
3169
3170                 /* Find the lowest MCLK frequency that is within
3171                  * the tolerable latency defined in DAL
3172                  */
3173                 latency = 0;
3174                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3175                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3176                                 (data->mclk_latency_table.entries[i].frequency >=
3177                                                 vega10_ps->performance_levels[0].mem_clock) &&
3178                                 (data->mclk_latency_table.entries[i].frequency <=
3179                                                 vega10_ps->performance_levels[1].mem_clock))
3180                                 mclk = data->mclk_latency_table.entries[i].frequency;
3181                 }
3182                 vega10_ps->performance_levels[0].mem_clock = mclk;
3183         } else {
3184                 if (vega10_ps->performance_levels[1].mem_clock <
3185                                 vega10_ps->performance_levels[0].mem_clock)
3186                         vega10_ps->performance_levels[0].mem_clock =
3187                                         vega10_ps->performance_levels[1].mem_clock;
3188         }
3189
3190         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3191                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3192                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3193                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3194                 }
3195         }
3196
3197         return 0;
3198 }
3199
3200 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3201 {
3202         struct vega10_hwmgr *data = hwmgr->backend;
3203
3204         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3205                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3206
3207         return 0;
3208 }
3209
3210 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3211                 struct pp_hwmgr *hwmgr, const void *input)
3212 {
3213         int result = 0;
3214         struct vega10_hwmgr *data = hwmgr->backend;
3215
3216         if (!data->need_update_dpm_table)
3217                 return 0;
3218
3219         if (data->need_update_dpm_table &
3220                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {
3221                 result = vega10_populate_all_graphic_levels(hwmgr);
3222                 PP_ASSERT_WITH_CODE((0 == result),
3223                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3224                                 return result);
3225         }
3226
3227         if (data->need_update_dpm_table &
3228                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3229                 result = vega10_populate_all_memory_levels(hwmgr);
3230                 PP_ASSERT_WITH_CODE((0 == result),
3231                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3232                                 return result);
3233         }
3234
3235         vega10_populate_vddc_soc_levels(hwmgr);
3236
3237         return result;
3238 }
3239
3240 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3241                 struct vega10_single_dpm_table *dpm_table,
3242                 uint32_t low_limit, uint32_t high_limit)
3243 {
3244         uint32_t i;
3245
3246         for (i = 0; i < dpm_table->count; i++) {
3247                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3248                     (dpm_table->dpm_levels[i].value > high_limit))
3249                         dpm_table->dpm_levels[i].enabled = false;
3250                 else
3251                         dpm_table->dpm_levels[i].enabled = true;
3252         }
3253         return 0;
3254 }
3255
3256 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3257                 struct vega10_single_dpm_table *dpm_table,
3258                 uint32_t low_limit, uint32_t high_limit,
3259                 uint32_t disable_dpm_mask)
3260 {
3261         uint32_t i;
3262
3263         for (i = 0; i < dpm_table->count; i++) {
3264                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3265                     (dpm_table->dpm_levels[i].value > high_limit))
3266                         dpm_table->dpm_levels[i].enabled = false;
3267                 else if (!((1 << i) & disable_dpm_mask))
3268                         dpm_table->dpm_levels[i].enabled = false;
3269                 else
3270                         dpm_table->dpm_levels[i].enabled = true;
3271         }
3272         return 0;
3273 }
3274
3275 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3276                 const struct vega10_power_state *vega10_ps)
3277 {
3278         struct vega10_hwmgr *data = hwmgr->backend;
3279         uint32_t high_limit_count;
3280
3281         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3282                         "power state did not have any performance level",
3283                         return -1);
3284
3285         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3286
3287         vega10_trim_single_dpm_states(hwmgr,
3288                         &(data->dpm_table.soc_table),
3289                         vega10_ps->performance_levels[0].soc_clock,
3290                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3291
3292         vega10_trim_single_dpm_states_with_mask(hwmgr,
3293                         &(data->dpm_table.gfx_table),
3294                         vega10_ps->performance_levels[0].gfx_clock,
3295                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3296                         data->disable_dpm_mask);
3297
3298         vega10_trim_single_dpm_states(hwmgr,
3299                         &(data->dpm_table.mem_table),
3300                         vega10_ps->performance_levels[0].mem_clock,
3301                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3302
3303         return 0;
3304 }
3305
3306 static uint32_t vega10_find_lowest_dpm_level(
3307                 struct vega10_single_dpm_table *table)
3308 {
3309         uint32_t i;
3310
3311         for (i = 0; i < table->count; i++) {
3312                 if (table->dpm_levels[i].enabled)
3313                         break;
3314         }
3315
3316         return i;
3317 }
3318
3319 static uint32_t vega10_find_highest_dpm_level(
3320                 struct vega10_single_dpm_table *table)
3321 {
3322         uint32_t i = 0;
3323
3324         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3325                 for (i = table->count; i > 0; i--) {
3326                         if (table->dpm_levels[i - 1].enabled)
3327                                 return i - 1;
3328                 }
3329         } else {
3330                 pr_info("DPM Table Has Too Many Entries!");
3331                 return MAX_REGULAR_DPM_NUMBER - 1;
3332         }
3333
3334         return i;
3335 }
3336
3337 static void vega10_apply_dal_minimum_voltage_request(
3338                 struct pp_hwmgr *hwmgr)
3339 {
3340         return;
3341 }
3342
3343 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3344 {
3345         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3346         struct phm_ppt_v2_information *table_info =
3347                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3348
3349         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3350
3351         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3352 }
3353
3354 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3355 {
3356         struct vega10_hwmgr *data = hwmgr->backend;
3357         uint32_t socclk_idx;
3358
3359         vega10_apply_dal_minimum_voltage_request(hwmgr);
3360
3361         if (!data->registry_data.sclk_dpm_key_disabled) {
3362                 if (data->smc_state_table.gfx_boot_level !=
3363                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3364                         smum_send_msg_to_smc_with_parameter(hwmgr,
3365                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3366                                 data->smc_state_table.gfx_boot_level);
3367                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3368                                         data->smc_state_table.gfx_boot_level;
3369                 }
3370         }
3371
3372         if (!data->registry_data.mclk_dpm_key_disabled) {
3373                 if (data->smc_state_table.mem_boot_level !=
3374                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3375                         if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
3376                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3377                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3378                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3379                                                 socclk_idx);
3380                         } else {
3381                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3382                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3383                                                 data->smc_state_table.mem_boot_level);
3384                         }
3385                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3386                                         data->smc_state_table.mem_boot_level;
3387                 }
3388         }
3389
3390         return 0;
3391 }
3392
3393 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3394 {
3395         struct vega10_hwmgr *data = hwmgr->backend;
3396
3397         vega10_apply_dal_minimum_voltage_request(hwmgr);
3398
3399         if (!data->registry_data.sclk_dpm_key_disabled) {
3400                 if (data->smc_state_table.gfx_max_level !=
3401                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3402                         smum_send_msg_to_smc_with_parameter(hwmgr,
3403                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3404                                 data->smc_state_table.gfx_max_level);
3405                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3406                                         data->smc_state_table.gfx_max_level;
3407                 }
3408         }
3409
3410         if (!data->registry_data.mclk_dpm_key_disabled) {
3411                 if (data->smc_state_table.mem_max_level !=
3412                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3413                         smum_send_msg_to_smc_with_parameter(hwmgr,
3414                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3415                                         data->smc_state_table.mem_max_level);
3416                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3417                                         data->smc_state_table.mem_max_level;
3418                 }
3419         }
3420
3421         return 0;
3422 }
3423
3424 static int vega10_generate_dpm_level_enable_mask(
3425                 struct pp_hwmgr *hwmgr, const void *input)
3426 {
3427         struct vega10_hwmgr *data = hwmgr->backend;
3428         const struct phm_set_power_state_input *states =
3429                         (const struct phm_set_power_state_input *)input;
3430         const struct vega10_power_state *vega10_ps =
3431                         cast_const_phw_vega10_power_state(states->pnew_state);
3432         int i;
3433
3434         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3435                         "Attempt to Trim DPM States Failed!",
3436                         return -1);
3437
3438         data->smc_state_table.gfx_boot_level =
3439                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3440         data->smc_state_table.gfx_max_level =
3441                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3442         data->smc_state_table.mem_boot_level =
3443                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3444         data->smc_state_table.mem_max_level =
3445                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3446
3447         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3448                         "Attempt to upload DPM Bootup Levels Failed!",
3449                         return -1);
3450         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3451                         "Attempt to upload DPM Max Levels Failed!",
3452                         return -1);
3453         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3454                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3455
3456
3457         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3458                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3459
3460         return 0;
3461 }
3462
3463 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3464 {
3465         struct vega10_hwmgr *data = hwmgr->backend;
3466
3467         if (data->smu_features[GNLD_DPM_VCE].supported) {
3468                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3469                                 enable,
3470                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3471                                 "Attempt to Enable/Disable DPM VCE Failed!",
3472                                 return -1);
3473                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3474         }
3475
3476         return 0;
3477 }
3478
3479 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3480 {
3481         struct vega10_hwmgr *data = hwmgr->backend;
3482         uint32_t low_sclk_interrupt_threshold = 0;
3483
3484         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3485                 (data->low_sclk_interrupt_threshold != 0)) {
3486                 low_sclk_interrupt_threshold =
3487                                 data->low_sclk_interrupt_threshold;
3488
3489                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3490                                 cpu_to_le32(low_sclk_interrupt_threshold);
3491
3492                 /* This message will also enable SmcToHost Interrupt */
3493                 smum_send_msg_to_smc_with_parameter(hwmgr,
3494                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3495                                 (uint32_t)low_sclk_interrupt_threshold);
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3502                 const void *input)
3503 {
3504         int tmp_result, result = 0;
3505         struct vega10_hwmgr *data = hwmgr->backend;
3506         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3507
3508         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3509         PP_ASSERT_WITH_CODE(!tmp_result,
3510                         "Failed to find DPM states clocks in DPM table!",
3511                         result = tmp_result);
3512
3513         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3514         PP_ASSERT_WITH_CODE(!tmp_result,
3515                         "Failed to populate and upload SCLK MCLK DPM levels!",
3516                         result = tmp_result);
3517
3518         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3519         PP_ASSERT_WITH_CODE(!tmp_result,
3520                         "Failed to generate DPM level enabled mask!",
3521                         result = tmp_result);
3522
3523         tmp_result = vega10_update_sclk_threshold(hwmgr);
3524         PP_ASSERT_WITH_CODE(!tmp_result,
3525                         "Failed to update SCLK threshold!",
3526                         result = tmp_result);
3527
3528         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3529         PP_ASSERT_WITH_CODE(!result,
3530                         "Failed to upload PPtable!", return result);
3531
3532         vega10_update_avfs(hwmgr);
3533
3534         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3535
3536         return 0;
3537 }
3538
3539 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3540 {
3541         struct pp_power_state *ps;
3542         struct vega10_power_state *vega10_ps;
3543
3544         if (hwmgr == NULL)
3545                 return -EINVAL;
3546
3547         ps = hwmgr->request_ps;
3548
3549         if (ps == NULL)
3550                 return -EINVAL;
3551
3552         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3553
3554         if (low)
3555                 return vega10_ps->performance_levels[0].gfx_clock;
3556         else
3557                 return vega10_ps->performance_levels
3558                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3559 }
3560
3561 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3562 {
3563         struct pp_power_state *ps;
3564         struct vega10_power_state *vega10_ps;
3565
3566         if (hwmgr == NULL)
3567                 return -EINVAL;
3568
3569         ps = hwmgr->request_ps;
3570
3571         if (ps == NULL)
3572                 return -EINVAL;
3573
3574         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3575
3576         if (low)
3577                 return vega10_ps->performance_levels[0].mem_clock;
3578         else
3579                 return vega10_ps->performance_levels
3580                                 [vega10_ps->performance_level_count-1].mem_clock;
3581 }
3582
3583 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3584                 uint32_t *query)
3585 {
3586         uint32_t value;
3587
3588         if (!query)
3589                 return -EINVAL;
3590
3591         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
3592         value = smum_get_argument(hwmgr);
3593
3594         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3595         *query = value << 8;
3596
3597         return 0;
3598 }
3599
3600 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3601                               void *value, int *size)
3602 {
3603         struct amdgpu_device *adev = hwmgr->adev;
3604         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3605         struct vega10_hwmgr *data = hwmgr->backend;
3606         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3607         int ret = 0;
3608         uint32_t val_vid;
3609
3610         switch (idx) {
3611         case AMDGPU_PP_SENSOR_GFX_SCLK:
3612                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
3613                 sclk_mhz = smum_get_argument(hwmgr);
3614                 *((uint32_t *)value) = sclk_mhz * 100;
3615                 break;
3616         case AMDGPU_PP_SENSOR_GFX_MCLK:
3617                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
3618                 mclk_idx = smum_get_argument(hwmgr);
3619                 if (mclk_idx < dpm_table->mem_table.count) {
3620                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3621                         *size = 4;
3622                 } else {
3623                         ret = -EINVAL;
3624                 }
3625                 break;
3626         case AMDGPU_PP_SENSOR_GPU_LOAD:
3627                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3628                 activity_percent = smum_get_argument(hwmgr);
3629                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3630                 *size = 4;
3631                 break;
3632         case AMDGPU_PP_SENSOR_GPU_TEMP:
3633                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3634                 *size = 4;
3635                 break;
3636         case AMDGPU_PP_SENSOR_UVD_POWER:
3637                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3638                 *size = 4;
3639                 break;
3640         case AMDGPU_PP_SENSOR_VCE_POWER:
3641                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3642                 *size = 4;
3643                 break;
3644         case AMDGPU_PP_SENSOR_GPU_POWER:
3645                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3646                 break;
3647         case AMDGPU_PP_SENSOR_VDDGFX:
3648                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3649                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3650                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3651                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3652                 return 0;
3653         default:
3654                 ret = -EINVAL;
3655                 break;
3656         }
3657
3658         return ret;
3659 }
3660
3661 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3662                 bool has_disp)
3663 {
3664         smum_send_msg_to_smc_with_parameter(hwmgr,
3665                         PPSMC_MSG_SetUclkFastSwitch,
3666                         has_disp ? 0 : 1);
3667 }
3668
3669 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3670                 struct pp_display_clock_request *clock_req)
3671 {
3672         int result = 0;
3673         enum amd_pp_clock_type clk_type = clock_req->clock_type;
3674         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3675         DSPCLK_e clk_select = 0;
3676         uint32_t clk_request = 0;
3677
3678         switch (clk_type) {
3679         case amd_pp_dcef_clock:
3680                 clk_select = DSPCLK_DCEFCLK;
3681                 break;
3682         case amd_pp_disp_clock:
3683                 clk_select = DSPCLK_DISPCLK;
3684                 break;
3685         case amd_pp_pixel_clock:
3686                 clk_select = DSPCLK_PIXCLK;
3687                 break;
3688         case amd_pp_phy_clock:
3689                 clk_select = DSPCLK_PHYCLK;
3690                 break;
3691         default:
3692                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3693                 result = -1;
3694                 break;
3695         }
3696
3697         if (!result) {
3698                 clk_request = (clk_freq << 16) | clk_select;
3699                 smum_send_msg_to_smc_with_parameter(hwmgr,
3700                                 PPSMC_MSG_RequestDisplayClockByFreq,
3701                                 clk_request);
3702         }
3703
3704         return result;
3705 }
3706
3707 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
3708                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
3709                                                 uint32_t frequency)
3710 {
3711         uint8_t count;
3712         uint8_t i;
3713
3714         if (mclk_table == NULL || mclk_table->count == 0)
3715                 return 0;
3716
3717         count = (uint8_t)(mclk_table->count);
3718
3719         for(i = 0; i < count; i++) {
3720                 if(mclk_table->entries[i].clk >= frequency)
3721                         return i;
3722         }
3723
3724         return i-1;
3725 }
3726
3727 static int vega10_notify_smc_display_config_after_ps_adjustment(
3728                 struct pp_hwmgr *hwmgr)
3729 {
3730         struct vega10_hwmgr *data = hwmgr->backend;
3731         struct vega10_single_dpm_table *dpm_table =
3732                         &data->dpm_table.dcef_table;
3733         struct phm_ppt_v2_information *table_info =
3734                         (struct phm_ppt_v2_information *)hwmgr->pptable;
3735         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
3736         uint32_t idx;
3737         struct PP_Clocks min_clocks = {0};
3738         uint32_t i;
3739         struct pp_display_clock_request clock_req;
3740
3741         if (hwmgr->display_config->num_display > 1)
3742                 vega10_notify_smc_display_change(hwmgr, false);
3743         else
3744                 vega10_notify_smc_display_change(hwmgr, true);
3745
3746         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3747         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3748         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3749
3750         for (i = 0; i < dpm_table->count; i++) {
3751                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
3752                         break;
3753         }
3754
3755         if (i < dpm_table->count) {
3756                 clock_req.clock_type = amd_pp_dcef_clock;
3757                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
3758                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
3759                         smum_send_msg_to_smc_with_parameter(
3760                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
3761                                         min_clocks.dcefClockInSR / 100);
3762                 } else {
3763                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3764                 }
3765         } else {
3766                 pr_debug("Cannot find requested DCEFCLK!");
3767         }
3768
3769         if (min_clocks.memoryClock != 0) {
3770                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
3771                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
3772                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
3773         }
3774
3775         return 0;
3776 }
3777
3778 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3779 {
3780         struct vega10_hwmgr *data = hwmgr->backend;
3781
3782         data->smc_state_table.gfx_boot_level =
3783         data->smc_state_table.gfx_max_level =
3784                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3785         data->smc_state_table.mem_boot_level =
3786         data->smc_state_table.mem_max_level =
3787                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3788
3789         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3790                         "Failed to upload boot level to highest!",
3791                         return -1);
3792
3793         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3794                         "Failed to upload dpm max level to highest!",
3795                         return -1);
3796
3797         return 0;
3798 }
3799
3800 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3801 {
3802         struct vega10_hwmgr *data = hwmgr->backend;
3803
3804         data->smc_state_table.gfx_boot_level =
3805         data->smc_state_table.gfx_max_level =
3806                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3807         data->smc_state_table.mem_boot_level =
3808         data->smc_state_table.mem_max_level =
3809                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3810
3811         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3812                         "Failed to upload boot level to highest!",
3813                         return -1);
3814
3815         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3816                         "Failed to upload dpm max level to highest!",
3817                         return -1);
3818
3819         return 0;
3820
3821 }
3822
3823 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3824 {
3825         struct vega10_hwmgr *data = hwmgr->backend;
3826
3827         data->smc_state_table.gfx_boot_level =
3828                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3829         data->smc_state_table.gfx_max_level =
3830                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3831         data->smc_state_table.mem_boot_level =
3832                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3833         data->smc_state_table.mem_max_level =
3834                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3835
3836         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3837                         "Failed to upload DPM Bootup Levels!",
3838                         return -1);
3839
3840         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3841                         "Failed to upload DPM Max Levels!",
3842                         return -1);
3843         return 0;
3844 }
3845
3846 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3847                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
3848 {
3849         struct phm_ppt_v2_information *table_info =
3850                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3851
3852         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3853                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
3854                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3855                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
3856                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
3857                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
3858                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3859                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3860         }
3861
3862         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3863                 *sclk_mask = 0;
3864         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3865                 *mclk_mask = 0;
3866         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3867                 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3868                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
3869                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
3870         }
3871         return 0;
3872 }
3873
3874 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
3875 {
3876         switch (mode) {
3877         case AMD_FAN_CTRL_NONE:
3878                 vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
3879                 break;
3880         case AMD_FAN_CTRL_MANUAL:
3881                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3882                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
3883                 break;
3884         case AMD_FAN_CTRL_AUTO:
3885                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3886                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
3887                 break;
3888         default:
3889                 break;
3890         }
3891 }
3892
3893 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
3894                 enum pp_clock_type type, uint32_t mask)
3895 {
3896         struct vega10_hwmgr *data = hwmgr->backend;
3897
3898         switch (type) {
3899         case PP_SCLK:
3900                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
3901                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
3902
3903                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3904                         "Failed to upload boot level to lowest!",
3905                         return -EINVAL);
3906
3907                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3908                         "Failed to upload dpm max level to highest!",
3909                         return -EINVAL);
3910                 break;
3911
3912         case PP_MCLK:
3913                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
3914                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
3915
3916                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3917                         "Failed to upload boot level to lowest!",
3918                         return -EINVAL);
3919
3920                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3921                         "Failed to upload dpm max level to highest!",
3922                         return -EINVAL);
3923
3924                 break;
3925
3926         case PP_PCIE:
3927         default:
3928                 break;
3929         }
3930
3931         return 0;
3932 }
3933
3934 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3935                                 enum amd_dpm_forced_level level)
3936 {
3937         int ret = 0;
3938         uint32_t sclk_mask = 0;
3939         uint32_t mclk_mask = 0;
3940         uint32_t soc_mask = 0;
3941
3942         if (hwmgr->pstate_sclk == 0)
3943                 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
3944
3945         switch (level) {
3946         case AMD_DPM_FORCED_LEVEL_HIGH:
3947                 ret = vega10_force_dpm_highest(hwmgr);
3948                 break;
3949         case AMD_DPM_FORCED_LEVEL_LOW:
3950                 ret = vega10_force_dpm_lowest(hwmgr);
3951                 break;
3952         case AMD_DPM_FORCED_LEVEL_AUTO:
3953                 ret = vega10_unforce_dpm_levels(hwmgr);
3954                 break;
3955         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
3956         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
3957         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
3958         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
3959                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
3960                 if (ret)
3961                         return ret;
3962                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
3963                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
3964                 break;
3965         case AMD_DPM_FORCED_LEVEL_MANUAL:
3966         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
3967         default:
3968                 break;
3969         }
3970
3971         if (!ret) {
3972                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3973                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
3974                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3975                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
3976         }
3977
3978         return ret;
3979 }
3980
3981 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
3982 {
3983         struct vega10_hwmgr *data = hwmgr->backend;
3984
3985         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
3986                 return AMD_FAN_CTRL_MANUAL;
3987         else
3988                 return AMD_FAN_CTRL_AUTO;
3989 }
3990
3991 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
3992                 struct amd_pp_simple_clock_info *info)
3993 {
3994         struct phm_ppt_v2_information *table_info =
3995                         (struct phm_ppt_v2_information *)hwmgr->pptable;
3996         struct phm_clock_and_voltage_limits *max_limits =
3997                         &table_info->max_clock_voltage_on_ac;
3998
3999         info->engine_max_clock = max_limits->sclk;
4000         info->memory_max_clock = max_limits->mclk;
4001
4002         return 0;
4003 }
4004
4005 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4006                 struct pp_clock_levels_with_latency *clocks)
4007 {
4008         struct phm_ppt_v2_information *table_info =
4009                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4010         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4011                         table_info->vdd_dep_on_sclk;
4012         uint32_t i;
4013
4014         for (i = 0; i < dep_table->count; i++) {
4015                 if (dep_table->entries[i].clk) {
4016                         clocks->data[clocks->num_levels].clocks_in_khz =
4017                                         dep_table->entries[i].clk;
4018                         clocks->num_levels++;
4019                 }
4020         }
4021
4022 }
4023
4024 static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
4025                 uint32_t clock)
4026 {
4027         if (clock >= MEM_FREQ_LOW_LATENCY &&
4028                         clock < MEM_FREQ_HIGH_LATENCY)
4029                 return MEM_LATENCY_HIGH;
4030         else if (clock >= MEM_FREQ_HIGH_LATENCY)
4031                 return MEM_LATENCY_LOW;
4032         else
4033                 return MEM_LATENCY_ERR;
4034 }
4035
4036 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4037                 struct pp_clock_levels_with_latency *clocks)
4038 {
4039         struct phm_ppt_v2_information *table_info =
4040                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4041         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4042                         table_info->vdd_dep_on_mclk;
4043         struct vega10_hwmgr *data = hwmgr->backend;
4044         uint32_t i;
4045
4046         clocks->num_levels = 0;
4047         data->mclk_latency_table.count = 0;
4048
4049         for (i = 0; i < dep_table->count; i++) {
4050                 if (dep_table->entries[i].clk) {
4051                         clocks->data[clocks->num_levels].clocks_in_khz =
4052                         data->mclk_latency_table.entries
4053                         [data->mclk_latency_table.count].frequency =
4054                                         dep_table->entries[i].clk;
4055                         clocks->data[clocks->num_levels].latency_in_us =
4056                         data->mclk_latency_table.entries
4057                         [data->mclk_latency_table.count].latency =
4058                                         vega10_get_mem_latency(hwmgr,
4059                                                 dep_table->entries[i].clk);
4060                         clocks->num_levels++;
4061                         data->mclk_latency_table.count++;
4062                 }
4063         }
4064 }
4065
4066 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4067                 struct pp_clock_levels_with_latency *clocks)
4068 {
4069         struct phm_ppt_v2_information *table_info =
4070                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4071         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4072                         table_info->vdd_dep_on_dcefclk;
4073         uint32_t i;
4074
4075         for (i = 0; i < dep_table->count; i++) {
4076                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
4077                 clocks->data[i].latency_in_us = 0;
4078                 clocks->num_levels++;
4079         }
4080 }
4081
4082 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4083                 struct pp_clock_levels_with_latency *clocks)
4084 {
4085         struct phm_ppt_v2_information *table_info =
4086                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4087         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4088                         table_info->vdd_dep_on_socclk;
4089         uint32_t i;
4090
4091         for (i = 0; i < dep_table->count; i++) {
4092                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
4093                 clocks->data[i].latency_in_us = 0;
4094                 clocks->num_levels++;
4095         }
4096 }
4097
4098 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4099                 enum amd_pp_clock_type type,
4100                 struct pp_clock_levels_with_latency *clocks)
4101 {
4102         switch (type) {
4103         case amd_pp_sys_clock:
4104                 vega10_get_sclks(hwmgr, clocks);
4105                 break;
4106         case amd_pp_mem_clock:
4107                 vega10_get_memclocks(hwmgr, clocks);
4108                 break;
4109         case amd_pp_dcef_clock:
4110                 vega10_get_dcefclocks(hwmgr, clocks);
4111                 break;
4112         case amd_pp_soc_clock:
4113                 vega10_get_socclocks(hwmgr, clocks);
4114                 break;
4115         default:
4116                 return -1;
4117         }
4118
4119         return 0;
4120 }
4121
4122 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4123                 enum amd_pp_clock_type type,
4124                 struct pp_clock_levels_with_voltage *clocks)
4125 {
4126         struct phm_ppt_v2_information *table_info =
4127                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4128         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4129         uint32_t i;
4130
4131         switch (type) {
4132         case amd_pp_mem_clock:
4133                 dep_table = table_info->vdd_dep_on_mclk;
4134                 break;
4135         case amd_pp_dcef_clock:
4136                 dep_table = table_info->vdd_dep_on_dcefclk;
4137                 break;
4138         case amd_pp_disp_clock:
4139                 dep_table = table_info->vdd_dep_on_dispclk;
4140                 break;
4141         case amd_pp_pixel_clock:
4142                 dep_table = table_info->vdd_dep_on_pixclk;
4143                 break;
4144         case amd_pp_phy_clock:
4145                 dep_table = table_info->vdd_dep_on_phyclk;
4146                 break;
4147         default:
4148                 return -1;
4149         }
4150
4151         for (i = 0; i < dep_table->count; i++) {
4152                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
4153                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4154                                 entries[dep_table->entries[i].vddInd].us_vdd);
4155                 clocks->num_levels++;
4156         }
4157
4158         if (i < dep_table->count)
4159                 return -1;
4160
4161         return 0;
4162 }
4163
4164 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4165                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
4166 {
4167         struct vega10_hwmgr *data = hwmgr->backend;
4168         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4169         int result = 0;
4170
4171         if (!data->registry_data.disable_water_mark) {
4172                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4173                 data->water_marks_bitmap = WaterMarksExist;
4174         }
4175
4176         return result;
4177 }
4178
4179 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4180                 enum pp_clock_type type, char *buf)
4181 {
4182         struct vega10_hwmgr *data = hwmgr->backend;
4183         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4184         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4185         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4186         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4187
4188         int i, now, size = 0;
4189
4190         switch (type) {
4191         case PP_SCLK:
4192                 if (data->registry_data.sclk_dpm_key_disabled)
4193                         break;
4194
4195                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
4196                 now = smum_get_argument(hwmgr);
4197
4198                 for (i = 0; i < sclk_table->count; i++)
4199                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4200                                         i, sclk_table->dpm_levels[i].value / 100,
4201                                         (i == now) ? "*" : "");
4202                 break;
4203         case PP_MCLK:
4204                 if (data->registry_data.mclk_dpm_key_disabled)
4205                         break;
4206
4207                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
4208                 now = smum_get_argument(hwmgr);
4209
4210                 for (i = 0; i < mclk_table->count; i++)
4211                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4212                                         i, mclk_table->dpm_levels[i].value / 100,
4213                                         (i == now) ? "*" : "");
4214                 break;
4215         case PP_PCIE:
4216                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
4217                 now = smum_get_argument(hwmgr);
4218
4219                 for (i = 0; i < pcie_table->count; i++)
4220                         size += sprintf(buf + size, "%d: %s %s\n", i,
4221                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
4222                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
4223                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
4224                                         (i == now) ? "*" : "");
4225                 break;
4226         case OD_SCLK:
4227                 if (hwmgr->od_enabled) {
4228                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4229                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4230                         for (i = 0; i < podn_vdd_dep->count; i++)
4231                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4232                                         i, podn_vdd_dep->entries[i].clk / 100,
4233                                                 podn_vdd_dep->entries[i].vddc);
4234                 }
4235                 break;
4236         case OD_MCLK:
4237                 if (hwmgr->od_enabled) {
4238                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4239                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4240                         for (i = 0; i < podn_vdd_dep->count; i++)
4241                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4242                                         i, podn_vdd_dep->entries[i].clk/100,
4243                                                 podn_vdd_dep->entries[i].vddc);
4244                 }
4245                 break;
4246         case OD_RANGE:
4247                 if (hwmgr->od_enabled) {
4248                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4249                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4250                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4251                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4252                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4253                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4254                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4255                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4256                                 data->odn_dpm_table.min_vddc,
4257                                 data->odn_dpm_table.max_vddc);
4258                 }
4259                 break;
4260         default:
4261                 break;
4262         }
4263         return size;
4264 }
4265
4266 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4267 {
4268         struct vega10_hwmgr *data = hwmgr->backend;
4269         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4270         int result = 0;
4271
4272         if ((data->water_marks_bitmap & WaterMarksExist) &&
4273                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4274                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4275                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4276                 data->water_marks_bitmap |= WaterMarksLoaded;
4277         }
4278
4279         if (data->water_marks_bitmap & WaterMarksLoaded) {
4280                 smum_send_msg_to_smc_with_parameter(hwmgr,
4281                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
4282         }
4283
4284         return result;
4285 }
4286
4287 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4288 {
4289         struct vega10_hwmgr *data = hwmgr->backend;
4290
4291         if (data->smu_features[GNLD_DPM_UVD].supported) {
4292                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4293                                 enable,
4294                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4295                                 "Attempt to Enable/Disable DPM UVD Failed!",
4296                                 return -1);
4297                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4298         }
4299         return 0;
4300 }
4301
4302 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4303 {
4304         struct vega10_hwmgr *data = hwmgr->backend;
4305
4306         data->vce_power_gated = bgate;
4307         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4308 }
4309
4310 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4311 {
4312         struct vega10_hwmgr *data = hwmgr->backend;
4313
4314         data->uvd_power_gated = bgate;
4315         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4316 }
4317
4318 static inline bool vega10_are_power_levels_equal(
4319                                 const struct vega10_performance_level *pl1,
4320                                 const struct vega10_performance_level *pl2)
4321 {
4322         return ((pl1->soc_clock == pl2->soc_clock) &&
4323                         (pl1->gfx_clock == pl2->gfx_clock) &&
4324                         (pl1->mem_clock == pl2->mem_clock));
4325 }
4326
4327 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4328                                 const struct pp_hw_power_state *pstate1,
4329                         const struct pp_hw_power_state *pstate2, bool *equal)
4330 {
4331         const struct vega10_power_state *psa;
4332         const struct vega10_power_state *psb;
4333         int i;
4334
4335         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4336                 return -EINVAL;
4337
4338         psa = cast_const_phw_vega10_power_state(pstate1);
4339         psb = cast_const_phw_vega10_power_state(pstate2);
4340         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4341         if (psa->performance_level_count != psb->performance_level_count) {
4342                 *equal = false;
4343                 return 0;
4344         }
4345
4346         for (i = 0; i < psa->performance_level_count; i++) {
4347                 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4348                         /* If we have found even one performance level pair that is different the states are different. */
4349                         *equal = false;
4350                         return 0;
4351                 }
4352         }
4353
4354         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4355         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4356         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4357         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4358
4359         return 0;
4360 }
4361
4362 static bool
4363 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4364 {
4365         struct vega10_hwmgr *data = hwmgr->backend;
4366         bool is_update_required = false;
4367
4368         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4369                 is_update_required = true;
4370
4371         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4372                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4373                         is_update_required = true;
4374         }
4375
4376         return is_update_required;
4377 }
4378
4379 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4380 {
4381         int tmp_result, result = 0;
4382
4383         if (PP_CAP(PHM_PlatformCaps_ThermalController))
4384                 vega10_disable_thermal_protection(hwmgr);
4385
4386         tmp_result = vega10_disable_power_containment(hwmgr);
4387         PP_ASSERT_WITH_CODE((tmp_result == 0),
4388                         "Failed to disable power containment!", result = tmp_result);
4389
4390         tmp_result = vega10_disable_didt_config(hwmgr);
4391         PP_ASSERT_WITH_CODE((tmp_result == 0),
4392                         "Failed to disable didt config!", result = tmp_result);
4393
4394         tmp_result = vega10_avfs_enable(hwmgr, false);
4395         PP_ASSERT_WITH_CODE((tmp_result == 0),
4396                         "Failed to disable AVFS!", result = tmp_result);
4397
4398         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
4399         PP_ASSERT_WITH_CODE((tmp_result == 0),
4400                         "Failed to stop DPM!", result = tmp_result);
4401
4402         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
4403         PP_ASSERT_WITH_CODE((tmp_result == 0),
4404                         "Failed to disable deep sleep!", result = tmp_result);
4405
4406         tmp_result = vega10_disable_ulv(hwmgr);
4407         PP_ASSERT_WITH_CODE((tmp_result == 0),
4408                         "Failed to disable ulv!", result = tmp_result);
4409
4410         tmp_result =  vega10_acg_disable(hwmgr);
4411         PP_ASSERT_WITH_CODE((tmp_result == 0),
4412                         "Failed to disable acg!", result = tmp_result);
4413
4414         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
4415         return result;
4416 }
4417
4418 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4419 {
4420         struct vega10_hwmgr *data = hwmgr->backend;
4421         int result;
4422
4423         result = vega10_disable_dpm_tasks(hwmgr);
4424         PP_ASSERT_WITH_CODE((0 == result),
4425                         "[disable_dpm_tasks] Failed to disable DPM!",
4426                         );
4427         data->water_marks_bitmap &= ~(WaterMarksLoaded);
4428
4429         return result;
4430 }
4431
4432 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4433 {
4434         struct vega10_hwmgr *data = hwmgr->backend;
4435         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4436         struct vega10_single_dpm_table *golden_sclk_table =
4437                         &(data->golden_dpm_table.gfx_table);
4438         int value;
4439
4440         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4441                         golden_sclk_table->dpm_levels
4442                         [golden_sclk_table->count - 1].value) *
4443                         100 /
4444                         golden_sclk_table->dpm_levels
4445                         [golden_sclk_table->count - 1].value;
4446
4447         return value;
4448 }
4449
4450 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4451 {
4452         struct vega10_hwmgr *data = hwmgr->backend;
4453         struct vega10_single_dpm_table *golden_sclk_table =
4454                         &(data->golden_dpm_table.gfx_table);
4455         struct pp_power_state *ps;
4456         struct vega10_power_state *vega10_ps;
4457
4458         ps = hwmgr->request_ps;
4459
4460         if (ps == NULL)
4461                 return -EINVAL;
4462
4463         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4464
4465         vega10_ps->performance_levels
4466         [vega10_ps->performance_level_count - 1].gfx_clock =
4467                         golden_sclk_table->dpm_levels
4468                         [golden_sclk_table->count - 1].value *
4469                         value / 100 +
4470                         golden_sclk_table->dpm_levels
4471                         [golden_sclk_table->count - 1].value;
4472
4473         if (vega10_ps->performance_levels
4474                         [vega10_ps->performance_level_count - 1].gfx_clock >
4475                         hwmgr->platform_descriptor.overdriveLimit.engineClock)
4476                 vega10_ps->performance_levels
4477                 [vega10_ps->performance_level_count - 1].gfx_clock =
4478                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
4479
4480         return 0;
4481 }
4482
4483 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4484 {
4485         struct vega10_hwmgr *data = hwmgr->backend;
4486         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4487         struct vega10_single_dpm_table *golden_mclk_table =
4488                         &(data->golden_dpm_table.mem_table);
4489         int value;
4490
4491         value = (mclk_table->dpm_levels
4492                         [mclk_table->count - 1].value -
4493                         golden_mclk_table->dpm_levels
4494                         [golden_mclk_table->count - 1].value) *
4495                         100 /
4496                         golden_mclk_table->dpm_levels
4497                         [golden_mclk_table->count - 1].value;
4498
4499         return value;
4500 }
4501
4502 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4503 {
4504         struct vega10_hwmgr *data = hwmgr->backend;
4505         struct vega10_single_dpm_table *golden_mclk_table =
4506                         &(data->golden_dpm_table.mem_table);
4507         struct pp_power_state  *ps;
4508         struct vega10_power_state  *vega10_ps;
4509
4510         ps = hwmgr->request_ps;
4511
4512         if (ps == NULL)
4513                 return -EINVAL;
4514
4515         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4516
4517         vega10_ps->performance_levels
4518         [vega10_ps->performance_level_count - 1].mem_clock =
4519                         golden_mclk_table->dpm_levels
4520                         [golden_mclk_table->count - 1].value *
4521                         value / 100 +
4522                         golden_mclk_table->dpm_levels
4523                         [golden_mclk_table->count - 1].value;
4524
4525         if (vega10_ps->performance_levels
4526                         [vega10_ps->performance_level_count - 1].mem_clock >
4527                         hwmgr->platform_descriptor.overdriveLimit.memoryClock)
4528                 vega10_ps->performance_levels
4529                 [vega10_ps->performance_level_count - 1].mem_clock =
4530                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4531
4532         return 0;
4533 }
4534
4535 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4536                                         uint32_t virtual_addr_low,
4537                                         uint32_t virtual_addr_hi,
4538                                         uint32_t mc_addr_low,
4539                                         uint32_t mc_addr_hi,
4540                                         uint32_t size)
4541 {
4542         smum_send_msg_to_smc_with_parameter(hwmgr,
4543                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4544                                         virtual_addr_hi);
4545         smum_send_msg_to_smc_with_parameter(hwmgr,
4546                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4547                                         virtual_addr_low);
4548         smum_send_msg_to_smc_with_parameter(hwmgr,
4549                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4550                                         mc_addr_hi);
4551
4552         smum_send_msg_to_smc_with_parameter(hwmgr,
4553                                         PPSMC_MSG_DramLogSetDramAddrLow,
4554                                         mc_addr_low);
4555
4556         smum_send_msg_to_smc_with_parameter(hwmgr,
4557                                         PPSMC_MSG_DramLogSetDramSize,
4558                                         size);
4559         return 0;
4560 }
4561
4562 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4563                 struct PP_TemperatureRange *thermal_data)
4564 {
4565         struct phm_ppt_v2_information *table_info =
4566                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4567
4568         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4569
4570         thermal_data->max = table_info->tdp_table->usSoftwareShutdownTemp *
4571                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4572
4573         return 0;
4574 }
4575
4576 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4577 {
4578         struct vega10_hwmgr *data = hwmgr->backend;
4579         uint32_t i, size = 0;
4580         static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
4581                                                 {90, 60, 0, 0,},
4582                                                 {70, 60, 0, 0,},
4583                                                 {70, 90, 0, 0,},
4584                                                 {30, 60, 0, 6,},
4585                                                 };
4586         static const char *profile_name[6] = {"3D_FULL_SCREEN",
4587                                         "POWER_SAVING",
4588                                         "VIDEO",
4589                                         "VR",
4590                                         "COMPUTE",
4591                                         "CUSTOM"};
4592         static const char *title[6] = {"NUM",
4593                         "MODE_NAME",
4594                         "BUSY_SET_POINT",
4595                         "FPS",
4596                         "USE_RLC_BUSY",
4597                         "MIN_ACTIVE_LEVEL"};
4598
4599         if (!buf)
4600                 return -EINVAL;
4601
4602         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
4603                         title[1], title[2], title[3], title[4], title[5]);
4604
4605         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
4606                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
4607                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4608                         profile_mode_setting[i][0], profile_mode_setting[i][1],
4609                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
4610         size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
4611                         profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4612                         data->custom_profile_mode[0], data->custom_profile_mode[1],
4613                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
4614         return size;
4615 }
4616
4617 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4618 {
4619         struct vega10_hwmgr *data = hwmgr->backend;
4620         uint8_t busy_set_point;
4621         uint8_t FPS;
4622         uint8_t use_rlc_busy;
4623         uint8_t min_active_level;
4624
4625         hwmgr->power_profile_mode = input[size];
4626
4627         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4628                                                 1<<hwmgr->power_profile_mode);
4629
4630         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4631                 if (size == 0 || size > 4)
4632                         return -EINVAL;
4633
4634                 data->custom_profile_mode[0] = busy_set_point = input[0];
4635                 data->custom_profile_mode[1] = FPS = input[1];
4636                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
4637                 data->custom_profile_mode[3] = min_active_level = input[3];
4638                 smum_send_msg_to_smc_with_parameter(hwmgr,
4639                                         PPSMC_MSG_SetCustomGfxDpmParameters,
4640                                         busy_set_point | FPS<<8 |
4641                                         use_rlc_busy << 16 | min_active_level<<24);
4642         }
4643
4644         return 0;
4645 }
4646
4647
4648 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4649                                         enum PP_OD_DPM_TABLE_COMMAND type,
4650                                         uint32_t clk,
4651                                         uint32_t voltage)
4652 {
4653         struct vega10_hwmgr *data = hwmgr->backend;
4654         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4655         struct vega10_single_dpm_table *golden_table;
4656
4657         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
4658                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
4659                 return false;
4660         }
4661
4662         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4663                 golden_table = &(data->golden_dpm_table.gfx_table);
4664                 if (golden_table->dpm_levels[0].value > clk ||
4665                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4666                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4667                                 golden_table->dpm_levels[0].value/100,
4668                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4669                         return false;
4670                 }
4671         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4672                 golden_table = &(data->golden_dpm_table.mem_table);
4673                 if (golden_table->dpm_levels[0].value > clk ||
4674                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4675                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4676                                 golden_table->dpm_levels[0].value/100,
4677                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4678                         return false;
4679                 }
4680         } else {
4681                 return false;
4682         }
4683
4684         return true;
4685 }
4686
4687 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
4688 {
4689         struct vega10_hwmgr *data = hwmgr->backend;
4690         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4691         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
4692         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4693         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
4694         uint32_t i;
4695
4696         dep_table = table_info->vdd_dep_on_mclk;
4697         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
4698
4699         for (i = 0; i < dep_table->count; i++) {
4700                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4701                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
4702                         return;
4703                 }
4704         }
4705
4706         dep_table = table_info->vdd_dep_on_sclk;
4707         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
4708         for (i = 0; i < dep_table->count; i++) {
4709                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4710                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
4711                         return;
4712                 }
4713         }
4714
4715         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
4716                 data->need_update_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
4717                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
4718         }
4719 }
4720
4721 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
4722                                                 enum PP_OD_DPM_TABLE_COMMAND type)
4723 {
4724         struct vega10_hwmgr *data = hwmgr->backend;
4725         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
4726         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
4727         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.soc_table;
4728
4729         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
4730                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
4731         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
4732
4733         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
4734         uint8_t i, j;
4735
4736         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4737                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4738                 for (i = 0; i < podn_vdd_dep->count - 1; i++)
4739                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4740                 if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
4741                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4742         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4743                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4744                 for (i = 0; i < dpm_table->count; i++) {
4745                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
4746                                 if (od_vddc_lookup_table->entries[j].us_vdd >
4747                                         podn_vdd_dep->entries[i].vddc)
4748                                         break;
4749                         }
4750                         if (j == od_vddc_lookup_table->count) {
4751                                 od_vddc_lookup_table->entries[j-1].us_vdd =
4752                                         podn_vdd_dep->entries[i].vddc;
4753                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4754                         }
4755                         podn_vdd_dep->entries[i].vddInd = j;
4756                 }
4757                 dpm_table = &data->dpm_table.soc_table;
4758                 for (i = 0; i < dep_table->count; i++) {
4759                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[dep_table->count-1].vddInd &&
4760                                         dep_table->entries[i].clk < podn_vdd_dep->entries[dep_table->count-1].clk) {
4761                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4762                                 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4763                                 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
4764                         }
4765                 }
4766                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
4767                                         podn_vdd_dep->entries[dep_table->count-1].clk) {
4768                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4769                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4770                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = podn_vdd_dep->entries[dep_table->count-1].clk;
4771                 }
4772                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
4773                                         podn_vdd_dep->entries[dep_table->count-1].vddInd) {
4774                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4775                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = podn_vdd_dep->entries[dep_table->count-1].vddInd;
4776                 }
4777         }
4778 }
4779
4780 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4781                                         enum PP_OD_DPM_TABLE_COMMAND type,
4782                                         long *input, uint32_t size)
4783 {
4784         struct vega10_hwmgr *data = hwmgr->backend;
4785         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
4786         struct vega10_single_dpm_table *dpm_table;
4787
4788         uint32_t input_clk;
4789         uint32_t input_vol;
4790         uint32_t input_level;
4791         uint32_t i;
4792
4793         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4794                                 return -EINVAL);
4795
4796         if (!hwmgr->od_enabled) {
4797                 pr_info("OverDrive feature not enabled\n");
4798                 return -EINVAL;
4799         }
4800
4801         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4802                 dpm_table = &data->dpm_table.gfx_table;
4803                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
4804                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4805         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4806                 dpm_table = &data->dpm_table.mem_table;
4807                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
4808                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4809         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4810                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
4811                 vega10_odn_initial_default_setting(hwmgr);
4812                 return 0;
4813         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4814                 vega10_check_dpm_table_updated(hwmgr);
4815                 return 0;
4816         } else {
4817                 return -EINVAL;
4818         }
4819
4820         for (i = 0; i < size; i += 3) {
4821                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
4822                         pr_info("invalid clock voltage input\n");
4823                         return 0;
4824                 }
4825                 input_level = input[i];
4826                 input_clk = input[i+1] * 100;
4827                 input_vol = input[i+2];
4828
4829                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4830                         dpm_table->dpm_levels[input_level].value = input_clk;
4831                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
4832                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
4833                 } else {
4834                         return -EINVAL;
4835                 }
4836         }
4837         vega10_odn_update_soc_table(hwmgr, type);
4838         return 0;
4839 }
4840
4841 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
4842         .backend_init = vega10_hwmgr_backend_init,
4843         .backend_fini = vega10_hwmgr_backend_fini,
4844         .asic_setup = vega10_setup_asic_task,
4845         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
4846         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
4847         .get_num_of_pp_table_entries =
4848                         vega10_get_number_of_powerplay_table_entries,
4849         .get_power_state_size = vega10_get_power_state_size,
4850         .get_pp_table_entry = vega10_get_pp_table_entry,
4851         .patch_boot_state = vega10_patch_boot_state,
4852         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
4853         .power_state_set = vega10_set_power_state_tasks,
4854         .get_sclk = vega10_dpm_get_sclk,
4855         .get_mclk = vega10_dpm_get_mclk,
4856         .notify_smc_display_config_after_ps_adjustment =
4857                         vega10_notify_smc_display_config_after_ps_adjustment,
4858         .force_dpm_level = vega10_dpm_force_dpm_level,
4859         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
4860         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
4861         .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
4862         .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
4863         .reset_fan_speed_to_default =
4864                         vega10_fan_ctrl_reset_fan_speed_to_default,
4865         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
4866         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
4867         .uninitialize_thermal_controller =
4868                         vega10_thermal_ctrl_uninitialize_thermal_controller,
4869         .set_fan_control_mode = vega10_set_fan_control_mode,
4870         .get_fan_control_mode = vega10_get_fan_control_mode,
4871         .read_sensor = vega10_read_sensor,
4872         .get_dal_power_level = vega10_get_dal_power_level,
4873         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
4874         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
4875         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
4876         .display_clock_voltage_request = vega10_display_clock_voltage_request,
4877         .force_clock_level = vega10_force_clock_level,
4878         .print_clock_levels = vega10_print_clock_levels,
4879         .display_config_changed = vega10_display_configuration_changed_task,
4880         .powergate_uvd = vega10_power_gate_uvd,
4881         .powergate_vce = vega10_power_gate_vce,
4882         .check_states_equal = vega10_check_states_equal,
4883         .check_smc_update_required_for_display_configuration =
4884                         vega10_check_smc_update_required_for_display_configuration,
4885         .power_off_asic = vega10_power_off_asic,
4886         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
4887         .get_sclk_od = vega10_get_sclk_od,
4888         .set_sclk_od = vega10_set_sclk_od,
4889         .get_mclk_od = vega10_get_mclk_od,
4890         .set_mclk_od = vega10_set_mclk_od,
4891         .avfs_control = vega10_avfs_enable,
4892         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
4893         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
4894         .register_irq_handlers = smu9_register_irq_handlers,
4895         .start_thermal_controller = vega10_start_thermal_controller,
4896         .get_power_profile_mode = vega10_get_power_profile_mode,
4897         .set_power_profile_mode = vega10_set_power_profile_mode,
4898         .set_power_limit = vega10_set_power_limit,
4899         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
4900 };
4901
4902 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
4903                 bool enable, uint32_t feature_mask)
4904 {
4905         int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
4906                         PPSMC_MSG_DisableSmuFeatures;
4907
4908         return smum_send_msg_to_smc_with_parameter(hwmgr,
4909                         msg, feature_mask);
4910 }
4911
4912 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
4913 {
4914         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
4915         hwmgr->pptable_func = &vega10_pptable_funcs;
4916
4917         return 0;
4918 }