drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smumgr.h"
  32 #include "hwmgr.h"
  33 #include "hardwaremanager.h"
  34 #include "rv_ppsmc.h"
  35 #include "smu10_hwmgr.h"
  36 #include "power_state.h"
  37 #include "soc15_common.h"
  38
  39 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
  40 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
  41 #define SCLK_MIN_DIV_INTV_SHIFT         12
  42 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
  43 #define SMC_RAM_END                     0x40000
  44
  45 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  46 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  47 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  51
  52 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
  53
  54
  55 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
  56                 struct pp_display_clock_request *clock_req)
  57 {
  58         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
  59         enum amd_pp_clock_type clk_type = clock_req->clock_type;
  60         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
  61         PPSMC_Msg        msg;
  62
  63         switch (clk_type) {
  64         case amd_pp_dcf_clock:
  65                 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
  66                         return 0;
  67                 msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
  68                 smu10_data->dcf_actual_hard_min_freq = clk_freq;
  69                 break;
  70         case amd_pp_soc_clock:
  71                  msg = PPSMC_MSG_SetHardMinSocclkByFreq;
  72                 break;
  73         case amd_pp_f_clock:
  74                 if (clk_freq == smu10_data->f_actual_hard_min_freq)
  75                         return 0;
  76                 smu10_data->f_actual_hard_min_freq = clk_freq;
  77                 msg = PPSMC_MSG_SetHardMinFclkByFreq;
  78                 break;
  79         default:
  80                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
  81                 return -EINVAL;
  82         }
  83         smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);
  84
  85         return 0;
  86 }
  87
  88 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
  89 {
  90         if (SMU10_Magic != hw_ps->magic)
  91                 return NULL;
  92
  93         return (struct smu10_power_state *)hw_ps;
  94 }
  95
  96 static const struct smu10_power_state *cast_const_smu10_ps(
  97                                 const struct pp_hw_power_state *hw_ps)
  98 {
  99         if (SMU10_Magic != hw_ps->magic)
 100                 return NULL;
 101
 102         return (struct smu10_power_state *)hw_ps;
 103 }
 104
 105 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 106 {
 107         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 108
 109         smu10_data->dce_slow_sclk_threshold = 30000;
 110         smu10_data->thermal_auto_throttling_treshold = 0;
 111         smu10_data->is_nb_dpm_enabled = 1;
 112         smu10_data->dpm_flags = 1;
 113         smu10_data->need_min_deep_sleep_dcefclk = true;
 114         smu10_data->num_active_display = 0;
 115         smu10_data->deep_sleep_dcefclk = 0;
 116
 117         if (hwmgr->feature_mask & PP_GFXOFF_MASK)
 118                 smu10_data->gfx_off_controled_by_driver = true;
 119         else
 120                 smu10_data->gfx_off_controled_by_driver = false;
 121
 122         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 123                                         PHM_PlatformCaps_SclkDeepSleep);
 124
 125         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 126                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 127
 128         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 129                                 PHM_PlatformCaps_PowerPlaySupport);
 130         return 0;
 131 }
 132
 133 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 134                         struct phm_clock_and_voltage_limits *table)
 135 {
 136         return 0;
 137 }
 138
 139 static int smu10_init_dynamic_state_adjustment_rule_settings(
 140                                                         struct pp_hwmgr *hwmgr)
 141 {
 142         struct phm_clock_voltage_dependency_table *table_clk_vlt;
 143
 144         table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7),
 145                                 GFP_KERNEL);
 146
 147         if (NULL == table_clk_vlt) {
 148                 pr_err("Can not allocate memory!\n");
 149                 return -ENOMEM;
 150         }
 151
 152         table_clk_vlt->count = 8;
 153         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 154         table_clk_vlt->entries[0].v = 0;
 155         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 156         table_clk_vlt->entries[1].v = 1;
 157         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 158         table_clk_vlt->entries[2].v = 2;
 159         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 160         table_clk_vlt->entries[3].v = 3;
 161         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 162         table_clk_vlt->entries[4].v = 4;
 163         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 164         table_clk_vlt->entries[5].v = 5;
 165         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 166         table_clk_vlt->entries[6].v = 6;
 167         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 168         table_clk_vlt->entries[7].v = 7;
 169         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 170
 171         return 0;
 172 }
 173
 174 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 175 {
 176         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
 177
 178         smu10_data->sys_info.htc_hyst_lmt = 5;
 179         smu10_data->sys_info.htc_tmp_lmt = 203;
 180
 181         if (smu10_data->thermal_auto_throttling_treshold == 0)
 182                  smu10_data->thermal_auto_throttling_treshold = 203;
 183
 184         smu10_construct_max_power_limits_table (hwmgr,
 185                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 186
 187         smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
 188
 189         return 0;
 190 }
 191
 192 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
 193 {
 194         return 0;
 195 }
 196
 197 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
 198 {
 199         struct PP_Clocks clocks = {0};
 200         struct pp_display_clock_request clock_req;
 201
 202         clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 203         clock_req.clock_type = amd_pp_dcf_clock;
 204         clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 205
 206         PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
 207                                 "Attempt to set DCF Clock Failed!", return -EINVAL);
 208
 209         return 0;
 210 }
 211
 212 static inline uint32_t convert_10k_to_mhz(uint32_t clock)
 213 {
 214         return (clock + 99) / 100;
 215 }
 216
 217 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
 218 {
 219         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 220
 221         if (smu10_data->need_min_deep_sleep_dcefclk &&
 222                 smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
 223                 smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
 224                 smum_send_msg_to_smc_with_parameter(hwmgr,
 225                                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 226                                         smu10_data->deep_sleep_dcefclk);
 227         }
 228         return 0;
 229 }
 230
 231 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 232 {
 233         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 234
 235         if (smu10_data->dcf_actual_hard_min_freq &&
 236                 smu10_data->dcf_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
 237                 smu10_data->dcf_actual_hard_min_freq = convert_10k_to_mhz(clock);
 238                 smum_send_msg_to_smc_with_parameter(hwmgr,
 239                                         PPSMC_MSG_SetHardMinDcefclkByFreq,
 240                                         smu10_data->dcf_actual_hard_min_freq);
 241         }
 242         return 0;
 243 }
 244
 245 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 246 {
 247         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 248
 249         if (smu10_data->f_actual_hard_min_freq &&
 250                 smu10_data->f_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
 251                 smu10_data->f_actual_hard_min_freq = convert_10k_to_mhz(clock);
 252                 smum_send_msg_to_smc_with_parameter(hwmgr,
 253                                         PPSMC_MSG_SetHardMinFclkByFreq,
 254                                         smu10_data->f_actual_hard_min_freq);
 255         }
 256         return 0;
 257 }
 258
 259 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
 260 {
 261         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 262
 263         if (smu10_data->num_active_display != count) {
 264                 smu10_data->num_active_display = count;
 265                 smum_send_msg_to_smc_with_parameter(hwmgr,
 266                                 PPSMC_MSG_SetDisplayCount,
 267                                 smu10_data->num_active_display);
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 274 {
 275         return smu10_set_clock_limit(hwmgr, input);
 276 }
 277
 278 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
 279 {
 280         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 281         struct amdgpu_device *adev = hwmgr->adev;
 282
 283         smu10_data->vcn_power_gated = true;
 284         smu10_data->isp_tileA_power_gated = true;
 285         smu10_data->isp_tileB_power_gated = true;
 286
 287         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
 288                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 289                                                            PPSMC_MSG_SetGfxCGPG,
 290                                                            true);
 291         else
 292                 return 0;
 293 }
 294
 295
 296 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
 297 {
 298         return smu10_init_power_gate_state(hwmgr);
 299 }
 300
 301 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
 302 {
 303         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 304
 305         smu10_data->separation_time = 0;
 306         smu10_data->cc6_disable = false;
 307         smu10_data->pstate_disable = false;
 308         smu10_data->cc6_setting_changed = false;
 309
 310         return 0;
 311 }
 312
 313 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
 314 {
 315         return smu10_reset_cc6_data(hwmgr);
 316 }
 317
 318 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 319 {
 320         uint32_t reg;
 321         struct amdgpu_device *adev = hwmgr->adev;
 322
 323         reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
 324         if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
 325             (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
 326                 return true;
 327
 328         return false;
 329 }
 330
 331 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 332 {
 333         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 334
 335         if (smu10_data->gfx_off_controled_by_driver) {
 336                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
 337
 338                 /* confirm gfx is back to "on" state */
 339                 while (!smu10_is_gfx_on(hwmgr))
 340                         msleep(1);
 341         }
 342
 343         return 0;
 344 }
 345
 346 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 347 {
 348         return 0;
 349 }
 350
 351 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 352 {
 353         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 354
 355         if (smu10_data->gfx_off_controled_by_driver)
 356                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);
 357
 358         return 0;
 359 }
 360
 361 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 362 {
 363         return 0;
 364 }
 365
 366 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
 367 {
 368         if (enable)
 369                 return smu10_enable_gfx_off(hwmgr);
 370         else
 371                 return smu10_disable_gfx_off(hwmgr);
 372 }
 373
 374 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 375                                 struct pp_power_state  *prequest_ps,
 376                         const struct pp_power_state *pcurrent_ps)
 377 {
 378         return 0;
 379 }
 380
 381 /* temporary hardcoded clock voltage breakdown tables */
 382 static const DpmClock_t VddDcfClk[]= {
 383         { 300, 2600},
 384         { 600, 3200},
 385         { 600, 3600},
 386 };
 387
 388 static const DpmClock_t VddSocClk[]= {
 389         { 478, 2600},
 390         { 722, 3200},
 391         { 722, 3600},
 392 };
 393
 394 static const DpmClock_t VddFClk[]= {
 395         { 400, 2600},
 396         {1200, 3200},
 397         {1200, 3600},
 398 };
 399
 400 static const DpmClock_t VddDispClk[]= {
 401         { 435, 2600},
 402         { 661, 3200},
 403         {1086, 3600},
 404 };
 405
 406 static const DpmClock_t VddDppClk[]= {
 407         { 435, 2600},
 408         { 661, 3200},
 409         { 661, 3600},
 410 };
 411
 412 static const DpmClock_t VddPhyClk[]= {
 413         { 540, 2600},
 414         { 810, 3200},
 415         { 810, 3600},
 416 };
 417
 418 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 419                         struct smu10_voltage_dependency_table **pptable,
 420                         uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
 421 {
 422         uint32_t table_size, i;
 423         struct smu10_voltage_dependency_table *ptable;
 424
 425         table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry;
 426         ptable = kzalloc(table_size, GFP_KERNEL);
 427
 428         if (NULL == ptable)
 429                 return -ENOMEM;
 430
 431         ptable->count = num_entry;
 432
 433         for (i = 0; i < ptable->count; i++) {
 434                 ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
 435                 ptable->entries[i].vol         = pclk_dependency_table->Vol;
 436                 pclk_dependency_table++;
 437         }
 438
 439         *pptable = ptable;
 440
 441         return 0;
 442 }
 443
 444
 445 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
 446 {
 447         uint32_t result;
 448
 449         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 450         DpmClocks_t  *table = &(smu10_data->clock_table);
 451         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 452
 453         result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
 454
 455         PP_ASSERT_WITH_CODE((0 == result),
 456                         "Attempt to copy clock table from smc failed",
 457                         return result);
 458
 459         if (0 == result && table->DcefClocks[0].Freq != 0) {
 460                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 461                                                 NUM_DCEFCLK_DPM_LEVELS,
 462                                                 &smu10_data->clock_table.DcefClocks[0]);
 463                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 464                                                 NUM_SOCCLK_DPM_LEVELS,
 465                                                 &smu10_data->clock_table.SocClocks[0]);
 466                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 467                                                 NUM_FCLK_DPM_LEVELS,
 468                                                 &smu10_data->clock_table.FClocks[0]);
 469                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
 470                                                 NUM_MEMCLK_DPM_LEVELS,
 471                                                 &smu10_data->clock_table.MemClocks[0]);
 472         } else {
 473                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 474                                                 ARRAY_SIZE(VddDcfClk),
 475                                                 &VddDcfClk[0]);
 476                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 477                                                 ARRAY_SIZE(VddSocClk),
 478                                                 &VddSocClk[0]);
 479                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 480                                                 ARRAY_SIZE(VddFClk),
 481                                                 &VddFClk[0]);
 482         }
 483         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
 484                                         ARRAY_SIZE(VddDispClk),
 485                                         &VddDispClk[0]);
 486         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
 487                                         ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
 488         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 489                                         ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 490
 491         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
 492         result = smum_get_argument(hwmgr);
 493         smu10_data->gfx_min_freq_limit = result / 10 * 1000;
 494
 495         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
 496         result = smum_get_argument(hwmgr);
 497         smu10_data->gfx_max_freq_limit = result / 10 * 1000;
 498
 499         return 0;
 500 }
 501
 502 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 503 {
 504         int result = 0;
 505         struct smu10_hwmgr *data;
 506
 507         data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
 508         if (data == NULL)
 509                 return -ENOMEM;
 510
 511         hwmgr->backend = data;
 512
 513         result = smu10_initialize_dpm_defaults(hwmgr);
 514         if (result != 0) {
 515                 pr_err("smu10_initialize_dpm_defaults failed\n");
 516                 return result;
 517         }
 518
 519         smu10_populate_clock_table(hwmgr);
 520
 521         result = smu10_get_system_info_data(hwmgr);
 522         if (result != 0) {
 523                 pr_err("smu10_get_system_info_data failed\n");
 524                 return result;
 525         }
 526
 527         smu10_construct_boot_state(hwmgr);
 528
 529         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 530                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 531
 532         hwmgr->platform_descriptor.hardwarePerformanceLevels =
 533                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 534
 535         hwmgr->platform_descriptor.vbiosInterruptId = 0;
 536
 537         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 538
 539         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 540
 541         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 542
 543         hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
 544         hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 545
 546         return result;
 547 }
 548
 549 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 550 {
 551         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 552         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 553
 554         kfree(pinfo->vdd_dep_on_dcefclk);
 555         pinfo->vdd_dep_on_dcefclk = NULL;
 556         kfree(pinfo->vdd_dep_on_socclk);
 557         pinfo->vdd_dep_on_socclk = NULL;
 558         kfree(pinfo->vdd_dep_on_fclk);
 559         pinfo->vdd_dep_on_fclk = NULL;
 560         kfree(pinfo->vdd_dep_on_dispclk);
 561         pinfo->vdd_dep_on_dispclk = NULL;
 562         kfree(pinfo->vdd_dep_on_dppclk);
 563         pinfo->vdd_dep_on_dppclk = NULL;
 564         kfree(pinfo->vdd_dep_on_phyclk);
 565         pinfo->vdd_dep_on_phyclk = NULL;
 566
 567         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 568         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 569
 570         kfree(hwmgr->backend);
 571         hwmgr->backend = NULL;
 572
 573         return 0;
 574 }
 575
 576 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 577                                 enum amd_dpm_forced_level level)
 578 {
 579         struct smu10_hwmgr *data = hwmgr->backend;
 580         struct amdgpu_device *adev = hwmgr->adev;
 581         uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
 582         uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
 583
 584         if (hwmgr->smu_version < 0x1E3700) {
 585                 pr_info("smu firmware version too old, can not set dpm level\n");
 586                 return 0;
 587         }
 588
 589         /* Disable UMDPSTATE support on rv2 temporarily */
 590         if ((adev->asic_type == CHIP_RAVEN) &&
 591             (adev->rev_id >= 8))
 592                 return 0;
 593
 594         if (min_sclk < data->gfx_min_freq_limit)
 595                 min_sclk = data->gfx_min_freq_limit;
 596
 597         min_sclk /= 100; /* transfer 10KHz to MHz */
 598         if (min_mclk < data->clock_table.FClocks[0].Freq)
 599                 min_mclk = data->clock_table.FClocks[0].Freq;
 600
 601         switch (level) {
 602         case AMD_DPM_FORCED_LEVEL_HIGH:
 603         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 604                 smum_send_msg_to_smc_with_parameter(hwmgr,
 605                                                 PPSMC_MSG_SetHardMinGfxClk,
 606                                                 data->gfx_max_freq_limit/100);
 607                 smum_send_msg_to_smc_with_parameter(hwmgr,
 608                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 609                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
 610                 smum_send_msg_to_smc_with_parameter(hwmgr,
 611                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 612                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK);
 613                 smum_send_msg_to_smc_with_parameter(hwmgr,
 614                                                 PPSMC_MSG_SetHardMinVcn,
 615                                                 SMU10_UMD_PSTATE_VCE);
 616
 617                 smum_send_msg_to_smc_with_parameter(hwmgr,
 618                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 619                                                 data->gfx_max_freq_limit/100);
 620                 smum_send_msg_to_smc_with_parameter(hwmgr,
 621                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 622                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
 623                 smum_send_msg_to_smc_with_parameter(hwmgr,
 624                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 625                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK);
 626                 smum_send_msg_to_smc_with_parameter(hwmgr,
 627                                                 PPSMC_MSG_SetSoftMaxVcn,
 628                                                 SMU10_UMD_PSTATE_VCE);
 629                 break;
 630         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 631                 smum_send_msg_to_smc_with_parameter(hwmgr,
 632                                                 PPSMC_MSG_SetHardMinGfxClk,
 633                                                 min_sclk);
 634                 smum_send_msg_to_smc_with_parameter(hwmgr,
 635                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 636                                                 min_sclk);
 637                 break;
 638         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 639                 smum_send_msg_to_smc_with_parameter(hwmgr,
 640                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 641                                                 min_mclk);
 642                 smum_send_msg_to_smc_with_parameter(hwmgr,
 643                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 644                                                 min_mclk);
 645                 break;
 646         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 647                 smum_send_msg_to_smc_with_parameter(hwmgr,
 648                                                 PPSMC_MSG_SetHardMinGfxClk,
 649                                                 SMU10_UMD_PSTATE_GFXCLK);
 650                 smum_send_msg_to_smc_with_parameter(hwmgr,
 651                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 652                                                 SMU10_UMD_PSTATE_FCLK);
 653                 smum_send_msg_to_smc_with_parameter(hwmgr,
 654                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 655                                                 SMU10_UMD_PSTATE_SOCCLK);
 656                 smum_send_msg_to_smc_with_parameter(hwmgr,
 657                                                 PPSMC_MSG_SetHardMinVcn,
 658                                                 SMU10_UMD_PSTATE_VCE);
 659
 660                 smum_send_msg_to_smc_with_parameter(hwmgr,
 661                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 662                                                 SMU10_UMD_PSTATE_GFXCLK);
 663                 smum_send_msg_to_smc_with_parameter(hwmgr,
 664                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 665                                                 SMU10_UMD_PSTATE_FCLK);
 666                 smum_send_msg_to_smc_with_parameter(hwmgr,
 667                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 668                                                 SMU10_UMD_PSTATE_SOCCLK);
 669                 smum_send_msg_to_smc_with_parameter(hwmgr,
 670                                                 PPSMC_MSG_SetSoftMaxVcn,
 671                                                 SMU10_UMD_PSTATE_VCE);
 672                 break;
 673         case AMD_DPM_FORCED_LEVEL_AUTO:
 674                 smum_send_msg_to_smc_with_parameter(hwmgr,
 675                                                 PPSMC_MSG_SetHardMinGfxClk,
 676                                                 min_sclk);
 677                 smum_send_msg_to_smc_with_parameter(hwmgr,
 678                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 679                                                 hwmgr->display_config->num_display > 3 ?
 680                                                 SMU10_UMD_PSTATE_PEAK_FCLK :
 681                                                 min_mclk);
 682
 683                 smum_send_msg_to_smc_with_parameter(hwmgr,
 684                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 685                                                 SMU10_UMD_PSTATE_MIN_SOCCLK);
 686                 smum_send_msg_to_smc_with_parameter(hwmgr,
 687                                                 PPSMC_MSG_SetHardMinVcn,
 688                                                 SMU10_UMD_PSTATE_MIN_VCE);
 689
 690                 smum_send_msg_to_smc_with_parameter(hwmgr,
 691                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 692                                                 data->gfx_max_freq_limit/100);
 693                 smum_send_msg_to_smc_with_parameter(hwmgr,
 694                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 695                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
 696                 smum_send_msg_to_smc_with_parameter(hwmgr,
 697                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 698                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK);
 699                 smum_send_msg_to_smc_with_parameter(hwmgr,
 700                                                 PPSMC_MSG_SetSoftMaxVcn,
 701                                                 SMU10_UMD_PSTATE_VCE);
 702                 break;
 703         case AMD_DPM_FORCED_LEVEL_LOW:
 704                 smum_send_msg_to_smc_with_parameter(hwmgr,
 705                                                 PPSMC_MSG_SetHardMinGfxClk,
 706                                                 data->gfx_min_freq_limit/100);
 707                 smum_send_msg_to_smc_with_parameter(hwmgr,
 708                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 709                                                 data->gfx_min_freq_limit/100);
 710                 smum_send_msg_to_smc_with_parameter(hwmgr,
 711                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 712                                                 min_mclk);
 713                 smum_send_msg_to_smc_with_parameter(hwmgr,
 714                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 715                                                 min_mclk);
 716                 break;
 717         case AMD_DPM_FORCED_LEVEL_MANUAL:
 718         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 719         default:
 720                 break;
 721         }
 722         return 0;
 723 }
 724
 725 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 726 {
 727         struct smu10_hwmgr *data;
 728
 729         if (hwmgr == NULL)
 730                 return -EINVAL;
 731
 732         data = (struct smu10_hwmgr *)(hwmgr->backend);
 733
 734         if (low)
 735                 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 736         else
 737                 return data->clock_vol_info.vdd_dep_on_fclk->entries[
 738                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 739 }
 740
 741 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
 742 {
 743         struct smu10_hwmgr *data;
 744
 745         if (hwmgr == NULL)
 746                 return -EINVAL;
 747
 748         data = (struct smu10_hwmgr *)(hwmgr->backend);
 749
 750         if (low)
 751                 return data->gfx_min_freq_limit;
 752         else
 753                 return data->gfx_max_freq_limit;
 754 }
 755
 756 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
 757                                         struct pp_hw_power_state *hw_ps)
 758 {
 759         return 0;
 760 }
 761
 762 static int smu10_dpm_get_pp_table_entry_callback(
 763                                                      struct pp_hwmgr *hwmgr,
 764                                            struct pp_hw_power_state *hw_ps,
 765                                                           unsigned int index,
 766                                                      const void *clock_info)
 767 {
 768         struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
 769
 770         smu10_ps->levels[index].engine_clock = 0;
 771
 772         smu10_ps->levels[index].vddc_index = 0;
 773         smu10_ps->level = index + 1;
 774
 775         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 776                 smu10_ps->levels[index].ds_divider_index = 5;
 777                 smu10_ps->levels[index].ss_divider_index = 5;
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
 784 {
 785         int result;
 786         unsigned long ret = 0;
 787
 788         result = pp_tables_get_num_of_entries(hwmgr, &ret);
 789
 790         return result ? 0 : ret;
 791 }
 792
 793 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 794                     unsigned long entry, struct pp_power_state *ps)
 795 {
 796         int result;
 797         struct smu10_power_state *smu10_ps;
 798
 799         ps->hardware.magic = SMU10_Magic;
 800
 801         smu10_ps = cast_smu10_ps(&(ps->hardware));
 802
 803         result = pp_tables_get_entry(hwmgr, entry, ps,
 804                         smu10_dpm_get_pp_table_entry_callback);
 805
 806         smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
 807         smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
 808
 809         return result;
 810 }
 811
 812 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
 813 {
 814         return sizeof(struct smu10_power_state);
 815 }
 816
 817 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 818 {
 819         return 0;
 820 }
 821
 822
 823 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 824                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 825 {
 826         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 827
 828         if (separation_time != data->separation_time ||
 829                         cc6_disable != data->cc6_disable ||
 830                         pstate_disable != data->pstate_disable) {
 831                 data->separation_time = separation_time;
 832                 data->cc6_disable = cc6_disable;
 833                 data->pstate_disable = pstate_disable;
 834                 data->cc6_setting_changed = true;
 835         }
 836         return 0;
 837 }
 838
 839 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
 840                 struct amd_pp_simple_clock_info *info)
 841 {
 842         return -EINVAL;
 843 }
 844
 845 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 846                 enum pp_clock_type type, uint32_t mask)
 847 {
 848         struct smu10_hwmgr *data = hwmgr->backend;
 849         struct smu10_voltage_dependency_table *mclk_table =
 850                                         data->clock_vol_info.vdd_dep_on_fclk;
 851         uint32_t low, high;
 852
 853         low = mask ? (ffs(mask) - 1) : 0;
 854         high = mask ? (fls(mask) - 1) : 0;
 855
 856         switch (type) {
 857         case PP_SCLK:
 858                 if (low > 2 || high > 2) {
 859                         pr_info("Currently sclk only support 3 levels on RV\n");
 860                         return -EINVAL;
 861                 }
 862
 863                 smum_send_msg_to_smc_with_parameter(hwmgr,
 864                                                 PPSMC_MSG_SetHardMinGfxClk,
 865                                                 low == 2 ? data->gfx_max_freq_limit/100 :
 866                                                 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 867                                                 data->gfx_min_freq_limit/100);
 868
 869                 smum_send_msg_to_smc_with_parameter(hwmgr,
 870                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 871                                                 high == 0 ? data->gfx_min_freq_limit/100 :
 872                                                 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 873                                                 data->gfx_max_freq_limit/100);
 874                 break;
 875
 876         case PP_MCLK:
 877                 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
 878                         return -EINVAL;
 879
 880                 smum_send_msg_to_smc_with_parameter(hwmgr,
 881                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 882                                                 mclk_table->entries[low].clk/100);
 883
 884                 smum_send_msg_to_smc_with_parameter(hwmgr,
 885                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 886                                                 mclk_table->entries[high].clk/100);
 887                 break;
 888
 889         case PP_PCIE:
 890         default:
 891                 break;
 892         }
 893         return 0;
 894 }
 895
 896 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
 897                 enum pp_clock_type type, char *buf)
 898 {
 899         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 900         struct smu10_voltage_dependency_table *mclk_table =
 901                         data->clock_vol_info.vdd_dep_on_fclk;
 902         uint32_t i, now, size = 0;
 903
 904         switch (type) {
 905         case PP_SCLK:
 906                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
 907                 now = smum_get_argument(hwmgr);
 908
 909         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 910                 if (now == data->gfx_max_freq_limit/100)
 911                         i = 2;
 912                 else if (now == data->gfx_min_freq_limit/100)
 913                         i = 0;
 914                 else
 915                         i = 1;
 916
 917                 size += sprintf(buf + size, "0: %uMhz %s\n",
 918                                         data->gfx_min_freq_limit/100,
 919                                         i == 0 ? "*" : "");
 920                 size += sprintf(buf + size, "1: %uMhz %s\n",
 921                                         i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
 922                                         i == 1 ? "*" : "");
 923                 size += sprintf(buf + size, "2: %uMhz %s\n",
 924                                         data->gfx_max_freq_limit/100,
 925                                         i == 2 ? "*" : "");
 926                 break;
 927         case PP_MCLK:
 928                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
 929                 now = smum_get_argument(hwmgr);
 930
 931                 for (i = 0; i < mclk_table->count; i++)
 932                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 933                                         i,
 934                                         mclk_table->entries[i].clk / 100,
 935                                         ((mclk_table->entries[i].clk / 100)
 936                                          == now) ? "*" : "");
 937                 break;
 938         default:
 939                 break;
 940         }
 941
 942         return size;
 943 }
 944
 945 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 946                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 947                                 PHM_PerformanceLevel *level)
 948 {
 949         struct smu10_hwmgr *data;
 950
 951         if (level == NULL || hwmgr == NULL || state == NULL)
 952                 return -EINVAL;
 953
 954         data = (struct smu10_hwmgr *)(hwmgr->backend);
 955
 956         if (index == 0) {
 957                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 958                 level->coreClock = data->gfx_min_freq_limit;
 959         } else {
 960                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
 961                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 962                 level->coreClock = data->gfx_max_freq_limit;
 963         }
 964
 965         level->nonLocalMemoryFreq = 0;
 966         level->nonLocalMemoryWidth = 0;
 967
 968         return 0;
 969 }
 970
 971 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
 972         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 973 {
 974         const struct smu10_power_state *ps = cast_const_smu10_ps(state);
 975
 976         clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
 977         clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
 978
 979         return 0;
 980 }
 981
 982 #define MEM_FREQ_LOW_LATENCY        25000
 983 #define MEM_FREQ_HIGH_LATENCY       80000
 984 #define MEM_LATENCY_HIGH            245
 985 #define MEM_LATENCY_LOW             35
 986 #define MEM_LATENCY_ERR             0xFFFF
 987
 988
 989 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
 990                 uint32_t clock)
 991 {
 992         if (clock >= MEM_FREQ_LOW_LATENCY &&
 993                         clock < MEM_FREQ_HIGH_LATENCY)
 994                 return MEM_LATENCY_HIGH;
 995         else if (clock >= MEM_FREQ_HIGH_LATENCY)
 996                 return MEM_LATENCY_LOW;
 997         else
 998                 return MEM_LATENCY_ERR;
 999 }
1000
1001 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1002                 enum amd_pp_clock_type type,
1003                 struct pp_clock_levels_with_latency *clocks)
1004 {
1005         uint32_t i;
1006         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1007         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1008         struct smu10_voltage_dependency_table *pclk_vol_table;
1009         bool latency_required = false;
1010
1011         if (pinfo == NULL)
1012                 return -EINVAL;
1013
1014         switch (type) {
1015         case amd_pp_mem_clock:
1016                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1017                 latency_required = true;
1018                 break;
1019         case amd_pp_f_clock:
1020                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1021                 latency_required = true;
1022                 break;
1023         case amd_pp_dcf_clock:
1024                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1025                 break;
1026         case amd_pp_disp_clock:
1027                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1028                 break;
1029         case amd_pp_phy_clock:
1030                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1031                 break;
1032         case amd_pp_dpp_clock:
1033                 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1034         default:
1035                 return -EINVAL;
1036         }
1037
1038         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1039                 return -EINVAL;
1040
1041         clocks->num_levels = 0;
1042         for (i = 0; i < pclk_vol_table->count; i++) {
1043                 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1044                 clocks->data[i].latency_in_us = latency_required ?
1045                                                 smu10_get_mem_latency(hwmgr,
1046                                                 pclk_vol_table->entries[i].clk) :
1047                                                 0;
1048                 clocks->num_levels++;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1055                 enum amd_pp_clock_type type,
1056                 struct pp_clock_levels_with_voltage *clocks)
1057 {
1058         uint32_t i;
1059         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1060         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1061         struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1062
1063         if (pinfo == NULL)
1064                 return -EINVAL;
1065
1066         switch (type) {
1067         case amd_pp_mem_clock:
1068                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1069                 break;
1070         case amd_pp_f_clock:
1071                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1072                 break;
1073         case amd_pp_dcf_clock:
1074                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1075                 break;
1076         case amd_pp_soc_clock:
1077                 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1078                 break;
1079         case amd_pp_disp_clock:
1080                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1081                 break;
1082         case amd_pp_phy_clock:
1083                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1084                 break;
1085         default:
1086                 return -EINVAL;
1087         }
1088
1089         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1090                 return -EINVAL;
1091
1092         clocks->num_levels = 0;
1093         for (i = 0; i < pclk_vol_table->count; i++) {
1094                 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
1095                 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
1096                 clocks->num_levels++;
1097         }
1098
1099         return 0;
1100 }
1101
1102
1103
1104 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1105 {
1106         clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1107         return 0;
1108 }
1109
1110 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1111 {
1112         struct amdgpu_device *adev = hwmgr->adev;
1113         uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1114         int cur_temp =
1115                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1116
1117         if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1118                 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1119         else
1120                 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1121
1122         return cur_temp;
1123 }
1124
1125 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1126                           void *value, int *size)
1127 {
1128         uint32_t sclk, mclk;
1129         int ret = 0;
1130
1131         switch (idx) {
1132         case AMDGPU_PP_SENSOR_GFX_SCLK:
1133                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
1134                 sclk = smum_get_argument(hwmgr);
1135                         /* in units of 10KHZ */
1136                 *((uint32_t *)value) = sclk * 100;
1137                 *size = 4;
1138                 break;
1139         case AMDGPU_PP_SENSOR_GFX_MCLK:
1140                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
1141                 mclk = smum_get_argument(hwmgr);
1142                         /* in units of 10KHZ */
1143                 *((uint32_t *)value) = mclk * 100;
1144                 *size = 4;
1145                 break;
1146         case AMDGPU_PP_SENSOR_GPU_TEMP:
1147                 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1148                 break;
1149         default:
1150                 ret = -EINVAL;
1151                 break;
1152         }
1153
1154         return ret;
1155 }
1156
1157 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1158                 void *clock_ranges)
1159 {
1160         struct smu10_hwmgr *data = hwmgr->backend;
1161         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1162         Watermarks_t *table = &(data->water_marks_table);
1163         int result = 0;
1164
1165         smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1166         smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1167         data->water_marks_exist = true;
1168         return result;
1169 }
1170
1171 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1172 {
1173
1174         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);
1175 }
1176
1177 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1178 {
1179         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
1180 }
1181
1182 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1183 {
1184         if (gate)
1185                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);
1186         else
1187                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);
1188 }
1189
1190 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1191 {
1192         if (bgate) {
1193                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1194                                                 AMD_IP_BLOCK_TYPE_VCN,
1195                                                 AMD_PG_STATE_GATE);
1196                 smum_send_msg_to_smc_with_parameter(hwmgr,
1197                                         PPSMC_MSG_PowerDownVcn, 0);
1198         } else {
1199                 smum_send_msg_to_smc_with_parameter(hwmgr,
1200                                                 PPSMC_MSG_PowerUpVcn, 0);
1201                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1202                                                 AMD_IP_BLOCK_TYPE_VCN,
1203                                                 AMD_PG_STATE_UNGATE);
1204         }
1205 }
1206
1207 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1208         .backend_init = smu10_hwmgr_backend_init,
1209         .backend_fini = smu10_hwmgr_backend_fini,
1210         .asic_setup = NULL,
1211         .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1212         .force_dpm_level = smu10_dpm_force_dpm_level,
1213         .get_power_state_size = smu10_get_power_state_size,
1214         .powerdown_uvd = NULL,
1215         .powergate_uvd = smu10_powergate_vcn,
1216         .powergate_vce = NULL,
1217         .get_mclk = smu10_dpm_get_mclk,
1218         .get_sclk = smu10_dpm_get_sclk,
1219         .patch_boot_state = smu10_dpm_patch_boot_state,
1220         .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1221         .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1222         .set_cpu_power_state = smu10_set_cpu_power_state,
1223         .store_cc6_data = smu10_store_cc6_data,
1224         .force_clock_level = smu10_force_clock_level,
1225         .print_clock_levels = smu10_print_clock_levels,
1226         .get_dal_power_level = smu10_get_dal_power_level,
1227         .get_performance_level = smu10_get_performance_level,
1228         .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1229         .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1230         .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1231         .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1232         .get_max_high_clocks = smu10_get_max_high_clocks,
1233         .read_sensor = smu10_read_sensor,
1234         .set_active_display_count = smu10_set_active_display_count,
1235         .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1236         .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1237         .power_off_asic = smu10_power_off_asic,
1238         .asic_setup = smu10_setup_asic_task,
1239         .power_state_set = smu10_set_power_state_tasks,
1240         .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1241         .powergate_mmhub = smu10_powergate_mmhub,
1242         .smus_notify_pwe = smu10_smus_notify_pwe,
1243         .display_clock_voltage_request = smu10_display_clock_voltage_request,
1244         .powergate_gfx = smu10_gfx_off_control,
1245         .powergate_sdma = smu10_powergate_sdma,
1246         .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1247         .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1248 };
1249
1250 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1251 {
1252         hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1253         hwmgr->pptable_func = &pptable_funcs;
1254         return 0;
1255 }