drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smumgr.h"
  32 #include "hwmgr.h"
  33 #include "hardwaremanager.h"
  34 #include "rv_ppsmc.h"
  35 #include "smu10_hwmgr.h"
  36 #include "power_state.h"
  37 #include "soc15_common.h"
  38 #include "smu10.h"
  39 #include "asic_reg/pwr/pwr_10_0_offset.h"
  40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
  41
  42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
  43 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
  44 #define SCLK_MIN_DIV_INTV_SHIFT         12
  45 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
  46 #define SMC_RAM_END                     0x40000
  47
  48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
  49
  50
  51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
  52                 struct pp_display_clock_request *clock_req)
  53 {
  54         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
  55         enum amd_pp_clock_type clk_type = clock_req->clock_type;
  56         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
  57         PPSMC_Msg        msg;
  58
  59         switch (clk_type) {
  60         case amd_pp_dcf_clock:
  61                 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
  62                         return 0;
  63                 msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
  64                 smu10_data->dcf_actual_hard_min_freq = clk_freq;
  65                 break;
  66         case amd_pp_soc_clock:
  67                  msg = PPSMC_MSG_SetHardMinSocclkByFreq;
  68                 break;
  69         case amd_pp_f_clock:
  70                 if (clk_freq == smu10_data->f_actual_hard_min_freq)
  71                         return 0;
  72                 smu10_data->f_actual_hard_min_freq = clk_freq;
  73                 msg = PPSMC_MSG_SetHardMinFclkByFreq;
  74                 break;
  75         default:
  76                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
  77                 return -EINVAL;
  78         }
  79         smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
  80
  81         return 0;
  82 }
  83
  84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
  85 {
  86         if (SMU10_Magic != hw_ps->magic)
  87                 return NULL;
  88
  89         return (struct smu10_power_state *)hw_ps;
  90 }
  91
  92 static const struct smu10_power_state *cast_const_smu10_ps(
  93                                 const struct pp_hw_power_state *hw_ps)
  94 {
  95         if (SMU10_Magic != hw_ps->magic)
  96                 return NULL;
  97
  98         return (struct smu10_power_state *)hw_ps;
  99 }
 100
 101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 102 {
 103         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 104
 105         smu10_data->dce_slow_sclk_threshold = 30000;
 106         smu10_data->thermal_auto_throttling_treshold = 0;
 107         smu10_data->is_nb_dpm_enabled = 1;
 108         smu10_data->dpm_flags = 1;
 109         smu10_data->need_min_deep_sleep_dcefclk = true;
 110         smu10_data->num_active_display = 0;
 111         smu10_data->deep_sleep_dcefclk = 0;
 112
 113         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 114                                         PHM_PlatformCaps_SclkDeepSleep);
 115
 116         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 117                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 118
 119         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 120                                 PHM_PlatformCaps_PowerPlaySupport);
 121         return 0;
 122 }
 123
 124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 125                         struct phm_clock_and_voltage_limits *table)
 126 {
 127         return 0;
 128 }
 129
 130 static int smu10_init_dynamic_state_adjustment_rule_settings(
 131                                                         struct pp_hwmgr *hwmgr)
 132 {
 133         struct phm_clock_voltage_dependency_table *table_clk_vlt;
 134
 135         table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7),
 136                                 GFP_KERNEL);
 137
 138         if (NULL == table_clk_vlt) {
 139                 pr_err("Can not allocate memory!\n");
 140                 return -ENOMEM;
 141         }
 142
 143         table_clk_vlt->count = 8;
 144         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 145         table_clk_vlt->entries[0].v = 0;
 146         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 147         table_clk_vlt->entries[1].v = 1;
 148         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 149         table_clk_vlt->entries[2].v = 2;
 150         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 151         table_clk_vlt->entries[3].v = 3;
 152         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 153         table_clk_vlt->entries[4].v = 4;
 154         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 155         table_clk_vlt->entries[5].v = 5;
 156         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 157         table_clk_vlt->entries[6].v = 6;
 158         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 159         table_clk_vlt->entries[7].v = 7;
 160         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 161
 162         return 0;
 163 }
 164
 165 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 166 {
 167         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
 168
 169         smu10_data->sys_info.htc_hyst_lmt = 5;
 170         smu10_data->sys_info.htc_tmp_lmt = 203;
 171
 172         if (smu10_data->thermal_auto_throttling_treshold == 0)
 173                  smu10_data->thermal_auto_throttling_treshold = 203;
 174
 175         smu10_construct_max_power_limits_table (hwmgr,
 176                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 177
 178         smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
 179
 180         return 0;
 181 }
 182
 183 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
 184 {
 185         return 0;
 186 }
 187
 188 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
 189 {
 190         struct PP_Clocks clocks = {0};
 191         struct pp_display_clock_request clock_req;
 192
 193         clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 194         clock_req.clock_type = amd_pp_dcf_clock;
 195         clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 196
 197         PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
 198                                 "Attempt to set DCF Clock Failed!", return -EINVAL);
 199
 200         return 0;
 201 }
 202
 203 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
 204 {
 205         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 206
 207         if (smu10_data->need_min_deep_sleep_dcefclk &&
 208                 smu10_data->deep_sleep_dcefclk != clock) {
 209                 smu10_data->deep_sleep_dcefclk = clock;
 210                 smum_send_msg_to_smc_with_parameter(hwmgr,
 211                                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 212                                         smu10_data->deep_sleep_dcefclk,
 213                                         NULL);
 214         }
 215         return 0;
 216 }
 217
 218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 219 {
 220         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 221
 222         if (smu10_data->dcf_actual_hard_min_freq &&
 223                 smu10_data->dcf_actual_hard_min_freq != clock) {
 224                 smu10_data->dcf_actual_hard_min_freq = clock;
 225                 smum_send_msg_to_smc_with_parameter(hwmgr,
 226                                         PPSMC_MSG_SetHardMinDcefclkByFreq,
 227                                         smu10_data->dcf_actual_hard_min_freq,
 228                                         NULL);
 229         }
 230         return 0;
 231 }
 232
 233 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 234 {
 235         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 236
 237         if (smu10_data->f_actual_hard_min_freq &&
 238                 smu10_data->f_actual_hard_min_freq != clock) {
 239                 smu10_data->f_actual_hard_min_freq = clock;
 240                 smum_send_msg_to_smc_with_parameter(hwmgr,
 241                                         PPSMC_MSG_SetHardMinFclkByFreq,
 242                                         smu10_data->f_actual_hard_min_freq,
 243                                         NULL);
 244         }
 245         return 0;
 246 }
 247
 248 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
 249 {
 250         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 251
 252         if (smu10_data->num_active_display != count) {
 253                 smu10_data->num_active_display = count;
 254                 smum_send_msg_to_smc_with_parameter(hwmgr,
 255                                 PPSMC_MSG_SetDisplayCount,
 256                                 smu10_data->num_active_display,
 257                                 NULL);
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 264 {
 265         return smu10_set_clock_limit(hwmgr, input);
 266 }
 267
 268 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
 269 {
 270         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 271         struct amdgpu_device *adev = hwmgr->adev;
 272
 273         smu10_data->vcn_power_gated = true;
 274         smu10_data->isp_tileA_power_gated = true;
 275         smu10_data->isp_tileB_power_gated = true;
 276
 277         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
 278                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 279                                                            PPSMC_MSG_SetGfxCGPG,
 280                                                            true,
 281                                                            NULL);
 282         else
 283                 return 0;
 284 }
 285
 286
 287 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
 288 {
 289         return smu10_init_power_gate_state(hwmgr);
 290 }
 291
 292 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
 293 {
 294         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 295
 296         smu10_data->separation_time = 0;
 297         smu10_data->cc6_disable = false;
 298         smu10_data->pstate_disable = false;
 299         smu10_data->cc6_setting_changed = false;
 300
 301         return 0;
 302 }
 303
 304 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
 305 {
 306         return smu10_reset_cc6_data(hwmgr);
 307 }
 308
 309 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 310 {
 311         uint32_t reg;
 312         struct amdgpu_device *adev = hwmgr->adev;
 313
 314         reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
 315         if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
 316             (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
 317                 return true;
 318
 319         return false;
 320 }
 321
 322 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 323 {
 324         struct amdgpu_device *adev = hwmgr->adev;
 325
 326         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 327                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
 328
 329                 /* confirm gfx is back to "on" state */
 330                 while (!smu10_is_gfx_on(hwmgr))
 331                         msleep(1);
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 338 {
 339         return 0;
 340 }
 341
 342 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 343 {
 344         struct amdgpu_device *adev = hwmgr->adev;
 345
 346         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 347                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
 348
 349         return 0;
 350 }
 351
 352 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 353 {
 354         return 0;
 355 }
 356
 357 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
 358 {
 359         if (enable)
 360                 return smu10_enable_gfx_off(hwmgr);
 361         else
 362                 return smu10_disable_gfx_off(hwmgr);
 363 }
 364
 365 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 366                                 struct pp_power_state  *prequest_ps,
 367                         const struct pp_power_state *pcurrent_ps)
 368 {
 369         return 0;
 370 }
 371
 372 /* temporary hardcoded clock voltage breakdown tables */
 373 static const DpmClock_t VddDcfClk[]= {
 374         { 300, 2600},
 375         { 600, 3200},
 376         { 600, 3600},
 377 };
 378
 379 static const DpmClock_t VddSocClk[]= {
 380         { 478, 2600},
 381         { 722, 3200},
 382         { 722, 3600},
 383 };
 384
 385 static const DpmClock_t VddFClk[]= {
 386         { 400, 2600},
 387         {1200, 3200},
 388         {1200, 3600},
 389 };
 390
 391 static const DpmClock_t VddDispClk[]= {
 392         { 435, 2600},
 393         { 661, 3200},
 394         {1086, 3600},
 395 };
 396
 397 static const DpmClock_t VddDppClk[]= {
 398         { 435, 2600},
 399         { 661, 3200},
 400         { 661, 3600},
 401 };
 402
 403 static const DpmClock_t VddPhyClk[]= {
 404         { 540, 2600},
 405         { 810, 3200},
 406         { 810, 3600},
 407 };
 408
 409 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 410                         struct smu10_voltage_dependency_table **pptable,
 411                         uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
 412 {
 413         uint32_t i;
 414         struct smu10_voltage_dependency_table *ptable;
 415
 416         ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
 417         if (NULL == ptable)
 418                 return -ENOMEM;
 419
 420         ptable->count = num_entry;
 421
 422         for (i = 0; i < ptable->count; i++) {
 423                 ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
 424                 ptable->entries[i].vol         = pclk_dependency_table->Vol;
 425                 pclk_dependency_table++;
 426         }
 427
 428         *pptable = ptable;
 429
 430         return 0;
 431 }
 432
 433
 434 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
 435 {
 436         uint32_t result;
 437
 438         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 439         DpmClocks_t  *table = &(smu10_data->clock_table);
 440         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 441
 442         result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
 443
 444         PP_ASSERT_WITH_CODE((0 == result),
 445                         "Attempt to copy clock table from smc failed",
 446                         return result);
 447
 448         if (0 == result && table->DcefClocks[0].Freq != 0) {
 449                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 450                                                 NUM_DCEFCLK_DPM_LEVELS,
 451                                                 &smu10_data->clock_table.DcefClocks[0]);
 452                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 453                                                 NUM_SOCCLK_DPM_LEVELS,
 454                                                 &smu10_data->clock_table.SocClocks[0]);
 455                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 456                                                 NUM_FCLK_DPM_LEVELS,
 457                                                 &smu10_data->clock_table.FClocks[0]);
 458                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
 459                                                 NUM_MEMCLK_DPM_LEVELS,
 460                                                 &smu10_data->clock_table.MemClocks[0]);
 461         } else {
 462                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 463                                                 ARRAY_SIZE(VddDcfClk),
 464                                                 &VddDcfClk[0]);
 465                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 466                                                 ARRAY_SIZE(VddSocClk),
 467                                                 &VddSocClk[0]);
 468                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 469                                                 ARRAY_SIZE(VddFClk),
 470                                                 &VddFClk[0]);
 471         }
 472         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
 473                                         ARRAY_SIZE(VddDispClk),
 474                                         &VddDispClk[0]);
 475         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
 476                                         ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
 477         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 478                                         ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 479
 480         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
 481         smu10_data->gfx_min_freq_limit = result / 10 * 1000;
 482
 483         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
 484         smu10_data->gfx_max_freq_limit = result / 10 * 1000;
 485
 486         return 0;
 487 }
 488
 489 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 490 {
 491         int result = 0;
 492         struct smu10_hwmgr *data;
 493
 494         data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
 495         if (data == NULL)
 496                 return -ENOMEM;
 497
 498         hwmgr->backend = data;
 499
 500         result = smu10_initialize_dpm_defaults(hwmgr);
 501         if (result != 0) {
 502                 pr_err("smu10_initialize_dpm_defaults failed\n");
 503                 return result;
 504         }
 505
 506         smu10_populate_clock_table(hwmgr);
 507
 508         result = smu10_get_system_info_data(hwmgr);
 509         if (result != 0) {
 510                 pr_err("smu10_get_system_info_data failed\n");
 511                 return result;
 512         }
 513
 514         smu10_construct_boot_state(hwmgr);
 515
 516         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 517                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 518
 519         hwmgr->platform_descriptor.hardwarePerformanceLevels =
 520                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 521
 522         hwmgr->platform_descriptor.vbiosInterruptId = 0;
 523
 524         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 525
 526         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 527
 528         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 529
 530         hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
 531         hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 532
 533         return result;
 534 }
 535
 536 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 537 {
 538         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 539         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 540
 541         kfree(pinfo->vdd_dep_on_dcefclk);
 542         pinfo->vdd_dep_on_dcefclk = NULL;
 543         kfree(pinfo->vdd_dep_on_socclk);
 544         pinfo->vdd_dep_on_socclk = NULL;
 545         kfree(pinfo->vdd_dep_on_fclk);
 546         pinfo->vdd_dep_on_fclk = NULL;
 547         kfree(pinfo->vdd_dep_on_dispclk);
 548         pinfo->vdd_dep_on_dispclk = NULL;
 549         kfree(pinfo->vdd_dep_on_dppclk);
 550         pinfo->vdd_dep_on_dppclk = NULL;
 551         kfree(pinfo->vdd_dep_on_phyclk);
 552         pinfo->vdd_dep_on_phyclk = NULL;
 553
 554         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 555         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 556
 557         kfree(hwmgr->backend);
 558         hwmgr->backend = NULL;
 559
 560         return 0;
 561 }
 562
 563 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 564                                 enum amd_dpm_forced_level level)
 565 {
 566         struct smu10_hwmgr *data = hwmgr->backend;
 567         uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
 568         uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
 569
 570         if (hwmgr->smu_version < 0x1E3700) {
 571                 pr_info("smu firmware version too old, can not set dpm level\n");
 572                 return 0;
 573         }
 574
 575         if (min_sclk < data->gfx_min_freq_limit)
 576                 min_sclk = data->gfx_min_freq_limit;
 577
 578         min_sclk /= 100; /* transfer 10KHz to MHz */
 579         if (min_mclk < data->clock_table.FClocks[0].Freq)
 580                 min_mclk = data->clock_table.FClocks[0].Freq;
 581
 582         switch (level) {
 583         case AMD_DPM_FORCED_LEVEL_HIGH:
 584         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 585                 smum_send_msg_to_smc_with_parameter(hwmgr,
 586                                                 PPSMC_MSG_SetHardMinGfxClk,
 587                                                 data->gfx_max_freq_limit/100,
 588                                                 NULL);
 589                 smum_send_msg_to_smc_with_parameter(hwmgr,
 590                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 591                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 592                                                 NULL);
 593                 smum_send_msg_to_smc_with_parameter(hwmgr,
 594                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 595                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 596                                                 NULL);
 597                 smum_send_msg_to_smc_with_parameter(hwmgr,
 598                                                 PPSMC_MSG_SetHardMinVcn,
 599                                                 SMU10_UMD_PSTATE_VCE,
 600                                                 NULL);
 601
 602                 smum_send_msg_to_smc_with_parameter(hwmgr,
 603                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 604                                                 data->gfx_max_freq_limit/100,
 605                                                 NULL);
 606                 smum_send_msg_to_smc_with_parameter(hwmgr,
 607                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 608                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 609                                                 NULL);
 610                 smum_send_msg_to_smc_with_parameter(hwmgr,
 611                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 612                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 613                                                 NULL);
 614                 smum_send_msg_to_smc_with_parameter(hwmgr,
 615                                                 PPSMC_MSG_SetSoftMaxVcn,
 616                                                 SMU10_UMD_PSTATE_VCE,
 617                                                 NULL);
 618                 break;
 619         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 620                 smum_send_msg_to_smc_with_parameter(hwmgr,
 621                                                 PPSMC_MSG_SetHardMinGfxClk,
 622                                                 min_sclk,
 623                                                 NULL);
 624                 smum_send_msg_to_smc_with_parameter(hwmgr,
 625                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 626                                                 min_sclk,
 627                                                 NULL);
 628                 break;
 629         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 630                 smum_send_msg_to_smc_with_parameter(hwmgr,
 631                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 632                                                 min_mclk,
 633                                                 NULL);
 634                 smum_send_msg_to_smc_with_parameter(hwmgr,
 635                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 636                                                 min_mclk,
 637                                                 NULL);
 638                 break;
 639         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 640                 smum_send_msg_to_smc_with_parameter(hwmgr,
 641                                                 PPSMC_MSG_SetHardMinGfxClk,
 642                                                 SMU10_UMD_PSTATE_GFXCLK,
 643                                                 NULL);
 644                 smum_send_msg_to_smc_with_parameter(hwmgr,
 645                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 646                                                 SMU10_UMD_PSTATE_FCLK,
 647                                                 NULL);
 648                 smum_send_msg_to_smc_with_parameter(hwmgr,
 649                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 650                                                 SMU10_UMD_PSTATE_SOCCLK,
 651                                                 NULL);
 652                 smum_send_msg_to_smc_with_parameter(hwmgr,
 653                                                 PPSMC_MSG_SetHardMinVcn,
 654                                                 SMU10_UMD_PSTATE_VCE,
 655                                                 NULL);
 656
 657                 smum_send_msg_to_smc_with_parameter(hwmgr,
 658                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 659                                                 SMU10_UMD_PSTATE_GFXCLK,
 660                                                 NULL);
 661                 smum_send_msg_to_smc_with_parameter(hwmgr,
 662                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 663                                                 SMU10_UMD_PSTATE_FCLK,
 664                                                 NULL);
 665                 smum_send_msg_to_smc_with_parameter(hwmgr,
 666                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 667                                                 SMU10_UMD_PSTATE_SOCCLK,
 668                                                 NULL);
 669                 smum_send_msg_to_smc_with_parameter(hwmgr,
 670                                                 PPSMC_MSG_SetSoftMaxVcn,
 671                                                 SMU10_UMD_PSTATE_VCE,
 672                                                 NULL);
 673                 break;
 674         case AMD_DPM_FORCED_LEVEL_AUTO:
 675                 smum_send_msg_to_smc_with_parameter(hwmgr,
 676                                                 PPSMC_MSG_SetHardMinGfxClk,
 677                                                 min_sclk,
 678                                                 NULL);
 679                 smum_send_msg_to_smc_with_parameter(hwmgr,
 680                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 681                                                 hwmgr->display_config->num_display > 3 ?
 682                                                 SMU10_UMD_PSTATE_PEAK_FCLK :
 683                                                 min_mclk,
 684                                                 NULL);
 685
 686                 smum_send_msg_to_smc_with_parameter(hwmgr,
 687                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 688                                                 SMU10_UMD_PSTATE_MIN_SOCCLK,
 689                                                 NULL);
 690                 smum_send_msg_to_smc_with_parameter(hwmgr,
 691                                                 PPSMC_MSG_SetHardMinVcn,
 692                                                 SMU10_UMD_PSTATE_MIN_VCE,
 693                                                 NULL);
 694
 695                 smum_send_msg_to_smc_with_parameter(hwmgr,
 696                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 697                                                 data->gfx_max_freq_limit/100,
 698                                                 NULL);
 699                 smum_send_msg_to_smc_with_parameter(hwmgr,
 700                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 701                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 702                                                 NULL);
 703                 smum_send_msg_to_smc_with_parameter(hwmgr,
 704                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 705                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 706                                                 NULL);
 707                 smum_send_msg_to_smc_with_parameter(hwmgr,
 708                                                 PPSMC_MSG_SetSoftMaxVcn,
 709                                                 SMU10_UMD_PSTATE_VCE,
 710                                                 NULL);
 711                 break;
 712         case AMD_DPM_FORCED_LEVEL_LOW:
 713                 smum_send_msg_to_smc_with_parameter(hwmgr,
 714                                                 PPSMC_MSG_SetHardMinGfxClk,
 715                                                 data->gfx_min_freq_limit/100,
 716                                                 NULL);
 717                 smum_send_msg_to_smc_with_parameter(hwmgr,
 718                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 719                                                 data->gfx_min_freq_limit/100,
 720                                                 NULL);
 721                 smum_send_msg_to_smc_with_parameter(hwmgr,
 722                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 723                                                 min_mclk,
 724                                                 NULL);
 725                 smum_send_msg_to_smc_with_parameter(hwmgr,
 726                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 727                                                 min_mclk,
 728                                                 NULL);
 729                 break;
 730         case AMD_DPM_FORCED_LEVEL_MANUAL:
 731         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 732         default:
 733                 break;
 734         }
 735         return 0;
 736 }
 737
 738 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 739 {
 740         struct smu10_hwmgr *data;
 741
 742         if (hwmgr == NULL)
 743                 return -EINVAL;
 744
 745         data = (struct smu10_hwmgr *)(hwmgr->backend);
 746
 747         if (low)
 748                 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 749         else
 750                 return data->clock_vol_info.vdd_dep_on_fclk->entries[
 751                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 752 }
 753
 754 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
 755 {
 756         struct smu10_hwmgr *data;
 757
 758         if (hwmgr == NULL)
 759                 return -EINVAL;
 760
 761         data = (struct smu10_hwmgr *)(hwmgr->backend);
 762
 763         if (low)
 764                 return data->gfx_min_freq_limit;
 765         else
 766                 return data->gfx_max_freq_limit;
 767 }
 768
 769 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
 770                                         struct pp_hw_power_state *hw_ps)
 771 {
 772         return 0;
 773 }
 774
 775 static int smu10_dpm_get_pp_table_entry_callback(
 776                                                      struct pp_hwmgr *hwmgr,
 777                                            struct pp_hw_power_state *hw_ps,
 778                                                           unsigned int index,
 779                                                      const void *clock_info)
 780 {
 781         struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
 782
 783         smu10_ps->levels[index].engine_clock = 0;
 784
 785         smu10_ps->levels[index].vddc_index = 0;
 786         smu10_ps->level = index + 1;
 787
 788         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 789                 smu10_ps->levels[index].ds_divider_index = 5;
 790                 smu10_ps->levels[index].ss_divider_index = 5;
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
 797 {
 798         int result;
 799         unsigned long ret = 0;
 800
 801         result = pp_tables_get_num_of_entries(hwmgr, &ret);
 802
 803         return result ? 0 : ret;
 804 }
 805
 806 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 807                     unsigned long entry, struct pp_power_state *ps)
 808 {
 809         int result;
 810         struct smu10_power_state *smu10_ps;
 811
 812         ps->hardware.magic = SMU10_Magic;
 813
 814         smu10_ps = cast_smu10_ps(&(ps->hardware));
 815
 816         result = pp_tables_get_entry(hwmgr, entry, ps,
 817                         smu10_dpm_get_pp_table_entry_callback);
 818
 819         smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
 820         smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
 821
 822         return result;
 823 }
 824
 825 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
 826 {
 827         return sizeof(struct smu10_power_state);
 828 }
 829
 830 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 831 {
 832         return 0;
 833 }
 834
 835
 836 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 837                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 838 {
 839         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 840
 841         if (separation_time != data->separation_time ||
 842                         cc6_disable != data->cc6_disable ||
 843                         pstate_disable != data->pstate_disable) {
 844                 data->separation_time = separation_time;
 845                 data->cc6_disable = cc6_disable;
 846                 data->pstate_disable = pstate_disable;
 847                 data->cc6_setting_changed = true;
 848         }
 849         return 0;
 850 }
 851
 852 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
 853                 struct amd_pp_simple_clock_info *info)
 854 {
 855         return -EINVAL;
 856 }
 857
 858 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 859                 enum pp_clock_type type, uint32_t mask)
 860 {
 861         struct smu10_hwmgr *data = hwmgr->backend;
 862         struct smu10_voltage_dependency_table *mclk_table =
 863                                         data->clock_vol_info.vdd_dep_on_fclk;
 864         uint32_t low, high;
 865
 866         low = mask ? (ffs(mask) - 1) : 0;
 867         high = mask ? (fls(mask) - 1) : 0;
 868
 869         switch (type) {
 870         case PP_SCLK:
 871                 if (low > 2 || high > 2) {
 872                         pr_info("Currently sclk only support 3 levels on RV\n");
 873                         return -EINVAL;
 874                 }
 875
 876                 smum_send_msg_to_smc_with_parameter(hwmgr,
 877                                                 PPSMC_MSG_SetHardMinGfxClk,
 878                                                 low == 2 ? data->gfx_max_freq_limit/100 :
 879                                                 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 880                                                 data->gfx_min_freq_limit/100,
 881                                                 NULL);
 882
 883                 smum_send_msg_to_smc_with_parameter(hwmgr,
 884                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 885                                                 high == 0 ? data->gfx_min_freq_limit/100 :
 886                                                 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 887                                                 data->gfx_max_freq_limit/100,
 888                                                 NULL);
 889                 break;
 890
 891         case PP_MCLK:
 892                 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
 893                         return -EINVAL;
 894
 895                 smum_send_msg_to_smc_with_parameter(hwmgr,
 896                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 897                                                 mclk_table->entries[low].clk/100,
 898                                                 NULL);
 899
 900                 smum_send_msg_to_smc_with_parameter(hwmgr,
 901                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 902                                                 mclk_table->entries[high].clk/100,
 903                                                 NULL);
 904                 break;
 905
 906         case PP_PCIE:
 907         default:
 908                 break;
 909         }
 910         return 0;
 911 }
 912
 913 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
 914                 enum pp_clock_type type, char *buf)
 915 {
 916         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 917         struct smu10_voltage_dependency_table *mclk_table =
 918                         data->clock_vol_info.vdd_dep_on_fclk;
 919         uint32_t i, now, size = 0;
 920
 921         switch (type) {
 922         case PP_SCLK:
 923                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
 924
 925         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 926                 if (now == data->gfx_max_freq_limit/100)
 927                         i = 2;
 928                 else if (now == data->gfx_min_freq_limit/100)
 929                         i = 0;
 930                 else
 931                         i = 1;
 932
 933                 size += sprintf(buf + size, "0: %uMhz %s\n",
 934                                         data->gfx_min_freq_limit/100,
 935                                         i == 0 ? "*" : "");
 936                 size += sprintf(buf + size, "1: %uMhz %s\n",
 937                                         i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
 938                                         i == 1 ? "*" : "");
 939                 size += sprintf(buf + size, "2: %uMhz %s\n",
 940                                         data->gfx_max_freq_limit/100,
 941                                         i == 2 ? "*" : "");
 942                 break;
 943         case PP_MCLK:
 944                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
 945
 946                 for (i = 0; i < mclk_table->count; i++)
 947                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 948                                         i,
 949                                         mclk_table->entries[i].clk / 100,
 950                                         ((mclk_table->entries[i].clk / 100)
 951                                          == now) ? "*" : "");
 952                 break;
 953         default:
 954                 break;
 955         }
 956
 957         return size;
 958 }
 959
 960 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 961                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 962                                 PHM_PerformanceLevel *level)
 963 {
 964         struct smu10_hwmgr *data;
 965
 966         if (level == NULL || hwmgr == NULL || state == NULL)
 967                 return -EINVAL;
 968
 969         data = (struct smu10_hwmgr *)(hwmgr->backend);
 970
 971         if (index == 0) {
 972                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 973                 level->coreClock = data->gfx_min_freq_limit;
 974         } else {
 975                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
 976                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 977                 level->coreClock = data->gfx_max_freq_limit;
 978         }
 979
 980         level->nonLocalMemoryFreq = 0;
 981         level->nonLocalMemoryWidth = 0;
 982
 983         return 0;
 984 }
 985
 986 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
 987         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 988 {
 989         const struct smu10_power_state *ps = cast_const_smu10_ps(state);
 990
 991         clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
 992         clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
 993
 994         return 0;
 995 }
 996
 997 #define MEM_FREQ_LOW_LATENCY        25000
 998 #define MEM_FREQ_HIGH_LATENCY       80000
 999 #define MEM_LATENCY_HIGH            245
1000 #define MEM_LATENCY_LOW             35
1001 #define MEM_LATENCY_ERR             0xFFFF
1002
1003
1004 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1005                 uint32_t clock)
1006 {
1007         if (clock >= MEM_FREQ_LOW_LATENCY &&
1008                         clock < MEM_FREQ_HIGH_LATENCY)
1009                 return MEM_LATENCY_HIGH;
1010         else if (clock >= MEM_FREQ_HIGH_LATENCY)
1011                 return MEM_LATENCY_LOW;
1012         else
1013                 return MEM_LATENCY_ERR;
1014 }
1015
1016 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1017                 enum amd_pp_clock_type type,
1018                 struct pp_clock_levels_with_latency *clocks)
1019 {
1020         uint32_t i;
1021         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1022         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1023         struct smu10_voltage_dependency_table *pclk_vol_table;
1024         bool latency_required = false;
1025
1026         if (pinfo == NULL)
1027                 return -EINVAL;
1028
1029         switch (type) {
1030         case amd_pp_mem_clock:
1031                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1032                 latency_required = true;
1033                 break;
1034         case amd_pp_f_clock:
1035                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1036                 latency_required = true;
1037                 break;
1038         case amd_pp_dcf_clock:
1039                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1040                 break;
1041         case amd_pp_disp_clock:
1042                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1043                 break;
1044         case amd_pp_phy_clock:
1045                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1046                 break;
1047         case amd_pp_dpp_clock:
1048                 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1049                 break;
1050         default:
1051                 return -EINVAL;
1052         }
1053
1054         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1055                 return -EINVAL;
1056
1057         clocks->num_levels = 0;
1058         for (i = 0; i < pclk_vol_table->count; i++) {
1059                 if (pclk_vol_table->entries[i].clk) {
1060                         clocks->data[clocks->num_levels].clocks_in_khz =
1061                                 pclk_vol_table->entries[i].clk * 10;
1062                         clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1063                                 smu10_get_mem_latency(hwmgr,
1064                                                       pclk_vol_table->entries[i].clk) :
1065                                 0;
1066                         clocks->num_levels++;
1067                 }
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1074                 enum amd_pp_clock_type type,
1075                 struct pp_clock_levels_with_voltage *clocks)
1076 {
1077         uint32_t i;
1078         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1079         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1080         struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1081
1082         if (pinfo == NULL)
1083                 return -EINVAL;
1084
1085         switch (type) {
1086         case amd_pp_mem_clock:
1087                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1088                 break;
1089         case amd_pp_f_clock:
1090                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1091                 break;
1092         case amd_pp_dcf_clock:
1093                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1094                 break;
1095         case amd_pp_soc_clock:
1096                 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1097                 break;
1098         case amd_pp_disp_clock:
1099                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1100                 break;
1101         case amd_pp_phy_clock:
1102                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1103                 break;
1104         default:
1105                 return -EINVAL;
1106         }
1107
1108         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1109                 return -EINVAL;
1110
1111         clocks->num_levels = 0;
1112         for (i = 0; i < pclk_vol_table->count; i++) {
1113                 if (pclk_vol_table->entries[i].clk) {
1114                         clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
1115                         clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1116                         clocks->num_levels++;
1117                 }
1118         }
1119
1120         return 0;
1121 }
1122
1123
1124
1125 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1126 {
1127         clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1128         return 0;
1129 }
1130
1131 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1132 {
1133         struct amdgpu_device *adev = hwmgr->adev;
1134         uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1135         int cur_temp =
1136                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1137
1138         if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1139                 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1140         else
1141                 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1142
1143         return cur_temp;
1144 }
1145
1146 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1147                           void *value, int *size)
1148 {
1149         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1150         uint32_t sclk, mclk;
1151         int ret = 0;
1152
1153         switch (idx) {
1154         case AMDGPU_PP_SENSOR_GFX_SCLK:
1155                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1156                         /* in units of 10KHZ */
1157                 *((uint32_t *)value) = sclk * 100;
1158                 *size = 4;
1159                 break;
1160         case AMDGPU_PP_SENSOR_GFX_MCLK:
1161                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1162                         /* in units of 10KHZ */
1163                 *((uint32_t *)value) = mclk * 100;
1164                 *size = 4;
1165                 break;
1166         case AMDGPU_PP_SENSOR_GPU_TEMP:
1167                 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1168                 break;
1169         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1170                 *(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
1171                 *size = 4;
1172                 break;
1173         default:
1174                 ret = -EINVAL;
1175                 break;
1176         }
1177
1178         return ret;
1179 }
1180
1181 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1182                 void *clock_ranges)
1183 {
1184         struct smu10_hwmgr *data = hwmgr->backend;
1185         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1186         Watermarks_t *table = &(data->water_marks_table);
1187
1188         smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1189         smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1190         data->water_marks_exist = true;
1191         return 0;
1192 }
1193
1194 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1195 {
1196
1197         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1198 }
1199
1200 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1201 {
1202         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1203 }
1204
1205 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1206 {
1207         if (gate)
1208                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1209         else
1210                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1211 }
1212
1213 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1214 {
1215         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1216
1217         if (bgate) {
1218                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1219                                                 AMD_IP_BLOCK_TYPE_VCN,
1220                                                 AMD_PG_STATE_GATE);
1221                 smum_send_msg_to_smc_with_parameter(hwmgr,
1222                                         PPSMC_MSG_PowerDownVcn, 0, NULL);
1223                 smu10_data->vcn_power_gated = true;
1224         } else {
1225                 smum_send_msg_to_smc_with_parameter(hwmgr,
1226                                                 PPSMC_MSG_PowerUpVcn, 0, NULL);
1227                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1228                                                 AMD_IP_BLOCK_TYPE_VCN,
1229                                                 AMD_PG_STATE_UNGATE);
1230                 smu10_data->vcn_power_gated = false;
1231         }
1232 }
1233
1234 static int conv_power_profile_to_pplib_workload(int power_profile)
1235 {
1236         int pplib_workload = 0;
1237
1238         switch (power_profile) {
1239         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
1240                 pplib_workload = WORKLOAD_DEFAULT_BIT;
1241                 break;
1242         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1243                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1244                 break;
1245         case PP_SMC_POWER_PROFILE_POWERSAVING:
1246                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
1247                 break;
1248         case PP_SMC_POWER_PROFILE_VIDEO:
1249                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1250                 break;
1251         case PP_SMC_POWER_PROFILE_VR:
1252                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1253                 break;
1254         case PP_SMC_POWER_PROFILE_COMPUTE:
1255                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1256                 break;
1257         }
1258
1259         return pplib_workload;
1260 }
1261
1262 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1263 {
1264         uint32_t i, size = 0;
1265         static const uint8_t
1266                 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1267                                                 {70, 60, 1, 3,},
1268                                                 {90, 60, 0, 0,},
1269                                                 {70, 60, 0, 0,},
1270                                                 {70, 90, 0, 0,},
1271                                                 {30, 60, 0, 6,},
1272                                                 };
1273         static const char *profile_name[6] = {
1274                                         "BOOTUP_DEFAULT",
1275                                         "3D_FULL_SCREEN",
1276                                         "POWER_SAVING",
1277                                         "VIDEO",
1278                                         "VR",
1279                                         "COMPUTE"};
1280         static const char *title[6] = {"NUM",
1281                         "MODE_NAME",
1282                         "BUSY_SET_POINT",
1283                         "FPS",
1284                         "USE_RLC_BUSY",
1285                         "MIN_ACTIVE_LEVEL"};
1286
1287         if (!buf)
1288                 return -EINVAL;
1289
1290         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
1291                         title[1], title[2], title[3], title[4], title[5]);
1292
1293         for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1294                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
1295                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1296                         profile_mode_setting[i][0], profile_mode_setting[i][1],
1297                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
1298
1299         return size;
1300 }
1301
1302 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1303 {
1304         struct amdgpu_device *adev = hwmgr->adev;
1305         if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1306             (hwmgr->smu_version >= 0x41e2b))
1307                 return true;
1308         else
1309                 return false;
1310 }
1311
1312 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1313 {
1314         int workload_type = 0;
1315         int result = 0;
1316
1317         if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1318                 pr_err("Invalid power profile mode %ld\n", input[size]);
1319                 return -EINVAL;
1320         }
1321         if (hwmgr->power_profile_mode == input[size])
1322                 return 0;
1323
1324         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1325         workload_type =
1326                 conv_power_profile_to_pplib_workload(input[size]);
1327         if (workload_type &&
1328             smu10_is_raven1_refresh(hwmgr) &&
1329             !hwmgr->gfxoff_state_changed_by_workload) {
1330                 smu10_gfx_off_control(hwmgr, false);
1331                 hwmgr->gfxoff_state_changed_by_workload = true;
1332         }
1333         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1334                                                 1 << workload_type,
1335                                                 NULL);
1336         if (!result)
1337                 hwmgr->power_profile_mode = input[size];
1338         if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1339                 smu10_gfx_off_control(hwmgr, true);
1340                 hwmgr->gfxoff_state_changed_by_workload = false;
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1347 {
1348         return smum_send_msg_to_smc_with_parameter(hwmgr,
1349                                                    PPSMC_MSG_DeviceDriverReset,
1350                                                    mode,
1351                                                    NULL);
1352 }
1353
1354 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1355         .backend_init = smu10_hwmgr_backend_init,
1356         .backend_fini = smu10_hwmgr_backend_fini,
1357         .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1358         .force_dpm_level = smu10_dpm_force_dpm_level,
1359         .get_power_state_size = smu10_get_power_state_size,
1360         .powerdown_uvd = NULL,
1361         .powergate_uvd = smu10_powergate_vcn,
1362         .powergate_vce = NULL,
1363         .get_mclk = smu10_dpm_get_mclk,
1364         .get_sclk = smu10_dpm_get_sclk,
1365         .patch_boot_state = smu10_dpm_patch_boot_state,
1366         .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1367         .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1368         .set_cpu_power_state = smu10_set_cpu_power_state,
1369         .store_cc6_data = smu10_store_cc6_data,
1370         .force_clock_level = smu10_force_clock_level,
1371         .print_clock_levels = smu10_print_clock_levels,
1372         .get_dal_power_level = smu10_get_dal_power_level,
1373         .get_performance_level = smu10_get_performance_level,
1374         .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1375         .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1376         .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1377         .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1378         .get_max_high_clocks = smu10_get_max_high_clocks,
1379         .read_sensor = smu10_read_sensor,
1380         .set_active_display_count = smu10_set_active_display_count,
1381         .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1382         .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1383         .power_off_asic = smu10_power_off_asic,
1384         .asic_setup = smu10_setup_asic_task,
1385         .power_state_set = smu10_set_power_state_tasks,
1386         .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1387         .powergate_mmhub = smu10_powergate_mmhub,
1388         .smus_notify_pwe = smu10_smus_notify_pwe,
1389         .display_clock_voltage_request = smu10_display_clock_voltage_request,
1390         .powergate_gfx = smu10_gfx_off_control,
1391         .powergate_sdma = smu10_powergate_sdma,
1392         .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1393         .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1394         .get_power_profile_mode = smu10_get_power_profile_mode,
1395         .set_power_profile_mode = smu10_set_power_profile_mode,
1396         .asic_reset = smu10_asic_reset,
1397 };
1398
1399 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1400 {
1401         hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1402         hwmgr->pptable_func = &pptable_funcs;
1403         return 0;
1404 }