drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smumgr.h"
  32 #include "hwmgr.h"
  33 #include "hardwaremanager.h"
  34 #include "rv_ppsmc.h"
  35 #include "smu10_hwmgr.h"
  36 #include "power_state.h"
  37 #include "soc15_common.h"
  38 #include "smu10.h"
  39 #include "asic_reg/pwr/pwr_10_0_offset.h"
  40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
  41
  42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
  43 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
  44 #define SCLK_MIN_DIV_INTV_SHIFT         12
  45 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
  46 #define SMC_RAM_END                     0x40000
  47
  48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
  49
  50
  51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
  52                 struct pp_display_clock_request *clock_req)
  53 {
  54         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
  55         enum amd_pp_clock_type clk_type = clock_req->clock_type;
  56         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
  57         PPSMC_Msg        msg;
  58
  59         switch (clk_type) {
  60         case amd_pp_dcf_clock:
  61                 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
  62                         return 0;
  63                 msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
  64                 smu10_data->dcf_actual_hard_min_freq = clk_freq;
  65                 break;
  66         case amd_pp_soc_clock:
  67                  msg = PPSMC_MSG_SetHardMinSocclkByFreq;
  68                 break;
  69         case amd_pp_f_clock:
  70                 if (clk_freq == smu10_data->f_actual_hard_min_freq)
  71                         return 0;
  72                 smu10_data->f_actual_hard_min_freq = clk_freq;
  73                 msg = PPSMC_MSG_SetHardMinFclkByFreq;
  74                 break;
  75         default:
  76                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
  77                 return -EINVAL;
  78         }
  79         smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
  80
  81         return 0;
  82 }
  83
  84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
  85 {
  86         if (SMU10_Magic != hw_ps->magic)
  87                 return NULL;
  88
  89         return (struct smu10_power_state *)hw_ps;
  90 }
  91
  92 static const struct smu10_power_state *cast_const_smu10_ps(
  93                                 const struct pp_hw_power_state *hw_ps)
  94 {
  95         if (SMU10_Magic != hw_ps->magic)
  96                 return NULL;
  97
  98         return (struct smu10_power_state *)hw_ps;
  99 }
 100
 101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 102 {
 103         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 104
 105         smu10_data->dce_slow_sclk_threshold = 30000;
 106         smu10_data->thermal_auto_throttling_treshold = 0;
 107         smu10_data->is_nb_dpm_enabled = 1;
 108         smu10_data->dpm_flags = 1;
 109         smu10_data->need_min_deep_sleep_dcefclk = true;
 110         smu10_data->num_active_display = 0;
 111         smu10_data->deep_sleep_dcefclk = 0;
 112
 113         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 114                                         PHM_PlatformCaps_SclkDeepSleep);
 115
 116         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 117                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 118
 119         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 120                                 PHM_PlatformCaps_PowerPlaySupport);
 121         return 0;
 122 }
 123
 124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 125                         struct phm_clock_and_voltage_limits *table)
 126 {
 127         return 0;
 128 }
 129
 130 static int smu10_init_dynamic_state_adjustment_rule_settings(
 131                                                         struct pp_hwmgr *hwmgr)
 132 {
 133         struct phm_clock_voltage_dependency_table *table_clk_vlt;
 134
 135         table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7),
 136                                 GFP_KERNEL);
 137
 138         if (NULL == table_clk_vlt) {
 139                 pr_err("Can not allocate memory!\n");
 140                 return -ENOMEM;
 141         }
 142
 143         table_clk_vlt->count = 8;
 144         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 145         table_clk_vlt->entries[0].v = 0;
 146         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 147         table_clk_vlt->entries[1].v = 1;
 148         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 149         table_clk_vlt->entries[2].v = 2;
 150         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 151         table_clk_vlt->entries[3].v = 3;
 152         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 153         table_clk_vlt->entries[4].v = 4;
 154         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 155         table_clk_vlt->entries[5].v = 5;
 156         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 157         table_clk_vlt->entries[6].v = 6;
 158         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 159         table_clk_vlt->entries[7].v = 7;
 160         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 161
 162         return 0;
 163 }
 164
 165 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 166 {
 167         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
 168
 169         smu10_data->sys_info.htc_hyst_lmt = 5;
 170         smu10_data->sys_info.htc_tmp_lmt = 203;
 171
 172         if (smu10_data->thermal_auto_throttling_treshold == 0)
 173                  smu10_data->thermal_auto_throttling_treshold = 203;
 174
 175         smu10_construct_max_power_limits_table (hwmgr,
 176                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 177
 178         smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
 179
 180         return 0;
 181 }
 182
 183 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
 184 {
 185         return 0;
 186 }
 187
 188 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
 189 {
 190         struct PP_Clocks clocks = {0};
 191         struct pp_display_clock_request clock_req;
 192
 193         clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 194         clock_req.clock_type = amd_pp_dcf_clock;
 195         clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 196
 197         PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
 198                                 "Attempt to set DCF Clock Failed!", return -EINVAL);
 199
 200         return 0;
 201 }
 202
 203 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
 204 {
 205         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 206
 207         if (smu10_data->need_min_deep_sleep_dcefclk &&
 208                 smu10_data->deep_sleep_dcefclk != clock) {
 209                 smu10_data->deep_sleep_dcefclk = clock;
 210                 smum_send_msg_to_smc_with_parameter(hwmgr,
 211                                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 212                                         smu10_data->deep_sleep_dcefclk,
 213                                         NULL);
 214         }
 215         return 0;
 216 }
 217
 218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 219 {
 220         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 221
 222         if (smu10_data->dcf_actual_hard_min_freq &&
 223                 smu10_data->dcf_actual_hard_min_freq != clock) {
 224                 smu10_data->dcf_actual_hard_min_freq = clock;
 225                 smum_send_msg_to_smc_with_parameter(hwmgr,
 226                                         PPSMC_MSG_SetHardMinDcefclkByFreq,
 227                                         smu10_data->dcf_actual_hard_min_freq,
 228                                         NULL);
 229         }
 230         return 0;
 231 }
 232
 233 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 234 {
 235         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 236
 237         if (smu10_data->f_actual_hard_min_freq &&
 238                 smu10_data->f_actual_hard_min_freq != clock) {
 239                 smu10_data->f_actual_hard_min_freq = clock;
 240                 smum_send_msg_to_smc_with_parameter(hwmgr,
 241                                         PPSMC_MSG_SetHardMinFclkByFreq,
 242                                         smu10_data->f_actual_hard_min_freq,
 243                                         NULL);
 244         }
 245         return 0;
 246 }
 247
 248 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
 249 {
 250         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 251
 252         if (smu10_data->num_active_display != count) {
 253                 smu10_data->num_active_display = count;
 254                 smum_send_msg_to_smc_with_parameter(hwmgr,
 255                                 PPSMC_MSG_SetDisplayCount,
 256                                 smu10_data->num_active_display,
 257                                 NULL);
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 264 {
 265         return smu10_set_clock_limit(hwmgr, input);
 266 }
 267
 268 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
 269 {
 270         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 271         struct amdgpu_device *adev = hwmgr->adev;
 272
 273         smu10_data->vcn_power_gated = true;
 274         smu10_data->isp_tileA_power_gated = true;
 275         smu10_data->isp_tileB_power_gated = true;
 276
 277         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
 278                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 279                                                            PPSMC_MSG_SetGfxCGPG,
 280                                                            true,
 281                                                            NULL);
 282         else
 283                 return 0;
 284 }
 285
 286
 287 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
 288 {
 289         return smu10_init_power_gate_state(hwmgr);
 290 }
 291
 292 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
 293 {
 294         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 295
 296         smu10_data->separation_time = 0;
 297         smu10_data->cc6_disable = false;
 298         smu10_data->pstate_disable = false;
 299         smu10_data->cc6_setting_changed = false;
 300
 301         return 0;
 302 }
 303
 304 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
 305 {
 306         return smu10_reset_cc6_data(hwmgr);
 307 }
 308
 309 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 310 {
 311         uint32_t reg;
 312         struct amdgpu_device *adev = hwmgr->adev;
 313
 314         reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
 315         if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
 316             (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
 317                 return true;
 318
 319         return false;
 320 }
 321
 322 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 323 {
 324         struct amdgpu_device *adev = hwmgr->adev;
 325
 326         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 327                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
 328
 329                 /* confirm gfx is back to "on" state */
 330                 while (!smu10_is_gfx_on(hwmgr))
 331                         msleep(1);
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 338 {
 339         return 0;
 340 }
 341
 342 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 343 {
 344         struct amdgpu_device *adev = hwmgr->adev;
 345
 346         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 347                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
 348
 349         return 0;
 350 }
 351
 352 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 353 {
 354         return 0;
 355 }
 356
 357 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
 358 {
 359         if (enable)
 360                 return smu10_enable_gfx_off(hwmgr);
 361         else
 362                 return smu10_disable_gfx_off(hwmgr);
 363 }
 364
 365 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 366                                 struct pp_power_state  *prequest_ps,
 367                         const struct pp_power_state *pcurrent_ps)
 368 {
 369         return 0;
 370 }
 371
 372 /* temporary hardcoded clock voltage breakdown tables */
 373 static const DpmClock_t VddDcfClk[]= {
 374         { 300, 2600},
 375         { 600, 3200},
 376         { 600, 3600},
 377 };
 378
 379 static const DpmClock_t VddSocClk[]= {
 380         { 478, 2600},
 381         { 722, 3200},
 382         { 722, 3600},
 383 };
 384
 385 static const DpmClock_t VddFClk[]= {
 386         { 400, 2600},
 387         {1200, 3200},
 388         {1200, 3600},
 389 };
 390
 391 static const DpmClock_t VddDispClk[]= {
 392         { 435, 2600},
 393         { 661, 3200},
 394         {1086, 3600},
 395 };
 396
 397 static const DpmClock_t VddDppClk[]= {
 398         { 435, 2600},
 399         { 661, 3200},
 400         { 661, 3600},
 401 };
 402
 403 static const DpmClock_t VddPhyClk[]= {
 404         { 540, 2600},
 405         { 810, 3200},
 406         { 810, 3600},
 407 };
 408
 409 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 410                         struct smu10_voltage_dependency_table **pptable,
 411                         uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
 412 {
 413         uint32_t table_size, i;
 414         struct smu10_voltage_dependency_table *ptable;
 415
 416         table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry;
 417         ptable = kzalloc(table_size, GFP_KERNEL);
 418
 419         if (NULL == ptable)
 420                 return -ENOMEM;
 421
 422         ptable->count = num_entry;
 423
 424         for (i = 0; i < ptable->count; i++) {
 425                 ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
 426                 ptable->entries[i].vol         = pclk_dependency_table->Vol;
 427                 pclk_dependency_table++;
 428         }
 429
 430         *pptable = ptable;
 431
 432         return 0;
 433 }
 434
 435
 436 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
 437 {
 438         uint32_t result;
 439
 440         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 441         DpmClocks_t  *table = &(smu10_data->clock_table);
 442         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 443
 444         result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
 445
 446         PP_ASSERT_WITH_CODE((0 == result),
 447                         "Attempt to copy clock table from smc failed",
 448                         return result);
 449
 450         if (0 == result && table->DcefClocks[0].Freq != 0) {
 451                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 452                                                 NUM_DCEFCLK_DPM_LEVELS,
 453                                                 &smu10_data->clock_table.DcefClocks[0]);
 454                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 455                                                 NUM_SOCCLK_DPM_LEVELS,
 456                                                 &smu10_data->clock_table.SocClocks[0]);
 457                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 458                                                 NUM_FCLK_DPM_LEVELS,
 459                                                 &smu10_data->clock_table.FClocks[0]);
 460                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
 461                                                 NUM_MEMCLK_DPM_LEVELS,
 462                                                 &smu10_data->clock_table.MemClocks[0]);
 463         } else {
 464                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 465                                                 ARRAY_SIZE(VddDcfClk),
 466                                                 &VddDcfClk[0]);
 467                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 468                                                 ARRAY_SIZE(VddSocClk),
 469                                                 &VddSocClk[0]);
 470                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 471                                                 ARRAY_SIZE(VddFClk),
 472                                                 &VddFClk[0]);
 473         }
 474         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
 475                                         ARRAY_SIZE(VddDispClk),
 476                                         &VddDispClk[0]);
 477         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
 478                                         ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
 479         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 480                                         ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 481
 482         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
 483         smu10_data->gfx_min_freq_limit = result / 10 * 1000;
 484
 485         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
 486         smu10_data->gfx_max_freq_limit = result / 10 * 1000;
 487
 488         return 0;
 489 }
 490
 491 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 492 {
 493         int result = 0;
 494         struct smu10_hwmgr *data;
 495
 496         data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
 497         if (data == NULL)
 498                 return -ENOMEM;
 499
 500         hwmgr->backend = data;
 501
 502         result = smu10_initialize_dpm_defaults(hwmgr);
 503         if (result != 0) {
 504                 pr_err("smu10_initialize_dpm_defaults failed\n");
 505                 return result;
 506         }
 507
 508         smu10_populate_clock_table(hwmgr);
 509
 510         result = smu10_get_system_info_data(hwmgr);
 511         if (result != 0) {
 512                 pr_err("smu10_get_system_info_data failed\n");
 513                 return result;
 514         }
 515
 516         smu10_construct_boot_state(hwmgr);
 517
 518         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 519                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 520
 521         hwmgr->platform_descriptor.hardwarePerformanceLevels =
 522                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 523
 524         hwmgr->platform_descriptor.vbiosInterruptId = 0;
 525
 526         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 527
 528         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 529
 530         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 531
 532         hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
 533         hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 534
 535         return result;
 536 }
 537
 538 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 539 {
 540         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 541         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 542
 543         kfree(pinfo->vdd_dep_on_dcefclk);
 544         pinfo->vdd_dep_on_dcefclk = NULL;
 545         kfree(pinfo->vdd_dep_on_socclk);
 546         pinfo->vdd_dep_on_socclk = NULL;
 547         kfree(pinfo->vdd_dep_on_fclk);
 548         pinfo->vdd_dep_on_fclk = NULL;
 549         kfree(pinfo->vdd_dep_on_dispclk);
 550         pinfo->vdd_dep_on_dispclk = NULL;
 551         kfree(pinfo->vdd_dep_on_dppclk);
 552         pinfo->vdd_dep_on_dppclk = NULL;
 553         kfree(pinfo->vdd_dep_on_phyclk);
 554         pinfo->vdd_dep_on_phyclk = NULL;
 555
 556         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 557         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 558
 559         kfree(hwmgr->backend);
 560         hwmgr->backend = NULL;
 561
 562         return 0;
 563 }
 564
 565 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 566                                 enum amd_dpm_forced_level level)
 567 {
 568         struct smu10_hwmgr *data = hwmgr->backend;
 569         uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
 570         uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
 571
 572         if (hwmgr->smu_version < 0x1E3700) {
 573                 pr_info("smu firmware version too old, can not set dpm level\n");
 574                 return 0;
 575         }
 576
 577         if (min_sclk < data->gfx_min_freq_limit)
 578                 min_sclk = data->gfx_min_freq_limit;
 579
 580         min_sclk /= 100; /* transfer 10KHz to MHz */
 581         if (min_mclk < data->clock_table.FClocks[0].Freq)
 582                 min_mclk = data->clock_table.FClocks[0].Freq;
 583
 584         switch (level) {
 585         case AMD_DPM_FORCED_LEVEL_HIGH:
 586         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 587                 smum_send_msg_to_smc_with_parameter(hwmgr,
 588                                                 PPSMC_MSG_SetHardMinGfxClk,
 589                                                 data->gfx_max_freq_limit/100,
 590                                                 NULL);
 591                 smum_send_msg_to_smc_with_parameter(hwmgr,
 592                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 593                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 594                                                 NULL);
 595                 smum_send_msg_to_smc_with_parameter(hwmgr,
 596                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 597                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 598                                                 NULL);
 599                 smum_send_msg_to_smc_with_parameter(hwmgr,
 600                                                 PPSMC_MSG_SetHardMinVcn,
 601                                                 SMU10_UMD_PSTATE_VCE,
 602                                                 NULL);
 603
 604                 smum_send_msg_to_smc_with_parameter(hwmgr,
 605                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 606                                                 data->gfx_max_freq_limit/100,
 607                                                 NULL);
 608                 smum_send_msg_to_smc_with_parameter(hwmgr,
 609                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 610                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 611                                                 NULL);
 612                 smum_send_msg_to_smc_with_parameter(hwmgr,
 613                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 614                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 615                                                 NULL);
 616                 smum_send_msg_to_smc_with_parameter(hwmgr,
 617                                                 PPSMC_MSG_SetSoftMaxVcn,
 618                                                 SMU10_UMD_PSTATE_VCE,
 619                                                 NULL);
 620                 break;
 621         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 622                 smum_send_msg_to_smc_with_parameter(hwmgr,
 623                                                 PPSMC_MSG_SetHardMinGfxClk,
 624                                                 min_sclk,
 625                                                 NULL);
 626                 smum_send_msg_to_smc_with_parameter(hwmgr,
 627                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 628                                                 min_sclk,
 629                                                 NULL);
 630                 break;
 631         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 632                 smum_send_msg_to_smc_with_parameter(hwmgr,
 633                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 634                                                 min_mclk,
 635                                                 NULL);
 636                 smum_send_msg_to_smc_with_parameter(hwmgr,
 637                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 638                                                 min_mclk,
 639                                                 NULL);
 640                 break;
 641         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 642                 smum_send_msg_to_smc_with_parameter(hwmgr,
 643                                                 PPSMC_MSG_SetHardMinGfxClk,
 644                                                 SMU10_UMD_PSTATE_GFXCLK,
 645                                                 NULL);
 646                 smum_send_msg_to_smc_with_parameter(hwmgr,
 647                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 648                                                 SMU10_UMD_PSTATE_FCLK,
 649                                                 NULL);
 650                 smum_send_msg_to_smc_with_parameter(hwmgr,
 651                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 652                                                 SMU10_UMD_PSTATE_SOCCLK,
 653                                                 NULL);
 654                 smum_send_msg_to_smc_with_parameter(hwmgr,
 655                                                 PPSMC_MSG_SetHardMinVcn,
 656                                                 SMU10_UMD_PSTATE_VCE,
 657                                                 NULL);
 658
 659                 smum_send_msg_to_smc_with_parameter(hwmgr,
 660                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 661                                                 SMU10_UMD_PSTATE_GFXCLK,
 662                                                 NULL);
 663                 smum_send_msg_to_smc_with_parameter(hwmgr,
 664                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 665                                                 SMU10_UMD_PSTATE_FCLK,
 666                                                 NULL);
 667                 smum_send_msg_to_smc_with_parameter(hwmgr,
 668                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 669                                                 SMU10_UMD_PSTATE_SOCCLK,
 670                                                 NULL);
 671                 smum_send_msg_to_smc_with_parameter(hwmgr,
 672                                                 PPSMC_MSG_SetSoftMaxVcn,
 673                                                 SMU10_UMD_PSTATE_VCE,
 674                                                 NULL);
 675                 break;
 676         case AMD_DPM_FORCED_LEVEL_AUTO:
 677                 smum_send_msg_to_smc_with_parameter(hwmgr,
 678                                                 PPSMC_MSG_SetHardMinGfxClk,
 679                                                 min_sclk,
 680                                                 NULL);
 681                 smum_send_msg_to_smc_with_parameter(hwmgr,
 682                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 683                                                 hwmgr->display_config->num_display > 3 ?
 684                                                 SMU10_UMD_PSTATE_PEAK_FCLK :
 685                                                 min_mclk,
 686                                                 NULL);
 687
 688                 smum_send_msg_to_smc_with_parameter(hwmgr,
 689                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 690                                                 SMU10_UMD_PSTATE_MIN_SOCCLK,
 691                                                 NULL);
 692                 smum_send_msg_to_smc_with_parameter(hwmgr,
 693                                                 PPSMC_MSG_SetHardMinVcn,
 694                                                 SMU10_UMD_PSTATE_MIN_VCE,
 695                                                 NULL);
 696
 697                 smum_send_msg_to_smc_with_parameter(hwmgr,
 698                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 699                                                 data->gfx_max_freq_limit/100,
 700                                                 NULL);
 701                 smum_send_msg_to_smc_with_parameter(hwmgr,
 702                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 703                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 704                                                 NULL);
 705                 smum_send_msg_to_smc_with_parameter(hwmgr,
 706                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 707                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 708                                                 NULL);
 709                 smum_send_msg_to_smc_with_parameter(hwmgr,
 710                                                 PPSMC_MSG_SetSoftMaxVcn,
 711                                                 SMU10_UMD_PSTATE_VCE,
 712                                                 NULL);
 713                 break;
 714         case AMD_DPM_FORCED_LEVEL_LOW:
 715                 smum_send_msg_to_smc_with_parameter(hwmgr,
 716                                                 PPSMC_MSG_SetHardMinGfxClk,
 717                                                 data->gfx_min_freq_limit/100,
 718                                                 NULL);
 719                 smum_send_msg_to_smc_with_parameter(hwmgr,
 720                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 721                                                 data->gfx_min_freq_limit/100,
 722                                                 NULL);
 723                 smum_send_msg_to_smc_with_parameter(hwmgr,
 724                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 725                                                 min_mclk,
 726                                                 NULL);
 727                 smum_send_msg_to_smc_with_parameter(hwmgr,
 728                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 729                                                 min_mclk,
 730                                                 NULL);
 731                 break;
 732         case AMD_DPM_FORCED_LEVEL_MANUAL:
 733         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 734         default:
 735                 break;
 736         }
 737         return 0;
 738 }
 739
 740 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 741 {
 742         struct smu10_hwmgr *data;
 743
 744         if (hwmgr == NULL)
 745                 return -EINVAL;
 746
 747         data = (struct smu10_hwmgr *)(hwmgr->backend);
 748
 749         if (low)
 750                 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 751         else
 752                 return data->clock_vol_info.vdd_dep_on_fclk->entries[
 753                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 754 }
 755
 756 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
 757 {
 758         struct smu10_hwmgr *data;
 759
 760         if (hwmgr == NULL)
 761                 return -EINVAL;
 762
 763         data = (struct smu10_hwmgr *)(hwmgr->backend);
 764
 765         if (low)
 766                 return data->gfx_min_freq_limit;
 767         else
 768                 return data->gfx_max_freq_limit;
 769 }
 770
 771 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
 772                                         struct pp_hw_power_state *hw_ps)
 773 {
 774         return 0;
 775 }
 776
 777 static int smu10_dpm_get_pp_table_entry_callback(
 778                                                      struct pp_hwmgr *hwmgr,
 779                                            struct pp_hw_power_state *hw_ps,
 780                                                           unsigned int index,
 781                                                      const void *clock_info)
 782 {
 783         struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
 784
 785         smu10_ps->levels[index].engine_clock = 0;
 786
 787         smu10_ps->levels[index].vddc_index = 0;
 788         smu10_ps->level = index + 1;
 789
 790         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 791                 smu10_ps->levels[index].ds_divider_index = 5;
 792                 smu10_ps->levels[index].ss_divider_index = 5;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
 799 {
 800         int result;
 801         unsigned long ret = 0;
 802
 803         result = pp_tables_get_num_of_entries(hwmgr, &ret);
 804
 805         return result ? 0 : ret;
 806 }
 807
 808 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 809                     unsigned long entry, struct pp_power_state *ps)
 810 {
 811         int result;
 812         struct smu10_power_state *smu10_ps;
 813
 814         ps->hardware.magic = SMU10_Magic;
 815
 816         smu10_ps = cast_smu10_ps(&(ps->hardware));
 817
 818         result = pp_tables_get_entry(hwmgr, entry, ps,
 819                         smu10_dpm_get_pp_table_entry_callback);
 820
 821         smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
 822         smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
 823
 824         return result;
 825 }
 826
 827 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
 828 {
 829         return sizeof(struct smu10_power_state);
 830 }
 831
 832 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 833 {
 834         return 0;
 835 }
 836
 837
 838 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 839                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 840 {
 841         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 842
 843         if (separation_time != data->separation_time ||
 844                         cc6_disable != data->cc6_disable ||
 845                         pstate_disable != data->pstate_disable) {
 846                 data->separation_time = separation_time;
 847                 data->cc6_disable = cc6_disable;
 848                 data->pstate_disable = pstate_disable;
 849                 data->cc6_setting_changed = true;
 850         }
 851         return 0;
 852 }
 853
 854 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
 855                 struct amd_pp_simple_clock_info *info)
 856 {
 857         return -EINVAL;
 858 }
 859
 860 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 861                 enum pp_clock_type type, uint32_t mask)
 862 {
 863         struct smu10_hwmgr *data = hwmgr->backend;
 864         struct smu10_voltage_dependency_table *mclk_table =
 865                                         data->clock_vol_info.vdd_dep_on_fclk;
 866         uint32_t low, high;
 867
 868         low = mask ? (ffs(mask) - 1) : 0;
 869         high = mask ? (fls(mask) - 1) : 0;
 870
 871         switch (type) {
 872         case PP_SCLK:
 873                 if (low > 2 || high > 2) {
 874                         pr_info("Currently sclk only support 3 levels on RV\n");
 875                         return -EINVAL;
 876                 }
 877
 878                 smum_send_msg_to_smc_with_parameter(hwmgr,
 879                                                 PPSMC_MSG_SetHardMinGfxClk,
 880                                                 low == 2 ? data->gfx_max_freq_limit/100 :
 881                                                 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 882                                                 data->gfx_min_freq_limit/100,
 883                                                 NULL);
 884
 885                 smum_send_msg_to_smc_with_parameter(hwmgr,
 886                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 887                                                 high == 0 ? data->gfx_min_freq_limit/100 :
 888                                                 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 889                                                 data->gfx_max_freq_limit/100,
 890                                                 NULL);
 891                 break;
 892
 893         case PP_MCLK:
 894                 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
 895                         return -EINVAL;
 896
 897                 smum_send_msg_to_smc_with_parameter(hwmgr,
 898                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 899                                                 mclk_table->entries[low].clk/100,
 900                                                 NULL);
 901
 902                 smum_send_msg_to_smc_with_parameter(hwmgr,
 903                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 904                                                 mclk_table->entries[high].clk/100,
 905                                                 NULL);
 906                 break;
 907
 908         case PP_PCIE:
 909         default:
 910                 break;
 911         }
 912         return 0;
 913 }
 914
 915 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
 916                 enum pp_clock_type type, char *buf)
 917 {
 918         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 919         struct smu10_voltage_dependency_table *mclk_table =
 920                         data->clock_vol_info.vdd_dep_on_fclk;
 921         uint32_t i, now, size = 0;
 922
 923         switch (type) {
 924         case PP_SCLK:
 925                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
 926
 927         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 928                 if (now == data->gfx_max_freq_limit/100)
 929                         i = 2;
 930                 else if (now == data->gfx_min_freq_limit/100)
 931                         i = 0;
 932                 else
 933                         i = 1;
 934
 935                 size += sprintf(buf + size, "0: %uMhz %s\n",
 936                                         data->gfx_min_freq_limit/100,
 937                                         i == 0 ? "*" : "");
 938                 size += sprintf(buf + size, "1: %uMhz %s\n",
 939                                         i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
 940                                         i == 1 ? "*" : "");
 941                 size += sprintf(buf + size, "2: %uMhz %s\n",
 942                                         data->gfx_max_freq_limit/100,
 943                                         i == 2 ? "*" : "");
 944                 break;
 945         case PP_MCLK:
 946                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
 947
 948                 for (i = 0; i < mclk_table->count; i++)
 949                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 950                                         i,
 951                                         mclk_table->entries[i].clk / 100,
 952                                         ((mclk_table->entries[i].clk / 100)
 953                                          == now) ? "*" : "");
 954                 break;
 955         default:
 956                 break;
 957         }
 958
 959         return size;
 960 }
 961
 962 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 963                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 964                                 PHM_PerformanceLevel *level)
 965 {
 966         struct smu10_hwmgr *data;
 967
 968         if (level == NULL || hwmgr == NULL || state == NULL)
 969                 return -EINVAL;
 970
 971         data = (struct smu10_hwmgr *)(hwmgr->backend);
 972
 973         if (index == 0) {
 974                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 975                 level->coreClock = data->gfx_min_freq_limit;
 976         } else {
 977                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
 978                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 979                 level->coreClock = data->gfx_max_freq_limit;
 980         }
 981
 982         level->nonLocalMemoryFreq = 0;
 983         level->nonLocalMemoryWidth = 0;
 984
 985         return 0;
 986 }
 987
 988 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
 989         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 990 {
 991         const struct smu10_power_state *ps = cast_const_smu10_ps(state);
 992
 993         clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
 994         clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
 995
 996         return 0;
 997 }
 998
 999 #define MEM_FREQ_LOW_LATENCY        25000
1000 #define MEM_FREQ_HIGH_LATENCY       80000
1001 #define MEM_LATENCY_HIGH            245
1002 #define MEM_LATENCY_LOW             35
1003 #define MEM_LATENCY_ERR             0xFFFF
1004
1005
1006 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1007                 uint32_t clock)
1008 {
1009         if (clock >= MEM_FREQ_LOW_LATENCY &&
1010                         clock < MEM_FREQ_HIGH_LATENCY)
1011                 return MEM_LATENCY_HIGH;
1012         else if (clock >= MEM_FREQ_HIGH_LATENCY)
1013                 return MEM_LATENCY_LOW;
1014         else
1015                 return MEM_LATENCY_ERR;
1016 }
1017
1018 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1019                 enum amd_pp_clock_type type,
1020                 struct pp_clock_levels_with_latency *clocks)
1021 {
1022         uint32_t i;
1023         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1024         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1025         struct smu10_voltage_dependency_table *pclk_vol_table;
1026         bool latency_required = false;
1027
1028         if (pinfo == NULL)
1029                 return -EINVAL;
1030
1031         switch (type) {
1032         case amd_pp_mem_clock:
1033                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1034                 latency_required = true;
1035                 break;
1036         case amd_pp_f_clock:
1037                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1038                 latency_required = true;
1039                 break;
1040         case amd_pp_dcf_clock:
1041                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1042                 break;
1043         case amd_pp_disp_clock:
1044                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1045                 break;
1046         case amd_pp_phy_clock:
1047                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1048                 break;
1049         case amd_pp_dpp_clock:
1050                 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1051                 break;
1052         default:
1053                 return -EINVAL;
1054         }
1055
1056         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1057                 return -EINVAL;
1058
1059         clocks->num_levels = 0;
1060         for (i = 0; i < pclk_vol_table->count; i++) {
1061                 if (pclk_vol_table->entries[i].clk) {
1062                         clocks->data[clocks->num_levels].clocks_in_khz =
1063                                 pclk_vol_table->entries[i].clk * 10;
1064                         clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1065                                 smu10_get_mem_latency(hwmgr,
1066                                                       pclk_vol_table->entries[i].clk) :
1067                                 0;
1068                         clocks->num_levels++;
1069                 }
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1076                 enum amd_pp_clock_type type,
1077                 struct pp_clock_levels_with_voltage *clocks)
1078 {
1079         uint32_t i;
1080         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1081         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1082         struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1083
1084         if (pinfo == NULL)
1085                 return -EINVAL;
1086
1087         switch (type) {
1088         case amd_pp_mem_clock:
1089                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1090                 break;
1091         case amd_pp_f_clock:
1092                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1093                 break;
1094         case amd_pp_dcf_clock:
1095                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1096                 break;
1097         case amd_pp_soc_clock:
1098                 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1099                 break;
1100         case amd_pp_disp_clock:
1101                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1102                 break;
1103         case amd_pp_phy_clock:
1104                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1105                 break;
1106         default:
1107                 return -EINVAL;
1108         }
1109
1110         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1111                 return -EINVAL;
1112
1113         clocks->num_levels = 0;
1114         for (i = 0; i < pclk_vol_table->count; i++) {
1115                 if (pclk_vol_table->entries[i].clk) {
1116                         clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
1117                         clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1118                         clocks->num_levels++;
1119                 }
1120         }
1121
1122         return 0;
1123 }
1124
1125
1126
1127 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1128 {
1129         clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1130         return 0;
1131 }
1132
1133 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1134 {
1135         struct amdgpu_device *adev = hwmgr->adev;
1136         uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1137         int cur_temp =
1138                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1139
1140         if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1141                 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1142         else
1143                 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1144
1145         return cur_temp;
1146 }
1147
1148 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1149                           void *value, int *size)
1150 {
1151         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1152         uint32_t sclk, mclk;
1153         int ret = 0;
1154
1155         switch (idx) {
1156         case AMDGPU_PP_SENSOR_GFX_SCLK:
1157                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1158                         /* in units of 10KHZ */
1159                 *((uint32_t *)value) = sclk * 100;
1160                 *size = 4;
1161                 break;
1162         case AMDGPU_PP_SENSOR_GFX_MCLK:
1163                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1164                         /* in units of 10KHZ */
1165                 *((uint32_t *)value) = mclk * 100;
1166                 *size = 4;
1167                 break;
1168         case AMDGPU_PP_SENSOR_GPU_TEMP:
1169                 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1170                 break;
1171         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1172                 *(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
1173                 *size = 4;
1174                 break;
1175         default:
1176                 ret = -EINVAL;
1177                 break;
1178         }
1179
1180         return ret;
1181 }
1182
1183 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1184                 void *clock_ranges)
1185 {
1186         struct smu10_hwmgr *data = hwmgr->backend;
1187         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1188         Watermarks_t *table = &(data->water_marks_table);
1189
1190         smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1191         smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1192         data->water_marks_exist = true;
1193         return 0;
1194 }
1195
1196 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1197 {
1198
1199         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1200 }
1201
1202 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1203 {
1204         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1205 }
1206
1207 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1208 {
1209         if (gate)
1210                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1211         else
1212                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1213 }
1214
1215 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1216 {
1217         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1218
1219         if (bgate) {
1220                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1221                                                 AMD_IP_BLOCK_TYPE_VCN,
1222                                                 AMD_PG_STATE_GATE);
1223                 smum_send_msg_to_smc_with_parameter(hwmgr,
1224                                         PPSMC_MSG_PowerDownVcn, 0, NULL);
1225                 smu10_data->vcn_power_gated = true;
1226         } else {
1227                 smum_send_msg_to_smc_with_parameter(hwmgr,
1228                                                 PPSMC_MSG_PowerUpVcn, 0, NULL);
1229                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1230                                                 AMD_IP_BLOCK_TYPE_VCN,
1231                                                 AMD_PG_STATE_UNGATE);
1232                 smu10_data->vcn_power_gated = false;
1233         }
1234 }
1235
1236 static int conv_power_profile_to_pplib_workload(int power_profile)
1237 {
1238         int pplib_workload = 0;
1239
1240         switch (power_profile) {
1241         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
1242                 pplib_workload = WORKLOAD_DEFAULT_BIT;
1243                 break;
1244         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1245                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1246                 break;
1247         case PP_SMC_POWER_PROFILE_POWERSAVING:
1248                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
1249                 break;
1250         case PP_SMC_POWER_PROFILE_VIDEO:
1251                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1252                 break;
1253         case PP_SMC_POWER_PROFILE_VR:
1254                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1255                 break;
1256         case PP_SMC_POWER_PROFILE_COMPUTE:
1257                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1258                 break;
1259         }
1260
1261         return pplib_workload;
1262 }
1263
1264 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1265 {
1266         uint32_t i, size = 0;
1267         static const uint8_t
1268                 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1269                                                 {70, 60, 1, 3,},
1270                                                 {90, 60, 0, 0,},
1271                                                 {70, 60, 0, 0,},
1272                                                 {70, 90, 0, 0,},
1273                                                 {30, 60, 0, 6,},
1274                                                 };
1275         static const char *profile_name[6] = {
1276                                         "BOOTUP_DEFAULT",
1277                                         "3D_FULL_SCREEN",
1278                                         "POWER_SAVING",
1279                                         "VIDEO",
1280                                         "VR",
1281                                         "COMPUTE"};
1282         static const char *title[6] = {"NUM",
1283                         "MODE_NAME",
1284                         "BUSY_SET_POINT",
1285                         "FPS",
1286                         "USE_RLC_BUSY",
1287                         "MIN_ACTIVE_LEVEL"};
1288
1289         if (!buf)
1290                 return -EINVAL;
1291
1292         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
1293                         title[1], title[2], title[3], title[4], title[5]);
1294
1295         for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1296                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
1297                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1298                         profile_mode_setting[i][0], profile_mode_setting[i][1],
1299                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
1300
1301         return size;
1302 }
1303
1304 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1305 {
1306         struct amdgpu_device *adev = hwmgr->adev;
1307         if ((adev->asic_type == CHIP_RAVEN) &&
1308             (adev->rev_id != 0x15d8) &&
1309             (hwmgr->smu_version >= 0x41e2b))
1310                 return true;
1311         else
1312                 return false;
1313 }
1314
1315 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1316 {
1317         int workload_type = 0;
1318         int result = 0;
1319
1320         if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1321                 pr_err("Invalid power profile mode %ld\n", input[size]);
1322                 return -EINVAL;
1323         }
1324         if (hwmgr->power_profile_mode == input[size])
1325                 return 0;
1326
1327         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1328         workload_type =
1329                 conv_power_profile_to_pplib_workload(input[size]);
1330         if (workload_type &&
1331             smu10_is_raven1_refresh(hwmgr) &&
1332             !hwmgr->gfxoff_state_changed_by_workload) {
1333                 smu10_gfx_off_control(hwmgr, false);
1334                 hwmgr->gfxoff_state_changed_by_workload = true;
1335         }
1336         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1337                                                 1 << workload_type,
1338                                                 NULL);
1339         if (!result)
1340                 hwmgr->power_profile_mode = input[size];
1341         if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1342                 smu10_gfx_off_control(hwmgr, true);
1343                 hwmgr->gfxoff_state_changed_by_workload = false;
1344         }
1345
1346         return 0;
1347 }
1348
1349 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1350 {
1351         return smum_send_msg_to_smc_with_parameter(hwmgr,
1352                                                    PPSMC_MSG_DeviceDriverReset,
1353                                                    mode,
1354                                                    NULL);
1355 }
1356
1357 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1358         .backend_init = smu10_hwmgr_backend_init,
1359         .backend_fini = smu10_hwmgr_backend_fini,
1360         .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1361         .force_dpm_level = smu10_dpm_force_dpm_level,
1362         .get_power_state_size = smu10_get_power_state_size,
1363         .powerdown_uvd = NULL,
1364         .powergate_uvd = smu10_powergate_vcn,
1365         .powergate_vce = NULL,
1366         .get_mclk = smu10_dpm_get_mclk,
1367         .get_sclk = smu10_dpm_get_sclk,
1368         .patch_boot_state = smu10_dpm_patch_boot_state,
1369         .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1370         .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1371         .set_cpu_power_state = smu10_set_cpu_power_state,
1372         .store_cc6_data = smu10_store_cc6_data,
1373         .force_clock_level = smu10_force_clock_level,
1374         .print_clock_levels = smu10_print_clock_levels,
1375         .get_dal_power_level = smu10_get_dal_power_level,
1376         .get_performance_level = smu10_get_performance_level,
1377         .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1378         .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1379         .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1380         .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1381         .get_max_high_clocks = smu10_get_max_high_clocks,
1382         .read_sensor = smu10_read_sensor,
1383         .set_active_display_count = smu10_set_active_display_count,
1384         .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1385         .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1386         .power_off_asic = smu10_power_off_asic,
1387         .asic_setup = smu10_setup_asic_task,
1388         .power_state_set = smu10_set_power_state_tasks,
1389         .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1390         .powergate_mmhub = smu10_powergate_mmhub,
1391         .smus_notify_pwe = smu10_smus_notify_pwe,
1392         .display_clock_voltage_request = smu10_display_clock_voltage_request,
1393         .powergate_gfx = smu10_gfx_off_control,
1394         .powergate_sdma = smu10_powergate_sdma,
1395         .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1396         .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1397         .get_power_profile_mode = smu10_get_power_profile_mode,
1398         .set_power_profile_mode = smu10_set_power_profile_mode,
1399         .asic_reset = smu10_asic_reset,
1400 };
1401
1402 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1403 {
1404         hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1405         hwmgr->pptable_func = &pptable_funcs;
1406         return 0;
1407 }