2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
33 #include "hardwaremanager.h"
35 #include "smu10_hwmgr.h"
36 #include "power_state.h"
37 #include "soc15_common.h"
39 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
40 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
41 #define SCLK_MIN_DIV_INTV_SHIFT 12
42 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
43 #define SMC_RAM_END 0x40000
45 #define mmPWR_MISC_CNTL_STATUS 0x0183
46 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
47 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
48 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
49 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
50 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
55 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
56 struct pp_display_clock_request *clock_req)
58 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
59 enum amd_pp_clock_type clk_type = clock_req->clock_type;
60 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
64 case amd_pp_dcf_clock:
65 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
67 msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
68 smu10_data->dcf_actual_hard_min_freq = clk_freq;
70 case amd_pp_soc_clock:
71 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
74 if (clk_freq == smu10_data->f_actual_hard_min_freq)
76 smu10_data->f_actual_hard_min_freq = clk_freq;
77 msg = PPSMC_MSG_SetHardMinFclkByFreq;
80 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
83 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);
88 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
90 if (SMU10_Magic != hw_ps->magic)
93 return (struct smu10_power_state *)hw_ps;
96 static const struct smu10_power_state *cast_const_smu10_ps(
97 const struct pp_hw_power_state *hw_ps)
99 if (SMU10_Magic != hw_ps->magic)
102 return (struct smu10_power_state *)hw_ps;
105 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
107 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
109 smu10_data->dce_slow_sclk_threshold = 30000;
110 smu10_data->thermal_auto_throttling_treshold = 0;
111 smu10_data->is_nb_dpm_enabled = 1;
112 smu10_data->dpm_flags = 1;
113 smu10_data->need_min_deep_sleep_dcefclk = true;
114 smu10_data->num_active_display = 0;
115 smu10_data->deep_sleep_dcefclk = 0;
117 if (hwmgr->feature_mask & PP_GFXOFF_MASK)
118 smu10_data->gfx_off_controled_by_driver = true;
120 smu10_data->gfx_off_controled_by_driver = false;
122 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
123 PHM_PlatformCaps_SclkDeepSleep);
125 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
126 PHM_PlatformCaps_SclkThrottleLowNotification);
128 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
129 PHM_PlatformCaps_PowerPlaySupport);
133 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
134 struct phm_clock_and_voltage_limits *table)
139 static int smu10_init_dynamic_state_adjustment_rule_settings(
140 struct pp_hwmgr *hwmgr)
142 struct phm_clock_voltage_dependency_table *table_clk_vlt;
144 table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7),
147 if (NULL == table_clk_vlt) {
148 pr_err("Can not allocate memory!\n");
152 table_clk_vlt->count = 8;
153 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
154 table_clk_vlt->entries[0].v = 0;
155 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
156 table_clk_vlt->entries[1].v = 1;
157 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
158 table_clk_vlt->entries[2].v = 2;
159 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
160 table_clk_vlt->entries[3].v = 3;
161 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
162 table_clk_vlt->entries[4].v = 4;
163 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
164 table_clk_vlt->entries[5].v = 5;
165 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
166 table_clk_vlt->entries[6].v = 6;
167 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
168 table_clk_vlt->entries[7].v = 7;
169 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
174 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
176 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
178 smu10_data->sys_info.htc_hyst_lmt = 5;
179 smu10_data->sys_info.htc_tmp_lmt = 203;
181 if (smu10_data->thermal_auto_throttling_treshold == 0)
182 smu10_data->thermal_auto_throttling_treshold = 203;
184 smu10_construct_max_power_limits_table (hwmgr,
185 &hwmgr->dyn_state.max_clock_voltage_on_ac);
187 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
192 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
197 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
199 struct PP_Clocks clocks = {0};
200 struct pp_display_clock_request clock_req;
202 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
203 clock_req.clock_type = amd_pp_dcf_clock;
204 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
206 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
207 "Attempt to set DCF Clock Failed!", return -EINVAL);
212 static inline uint32_t convert_10k_to_mhz(uint32_t clock)
214 return (clock + 99) / 100;
217 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
219 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
221 if (smu10_data->need_min_deep_sleep_dcefclk &&
222 smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
223 smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
224 smum_send_msg_to_smc_with_parameter(hwmgr,
225 PPSMC_MSG_SetMinDeepSleepDcefclk,
226 smu10_data->deep_sleep_dcefclk);
231 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
233 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
235 if (smu10_data->dcf_actual_hard_min_freq &&
236 smu10_data->dcf_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
237 smu10_data->dcf_actual_hard_min_freq = convert_10k_to_mhz(clock);
238 smum_send_msg_to_smc_with_parameter(hwmgr,
239 PPSMC_MSG_SetHardMinDcefclkByFreq,
240 smu10_data->dcf_actual_hard_min_freq);
245 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
247 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
249 if (smu10_data->f_actual_hard_min_freq &&
250 smu10_data->f_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
251 smu10_data->f_actual_hard_min_freq = convert_10k_to_mhz(clock);
252 smum_send_msg_to_smc_with_parameter(hwmgr,
253 PPSMC_MSG_SetHardMinFclkByFreq,
254 smu10_data->f_actual_hard_min_freq);
259 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
261 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
263 if (smu10_data->num_active_display != count) {
264 smu10_data->num_active_display = count;
265 smum_send_msg_to_smc_with_parameter(hwmgr,
266 PPSMC_MSG_SetDisplayCount,
267 smu10_data->num_active_display);
273 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
275 return smu10_set_clock_limit(hwmgr, input);
278 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
280 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
281 struct amdgpu_device *adev = hwmgr->adev;
283 smu10_data->vcn_power_gated = true;
284 smu10_data->isp_tileA_power_gated = true;
285 smu10_data->isp_tileB_power_gated = true;
287 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
288 return smum_send_msg_to_smc_with_parameter(hwmgr,
289 PPSMC_MSG_SetGfxCGPG,
296 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
298 return smu10_init_power_gate_state(hwmgr);
301 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
303 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
305 smu10_data->separation_time = 0;
306 smu10_data->cc6_disable = false;
307 smu10_data->pstate_disable = false;
308 smu10_data->cc6_setting_changed = false;
313 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
315 return smu10_reset_cc6_data(hwmgr);
318 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
321 struct amdgpu_device *adev = hwmgr->adev;
323 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
324 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
325 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
331 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
333 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
335 if (smu10_data->gfx_off_controled_by_driver) {
336 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
338 /* confirm gfx is back to "on" state */
339 while (!smu10_is_gfx_on(hwmgr))
346 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
351 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
353 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
355 if (smu10_data->gfx_off_controled_by_driver)
356 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);
361 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
366 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
369 return smu10_enable_gfx_off(hwmgr);
371 return smu10_disable_gfx_off(hwmgr);
374 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
375 struct pp_power_state *prequest_ps,
376 const struct pp_power_state *pcurrent_ps)
381 /* temporary hardcoded clock voltage breakdown tables */
382 static const DpmClock_t VddDcfClk[]= {
388 static const DpmClock_t VddSocClk[]= {
394 static const DpmClock_t VddFClk[]= {
400 static const DpmClock_t VddDispClk[]= {
406 static const DpmClock_t VddDppClk[]= {
412 static const DpmClock_t VddPhyClk[]= {
418 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
419 struct smu10_voltage_dependency_table **pptable,
420 uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
422 uint32_t table_size, i;
423 struct smu10_voltage_dependency_table *ptable;
425 table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry;
426 ptable = kzalloc(table_size, GFP_KERNEL);
431 ptable->count = num_entry;
433 for (i = 0; i < ptable->count; i++) {
434 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
435 ptable->entries[i].vol = pclk_dependency_table->Vol;
436 pclk_dependency_table++;
445 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
449 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
450 DpmClocks_t *table = &(smu10_data->clock_table);
451 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
453 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
455 PP_ASSERT_WITH_CODE((0 == result),
456 "Attempt to copy clock table from smc failed",
459 if (0 == result && table->DcefClocks[0].Freq != 0) {
460 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
461 NUM_DCEFCLK_DPM_LEVELS,
462 &smu10_data->clock_table.DcefClocks[0]);
463 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
464 NUM_SOCCLK_DPM_LEVELS,
465 &smu10_data->clock_table.SocClocks[0]);
466 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
468 &smu10_data->clock_table.FClocks[0]);
469 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
470 NUM_MEMCLK_DPM_LEVELS,
471 &smu10_data->clock_table.MemClocks[0]);
473 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
474 ARRAY_SIZE(VddDcfClk),
476 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
477 ARRAY_SIZE(VddSocClk),
479 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
483 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
484 ARRAY_SIZE(VddDispClk),
486 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
487 ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
488 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
489 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
491 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
492 result = smum_get_argument(hwmgr);
493 smu10_data->gfx_min_freq_limit = result / 10 * 1000;
495 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
496 result = smum_get_argument(hwmgr);
497 smu10_data->gfx_max_freq_limit = result / 10 * 1000;
502 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
505 struct smu10_hwmgr *data;
507 data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
511 hwmgr->backend = data;
513 result = smu10_initialize_dpm_defaults(hwmgr);
515 pr_err("smu10_initialize_dpm_defaults failed\n");
519 smu10_populate_clock_table(hwmgr);
521 result = smu10_get_system_info_data(hwmgr);
523 pr_err("smu10_get_system_info_data failed\n");
527 smu10_construct_boot_state(hwmgr);
529 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
530 SMU10_MAX_HARDWARE_POWERLEVELS;
532 hwmgr->platform_descriptor.hardwarePerformanceLevels =
533 SMU10_MAX_HARDWARE_POWERLEVELS;
535 hwmgr->platform_descriptor.vbiosInterruptId = 0;
537 hwmgr->platform_descriptor.clockStep.engineClock = 500;
539 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
541 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
543 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
544 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
549 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
551 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
552 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
554 kfree(pinfo->vdd_dep_on_dcefclk);
555 pinfo->vdd_dep_on_dcefclk = NULL;
556 kfree(pinfo->vdd_dep_on_socclk);
557 pinfo->vdd_dep_on_socclk = NULL;
558 kfree(pinfo->vdd_dep_on_fclk);
559 pinfo->vdd_dep_on_fclk = NULL;
560 kfree(pinfo->vdd_dep_on_dispclk);
561 pinfo->vdd_dep_on_dispclk = NULL;
562 kfree(pinfo->vdd_dep_on_dppclk);
563 pinfo->vdd_dep_on_dppclk = NULL;
564 kfree(pinfo->vdd_dep_on_phyclk);
565 pinfo->vdd_dep_on_phyclk = NULL;
567 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
568 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
570 kfree(hwmgr->backend);
571 hwmgr->backend = NULL;
576 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
577 enum amd_dpm_forced_level level)
579 struct smu10_hwmgr *data = hwmgr->backend;
580 struct amdgpu_device *adev = hwmgr->adev;
581 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
582 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
584 if (hwmgr->smu_version < 0x1E3700) {
585 pr_info("smu firmware version too old, can not set dpm level\n");
589 /* Disable UMDPSTATE support on rv2 temporarily */
590 if ((adev->asic_type == CHIP_RAVEN) &&
594 if (min_sclk < data->gfx_min_freq_limit)
595 min_sclk = data->gfx_min_freq_limit;
597 min_sclk /= 100; /* transfer 10KHz to MHz */
598 if (min_mclk < data->clock_table.FClocks[0].Freq)
599 min_mclk = data->clock_table.FClocks[0].Freq;
602 case AMD_DPM_FORCED_LEVEL_HIGH:
603 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
604 smum_send_msg_to_smc_with_parameter(hwmgr,
605 PPSMC_MSG_SetHardMinGfxClk,
606 data->gfx_max_freq_limit/100);
607 smum_send_msg_to_smc_with_parameter(hwmgr,
608 PPSMC_MSG_SetHardMinFclkByFreq,
609 SMU10_UMD_PSTATE_PEAK_FCLK);
610 smum_send_msg_to_smc_with_parameter(hwmgr,
611 PPSMC_MSG_SetHardMinSocclkByFreq,
612 SMU10_UMD_PSTATE_PEAK_SOCCLK);
613 smum_send_msg_to_smc_with_parameter(hwmgr,
614 PPSMC_MSG_SetHardMinVcn,
615 SMU10_UMD_PSTATE_VCE);
617 smum_send_msg_to_smc_with_parameter(hwmgr,
618 PPSMC_MSG_SetSoftMaxGfxClk,
619 data->gfx_max_freq_limit/100);
620 smum_send_msg_to_smc_with_parameter(hwmgr,
621 PPSMC_MSG_SetSoftMaxFclkByFreq,
622 SMU10_UMD_PSTATE_PEAK_FCLK);
623 smum_send_msg_to_smc_with_parameter(hwmgr,
624 PPSMC_MSG_SetSoftMaxSocclkByFreq,
625 SMU10_UMD_PSTATE_PEAK_SOCCLK);
626 smum_send_msg_to_smc_with_parameter(hwmgr,
627 PPSMC_MSG_SetSoftMaxVcn,
628 SMU10_UMD_PSTATE_VCE);
630 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
631 smum_send_msg_to_smc_with_parameter(hwmgr,
632 PPSMC_MSG_SetHardMinGfxClk,
634 smum_send_msg_to_smc_with_parameter(hwmgr,
635 PPSMC_MSG_SetSoftMaxGfxClk,
638 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
639 smum_send_msg_to_smc_with_parameter(hwmgr,
640 PPSMC_MSG_SetHardMinFclkByFreq,
642 smum_send_msg_to_smc_with_parameter(hwmgr,
643 PPSMC_MSG_SetSoftMaxFclkByFreq,
646 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
647 smum_send_msg_to_smc_with_parameter(hwmgr,
648 PPSMC_MSG_SetHardMinGfxClk,
649 SMU10_UMD_PSTATE_GFXCLK);
650 smum_send_msg_to_smc_with_parameter(hwmgr,
651 PPSMC_MSG_SetHardMinFclkByFreq,
652 SMU10_UMD_PSTATE_FCLK);
653 smum_send_msg_to_smc_with_parameter(hwmgr,
654 PPSMC_MSG_SetHardMinSocclkByFreq,
655 SMU10_UMD_PSTATE_SOCCLK);
656 smum_send_msg_to_smc_with_parameter(hwmgr,
657 PPSMC_MSG_SetHardMinVcn,
658 SMU10_UMD_PSTATE_VCE);
660 smum_send_msg_to_smc_with_parameter(hwmgr,
661 PPSMC_MSG_SetSoftMaxGfxClk,
662 SMU10_UMD_PSTATE_GFXCLK);
663 smum_send_msg_to_smc_with_parameter(hwmgr,
664 PPSMC_MSG_SetSoftMaxFclkByFreq,
665 SMU10_UMD_PSTATE_FCLK);
666 smum_send_msg_to_smc_with_parameter(hwmgr,
667 PPSMC_MSG_SetSoftMaxSocclkByFreq,
668 SMU10_UMD_PSTATE_SOCCLK);
669 smum_send_msg_to_smc_with_parameter(hwmgr,
670 PPSMC_MSG_SetSoftMaxVcn,
671 SMU10_UMD_PSTATE_VCE);
673 case AMD_DPM_FORCED_LEVEL_AUTO:
674 smum_send_msg_to_smc_with_parameter(hwmgr,
675 PPSMC_MSG_SetHardMinGfxClk,
677 smum_send_msg_to_smc_with_parameter(hwmgr,
678 PPSMC_MSG_SetHardMinFclkByFreq,
679 hwmgr->display_config->num_display > 3 ?
680 SMU10_UMD_PSTATE_PEAK_FCLK :
683 smum_send_msg_to_smc_with_parameter(hwmgr,
684 PPSMC_MSG_SetHardMinSocclkByFreq,
685 SMU10_UMD_PSTATE_MIN_SOCCLK);
686 smum_send_msg_to_smc_with_parameter(hwmgr,
687 PPSMC_MSG_SetHardMinVcn,
688 SMU10_UMD_PSTATE_MIN_VCE);
690 smum_send_msg_to_smc_with_parameter(hwmgr,
691 PPSMC_MSG_SetSoftMaxGfxClk,
692 data->gfx_max_freq_limit/100);
693 smum_send_msg_to_smc_with_parameter(hwmgr,
694 PPSMC_MSG_SetSoftMaxFclkByFreq,
695 SMU10_UMD_PSTATE_PEAK_FCLK);
696 smum_send_msg_to_smc_with_parameter(hwmgr,
697 PPSMC_MSG_SetSoftMaxSocclkByFreq,
698 SMU10_UMD_PSTATE_PEAK_SOCCLK);
699 smum_send_msg_to_smc_with_parameter(hwmgr,
700 PPSMC_MSG_SetSoftMaxVcn,
701 SMU10_UMD_PSTATE_VCE);
703 case AMD_DPM_FORCED_LEVEL_LOW:
704 smum_send_msg_to_smc_with_parameter(hwmgr,
705 PPSMC_MSG_SetHardMinGfxClk,
706 data->gfx_min_freq_limit/100);
707 smum_send_msg_to_smc_with_parameter(hwmgr,
708 PPSMC_MSG_SetSoftMaxGfxClk,
709 data->gfx_min_freq_limit/100);
710 smum_send_msg_to_smc_with_parameter(hwmgr,
711 PPSMC_MSG_SetHardMinFclkByFreq,
713 smum_send_msg_to_smc_with_parameter(hwmgr,
714 PPSMC_MSG_SetSoftMaxFclkByFreq,
717 case AMD_DPM_FORCED_LEVEL_MANUAL:
718 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
725 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
727 struct smu10_hwmgr *data;
732 data = (struct smu10_hwmgr *)(hwmgr->backend);
735 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
737 return data->clock_vol_info.vdd_dep_on_fclk->entries[
738 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
741 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
743 struct smu10_hwmgr *data;
748 data = (struct smu10_hwmgr *)(hwmgr->backend);
751 return data->gfx_min_freq_limit;
753 return data->gfx_max_freq_limit;
756 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
757 struct pp_hw_power_state *hw_ps)
762 static int smu10_dpm_get_pp_table_entry_callback(
763 struct pp_hwmgr *hwmgr,
764 struct pp_hw_power_state *hw_ps,
766 const void *clock_info)
768 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
770 smu10_ps->levels[index].engine_clock = 0;
772 smu10_ps->levels[index].vddc_index = 0;
773 smu10_ps->level = index + 1;
775 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
776 smu10_ps->levels[index].ds_divider_index = 5;
777 smu10_ps->levels[index].ss_divider_index = 5;
783 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
786 unsigned long ret = 0;
788 result = pp_tables_get_num_of_entries(hwmgr, &ret);
790 return result ? 0 : ret;
793 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
794 unsigned long entry, struct pp_power_state *ps)
797 struct smu10_power_state *smu10_ps;
799 ps->hardware.magic = SMU10_Magic;
801 smu10_ps = cast_smu10_ps(&(ps->hardware));
803 result = pp_tables_get_entry(hwmgr, entry, ps,
804 smu10_dpm_get_pp_table_entry_callback);
806 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
807 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
812 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
814 return sizeof(struct smu10_power_state);
817 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
823 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
824 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
826 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
828 if (separation_time != data->separation_time ||
829 cc6_disable != data->cc6_disable ||
830 pstate_disable != data->pstate_disable) {
831 data->separation_time = separation_time;
832 data->cc6_disable = cc6_disable;
833 data->pstate_disable = pstate_disable;
834 data->cc6_setting_changed = true;
839 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
840 struct amd_pp_simple_clock_info *info)
845 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
846 enum pp_clock_type type, uint32_t mask)
848 struct smu10_hwmgr *data = hwmgr->backend;
849 struct smu10_voltage_dependency_table *mclk_table =
850 data->clock_vol_info.vdd_dep_on_fclk;
853 low = mask ? (ffs(mask) - 1) : 0;
854 high = mask ? (fls(mask) - 1) : 0;
858 if (low > 2 || high > 2) {
859 pr_info("Currently sclk only support 3 levels on RV\n");
863 smum_send_msg_to_smc_with_parameter(hwmgr,
864 PPSMC_MSG_SetHardMinGfxClk,
865 low == 2 ? data->gfx_max_freq_limit/100 :
866 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
867 data->gfx_min_freq_limit/100);
869 smum_send_msg_to_smc_with_parameter(hwmgr,
870 PPSMC_MSG_SetSoftMaxGfxClk,
871 high == 0 ? data->gfx_min_freq_limit/100 :
872 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
873 data->gfx_max_freq_limit/100);
877 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
880 smum_send_msg_to_smc_with_parameter(hwmgr,
881 PPSMC_MSG_SetHardMinFclkByFreq,
882 mclk_table->entries[low].clk/100);
884 smum_send_msg_to_smc_with_parameter(hwmgr,
885 PPSMC_MSG_SetSoftMaxFclkByFreq,
886 mclk_table->entries[high].clk/100);
896 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
897 enum pp_clock_type type, char *buf)
899 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
900 struct smu10_voltage_dependency_table *mclk_table =
901 data->clock_vol_info.vdd_dep_on_fclk;
902 uint32_t i, now, size = 0;
906 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
907 now = smum_get_argument(hwmgr);
909 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
910 if (now == data->gfx_max_freq_limit/100)
912 else if (now == data->gfx_min_freq_limit/100)
917 size += sprintf(buf + size, "0: %uMhz %s\n",
918 data->gfx_min_freq_limit/100,
920 size += sprintf(buf + size, "1: %uMhz %s\n",
921 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
923 size += sprintf(buf + size, "2: %uMhz %s\n",
924 data->gfx_max_freq_limit/100,
928 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
929 now = smum_get_argument(hwmgr);
931 for (i = 0; i < mclk_table->count; i++)
932 size += sprintf(buf + size, "%d: %uMhz %s\n",
934 mclk_table->entries[i].clk / 100,
935 ((mclk_table->entries[i].clk / 100)
945 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
946 PHM_PerformanceLevelDesignation designation, uint32_t index,
947 PHM_PerformanceLevel *level)
949 struct smu10_hwmgr *data;
951 if (level == NULL || hwmgr == NULL || state == NULL)
954 data = (struct smu10_hwmgr *)(hwmgr->backend);
957 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
958 level->coreClock = data->gfx_min_freq_limit;
960 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
961 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
962 level->coreClock = data->gfx_max_freq_limit;
965 level->nonLocalMemoryFreq = 0;
966 level->nonLocalMemoryWidth = 0;
971 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
972 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
974 const struct smu10_power_state *ps = cast_const_smu10_ps(state);
976 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
977 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
982 #define MEM_FREQ_LOW_LATENCY 25000
983 #define MEM_FREQ_HIGH_LATENCY 80000
984 #define MEM_LATENCY_HIGH 245
985 #define MEM_LATENCY_LOW 35
986 #define MEM_LATENCY_ERR 0xFFFF
989 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
992 if (clock >= MEM_FREQ_LOW_LATENCY &&
993 clock < MEM_FREQ_HIGH_LATENCY)
994 return MEM_LATENCY_HIGH;
995 else if (clock >= MEM_FREQ_HIGH_LATENCY)
996 return MEM_LATENCY_LOW;
998 return MEM_LATENCY_ERR;
1001 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1002 enum amd_pp_clock_type type,
1003 struct pp_clock_levels_with_latency *clocks)
1006 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1007 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1008 struct smu10_voltage_dependency_table *pclk_vol_table;
1009 bool latency_required = false;
1015 case amd_pp_mem_clock:
1016 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1017 latency_required = true;
1019 case amd_pp_f_clock:
1020 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1021 latency_required = true;
1023 case amd_pp_dcf_clock:
1024 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1026 case amd_pp_disp_clock:
1027 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1029 case amd_pp_phy_clock:
1030 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1032 case amd_pp_dpp_clock:
1033 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1039 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1042 clocks->num_levels = 0;
1043 for (i = 0; i < pclk_vol_table->count; i++) {
1044 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1045 clocks->data[i].latency_in_us = latency_required ?
1046 smu10_get_mem_latency(hwmgr,
1047 pclk_vol_table->entries[i].clk) :
1049 clocks->num_levels++;
1055 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1056 enum amd_pp_clock_type type,
1057 struct pp_clock_levels_with_voltage *clocks)
1060 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1061 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1062 struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1068 case amd_pp_mem_clock:
1069 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1071 case amd_pp_f_clock:
1072 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1074 case amd_pp_dcf_clock:
1075 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1077 case amd_pp_soc_clock:
1078 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1080 case amd_pp_disp_clock:
1081 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1083 case amd_pp_phy_clock:
1084 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1090 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1093 clocks->num_levels = 0;
1094 for (i = 0; i < pclk_vol_table->count; i++) {
1095 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1096 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
1097 clocks->num_levels++;
1105 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1107 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1111 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1113 struct amdgpu_device *adev = hwmgr->adev;
1114 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1116 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1118 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1119 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1121 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1126 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1127 void *value, int *size)
1129 uint32_t sclk, mclk;
1133 case AMDGPU_PP_SENSOR_GFX_SCLK:
1134 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
1135 sclk = smum_get_argument(hwmgr);
1136 /* in units of 10KHZ */
1137 *((uint32_t *)value) = sclk * 100;
1140 case AMDGPU_PP_SENSOR_GFX_MCLK:
1141 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
1142 mclk = smum_get_argument(hwmgr);
1143 /* in units of 10KHZ */
1144 *((uint32_t *)value) = mclk * 100;
1147 case AMDGPU_PP_SENSOR_GPU_TEMP:
1148 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1158 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1161 struct smu10_hwmgr *data = hwmgr->backend;
1162 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1163 Watermarks_t *table = &(data->water_marks_table);
1166 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1167 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1168 data->water_marks_exist = true;
1172 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1175 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);
1178 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1180 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
1183 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1186 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);
1188 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);
1191 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1194 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1195 AMD_IP_BLOCK_TYPE_VCN,
1197 smum_send_msg_to_smc_with_parameter(hwmgr,
1198 PPSMC_MSG_PowerDownVcn, 0);
1200 smum_send_msg_to_smc_with_parameter(hwmgr,
1201 PPSMC_MSG_PowerUpVcn, 0);
1202 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1203 AMD_IP_BLOCK_TYPE_VCN,
1204 AMD_PG_STATE_UNGATE);
1208 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1209 .backend_init = smu10_hwmgr_backend_init,
1210 .backend_fini = smu10_hwmgr_backend_fini,
1212 .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1213 .force_dpm_level = smu10_dpm_force_dpm_level,
1214 .get_power_state_size = smu10_get_power_state_size,
1215 .powerdown_uvd = NULL,
1216 .powergate_uvd = smu10_powergate_vcn,
1217 .powergate_vce = NULL,
1218 .get_mclk = smu10_dpm_get_mclk,
1219 .get_sclk = smu10_dpm_get_sclk,
1220 .patch_boot_state = smu10_dpm_patch_boot_state,
1221 .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1222 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1223 .set_cpu_power_state = smu10_set_cpu_power_state,
1224 .store_cc6_data = smu10_store_cc6_data,
1225 .force_clock_level = smu10_force_clock_level,
1226 .print_clock_levels = smu10_print_clock_levels,
1227 .get_dal_power_level = smu10_get_dal_power_level,
1228 .get_performance_level = smu10_get_performance_level,
1229 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1230 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1231 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1232 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1233 .get_max_high_clocks = smu10_get_max_high_clocks,
1234 .read_sensor = smu10_read_sensor,
1235 .set_active_display_count = smu10_set_active_display_count,
1236 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1237 .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1238 .power_off_asic = smu10_power_off_asic,
1239 .asic_setup = smu10_setup_asic_task,
1240 .power_state_set = smu10_set_power_state_tasks,
1241 .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1242 .powergate_mmhub = smu10_powergate_mmhub,
1243 .smus_notify_pwe = smu10_smus_notify_pwe,
1244 .display_clock_voltage_request = smu10_display_clock_voltage_request,
1245 .powergate_gfx = smu10_gfx_off_control,
1246 .powergate_sdma = smu10_powergate_sdma,
1247 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1248 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1251 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1253 hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1254 hwmgr->pptable_func = &pptable_funcs;