drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
 393 {
 394         /* Reset voting clients before disabling DPM */
 395         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 396                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 397         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 398                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 399
 400         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 401                         ixCG_FREQ_TRAN_VOTING_0, 0);
 402         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 403                         ixCG_FREQ_TRAN_VOTING_1, 0);
 404         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 405                         ixCG_FREQ_TRAN_VOTING_2, 0);
 406         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 407                         ixCG_FREQ_TRAN_VOTING_3, 0);
 408         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 409                         ixCG_FREQ_TRAN_VOTING_4, 0);
 410         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 411                         ixCG_FREQ_TRAN_VOTING_5, 0);
 412         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 413                         ixCG_FREQ_TRAN_VOTING_6, 0);
 414         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 415                         ixCG_FREQ_TRAN_VOTING_7, 0);
 416
 417         return 0;
 418 }
 419
 420 /**
 421 * Get the location of various tables inside the FW image.
 422 *
 423 * @param    hwmgr  the address of the powerplay hardware manager.
 424 * @return   always  0
 425 */
 426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 427 {
 428         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 429         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 430         uint32_t tmp;
 431         int result;
 432         bool error = false;
 433
 434         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 435                         SMU7_FIRMWARE_HEADER_LOCATION +
 436                         offsetof(SMU74_Firmware_Header, DpmTable),
 437                         &tmp, data->sram_end);
 438
 439         if (0 == result)
 440                 data->dpm_table_start = tmp;
 441
 442         error |= (0 != result);
 443
 444         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 445                         SMU7_FIRMWARE_HEADER_LOCATION +
 446                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 447                         &tmp, data->sram_end);
 448
 449         if (!result) {
 450                 data->soft_regs_start = tmp;
 451                 smu_data->soft_regs_start = tmp;
 452         }
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 data->mc_reg_table_start = tmp;
 463
 464         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 465                         SMU7_FIRMWARE_HEADER_LOCATION +
 466                         offsetof(SMU74_Firmware_Header, FanTable),
 467                         &tmp, data->sram_end);
 468
 469         if (!result)
 470                 data->fan_table_start = tmp;
 471
 472         error |= (0 != result);
 473
 474         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 475                         SMU7_FIRMWARE_HEADER_LOCATION +
 476                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 477                         &tmp, data->sram_end);
 478
 479         if (!result)
 480                 data->arb_table_start = tmp;
 481
 482         error |= (0 != result);
 483
 484         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 485                         SMU7_FIRMWARE_HEADER_LOCATION +
 486                         offsetof(SMU74_Firmware_Header, Version),
 487                         &tmp, data->sram_end);
 488
 489         if (!result)
 490                 hwmgr->microcode_version_info.SMC = tmp;
 491
 492         error |= (0 != result);
 493
 494         return error ? -1 : 0;
 495 }
 496
 497 /* Copy one arb setting to another and then switch the active set.
 498  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 499  */
 500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 501                 uint32_t arb_src, uint32_t arb_dest)
 502 {
 503         uint32_t mc_arb_dram_timing;
 504         uint32_t mc_arb_dram_timing2;
 505         uint32_t burst_time;
 506         uint32_t mc_cg_config;
 507
 508         switch (arb_src) {
 509         case MC_CG_ARB_FREQ_F0:
 510                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 511                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 512                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 513                 break;
 514         case MC_CG_ARB_FREQ_F1:
 515                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 516                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 517                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         switch (arb_dest) {
 524         case MC_CG_ARB_FREQ_F0:
 525                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 526                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 527                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 528                 break;
 529         case MC_CG_ARB_FREQ_F1:
 530                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 531                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 532                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 533                 break;
 534         default:
 535                 return -EINVAL;
 536         }
 537
 538         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 539         mc_cg_config |= 0x0000000F;
 540         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 541         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 542
 543         return 0;
 544 }
 545
 546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
 547 {
 548         return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
 549 }
 550
 551 /**
 552 * Initial switch from ARB F0->F1
 553 *
 554 * @param    hwmgr  the address of the powerplay hardware manager.
 555 * @return   always 0
 556 * This function is to be called from the SetPowerState table.
 557 */
 558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 559 {
 560         return polaris10_copy_and_switch_arb_sets(hwmgr,
 561                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 562 }
 563
 564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 565 {
 566         uint32_t tmp;
 567
 568         tmp = (cgs_read_ind_register(hwmgr->device,
 569                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 570                         0x0000ff00) >> 8;
 571
 572         if (tmp == MC_CG_ARB_FREQ_F0)
 573                 return 0;
 574
 575         return polaris10_copy_and_switch_arb_sets(hwmgr,
 576                         tmp, MC_CG_ARB_FREQ_F0);
 577 }
 578
 579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 580 {
 581         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 582         struct phm_ppt_v1_information *table_info =
 583                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 584         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 585         uint32_t i, max_entry;
 586
 587         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 588                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 589                         return -EINVAL);
 590
 591         if (data->use_pcie_performance_levels &&
 592                         !data->use_pcie_power_saving_levels) {
 593                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 594                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 595         } else if (!data->use_pcie_performance_levels &&
 596                         data->use_pcie_power_saving_levels) {
 597                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 598                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 599         }
 600
 601         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 602                                         SMU74_MAX_LEVELS_LINK,
 603                                         MAX_REGULAR_DPM_NUMBER);
 604
 605         if (pcie_table != NULL) {
 606                 /* max_entry is used to make sure we reserve one PCIE level
 607                  * for boot level (fix for A+A PSPP issue).
 608                  * If PCIE table from PPTable have ULV entry + 8 entries,
 609                  * then ignore the last entry.*/
 610                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 611                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 612                 for (i = 1; i < max_entry; i++) {
 613                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 614                                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                                         pcie_table->entries[i].gen_speed),
 616                                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                                         pcie_table->entries[i].lane_width));
 618                 }
 619                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 620
 621                 /* Setup BIF_SCLK levels */
 622                 for (i = 0; i < max_entry; i++)
 623                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 624         } else {
 625                 /* Hardcode Pcie Table */
 626                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 627                                 get_pcie_gen_support(data->pcie_gen_cap,
 628                                                 PP_Min_PCIEGen),
 629                                 get_pcie_lane_support(data->pcie_lane_cap,
 630                                                 PP_Max_PCIELane));
 631                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 632                                 get_pcie_gen_support(data->pcie_gen_cap,
 633                                                 PP_Min_PCIEGen),
 634                                 get_pcie_lane_support(data->pcie_lane_cap,
 635                                                 PP_Max_PCIELane));
 636                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 637                                 get_pcie_gen_support(data->pcie_gen_cap,
 638                                                 PP_Max_PCIEGen),
 639                                 get_pcie_lane_support(data->pcie_lane_cap,
 640                                                 PP_Max_PCIELane));
 641                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 642                                 get_pcie_gen_support(data->pcie_gen_cap,
 643                                                 PP_Max_PCIEGen),
 644                                 get_pcie_lane_support(data->pcie_lane_cap,
 645                                                 PP_Max_PCIELane));
 646                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 647                                 get_pcie_gen_support(data->pcie_gen_cap,
 648                                                 PP_Max_PCIEGen),
 649                                 get_pcie_lane_support(data->pcie_lane_cap,
 650                                                 PP_Max_PCIELane));
 651                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 652                                 get_pcie_gen_support(data->pcie_gen_cap,
 653                                                 PP_Max_PCIEGen),
 654                                 get_pcie_lane_support(data->pcie_lane_cap,
 655                                                 PP_Max_PCIELane));
 656
 657                 data->dpm_table.pcie_speed_table.count = 6;
 658         }
 659         /* Populate last level for boot PCIE level, but do not increment count. */
 660         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 661                         data->dpm_table.pcie_speed_table.count,
 662                         get_pcie_gen_support(data->pcie_gen_cap,
 663                                         PP_Min_PCIEGen),
 664                         get_pcie_lane_support(data->pcie_lane_cap,
 665                                         PP_Max_PCIELane));
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * This function is to initalize all DPM state tables
 672  * for SMU7 based on the dependency table.
 673  * Dynamic state patching function will then trim these
 674  * state tables to the allowed range based
 675  * on the power policy or external client requests,
 676  * such as UVD request, etc.
 677  */
 678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 679 {
 680         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 681         struct phm_ppt_v1_information *table_info =
 682                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 683         uint32_t i;
 684
 685         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 686                         table_info->vdd_dep_on_sclk;
 687         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 688                         table_info->vdd_dep_on_mclk;
 689
 690         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 691                         "SCLK dependency table is missing. This table is mandatory",
 692                         return -EINVAL);
 693         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 694                         "SCLK dependency table has to have is missing."
 695                         "This table is mandatory",
 696                         return -EINVAL);
 697
 698         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 699                         "MCLK dependency table is missing. This table is mandatory",
 700                         return -EINVAL);
 701         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 702                         "MCLK dependency table has to have is missing."
 703                         "This table is mandatory",
 704                         return -EINVAL);
 705
 706         /* clear the state table to reset everything to default */
 707         phm_reset_single_dpm_table(
 708                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 709         phm_reset_single_dpm_table(
 710                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 711
 712
 713         /* Initialize Sclk DPM table based on allow Sclk values */
 714         data->dpm_table.sclk_table.count = 0;
 715         for (i = 0; i < dep_sclk_table->count; i++) {
 716                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 717                                                 dep_sclk_table->entries[i].clk) {
 718
 719                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 720                                         dep_sclk_table->entries[i].clk;
 721
 722                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 723                                         (i == 0) ? true : false;
 724                         data->dpm_table.sclk_table.count++;
 725                 }
 726         }
 727
 728         /* Initialize Mclk DPM table based on allow Mclk values */
 729         data->dpm_table.mclk_table.count = 0;
 730         for (i = 0; i < dep_mclk_table->count; i++) {
 731                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 732                                 [data->dpm_table.mclk_table.count - 1].value !=
 733                                                 dep_mclk_table->entries[i].clk) {
 734                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 735                                                         dep_mclk_table->entries[i].clk;
 736                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 737                                                         (i == 0) ? true : false;
 738                         data->dpm_table.mclk_table.count++;
 739                 }
 740         }
 741
 742         /* setup PCIE gen speed levels */
 743         polaris10_setup_default_pcie_table(hwmgr);
 744
 745         /* save a copy of the default DPM table */
 746         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 747                         sizeof(struct polaris10_dpm_table));
 748
 749         return 0;
 750 }
 751
 752 uint8_t convert_to_vid(uint16_t vddc)
 753 {
 754         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 755 }
 756
 757 /**
 758  * Mvdd table preparation for SMC.
 759  *
 760  * @param    *hwmgr The address of the hardware manager.
 761  * @param    *table The SMC DPM table structure to be populated.
 762  * @return   0
 763  */
 764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 765                         SMU74_Discrete_DpmTable *table)
 766 {
 767         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 768         uint32_t count, level;
 769
 770         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 771                 count = data->mvdd_voltage_table.count;
 772                 if (count > SMU_MAX_SMIO_LEVELS)
 773                         count = SMU_MAX_SMIO_LEVELS;
 774                 for (level = 0; level < count; level++) {
 775                         table->SmioTable2.Pattern[level].Voltage =
 776                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 777                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 778                         table->SmioTable2.Pattern[level].Smio =
 779                                 (uint8_t) level;
 780                         table->Smio[level] |=
 781                                 data->mvdd_voltage_table.entries[level].smio_low;
 782                 }
 783                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 784
 785                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 792                                         struct SMU74_Discrete_DpmTable *table)
 793 {
 794         uint32_t count, level;
 795         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 796
 797         count = data->vddci_voltage_table.count;
 798
 799         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 800                 if (count > SMU_MAX_SMIO_LEVELS)
 801                         count = SMU_MAX_SMIO_LEVELS;
 802                 for (level = 0; level < count; ++level) {
 803                         table->SmioTable1.Pattern[level].Voltage =
 804                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 805                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 806
 807                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 808                 }
 809         }
 810
 811         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 812
 813         return 0;
 814 }
 815
 816 /**
 817 * Preparation of vddc and vddgfx CAC tables for SMC.
 818 *
 819 * @param    hwmgr  the address of the hardware manager
 820 * @param    table  the SMC DPM table structure to be populated
 821 * @return   always 0
 822 */
 823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 824                 struct SMU74_Discrete_DpmTable *table)
 825 {
 826         uint32_t count;
 827         uint8_t index;
 828         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 829         struct phm_ppt_v1_information *table_info =
 830                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 831         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 832                         table_info->vddc_lookup_table;
 833         /* tables is already swapped, so in order to use the value from it,
 834          * we need to swap it back.
 835          * We are populating vddc CAC data to BapmVddc table
 836          * in split and merged mode
 837          */
 838         for (count = 0; count < lookup_table->count; count++) {
 839                 index = phm_get_voltage_index(lookup_table,
 840                                 data->vddc_voltage_table.entries[count].value);
 841                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 842                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 843                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 844         }
 845
 846         return 0;
 847 }
 848
 849 /**
 850 * Preparation of voltage tables for SMC.
 851 *
 852 * @param    hwmgr   the address of the hardware manager
 853 * @param    table   the SMC DPM table structure to be populated
 854 * @return   always  0
 855 */
 856
 857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 858                 struct SMU74_Discrete_DpmTable *table)
 859 {
 860         polaris10_populate_smc_vddci_table(hwmgr, table);
 861         polaris10_populate_smc_mvdd_table(hwmgr, table);
 862         polaris10_populate_cac_table(hwmgr, table);
 863
 864         return 0;
 865 }
 866
 867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 868                 struct SMU74_Discrete_Ulv *state)
 869 {
 870         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 871         struct phm_ppt_v1_information *table_info =
 872                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 873
 874         state->CcPwrDynRm = 0;
 875         state->CcPwrDynRm1 = 0;
 876
 877         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 878         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 879                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 880
 881         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 882
 883         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 884         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 885         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 886
 887         return 0;
 888 }
 889
 890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 891                 struct SMU74_Discrete_DpmTable *table)
 892 {
 893         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 894 }
 895
 896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 897                 struct SMU74_Discrete_DpmTable *table)
 898 {
 899         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 900         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 901         int i;
 902
 903         /* Index (dpm_table->pcie_speed_table.count)
 904          * is reserved for PCIE boot level. */
 905         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 906                 table->LinkLevel[i].PcieGenSpeed  =
 907                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 908                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 909                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 910                 table->LinkLevel[i].EnabledForActivity = 1;
 911                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 912                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 913                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 914         }
 915
 916         data->smc_state_table.LinkLevelCount =
 917                         (uint8_t)dpm_table->pcie_speed_table.count;
 918         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 919                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 920
 921         return 0;
 922 }
 923
 924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 925 {
 926         uint32_t reference_clock, tmp;
 927         struct cgs_display_info info = {0};
 928         struct cgs_mode_info mode_info;
 929
 930         info.mode_info = &mode_info;
 931
 932         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 933
 934         if (tmp)
 935                 return TCLK;
 936
 937         cgs_get_active_displays_info(hwmgr->device, &info);
 938         reference_clock = mode_info.ref_clock;
 939
 940         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 941
 942         if (0 != tmp)
 943                 return reference_clock / 4;
 944
 945         return reference_clock;
 946 }
 947
 948 /**
 949 * Calculates the SCLK dividers using the provided engine clock
 950 *
 951 * @param    hwmgr  the address of the hardware manager
 952 * @param    clock  the engine clock to use to populate the structure
 953 * @param    sclk   the SMC SCLK structure to be populated
 954 */
 955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 956                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 957 {
 958         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 959         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 960         struct pp_atomctrl_clock_dividers_ai dividers;
 961
 962         uint32_t ref_clock;
 963         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 964         uint8_t i;
 965         int result;
 966         uint64_t temp;
 967
 968         sclk_setting->SclkFrequency = clock;
 969         /* get the engine clock dividers for this clock value */
 970         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 971         if (result == 0) {
 972                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 973                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 974                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 975                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 976                 sclk_setting->Sclk_slew_rate = 0x400;
 977                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 978                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 979                 sclk_setting->SSc_En = dividers.ucSscEnable;
 980                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 981                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 982                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 983                 return result;
 984         }
 985
 986         ref_clock = polaris10_get_xclk(hwmgr);
 987
 988         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 989                 if (clock > data->range_table[i].trans_lower_frequency
 990                 && clock <= data->range_table[i].trans_upper_frequency) {
 991                         sclk_setting->PllRange = i;
 992                         break;
 993                 }
 994         }
 995
 996         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 997         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 998         temp <<= 0x10;
 999         do_div(temp, ref_clock);
1000         sclk_setting->Fcw_frac = temp & 0xffff;
1001
1002         pcc_target_percent = 10; /*  Hardcode 10% for now. */
1003         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1005
1006         ss_target_percent = 2; /*  Hardcode 2% for now. */
1007         sclk_setting->SSc_En = 0;
1008         if (ss_target_percent) {
1009                 sclk_setting->SSc_En = 1;
1010                 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1013                 temp <<= 0x10;
1014                 do_div(temp, ref_clock);
1015                 sclk_setting->Fcw1_frac = temp & 0xffff;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1024 {
1025         uint32_t i;
1026         uint16_t vddci;
1027         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1028
1029         *voltage = *mvdd = 0;
1030
1031         /* clock - voltage dependency table is empty table */
1032         if (dep_table->count == 0)
1033                 return -EINVAL;
1034
1035         for (i = 0; i < dep_table->count; i++) {
1036                 /* find first sclk bigger than request */
1037                 if (dep_table->entries[i].clk >= clock) {
1038                         *voltage |= (dep_table->entries[i].vddc *
1039                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1040                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043                         else if (dep_table->entries[i].vddci)
1044                                 *voltage |= (dep_table->entries[i].vddci *
1045                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1046                         else {
1047                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048                                                 (dep_table->entries[i].vddc -
1049                                                                 (uint16_t)data->vddc_vddci_delta));
1050                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1051                         }
1052
1053                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1055                                         VOLTAGE_SCALE;
1056                         else if (dep_table->entries[i].mvdd)
1057                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1058                                         VOLTAGE_SCALE;
1059
1060                         *voltage |= 1 << PHASES_SHIFT;
1061                         return 0;
1062                 }
1063         }
1064
1065         /* sclk is bigger than max sclk in the dependence table */
1066         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1067
1068         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071         else if (dep_table->entries[i-1].vddci) {
1072                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073                                 (dep_table->entries[i].vddc -
1074                                                 (uint16_t)data->vddc_vddci_delta));
1075                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1076         }
1077
1078         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080         else if (dep_table->entries[i].mvdd)
1081                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1082
1083         return 0;
1084 }
1085
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1088   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1090   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1091   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1092   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1093   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1094   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1095
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1097 {
1098         uint32_t i, ref_clk;
1099         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1101         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1102
1103         ref_clk = polaris10_get_xclk(hwmgr);
1104
1105         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1110
1111                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1113
1114                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1117                 }
1118                 return;
1119         }
1120
1121         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1122
1123                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1125
1126                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1129
1130                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1132
1133                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1136         }
1137 }
1138
1139 /**
1140 * Populates single SMC SCLK structure using the provided engine clock
1141 *
1142 * @param    hwmgr      the address of the hardware manager
1143 * @param    clock the engine clock to use to populate the structure
1144 * @param    sclk        the SMC SCLK structure to be populated
1145 */
1146
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148                 uint32_t clock, uint16_t sclk_al_threshold,
1149                 struct SMU74_Discrete_GraphicsLevel *level)
1150 {
1151         int result, i, temp;
1152         /* PP_Clocks minClocks; */
1153         uint32_t mvdd;
1154         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155         struct phm_ppt_v1_information *table_info =
1156                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157         SMU_SclkSetting curr_sclk_setting = { 0 };
1158
1159         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1160
1161         /* populate graphics levels */
1162         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163                         table_info->vdd_dep_on_sclk, clock,
1164                         &level->MinVoltage, &mvdd);
1165
1166         PP_ASSERT_WITH_CODE((0 == result),
1167                         "can not find VDDC voltage value for "
1168                         "VDDC engine clock dependency table",
1169                         return result);
1170         level->ActivityLevel = sclk_al_threshold;
1171
1172         level->CcPwrDynRm = 0;
1173         level->CcPwrDynRm1 = 0;
1174         level->EnabledForActivity = 0;
1175         level->EnabledForThrottle = 1;
1176         level->UpHyst = 10;
1177         level->DownHyst = 0;
1178         level->VoltageDownHyst = 0;
1179         level->PowerThrottle = 0;
1180
1181         /*
1182         * TODO: get minimum clocks from dal configaration
1183         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1184         */
1185         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1186
1187         /* get level->DeepSleepDivId
1188         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1190         */
1191         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1193                 temp = clock >> i;
1194
1195                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1196                         break;
1197         }
1198
1199         level->DeepSleepDivId = i;
1200
1201         /* Default to slow, highest DPM level will be
1202          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1203          */
1204         if (data->update_up_hyst)
1205                 level->UpHyst = (uint8_t)data->up_hyst;
1206         if (data->update_down_hyst)
1207                 level->DownHyst = (uint8_t)data->down_hyst;
1208
1209         level->SclkSetting = curr_sclk_setting;
1210
1211         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1225         return 0;
1226 }
1227
1228 /**
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1230 *
1231 * @param    hwmgr      the address of the hardware manager
1232 */
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1234 {
1235         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237         struct phm_ppt_v1_information *table_info =
1238                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1241         int result = 0;
1242         uint32_t array = data->dpm_table_start +
1243                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245                         SMU74_MAX_LEVELS_GRAPHICS;
1246         struct SMU74_Discrete_GraphicsLevel *levels =
1247                         data->smc_state_table.GraphicsLevel;
1248         uint32_t i, max_entry;
1249         uint8_t hightest_pcie_level_enabled = 0,
1250                 lowest_pcie_level_enabled = 0,
1251                 mid_pcie_level_enabled = 0,
1252                 count = 0;
1253
1254         polaris10_get_sclk_range_table(hwmgr);
1255
1256         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1257
1258                 result = polaris10_populate_single_graphic_level(hwmgr,
1259                                 dpm_table->sclk_table.dpm_levels[i].value,
1260                                 (uint16_t)data->activity_target[i],
1261                                 &(data->smc_state_table.GraphicsLevel[i]));
1262                 if (result)
1263                         return result;
1264
1265                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1266                 if (i > 1)
1267                         levels[i].DeepSleepDivId = 0;
1268         }
1269         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270                                         PHM_PlatformCaps_SPLLShutdownSupport))
1271                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1272
1273         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274         data->smc_state_table.GraphicsDpmLevelCount =
1275                         (uint8_t)dpm_table->sclk_table.count;
1276         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1278
1279
1280         if (pcie_table != NULL) {
1281                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282                                 "There must be 1 or more PCIE levels defined in PPTable.",
1283                                 return -EINVAL);
1284                 max_entry = pcie_entry_cnt - 1;
1285                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286                         levels[i].pcieDpmLevel =
1287                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1288         } else {
1289                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292                         hightest_pcie_level_enabled++;
1293
1294                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296                                                 (1 << lowest_pcie_level_enabled)) == 0))
1297                         lowest_pcie_level_enabled++;
1298
1299                 while ((count < hightest_pcie_level_enabled) &&
1300                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1302                         count++;
1303
1304                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305                                 hightest_pcie_level_enabled ?
1306                                                 (lowest_pcie_level_enabled + 1 + count) :
1307                                                 hightest_pcie_level_enabled;
1308
1309                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1312
1313                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1315
1316                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1318         }
1319         /* level count will send to smc once at init smc table and never change */
1320         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321                         (uint32_t)array_size, data->sram_end);
1322
1323         return result;
1324 }
1325
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1328 {
1329         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330         struct phm_ppt_v1_information *table_info =
1331                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1332         int result = 0;
1333         struct cgs_display_info info = {0, 0, NULL};
1334
1335         cgs_get_active_displays_info(hwmgr->device, &info);
1336
1337         if (table_info->vdd_dep_on_mclk) {
1338                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339                                 table_info->vdd_dep_on_mclk, clock,
1340                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341                 PP_ASSERT_WITH_CODE((0 == result),
1342                                 "can not find MinVddc voltage value from memory "
1343                                 "VDDC voltage dependency table", return result);
1344         }
1345
1346         mem_level->MclkFrequency = clock;
1347         mem_level->EnabledForThrottle = 1;
1348         mem_level->EnabledForActivity = 0;
1349         mem_level->UpHyst = 0;
1350         mem_level->DownHyst = 100;
1351         mem_level->VoltageDownHyst = 0;
1352         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353         mem_level->StutterEnable = false;
1354         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1355
1356         data->display_timing.num_existing_displays = info.display_count;
1357
1358         if ((data->mclk_stutter_mode_threshold) &&
1359                 (clock <= data->mclk_stutter_mode_threshold) &&
1360                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361                                 STUTTER_ENABLE) & 0x1))
1362                 mem_level->StutterEnable = true;
1363
1364         if (!result) {
1365                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1369         }
1370         return result;
1371 }
1372
1373 /**
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1375 *
1376 * @param    hwmgr      the address of the hardware manager
1377 */
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1379 {
1380         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1382         int result;
1383         /* populate MCLK dpm table to SMU7 */
1384         uint32_t array = data->dpm_table_start +
1385                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387                         SMU74_MAX_LEVELS_MEMORY;
1388         struct SMU74_Discrete_MemoryLevel *levels =
1389                         data->smc_state_table.MemoryLevel;
1390         uint32_t i;
1391
1392         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394                                 "can not populate memory level as memory clock is zero",
1395                                 return -EINVAL);
1396                 result = polaris10_populate_single_memory_level(hwmgr,
1397                                 dpm_table->mclk_table.dpm_levels[i].value,
1398                                 &levels[i]);
1399                 if (i == dpm_table->mclk_table.count - 1) {
1400                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401                         levels[i].EnabledForActivity = 1;
1402                 }
1403                 if (result)
1404                         return result;
1405         }
1406
1407         /* in order to prevent MC activity from stutter mode to push DPM up.
1408          * the UVD change complements this by putting the MCLK in
1409          * a higher state by default such that we are not effected by
1410          * up threshold or and MCLK DPM latency.
1411          */
1412         levels[0].ActivityLevel = 0x1f;
1413         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1414
1415         data->smc_state_table.MemoryDpmLevelCount =
1416                         (uint8_t)dpm_table->mclk_table.count;
1417         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1419
1420         /* level count will send to smc once at init smc table and never change */
1421         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422                         (uint32_t)array_size, data->sram_end);
1423
1424         return result;
1425 }
1426
1427 /**
1428 * Populates the SMC MVDD structure using the provided memory clock.
1429 *
1430 * @param    hwmgr      the address of the hardware manager
1431 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param    voltage     the SMC VOLTAGE structure to be populated
1433 */
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435                 uint32_t mclk, SMIO_Pattern *smio_pat)
1436 {
1437         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438         struct phm_ppt_v1_information *table_info =
1439                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1440         uint32_t i = 0;
1441
1442         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443                 /* find mvdd value which clock is more than request */
1444                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1447                                 break;
1448                         }
1449                 }
1450                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451                                 "MVDD Voltage is outside the supported range.",
1452                                 return -EINVAL);
1453         } else
1454                 return -EINVAL;
1455
1456         return 0;
1457 }
1458
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460                 SMU74_Discrete_DpmTable *table)
1461 {
1462         int result = 0;
1463         uint32_t sclk_frequency;
1464         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465         struct phm_ppt_v1_information *table_info =
1466                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467         SMIO_Pattern vol_level;
1468         uint32_t mvdd;
1469         uint16_t us_mvdd;
1470
1471         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1472
1473         if (!data->sclk_dpm_key_disabled) {
1474                 /* Get MinVoltage and Frequency from DPM0,
1475                  * already converted to SMC_UL */
1476                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1477                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478                                 table_info->vdd_dep_on_sclk,
1479                                 table->ACPILevel.SclkFrequency,
1480                                 &table->ACPILevel.MinVoltage, &mvdd);
1481                 PP_ASSERT_WITH_CODE((0 == result),
1482                                 "Cannot find ACPI VDDC voltage value "
1483                                 "in Clock Dependency Table", );
1484         } else {
1485                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1486                 table->ACPILevel.MinVoltage =
1487                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1488         }
1489
1490         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1491         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1492
1493         table->ACPILevel.DeepSleepDivId = 0;
1494         table->ACPILevel.CcPwrDynRm = 0;
1495         table->ACPILevel.CcPwrDynRm1 = 0;
1496
1497         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1498         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1499         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1500         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1501
1502         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1503         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1504         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1505         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1506         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1507         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1508         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1509         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1510         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1511         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1512
1513         if (!data->mclk_dpm_key_disabled) {
1514                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1515                 table->MemoryACPILevel.MclkFrequency =
1516                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1517                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1518                                 table_info->vdd_dep_on_mclk,
1519                                 table->MemoryACPILevel.MclkFrequency,
1520                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1521                 PP_ASSERT_WITH_CODE((0 == result),
1522                                 "Cannot find ACPI VDDCI voltage value "
1523                                 "in Clock Dependency Table",
1524                                 );
1525         } else {
1526                 table->MemoryACPILevel.MclkFrequency =
1527                                 data->vbios_boot_state.mclk_bootup_value;
1528                 table->MemoryACPILevel.MinVoltage =
1529                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1530         }
1531
1532         us_mvdd = 0;
1533         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1534                         (data->mclk_dpm_key_disabled))
1535                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1536         else {
1537                 if (!polaris10_populate_mvdd_value(hwmgr,
1538                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1539                                 &vol_level))
1540                         us_mvdd = vol_level.Voltage;
1541         }
1542
1543         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1544                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1545         else
1546                 table->MemoryACPILevel.MinMvdd = 0;
1547
1548         table->MemoryACPILevel.StutterEnable = false;
1549
1550         table->MemoryACPILevel.EnabledForThrottle = 0;
1551         table->MemoryACPILevel.EnabledForActivity = 0;
1552         table->MemoryACPILevel.UpHyst = 0;
1553         table->MemoryACPILevel.DownHyst = 100;
1554         table->MemoryACPILevel.VoltageDownHyst = 0;
1555         table->MemoryACPILevel.ActivityLevel =
1556                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1557
1558         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1559         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1560
1561         return result;
1562 }
1563
1564 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1565                 SMU74_Discrete_DpmTable *table)
1566 {
1567         int result = -EINVAL;
1568         uint8_t count;
1569         struct pp_atomctrl_clock_dividers_vi dividers;
1570         struct phm_ppt_v1_information *table_info =
1571                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1572         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1573                         table_info->mm_dep_table;
1574         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1575
1576         table->VceLevelCount = (uint8_t)(mm_table->count);
1577         table->VceBootLevel = 0;
1578
1579         for (count = 0; count < table->VceLevelCount; count++) {
1580                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1581                 table->VceLevel[count].MinVoltage = 0;
1582                 table->VceLevel[count].MinVoltage |=
1583                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1584                 table->VceLevel[count].MinVoltage |=
1585                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1586                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1587                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1588
1589                 /*retrieve divider value for VBIOS */
1590                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1591                                 table->VceLevel[count].Frequency, &dividers);
1592                 PP_ASSERT_WITH_CODE((0 == result),
1593                                 "can not find divide id for VCE engine clock",
1594                                 return result);
1595
1596                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1597
1598                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1599                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1600         }
1601         return result;
1602 }
1603
1604 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1605                 SMU74_Discrete_DpmTable *table)
1606 {
1607         int result = -EINVAL;
1608         uint8_t count;
1609         struct pp_atomctrl_clock_dividers_vi dividers;
1610         struct phm_ppt_v1_information *table_info =
1611                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1612         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1613                         table_info->mm_dep_table;
1614         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1615
1616         table->SamuBootLevel = 0;
1617         table->SamuLevelCount = (uint8_t)(mm_table->count);
1618
1619         for (count = 0; count < table->SamuLevelCount; count++) {
1620                 /* not sure whether we need evclk or not */
1621                 table->SamuLevel[count].MinVoltage = 0;
1622                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1623                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1624                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1625                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1626                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1627                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1628
1629                 /* retrieve divider value for VBIOS */
1630                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1631                                 table->SamuLevel[count].Frequency, &dividers);
1632                 PP_ASSERT_WITH_CODE((0 == result),
1633                                 "can not find divide id for samu clock", return result);
1634
1635                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1636
1637                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1638                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1639         }
1640         return result;
1641 }
1642
1643 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1644                 int32_t eng_clock, int32_t mem_clock,
1645                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1646 {
1647         uint32_t dram_timing;
1648         uint32_t dram_timing2;
1649         uint32_t burst_time;
1650         int result;
1651
1652         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1653                         eng_clock, mem_clock);
1654         PP_ASSERT_WITH_CODE(result == 0,
1655                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1656
1657         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1658         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1659         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1660
1661
1662         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1663         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1664         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1665
1666         return 0;
1667 }
1668
1669 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1670 {
1671         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1672         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1673         uint32_t i, j;
1674         int result = 0;
1675
1676         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1677                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1678                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1679                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1680                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1681                                         &arb_regs.entries[i][j]);
1682                         if (result == 0)
1683                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1684                         if (result != 0)
1685                                 return result;
1686                 }
1687         }
1688
1689         result = polaris10_copy_bytes_to_smc(
1690                         hwmgr->smumgr,
1691                         data->arb_table_start,
1692                         (uint8_t *)&arb_regs,
1693                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1694                         data->sram_end);
1695         return result;
1696 }
1697
1698 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1699                 struct SMU74_Discrete_DpmTable *table)
1700 {
1701         int result = -EINVAL;
1702         uint8_t count;
1703         struct pp_atomctrl_clock_dividers_vi dividers;
1704         struct phm_ppt_v1_information *table_info =
1705                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1707                         table_info->mm_dep_table;
1708         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1709
1710         table->UvdLevelCount = (uint8_t)(mm_table->count);
1711         table->UvdBootLevel = 0;
1712
1713         for (count = 0; count < table->UvdLevelCount; count++) {
1714                 table->UvdLevel[count].MinVoltage = 0;
1715                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1716                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1717                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1718                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1719                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1720                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1721                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1722
1723                 /* retrieve divider value for VBIOS */
1724                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1725                                 table->UvdLevel[count].VclkFrequency, &dividers);
1726                 PP_ASSERT_WITH_CODE((0 == result),
1727                                 "can not find divide id for Vclk clock", return result);
1728
1729                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1730
1731                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1732                                 table->UvdLevel[count].DclkFrequency, &dividers);
1733                 PP_ASSERT_WITH_CODE((0 == result),
1734                                 "can not find divide id for Dclk clock", return result);
1735
1736                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1737
1738                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1739                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1740                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1741
1742         }
1743         return result;
1744 }
1745
1746 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1747                 struct SMU74_Discrete_DpmTable *table)
1748 {
1749         int result = 0;
1750         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1751
1752         table->GraphicsBootLevel = 0;
1753         table->MemoryBootLevel = 0;
1754
1755         /* find boot level from dpm table */
1756         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1757                         data->vbios_boot_state.sclk_bootup_value,
1758                         (uint32_t *)&(table->GraphicsBootLevel));
1759
1760         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1761                         data->vbios_boot_state.mclk_bootup_value,
1762                         (uint32_t *)&(table->MemoryBootLevel));
1763
1764         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1765                         VOLTAGE_SCALE;
1766         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1767                         VOLTAGE_SCALE;
1768         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1769                         VOLTAGE_SCALE;
1770
1771         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1772         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1773         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1774
1775         return 0;
1776 }
1777
1778
1779 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1780 {
1781         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1782         struct phm_ppt_v1_information *table_info =
1783                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1784         uint8_t count, level;
1785
1786         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1787
1788         for (level = 0; level < count; level++) {
1789                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1790                                 data->vbios_boot_state.sclk_bootup_value) {
1791                         data->smc_state_table.GraphicsBootLevel = level;
1792                         break;
1793                 }
1794         }
1795
1796         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1797         for (level = 0; level < count; level++) {
1798                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1799                                 data->vbios_boot_state.mclk_bootup_value) {
1800                         data->smc_state_table.MemoryBootLevel = level;
1801                         break;
1802                 }
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1809 {
1810         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1811         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1812         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1813         struct phm_ppt_v1_information *table_info =
1814                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1815         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1816                         table_info->vdd_dep_on_sclk;
1817
1818         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1819
1820         /* Read SMU_Eefuse to read and calculate RO and determine
1821          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1822          */
1823         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1824                         ixSMU_EFUSE_0 + (67 * 4));
1825         efuse &= 0xFF000000;
1826         efuse = efuse >> 24;
1827
1828         if (hwmgr->chip_id == CHIP_POLARIS10) {
1829                 min = 1000;
1830                 max = 2300;
1831         } else {
1832                 min = 1100;
1833                 max = 2100;
1834         }
1835
1836         ro = efuse * (max -min)/255 + min;
1837
1838         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1839         for (i = 0; i < sclk_table->count; i++) {
1840                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1841                                 sclk_table->entries[i].cks_enable << i;
1842
1843                 volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1844                                         (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1845
1846                 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1847                                 (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
1848
1849                 if (volt_without_cks >= volt_with_cks)
1850                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1851                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1852
1853                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1854         }
1855
1856         /* Populate CKS Lookup Table */
1857         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1858                 stretch_amount2 = 0;
1859         else if (stretch_amount == 3 || stretch_amount == 4)
1860                 stretch_amount2 = 1;
1861         else {
1862                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1863                                 PHM_PlatformCaps_ClockStretcher);
1864                 PP_ASSERT_WITH_CODE(false,
1865                                 "Stretch Amount in PPTable not supported\n",
1866                                 return -EINVAL);
1867         }
1868
1869         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1870         value &= 0xFFFFFFFE;
1871         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1872
1873         return 0;
1874 }
1875
1876 /**
1877 * Populates the SMC VRConfig field in DPM table.
1878 *
1879 * @param    hwmgr   the address of the hardware manager
1880 * @param    table   the SMC DPM table structure to be populated
1881 * @return   always 0
1882 */
1883 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1884                 struct SMU74_Discrete_DpmTable *table)
1885 {
1886         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1887         uint16_t config;
1888
1889         config = VR_MERGED_WITH_VDDC;
1890         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1891
1892         /* Set Vddc Voltage Controller */
1893         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1894                 config = VR_SVI2_PLANE_1;
1895                 table->VRConfig |= config;
1896         } else {
1897                 PP_ASSERT_WITH_CODE(false,
1898                                 "VDDC should be on SVI2 control in merged mode!",
1899                                 );
1900         }
1901         /* Set Vddci Voltage Controller */
1902         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1903                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1904                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1905         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1906                 config = VR_SMIO_PATTERN_1;
1907                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1908         } else {
1909                 config = VR_STATIC_VOLTAGE;
1910                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1911         }
1912         /* Set Mvdd Voltage Controller */
1913         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1914                 config = VR_SVI2_PLANE_2;
1915                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1916         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1917                 config = VR_SMIO_PATTERN_2;
1918                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1919         } else {
1920                 config = VR_STATIC_VOLTAGE;
1921                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1922         }
1923
1924         return 0;
1925 }
1926
1927
1928 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1929 {
1930         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1931         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1932         int result = 0;
1933         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1934         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1935         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1936         uint32_t tmp, i;
1937         struct pp_smumgr *smumgr = hwmgr->smumgr;
1938         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1939
1940         struct phm_ppt_v1_information *table_info =
1941                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1942         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1943                         table_info->vdd_dep_on_sclk;
1944
1945
1946         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1947                 return result;
1948
1949         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1950
1951         if (0 == result) {
1952                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1953                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1954                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1955                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1956                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1957                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1958                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1959                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1960                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1961                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1962                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1963                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1964                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1965                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1966                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1967                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1968                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1969                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1970                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1971                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1972                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1973                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1974                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1975                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1976
1977                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1978                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1979                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1980                 }
1981
1982                 result = polaris10_read_smc_sram_dword(smumgr,
1983                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1984                                 &tmp, data->sram_end);
1985
1986                 polaris10_copy_bytes_to_smc(smumgr,
1987                                         tmp,
1988                                         (uint8_t *)&AVFS_meanNsigma,
1989                                         sizeof(AVFS_meanNsigma_t),
1990                                         data->sram_end);
1991
1992                 result = polaris10_read_smc_sram_dword(smumgr,
1993                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1994                                 &tmp, data->sram_end);
1995                 polaris10_copy_bytes_to_smc(smumgr,
1996                                         tmp,
1997                                         (uint8_t *)&AVFS_SclkOffset,
1998                                         sizeof(AVFS_Sclk_Offset_t),
1999                                         data->sram_end);
2000
2001                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2002                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2003                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2004                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2005                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2006         }
2007         return result;
2008 }
2009
2010
2011 /**
2012 * Initializes the SMC table and uploads it
2013 *
2014 * @param    hwmgr  the address of the powerplay hardware manager.
2015 * @return   always 0
2016 */
2017 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2018 {
2019         int result;
2020         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2021         struct phm_ppt_v1_information *table_info =
2022                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2023         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2024         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2025         uint8_t i;
2026         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2027         pp_atomctrl_clock_dividers_vi dividers;
2028
2029         result = polaris10_setup_default_dpm_tables(hwmgr);
2030         PP_ASSERT_WITH_CODE(0 == result,
2031                         "Failed to setup default DPM tables!", return result);
2032
2033         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2034                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2035
2036         table->SystemFlags = 0;
2037         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2038                         PHM_PlatformCaps_AutomaticDCTransition))
2039                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2040
2041         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2042                         PHM_PlatformCaps_StepVddc))
2043                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2044
2045         if (data->is_memory_gddr5)
2046                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2047
2048         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2049                 result = polaris10_populate_ulv_state(hwmgr, table);
2050                 PP_ASSERT_WITH_CODE(0 == result,
2051                                 "Failed to initialize ULV state!", return result);
2052                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2053                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2054         }
2055
2056         result = polaris10_populate_smc_link_level(hwmgr, table);
2057         PP_ASSERT_WITH_CODE(0 == result,
2058                         "Failed to initialize Link Level!", return result);
2059
2060         result = polaris10_populate_all_graphic_levels(hwmgr);
2061         PP_ASSERT_WITH_CODE(0 == result,
2062                         "Failed to initialize Graphics Level!", return result);
2063
2064         result = polaris10_populate_all_memory_levels(hwmgr);
2065         PP_ASSERT_WITH_CODE(0 == result,
2066                         "Failed to initialize Memory Level!", return result);
2067
2068         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2069         PP_ASSERT_WITH_CODE(0 == result,
2070                         "Failed to initialize ACPI Level!", return result);
2071
2072         result = polaris10_populate_smc_vce_level(hwmgr, table);
2073         PP_ASSERT_WITH_CODE(0 == result,
2074                         "Failed to initialize VCE Level!", return result);
2075
2076         result = polaris10_populate_smc_samu_level(hwmgr, table);
2077         PP_ASSERT_WITH_CODE(0 == result,
2078                         "Failed to initialize SAMU Level!", return result);
2079
2080         /* Since only the initial state is completely set up at this point
2081          * (the other states are just copies of the boot state) we only
2082          * need to populate the  ARB settings for the initial state.
2083          */
2084         result = polaris10_program_memory_timing_parameters(hwmgr);
2085         PP_ASSERT_WITH_CODE(0 == result,
2086                         "Failed to Write ARB settings for the initial state.", return result);
2087
2088         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2089         PP_ASSERT_WITH_CODE(0 == result,
2090                         "Failed to initialize UVD Level!", return result);
2091
2092         result = polaris10_populate_smc_boot_level(hwmgr, table);
2093         PP_ASSERT_WITH_CODE(0 == result,
2094                         "Failed to initialize Boot Level!", return result);
2095
2096         result = polaris10_populate_smc_initailial_state(hwmgr);
2097         PP_ASSERT_WITH_CODE(0 == result,
2098                         "Failed to initialize Boot State!", return result);
2099
2100         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2101         PP_ASSERT_WITH_CODE(0 == result,
2102                         "Failed to populate BAPM Parameters!", return result);
2103
2104         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2105                         PHM_PlatformCaps_ClockStretcher)) {
2106                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2107                 PP_ASSERT_WITH_CODE(0 == result,
2108                                 "Failed to populate Clock Stretcher Data Table!",
2109                                 return result);
2110         }
2111
2112         result = polaris10_populate_avfs_parameters(hwmgr);
2113         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2114
2115         table->CurrSclkPllRange = 0xff;
2116         table->GraphicsVoltageChangeEnable  = 1;
2117         table->GraphicsThermThrottleEnable  = 1;
2118         table->GraphicsInterval = 1;
2119         table->VoltageInterval  = 1;
2120         table->ThermalInterval  = 1;
2121         table->TemperatureLimitHigh =
2122                         table_info->cac_dtp_table->usTargetOperatingTemp *
2123                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2124         table->TemperatureLimitLow  =
2125                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2126                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2127         table->MemoryVoltageChangeEnable = 1;
2128         table->MemoryInterval = 1;
2129         table->VoltageResponseTime = 0;
2130         table->PhaseResponseTime = 0;
2131         table->MemoryThermThrottleEnable = 1;
2132         table->PCIeBootLinkLevel = 0;
2133         table->PCIeGenInterval = 1;
2134         table->VRConfig = 0;
2135
2136         result = polaris10_populate_vr_config(hwmgr, table);
2137         PP_ASSERT_WITH_CODE(0 == result,
2138                         "Failed to populate VRConfig setting!", return result);
2139
2140         table->ThermGpio = 17;
2141         table->SclkStepSize = 0x4000;
2142
2143         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2144                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2145         } else {
2146                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2147                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2148                                 PHM_PlatformCaps_RegulatorHot);
2149         }
2150
2151         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2152                         &gpio_pin)) {
2153                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2154                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2155                                 PHM_PlatformCaps_AutomaticDCTransition);
2156         } else {
2157                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2158                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2159                                 PHM_PlatformCaps_AutomaticDCTransition);
2160         }
2161
2162         /* Thermal Output GPIO */
2163         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2164                         &gpio_pin)) {
2165                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2166                                 PHM_PlatformCaps_ThermalOutGPIO);
2167
2168                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2169
2170                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2171                  * since VBIOS will program this register to set 'inactive state',
2172                  * driver can then determine 'active state' from this and
2173                  * program SMU with correct polarity
2174                  */
2175                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2176                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2177                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2178
2179                 /* if required, combine VRHot/PCC with thermal out GPIO */
2180                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2181                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2182                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2183         } else {
2184                 table->ThermOutGpio = 17;
2185                 table->ThermOutPolarity = 1;
2186                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2187         }
2188
2189         /* Populate BIF_SCLK levels into SMC DPM table */
2190         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2191                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2192                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2193
2194                 if (i == 0)
2195                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2196                 else
2197                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2198         }
2199
2200         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2201                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2202
2203         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2204         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2205         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2206         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2207         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2208         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2209         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2210         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2211         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2212         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2213
2214         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2215         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2216                         data->dpm_table_start +
2217                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2218                         (uint8_t *)&(table->SystemFlags),
2219                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2220                         data->sram_end);
2221         PP_ASSERT_WITH_CODE(0 == result,
2222                         "Failed to upload dpm data to SMC memory!", return result);
2223
2224         return 0;
2225 }
2226
2227 /**
2228 * Initialize the ARB DRAM timing table's index field.
2229 *
2230 * @param    hwmgr  the address of the powerplay hardware manager.
2231 * @return   always 0
2232 */
2233 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2234 {
2235         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2236         uint32_t tmp;
2237         int result;
2238
2239         /* This is a read-modify-write on the first byte of the ARB table.
2240          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2241          * is the field 'current'.
2242          * This solution is ugly, but we never write the whole table only
2243          * individual fields in it.
2244          * In reality this field should not be in that structure
2245          * but in a soft register.
2246          */
2247         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2248                         data->arb_table_start, &tmp, data->sram_end);
2249
2250         if (result)
2251                 return result;
2252
2253         tmp &= 0x00FFFFFF;
2254         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2255
2256         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2257                         data->arb_table_start, tmp, data->sram_end);
2258 }
2259
2260 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2261 {
2262         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2263                         PHM_PlatformCaps_RegulatorHot))
2264                 return smum_send_msg_to_smc(hwmgr->smumgr,
2265                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2266
2267         return 0;
2268 }
2269
2270 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2271 {
2272         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2273                         SCLK_PWRMGT_OFF, 0);
2274         return 0;
2275 }
2276
2277 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2278 {
2279         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2280         struct polaris10_ulv_parm *ulv = &(data->ulv);
2281
2282         if (ulv->ulv_supported)
2283                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2284
2285         return 0;
2286 }
2287
2288 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2289 {
2290         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2291         struct polaris10_ulv_parm *ulv = &(data->ulv);
2292
2293         if (ulv->ulv_supported)
2294                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2295
2296         return 0;
2297 }
2298
2299 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2300 {
2301         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2302                         PHM_PlatformCaps_SclkDeepSleep)) {
2303                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2304                         PP_ASSERT_WITH_CODE(false,
2305                                         "Attempt to enable Master Deep Sleep switch failed!",
2306                                         return -1);
2307         } else {
2308                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2309                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2310                         PP_ASSERT_WITH_CODE(false,
2311                                         "Attempt to disable Master Deep Sleep switch failed!",
2312                                         return -1);
2313                 }
2314         }
2315
2316         return 0;
2317 }
2318
2319 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2320 {
2321         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2322                         PHM_PlatformCaps_SclkDeepSleep)) {
2323                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2324                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2325                         PP_ASSERT_WITH_CODE(false,
2326                                         "Attempt to disable Master Deep Sleep switch failed!",
2327                                         return -1);
2328                 }
2329         }
2330
2331         return 0;
2332 }
2333
2334 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2335 {
2336         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2337         uint32_t soft_register_value = 0;
2338         uint32_t handshake_disables_offset = data->soft_regs_start
2339                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2340
2341         /* enable SCLK dpm */
2342         if (!data->sclk_dpm_key_disabled)
2343                 PP_ASSERT_WITH_CODE(
2344                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2345                 "Failed to enable SCLK DPM during DPM Start Function!",
2346                 return -1);
2347
2348         /* enable MCLK dpm */
2349         if (0 == data->mclk_dpm_key_disabled) {
2350 /* Disable UVD - SMU handshake for MCLK. */
2351                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2352                                         CGS_IND_REG__SMC, handshake_disables_offset);
2353                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2354                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2355                                 handshake_disables_offset, soft_register_value);
2356
2357                 PP_ASSERT_WITH_CODE(
2358                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2359                                                 PPSMC_MSG_MCLKDPM_Enable)),
2360                                 "Failed to enable MCLK DPM during DPM Start Function!",
2361                                 return -1);
2362
2363                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2364
2365                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2366                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2367                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2368                 udelay(10);
2369                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2370                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2371                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2378 {
2379         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2380
2381         /*enable general power management */
2382
2383         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2384                         GLOBAL_PWRMGT_EN, 1);
2385
2386         /* enable sclk deep sleep */
2387
2388         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2389                         DYNAMIC_PM_EN, 1);
2390
2391         /* prepare for PCIE DPM */
2392
2393         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2394                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2395                                         VoltageChangeTimeout), 0x1000);
2396         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2397                         SWRST_COMMAND_1, RESETLC, 0x0);
2398 /*
2399         PP_ASSERT_WITH_CODE(
2400                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2401                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2402                         "Failed to enable voltage DPM during DPM Start Function!",
2403                         return -1);
2404 */
2405
2406         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2407                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2408                 return -1;
2409         }
2410
2411         /* enable PCIE dpm */
2412         if (0 == data->pcie_dpm_key_disabled) {
2413                 PP_ASSERT_WITH_CODE(
2414                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2415                                                 PPSMC_MSG_PCIeDPM_Enable)),
2416                                 "Failed to enable pcie DPM during DPM Start Function!",
2417                                 return -1);
2418         }
2419
2420         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2421                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2422                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2423                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2424                                 "Failed to enable AC DC GPIO Interrupt!",
2425                                 );
2426         }
2427
2428         return 0;
2429 }
2430
2431 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2432 {
2433         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2434
2435         /* disable SCLK dpm */
2436         if (!data->sclk_dpm_key_disabled)
2437                 PP_ASSERT_WITH_CODE(
2438                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2439                                                 PPSMC_MSG_DPM_Disable) == 0),
2440                                 "Failed to disable SCLK DPM!",
2441                                 return -1);
2442
2443         /* disable MCLK dpm */
2444         if (!data->mclk_dpm_key_disabled) {
2445                 PP_ASSERT_WITH_CODE(
2446                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2447                                                 PPSMC_MSG_MCLKDPM_Disable) == 0),
2448                                 "Failed to disable MCLK DPM!",
2449                                 return -1);
2450         }
2451
2452         return 0;
2453 }
2454
2455 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2456 {
2457         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2458
2459         /* disable general power management */
2460         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2461                         GLOBAL_PWRMGT_EN, 0);
2462         /* disable sclk deep sleep */
2463         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2464                         DYNAMIC_PM_EN, 0);
2465
2466         /* disable PCIE dpm */
2467         if (!data->pcie_dpm_key_disabled) {
2468                 PP_ASSERT_WITH_CODE(
2469                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2470                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
2471                                 "Failed to disable pcie DPM during DPM Stop Function!",
2472                                 return -1);
2473         }
2474
2475         if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2476                 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2477                 return -1;
2478         }
2479
2480         return 0;
2481 }
2482
2483 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2484 {
2485         bool protection;
2486         enum DPM_EVENT_SRC src;
2487
2488         switch (sources) {
2489         default:
2490                 printk(KERN_ERR "Unknown throttling event sources.");
2491                 /* fall through */
2492         case 0:
2493                 protection = false;
2494                 /* src is unused */
2495                 break;
2496         case (1 << PHM_AutoThrottleSource_Thermal):
2497                 protection = true;
2498                 src = DPM_EVENT_SRC_DIGITAL;
2499                 break;
2500         case (1 << PHM_AutoThrottleSource_External):
2501                 protection = true;
2502                 src = DPM_EVENT_SRC_EXTERNAL;
2503                 break;
2504         case (1 << PHM_AutoThrottleSource_External) |
2505                         (1 << PHM_AutoThrottleSource_Thermal):
2506                 protection = true;
2507                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2508                 break;
2509         }
2510         /* Order matters - don't enable thermal protection for the wrong source. */
2511         if (protection) {
2512                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2513                                 DPM_EVENT_SRC, src);
2514                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2515                                 THERMAL_PROTECTION_DIS,
2516                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2517                                                 PHM_PlatformCaps_ThermalController));
2518         } else
2519                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2520                                 THERMAL_PROTECTION_DIS, 1);
2521 }
2522
2523 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2524                 PHM_AutoThrottleSource source)
2525 {
2526         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2527
2528         if (!(data->active_auto_throttle_sources & (1 << source))) {
2529                 data->active_auto_throttle_sources |= 1 << source;
2530                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2531         }
2532         return 0;
2533 }
2534
2535 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2536 {
2537         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2538 }
2539
2540 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2541                 PHM_AutoThrottleSource source)
2542 {
2543         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2544
2545         if (data->active_auto_throttle_sources & (1 << source)) {
2546                 data->active_auto_throttle_sources &= ~(1 << source);
2547                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2548         }
2549         return 0;
2550 }
2551
2552 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2553 {
2554         return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2555 }
2556
2557 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2558 {
2559         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2560         data->pcie_performance_request = true;
2561
2562         return 0;
2563 }
2564
2565 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2566 {
2567         int tmp_result, result = 0;
2568         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2569         PP_ASSERT_WITH_CODE(result == 0,
2570                         "DPM is already running right now, no need to enable DPM!",
2571                         return 0);
2572
2573         if (polaris10_voltage_control(hwmgr)) {
2574                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2575                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2576                                 "Failed to enable voltage control!",
2577                                 result = tmp_result);
2578
2579                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2580                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2581                                 "Failed to contruct voltage tables!",
2582                                 result = tmp_result);
2583         }
2584
2585         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2586                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2587                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2588                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2589
2590         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2591                         PHM_PlatformCaps_ThermalController))
2592                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2593                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2594
2595         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2596         PP_ASSERT_WITH_CODE((0 == tmp_result),
2597                         "Failed to program static screen threshold parameters!",
2598                         result = tmp_result);
2599
2600         tmp_result = polaris10_enable_display_gap(hwmgr);
2601         PP_ASSERT_WITH_CODE((0 == tmp_result),
2602                         "Failed to enable display gap!", result = tmp_result);
2603
2604         tmp_result = polaris10_program_voting_clients(hwmgr);
2605         PP_ASSERT_WITH_CODE((0 == tmp_result),
2606                         "Failed to program voting clients!", result = tmp_result);
2607
2608         tmp_result = polaris10_process_firmware_header(hwmgr);
2609         PP_ASSERT_WITH_CODE((0 == tmp_result),
2610                         "Failed to process firmware header!", result = tmp_result);
2611
2612         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2613         PP_ASSERT_WITH_CODE((0 == tmp_result),
2614                         "Failed to initialize switch from ArbF0 to F1!",
2615                         result = tmp_result);
2616
2617         tmp_result = polaris10_init_smc_table(hwmgr);
2618         PP_ASSERT_WITH_CODE((0 == tmp_result),
2619                         "Failed to initialize SMC table!", result = tmp_result);
2620
2621         tmp_result = polaris10_init_arb_table_index(hwmgr);
2622         PP_ASSERT_WITH_CODE((0 == tmp_result),
2623                         "Failed to initialize ARB table index!", result = tmp_result);
2624
2625         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2626         PP_ASSERT_WITH_CODE((0 == tmp_result),
2627                         "Failed to populate PM fuses!", result = tmp_result);
2628
2629         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2630         PP_ASSERT_WITH_CODE((0 == tmp_result),
2631                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2632
2633         tmp_result = polaris10_enable_sclk_control(hwmgr);
2634         PP_ASSERT_WITH_CODE((0 == tmp_result),
2635                         "Failed to enable SCLK control!", result = tmp_result);
2636
2637         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2638         PP_ASSERT_WITH_CODE((0 == tmp_result),
2639                         "Failed to enable voltage control!", result = tmp_result);
2640
2641         tmp_result = polaris10_enable_ulv(hwmgr);
2642         PP_ASSERT_WITH_CODE((0 == tmp_result),
2643                         "Failed to enable ULV!", result = tmp_result);
2644
2645         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2646         PP_ASSERT_WITH_CODE((0 == tmp_result),
2647                         "Failed to enable deep sleep master switch!", result = tmp_result);
2648
2649         tmp_result = polaris10_start_dpm(hwmgr);
2650         PP_ASSERT_WITH_CODE((0 == tmp_result),
2651                         "Failed to start DPM!", result = tmp_result);
2652
2653         tmp_result = polaris10_enable_smc_cac(hwmgr);
2654         PP_ASSERT_WITH_CODE((0 == tmp_result),
2655                         "Failed to enable SMC CAC!", result = tmp_result);
2656
2657         tmp_result = polaris10_enable_power_containment(hwmgr);
2658         PP_ASSERT_WITH_CODE((0 == tmp_result),
2659                         "Failed to enable power containment!", result = tmp_result);
2660
2661         tmp_result = polaris10_power_control_set_level(hwmgr);
2662         PP_ASSERT_WITH_CODE((0 == tmp_result),
2663                         "Failed to power control set level!", result = tmp_result);
2664
2665         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2666         PP_ASSERT_WITH_CODE((0 == tmp_result),
2667                         "Failed to enable thermal auto throttle!", result = tmp_result);
2668
2669         tmp_result = polaris10_pcie_performance_request(hwmgr);
2670         PP_ASSERT_WITH_CODE((0 == tmp_result),
2671                         "pcie performance request failed!", result = tmp_result);
2672
2673         return result;
2674 }
2675
2676 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2677 {
2678         int tmp_result, result = 0;
2679
2680         tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2681         PP_ASSERT_WITH_CODE(tmp_result == 0,
2682                         "DPM is not running right now, no need to disable DPM!",
2683                         return 0);
2684
2685         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2686                         PHM_PlatformCaps_ThermalController))
2687                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2688                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2689
2690         tmp_result = polaris10_disable_power_containment(hwmgr);
2691         PP_ASSERT_WITH_CODE((tmp_result == 0),
2692                         "Failed to disable power containment!", result = tmp_result);
2693
2694         tmp_result = polaris10_disable_smc_cac(hwmgr);
2695         PP_ASSERT_WITH_CODE((tmp_result == 0),
2696                         "Failed to disable SMC CAC!", result = tmp_result);
2697
2698         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2699                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2700         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2701                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2702
2703         tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2704         PP_ASSERT_WITH_CODE((tmp_result == 0),
2705                         "Failed to disable thermal auto throttle!", result = tmp_result);
2706
2707         tmp_result = polaris10_stop_dpm(hwmgr);
2708         PP_ASSERT_WITH_CODE((tmp_result == 0),
2709                         "Failed to stop DPM!", result = tmp_result);
2710
2711         tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2712         PP_ASSERT_WITH_CODE((tmp_result == 0),
2713                         "Failed to disable deep sleep master switch!", result = tmp_result);
2714
2715         tmp_result = polaris10_disable_ulv(hwmgr);
2716         PP_ASSERT_WITH_CODE((tmp_result == 0),
2717                         "Failed to disable ULV!", result = tmp_result);
2718
2719         tmp_result = polaris10_clear_voting_clients(hwmgr);
2720         PP_ASSERT_WITH_CODE((tmp_result == 0),
2721                         "Failed to clear voting clients!", result = tmp_result);
2722
2723         tmp_result = polaris10_reset_to_default(hwmgr);
2724         PP_ASSERT_WITH_CODE((tmp_result == 0),
2725                         "Failed to reset to default!", result = tmp_result);
2726
2727         tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2728         PP_ASSERT_WITH_CODE((tmp_result == 0),
2729                         "Failed to force to switch arbf0!", result = tmp_result);
2730
2731         return result;
2732 }
2733
2734 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2735 {
2736
2737         return 0;
2738 }
2739
2740 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2741 {
2742         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2743
2744         if (data->soft_pp_table) {
2745                 kfree(data->soft_pp_table);
2746                 data->soft_pp_table = NULL;
2747         }
2748
2749         return phm_hwmgr_backend_fini(hwmgr);
2750 }
2751
2752 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2753 {
2754         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2755
2756         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2757                         PHM_PlatformCaps_SclkDeepSleep);
2758
2759         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2760                 PHM_PlatformCaps_DynamicPatchPowerState);
2761
2762         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2763                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2764                                 PHM_PlatformCaps_EnableMVDDControl);
2765
2766         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2767                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2768                                 PHM_PlatformCaps_ControlVDDCI);
2769
2770         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2771                          PHM_PlatformCaps_TablelessHardwareInterface);
2772
2773         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2774                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2775
2776         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2777                         PHM_PlatformCaps_DynamicPowerManagement);
2778
2779         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2780                         PHM_PlatformCaps_UnTabledHardwareInterface);
2781
2782         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2783                         PHM_PlatformCaps_TablelessHardwareInterface);
2784
2785         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2786                                         PHM_PlatformCaps_SMC);
2787
2788         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2789                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2790
2791         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2792                                         PHM_PlatformCaps_DynamicUVDState);
2793
2794         /* power tune caps Assume disabled */
2795         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2796                                                 PHM_PlatformCaps_SQRamping);
2797         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2798                                                 PHM_PlatformCaps_DBRamping);
2799         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2800                                                 PHM_PlatformCaps_TDRamping);
2801         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2802                                                 PHM_PlatformCaps_TCPRamping);
2803
2804         if (hwmgr->powercontainment_enabled)
2805                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2806                             PHM_PlatformCaps_PowerContainment);
2807         else
2808                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2809                             PHM_PlatformCaps_PowerContainment);
2810
2811         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2812                                                         PHM_PlatformCaps_CAC);
2813
2814         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2815                                                 PHM_PlatformCaps_RegulatorHot);
2816
2817         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2818                                                 PHM_PlatformCaps_AutomaticDCTransition);
2819
2820         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2821                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2822
2823         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2824                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2825
2826         if (hwmgr->chip_id == CHIP_POLARIS11)
2827                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2828                                         PHM_PlatformCaps_SPLLShutdownSupport);
2829         return 0;
2830 }
2831
2832 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2833 {
2834         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2835
2836         polaris10_initialize_power_tune_defaults(hwmgr);
2837
2838         data->pcie_gen_performance.max = PP_PCIEGen1;
2839         data->pcie_gen_performance.min = PP_PCIEGen3;
2840         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2841         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2842         data->pcie_lane_performance.max = 0;
2843         data->pcie_lane_performance.min = 16;
2844         data->pcie_lane_power_saving.max = 0;
2845         data->pcie_lane_power_saving.min = 16;
2846 }
2847
2848 /**
2849 * Get Leakage VDDC based on leakage ID.
2850 *
2851 * @param    hwmgr  the address of the powerplay hardware manager.
2852 * @return   always 0
2853 */
2854 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2855 {
2856         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2857         uint16_t vv_id;
2858         uint16_t vddc = 0;
2859         uint16_t i, j;
2860         uint32_t sclk = 0;
2861         struct phm_ppt_v1_information *table_info =
2862                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2863         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2864                         table_info->vdd_dep_on_sclk;
2865         int result;
2866
2867         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2868                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2869                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2870                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2871                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2872                                         PHM_PlatformCaps_ClockStretcher)) {
2873                                 for (j = 1; j < sclk_table->count; j++) {
2874                                         if (sclk_table->entries[j].clk == sclk &&
2875                                                         sclk_table->entries[j].cks_enable == 0) {
2876                                                 sclk += 5000;
2877                                                 break;
2878                                         }
2879                                 }
2880                         }
2881
2882
2883                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2884                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2885                                                 "Error retrieving EVV voltage value!",
2886                                                 continue);
2887
2888
2889                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2890                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2891                                         "Invalid VDDC value", result = -EINVAL;);
2892
2893                         /* the voltage should not be zero nor equal to leakage ID */
2894                         if (vddc != 0 && vddc != vv_id) {
2895                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2896                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2897                                 data->vddc_leakage.count++;
2898                         }
2899                 }
2900         }
2901
2902         return 0;
2903 }
2904
2905 /**
2906  * Change virtual leakage voltage to actual value.
2907  *
2908  * @param     hwmgr  the address of the powerplay hardware manager.
2909  * @param     pointer to changing voltage
2910  * @param     pointer to leakage table
2911  */
2912 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2913                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2914 {
2915         uint32_t index;
2916
2917         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2918         for (index = 0; index < leakage_table->count; index++) {
2919                 /* if this voltage matches a leakage voltage ID */
2920                 /* patch with actual leakage voltage */
2921                 if (leakage_table->leakage_id[index] == *voltage) {
2922                         *voltage = leakage_table->actual_voltage[index];
2923                         break;
2924                 }
2925         }
2926
2927         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2928                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2929 }
2930
2931 /**
2932 * Patch voltage lookup table by EVV leakages.
2933 *
2934 * @param     hwmgr  the address of the powerplay hardware manager.
2935 * @param     pointer to voltage lookup table
2936 * @param     pointer to leakage table
2937 * @return     always 0
2938 */
2939 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2940                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2941                 struct polaris10_leakage_voltage *leakage_table)
2942 {
2943         uint32_t i;
2944
2945         for (i = 0; i < lookup_table->count; i++)
2946                 polaris10_patch_with_vdd_leakage(hwmgr,
2947                                 &lookup_table->entries[i].us_vdd, leakage_table);
2948
2949         return 0;
2950 }
2951
2952 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2953                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2954                 uint16_t *vddc)
2955 {
2956         struct phm_ppt_v1_information *table_info =
2957                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2958         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2959         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2960                         table_info->max_clock_voltage_on_dc.vddc;
2961         return 0;
2962 }
2963
2964 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2965                 struct pp_hwmgr *hwmgr)
2966 {
2967         uint8_t entryId;
2968         uint8_t voltageId;
2969         struct phm_ppt_v1_information *table_info =
2970                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2971
2972         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2973                         table_info->vdd_dep_on_sclk;
2974         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2975                         table_info->vdd_dep_on_mclk;
2976         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2977                         table_info->mm_dep_table;
2978
2979         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2980                 voltageId = sclk_table->entries[entryId].vddInd;
2981                 sclk_table->entries[entryId].vddc =
2982                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2983         }
2984
2985         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2986                 voltageId = mclk_table->entries[entryId].vddInd;
2987                 mclk_table->entries[entryId].vddc =
2988                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2989         }
2990
2991         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2992                 voltageId = mm_table->entries[entryId].vddcInd;
2993                 mm_table->entries[entryId].vddc =
2994                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2995         }
2996
2997         return 0;
2998
2999 }
3000
3001 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3002 {
3003         /* Need to determine if we need calculated voltage. */
3004         return 0;
3005 }
3006
3007 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3008 {
3009         /* Need to determine if we need calculated voltage from mm table. */
3010         return 0;
3011 }
3012
3013 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3014                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3015 {
3016         uint32_t table_size, i, j;
3017         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3018         table_size = lookup_table->count;
3019
3020         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3021                 "Lookup table is empty", return -EINVAL);
3022
3023         /* Sorting voltages */
3024         for (i = 0; i < table_size - 1; i++) {
3025                 for (j = i + 1; j > 0; j--) {
3026                         if (lookup_table->entries[j].us_vdd <
3027                                         lookup_table->entries[j - 1].us_vdd) {
3028                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3029                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
3030                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
3031                         }
3032                 }
3033         }
3034
3035         return 0;
3036 }
3037
3038 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3039 {
3040         int result = 0;
3041         int tmp_result;
3042         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3043         struct phm_ppt_v1_information *table_info =
3044                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3045
3046         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3047                         table_info->vddc_lookup_table, &(data->vddc_leakage));
3048         if (tmp_result)
3049                 result = tmp_result;
3050
3051         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3052                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3053         if (tmp_result)
3054                 result = tmp_result;
3055
3056         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3057         if (tmp_result)
3058                 result = tmp_result;
3059
3060         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3061         if (tmp_result)
3062                 result = tmp_result;
3063
3064         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3065         if (tmp_result)
3066                 result = tmp_result;
3067
3068         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3069         if (tmp_result)
3070                 result = tmp_result;
3071
3072         return result;
3073 }
3074
3075 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3076 {
3077         struct phm_ppt_v1_information *table_info =
3078                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3079
3080         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3081                                                 table_info->vdd_dep_on_sclk;
3082         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3083                                                 table_info->vdd_dep_on_mclk;
3084
3085         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3086                 "VDD dependency on SCLK table is missing.       \
3087                 This table is mandatory", return -EINVAL);
3088         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3089                 "VDD dependency on SCLK table has to have is missing.   \
3090                 This table is mandatory", return -EINVAL);
3091
3092         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3093                 "VDD dependency on MCLK table is missing.       \
3094                 This table is mandatory", return -EINVAL);
3095         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3096                 "VDD dependency on MCLK table has to have is missing.    \
3097                 This table is mandatory", return -EINVAL);
3098
3099         table_info->max_clock_voltage_on_ac.sclk =
3100                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3101         table_info->max_clock_voltage_on_ac.mclk =
3102                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3103         table_info->max_clock_voltage_on_ac.vddc =
3104                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3105         table_info->max_clock_voltage_on_ac.vddci =
3106                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3107
3108         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3109         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3110         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3111         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3112
3113         return 0;
3114 }
3115
3116 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3117 {
3118         struct polaris10_hwmgr *data;
3119         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3120         uint32_t temp_reg;
3121         int result;
3122         struct phm_ppt_v1_information *table_info =
3123                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3124
3125         data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3126         if (data == NULL)
3127                 return -ENOMEM;
3128
3129         hwmgr->backend = data;
3130
3131         data->dll_default_on = false;
3132         data->sram_end = SMC_RAM_END;
3133         data->mclk_dpm0_activity_target = 0xa;
3134         data->disable_dpm_mask = 0xFF;
3135         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3136         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3137         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3138         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3139         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3140         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3141         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3142         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3143         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3144         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3145
3146         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3147         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3148         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3149         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3150         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3151         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3152         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3153         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3154
3155         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3156
3157         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3158
3159         /* need to set voltage control types before EVV patching */
3160         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3161         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3162         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3163
3164         data->enable_tdc_limit_feature = true;
3165         data->enable_pkg_pwr_tracking_feature = true;
3166         data->force_pcie_gen = PP_PCIEGenInvalid;
3167         data->mclk_stutter_mode_threshold = 40000;
3168
3169         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3170                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3171                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3172
3173         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3174                         PHM_PlatformCaps_EnableMVDDControl)) {
3175                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3176                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3177                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3178                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3179                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3180                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3181         }
3182
3183         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3184                         PHM_PlatformCaps_ControlVDDCI)) {
3185                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3186                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3187                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3188                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3189                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3190                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3191         }
3192
3193         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3194                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3195                                         PHM_PlatformCaps_ClockStretcher);
3196
3197         polaris10_set_features_platform_caps(hwmgr);
3198
3199         polaris10_init_dpm_defaults(hwmgr);
3200
3201         /* Get leakage voltage based on leakage ID. */
3202         result = polaris10_get_evv_voltages(hwmgr);
3203
3204         if (result) {
3205                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3206                 return -1;
3207         }
3208
3209         polaris10_complete_dependency_tables(hwmgr);
3210         polaris10_set_private_data_based_on_pptable(hwmgr);
3211
3212         /* Initalize Dynamic State Adjustment Rule Settings */
3213         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3214
3215         if (0 == result) {
3216                 struct cgs_system_info sys_info = {0};
3217
3218                 data->is_tlu_enabled = 0;
3219
3220                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3221                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3222                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3223                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3224
3225
3226                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3227                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3228                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3229                         case 0:
3230                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3231                                 break;
3232                         case 1:
3233                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3234                                 break;
3235                         case 2:
3236                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3237                                 break;
3238                         case 3:
3239                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3240                                 break;
3241                         case 4:
3242                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3243                                 break;
3244                         default:
3245                                 PP_ASSERT_WITH_CODE(0,
3246                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3247                                 );
3248                                 break;
3249                         }
3250                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3251                 }
3252
3253                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3254                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3255                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3256                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3257
3258                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3259                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3260
3261                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3262
3263                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3264
3265                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3266                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3267
3268                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3269
3270                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3271                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3272
3273                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3274                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3275                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3276
3277                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3278                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3279
3280                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3281                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3282
3283                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3284                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3285
3286                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3287                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3288
3289                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3290                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3291
3292                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3293                                        table_info->cac_dtp_table->usOperatingTempStep;
3294
3295                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3296                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3297                 }
3298
3299                 sys_info.size = sizeof(struct cgs_system_info);
3300                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3301                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3302                 if (result)
3303                         data->pcie_gen_cap = 0x30007;
3304                 else
3305                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3306                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3307                         data->pcie_spc_cap = 20;
3308                 sys_info.size = sizeof(struct cgs_system_info);
3309                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3310                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3311                 if (result)
3312                         data->pcie_lane_cap = 0x2f0000;
3313                 else
3314                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3315
3316                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3317 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3318                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3319                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3320         } else {
3321                 /* Ignore return value in here, we are cleaning up a mess. */
3322                 polaris10_hwmgr_backend_fini(hwmgr);
3323         }
3324
3325         return 0;
3326 }
3327
3328 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3329 {
3330         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3331         uint32_t level, tmp;
3332
3333         if (!data->pcie_dpm_key_disabled) {
3334                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3335                         level = 0;
3336                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3337                         while (tmp >>= 1)
3338                                 level++;
3339
3340                         if (level)
3341                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3342                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3343                 }
3344         }
3345
3346         if (!data->sclk_dpm_key_disabled) {
3347                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3348                         level = 0;
3349                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3350                         while (tmp >>= 1)
3351                                 level++;
3352
3353                         if (level)
3354                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3355                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3356                                                 (1 << level));
3357                 }
3358         }
3359
3360         if (!data->mclk_dpm_key_disabled) {
3361                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3362                         level = 0;
3363                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3364                         while (tmp >>= 1)
3365                                 level++;
3366
3367                         if (level)
3368                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3369                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3370                                                 (1 << level));
3371                 }
3372         }
3373
3374         return 0;
3375 }
3376
3377 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3378 {
3379         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3380
3381         phm_apply_dal_min_voltage_request(hwmgr);
3382
3383         if (!data->sclk_dpm_key_disabled) {
3384                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3385                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3386                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3387                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3388         }
3389
3390         if (!data->mclk_dpm_key_disabled) {
3391                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3392                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3393                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3394                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3395         }
3396
3397         return 0;
3398 }
3399
3400 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3401 {
3402         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3403
3404         if (!polaris10_is_dpm_running(hwmgr))
3405                 return -EINVAL;
3406
3407         if (!data->pcie_dpm_key_disabled) {
3408                 smum_send_msg_to_smc(hwmgr->smumgr,
3409                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3410         }
3411
3412         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3413 }
3414
3415 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3416 {
3417         struct polaris10_hwmgr *data =
3418                         (struct polaris10_hwmgr *)(hwmgr->backend);
3419         uint32_t level;
3420
3421         if (!data->sclk_dpm_key_disabled)
3422                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3423                         level = phm_get_lowest_enabled_level(hwmgr,
3424                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3425                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3426                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3427                                                             (1 << level));
3428
3429         }
3430
3431         if (!data->mclk_dpm_key_disabled) {
3432                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3433                         level = phm_get_lowest_enabled_level(hwmgr,
3434                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3435                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3436                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3437                                                             (1 << level));
3438                 }
3439         }
3440
3441         if (!data->pcie_dpm_key_disabled) {
3442                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3443                         level = phm_get_lowest_enabled_level(hwmgr,
3444                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3445                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3446                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3447                                                             (level));
3448                 }
3449         }
3450
3451         return 0;
3452
3453 }
3454 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3455                                 enum amd_dpm_forced_level level)
3456 {
3457         int ret = 0;
3458
3459         switch (level) {
3460         case AMD_DPM_FORCED_LEVEL_HIGH:
3461                 ret = polaris10_force_dpm_highest(hwmgr);
3462                 if (ret)
3463                         return ret;
3464                 break;
3465         case AMD_DPM_FORCED_LEVEL_LOW:
3466                 ret = polaris10_force_dpm_lowest(hwmgr);
3467                 if (ret)
3468                         return ret;
3469                 break;
3470         case AMD_DPM_FORCED_LEVEL_AUTO:
3471                 ret = polaris10_unforce_dpm_levels(hwmgr);
3472                 if (ret)
3473                         return ret;
3474                 break;
3475         default:
3476                 break;
3477         }
3478
3479         hwmgr->dpm_level = level;
3480
3481         return ret;
3482 }
3483
3484 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3485 {
3486         return sizeof(struct polaris10_power_state);
3487 }
3488
3489
3490 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3491                                 struct pp_power_state *request_ps,
3492                         const struct pp_power_state *current_ps)
3493 {
3494
3495         struct polaris10_power_state *polaris10_ps =
3496                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3497         uint32_t sclk;
3498         uint32_t mclk;
3499         struct PP_Clocks minimum_clocks = {0};
3500         bool disable_mclk_switching;
3501         bool disable_mclk_switching_for_frame_lock;
3502         struct cgs_display_info info = {0};
3503         const struct phm_clock_and_voltage_limits *max_limits;
3504         uint32_t i;
3505         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3506         struct phm_ppt_v1_information *table_info =
3507                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3508         int32_t count;
3509         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3510
3511         data->battery_state = (PP_StateUILabel_Battery ==
3512                         request_ps->classification.ui_label);
3513
3514         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3515                                  "VI should always have 2 performance levels",
3516                                 );
3517
3518         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3519                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3520                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3521
3522         /* Cap clock DPM tables at DC MAX if it is in DC. */
3523         if (PP_PowerSource_DC == hwmgr->power_source) {
3524                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3525                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3526                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3527                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3528                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3529                 }
3530         }
3531
3532         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3533         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3534
3535         cgs_get_active_displays_info(hwmgr->device, &info);
3536
3537         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3538
3539         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3540
3541         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3542                         PHM_PlatformCaps_StablePState)) {
3543                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3544                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3545
3546                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3547                                 count >= 0; count--) {
3548                         if (stable_pstate_sclk >=
3549                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3550                                 stable_pstate_sclk =
3551                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3552                                 break;
3553                         }
3554                 }
3555
3556                 if (count < 0)
3557                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3558
3559                 stable_pstate_mclk = max_limits->mclk;
3560
3561                 minimum_clocks.engineClock = stable_pstate_sclk;
3562                 minimum_clocks.memoryClock = stable_pstate_mclk;
3563         }
3564
3565         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3566                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3567
3568         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3569                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3570
3571         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3572
3573         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3574                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3575                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3576                                 "Overdrive sclk exceeds limit",
3577                                 hwmgr->gfx_arbiter.sclk_over_drive =
3578                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3579
3580                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3581                         polaris10_ps->performance_levels[1].engine_clock =
3582                                         hwmgr->gfx_arbiter.sclk_over_drive;
3583         }
3584
3585         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3586                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3587                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3588                                 "Overdrive mclk exceeds limit",
3589                                 hwmgr->gfx_arbiter.mclk_over_drive =
3590                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3591
3592                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3593                         polaris10_ps->performance_levels[1].memory_clock =
3594                                         hwmgr->gfx_arbiter.mclk_over_drive;
3595         }
3596
3597         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3598                                     hwmgr->platform_descriptor.platformCaps,
3599                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3600
3601         disable_mclk_switching = (1 < info.display_count) ||
3602                                     disable_mclk_switching_for_frame_lock;
3603
3604         sclk = polaris10_ps->performance_levels[0].engine_clock;
3605         mclk = polaris10_ps->performance_levels[0].memory_clock;
3606
3607         if (disable_mclk_switching)
3608                 mclk = polaris10_ps->performance_levels
3609                 [polaris10_ps->performance_level_count - 1].memory_clock;
3610
3611         if (sclk < minimum_clocks.engineClock)
3612                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3613                                 max_limits->sclk : minimum_clocks.engineClock;
3614
3615         if (mclk < minimum_clocks.memoryClock)
3616                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3617                                 max_limits->mclk : minimum_clocks.memoryClock;
3618
3619         polaris10_ps->performance_levels[0].engine_clock = sclk;
3620         polaris10_ps->performance_levels[0].memory_clock = mclk;
3621
3622         polaris10_ps->performance_levels[1].engine_clock =
3623                 (polaris10_ps->performance_levels[1].engine_clock >=
3624                                 polaris10_ps->performance_levels[0].engine_clock) ?
3625                                                 polaris10_ps->performance_levels[1].engine_clock :
3626                                                 polaris10_ps->performance_levels[0].engine_clock;
3627
3628         if (disable_mclk_switching) {
3629                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3630                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3631
3632                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3633                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3634         } else {
3635                 if (polaris10_ps->performance_levels[1].memory_clock <
3636                                 polaris10_ps->performance_levels[0].memory_clock)
3637                         polaris10_ps->performance_levels[1].memory_clock =
3638                                         polaris10_ps->performance_levels[0].memory_clock;
3639         }
3640
3641         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3642                         PHM_PlatformCaps_StablePState)) {
3643                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3644                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3645                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3646                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3647                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3648                 }
3649         }
3650         return 0;
3651 }
3652
3653
3654 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3655 {
3656         struct pp_power_state  *ps;
3657         struct polaris10_power_state  *polaris10_ps;
3658
3659         if (hwmgr == NULL)
3660                 return -EINVAL;
3661
3662         ps = hwmgr->request_ps;
3663
3664         if (ps == NULL)
3665                 return -EINVAL;
3666
3667         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3668
3669         if (low)
3670                 return polaris10_ps->performance_levels[0].memory_clock;
3671         else
3672                 return polaris10_ps->performance_levels
3673                                 [polaris10_ps->performance_level_count-1].memory_clock;
3674 }
3675
3676 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3677 {
3678         struct pp_power_state  *ps;
3679         struct polaris10_power_state  *polaris10_ps;
3680
3681         if (hwmgr == NULL)
3682                 return -EINVAL;
3683
3684         ps = hwmgr->request_ps;
3685
3686         if (ps == NULL)
3687                 return -EINVAL;
3688
3689         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3690
3691         if (low)
3692                 return polaris10_ps->performance_levels[0].engine_clock;
3693         else
3694                 return polaris10_ps->performance_levels
3695                                 [polaris10_ps->performance_level_count-1].engine_clock;
3696 }
3697
3698 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3699                                         struct pp_hw_power_state *hw_ps)
3700 {
3701         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3702         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3703         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3704         uint16_t size;
3705         uint8_t frev, crev;
3706         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3707
3708         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3709          * We assume here that fw_info is unchanged if this call fails.
3710          */
3711         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3712                         hwmgr->device, index,
3713                         &size, &frev, &crev);
3714         if (!fw_info)
3715                 /* During a test, there is no firmware info table. */
3716                 return 0;
3717
3718         /* Patch the state. */
3719         data->vbios_boot_state.sclk_bootup_value =
3720                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3721         data->vbios_boot_state.mclk_bootup_value =
3722                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3723         data->vbios_boot_state.mvdd_bootup_value =
3724                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3725         data->vbios_boot_state.vddc_bootup_value =
3726                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3727         data->vbios_boot_state.vddci_bootup_value =
3728                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3729         data->vbios_boot_state.pcie_gen_bootup_value =
3730                         phm_get_current_pcie_speed(hwmgr);
3731
3732         data->vbios_boot_state.pcie_lane_bootup_value =
3733                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3734
3735         /* set boot power state */
3736         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3737         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3738         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3739         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3740
3741         return 0;
3742 }
3743
3744 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3745                 void *state, struct pp_power_state *power_state,
3746                 void *pp_table, uint32_t classification_flag)
3747 {
3748         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3749         struct polaris10_power_state  *polaris10_power_state =
3750                         (struct polaris10_power_state *)(&(power_state->hardware));
3751         struct polaris10_performance_level *performance_level;
3752         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3753         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3754                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3755         PPTable_Generic_SubTable_Header *sclk_dep_table =
3756                         (PPTable_Generic_SubTable_Header *)
3757                         (((unsigned long)powerplay_table) +
3758                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3759
3760         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3761                         (ATOM_Tonga_MCLK_Dependency_Table *)
3762                         (((unsigned long)powerplay_table) +
3763                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3764
3765         /* The following fields are not initialized here: id orderedList allStatesList */
3766         power_state->classification.ui_label =
3767                         (le16_to_cpu(state_entry->usClassification) &
3768                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3769                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3770         power_state->classification.flags = classification_flag;
3771         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3772
3773         power_state->classification.temporary_state = false;
3774         power_state->classification.to_be_deleted = false;
3775
3776         power_state->validation.disallowOnDC =
3777                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3778                                         ATOM_Tonga_DISALLOW_ON_DC));
3779
3780         power_state->pcie.lanes = 0;
3781
3782         power_state->display.disableFrameModulation = false;
3783         power_state->display.limitRefreshrate = false;
3784         power_state->display.enableVariBright =
3785                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3786                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3787
3788         power_state->validation.supportedPowerLevels = 0;
3789         power_state->uvd_clocks.VCLK = 0;
3790         power_state->uvd_clocks.DCLK = 0;
3791         power_state->temperatures.min = 0;
3792         power_state->temperatures.max = 0;
3793
3794         performance_level = &(polaris10_power_state->performance_levels
3795                         [polaris10_power_state->performance_level_count++]);
3796
3797         PP_ASSERT_WITH_CODE(
3798                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3799                         "Performance levels exceeds SMC limit!",
3800                         return -1);
3801
3802         PP_ASSERT_WITH_CODE(
3803                         (polaris10_power_state->performance_level_count <=
3804                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3805                         "Performance levels exceeds Driver limit!",
3806                         return -1);
3807
3808         /* Performance levels are arranged from low to high. */
3809         performance_level->memory_clock = mclk_dep_table->entries
3810                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3811         if (sclk_dep_table->ucRevId == 0)
3812                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3813                         [state_entry->ucEngineClockIndexLow].ulSclk;
3814         else if (sclk_dep_table->ucRevId == 1)
3815                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3816                         [state_entry->ucEngineClockIndexLow].ulSclk;
3817         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3818                         state_entry->ucPCIEGenLow);
3819         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3820                         state_entry->ucPCIELaneHigh);
3821
3822         performance_level = &(polaris10_power_state->performance_levels
3823                         [polaris10_power_state->performance_level_count++]);
3824         performance_level->memory_clock = mclk_dep_table->entries
3825                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3826
3827         if (sclk_dep_table->ucRevId == 0)
3828                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3829                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3830         else if (sclk_dep_table->ucRevId == 1)
3831                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3832                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3833
3834         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3835                         state_entry->ucPCIEGenHigh);
3836         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3837                         state_entry->ucPCIELaneHigh);
3838
3839         return 0;
3840 }
3841
3842 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3843                 unsigned long entry_index, struct pp_power_state *state)
3844 {
3845         int result;
3846         struct polaris10_power_state *ps;
3847         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3848         struct phm_ppt_v1_information *table_info =
3849                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3850         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3851                         table_info->vdd_dep_on_mclk;
3852
3853         state->hardware.magic = PHM_VIslands_Magic;
3854
3855         ps = (struct polaris10_power_state *)(&state->hardware);
3856
3857         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3858                         polaris10_get_pp_table_entry_callback_func);
3859
3860         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3861          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3862          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3863          */
3864         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3865                 if (dep_mclk_table->entries[0].clk !=
3866                                 data->vbios_boot_state.mclk_bootup_value)
3867                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3868                                         "does not match VBIOS boot MCLK level");
3869                 if (dep_mclk_table->entries[0].vddci !=
3870                                 data->vbios_boot_state.vddci_bootup_value)
3871                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3872                                         "does not match VBIOS boot VDDCI level");
3873         }
3874
3875         /* set DC compatible flag if this state supports DC */
3876         if (!state->validation.disallowOnDC)
3877                 ps->dc_compatible = true;
3878
3879         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3880                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3881
3882         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3883         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3884
3885         if (!result) {
3886                 uint32_t i;
3887
3888                 switch (state->classification.ui_label) {
3889                 case PP_StateUILabel_Performance:
3890                         data->use_pcie_performance_levels = true;
3891                         for (i = 0; i < ps->performance_level_count; i++) {
3892                                 if (data->pcie_gen_performance.max <
3893                                                 ps->performance_levels[i].pcie_gen)
3894                                         data->pcie_gen_performance.max =
3895                                                         ps->performance_levels[i].pcie_gen;
3896
3897                                 if (data->pcie_gen_performance.min >
3898                                                 ps->performance_levels[i].pcie_gen)
3899                                         data->pcie_gen_performance.min =
3900                                                         ps->performance_levels[i].pcie_gen;
3901
3902                                 if (data->pcie_lane_performance.max <
3903                                                 ps->performance_levels[i].pcie_lane)
3904                                         data->pcie_lane_performance.max =
3905                                                         ps->performance_levels[i].pcie_lane;
3906                                 if (data->pcie_lane_performance.min >
3907                                                 ps->performance_levels[i].pcie_lane)
3908                                         data->pcie_lane_performance.min =
3909                                                         ps->performance_levels[i].pcie_lane;
3910                         }
3911                         break;
3912                 case PP_StateUILabel_Battery:
3913                         data->use_pcie_power_saving_levels = true;
3914
3915                         for (i = 0; i < ps->performance_level_count; i++) {
3916                                 if (data->pcie_gen_power_saving.max <
3917                                                 ps->performance_levels[i].pcie_gen)
3918                                         data->pcie_gen_power_saving.max =
3919                                                         ps->performance_levels[i].pcie_gen;
3920
3921                                 if (data->pcie_gen_power_saving.min >
3922                                                 ps->performance_levels[i].pcie_gen)
3923                                         data->pcie_gen_power_saving.min =
3924                                                         ps->performance_levels[i].pcie_gen;
3925
3926                                 if (data->pcie_lane_power_saving.max <
3927                                                 ps->performance_levels[i].pcie_lane)
3928                                         data->pcie_lane_power_saving.max =
3929                                                         ps->performance_levels[i].pcie_lane;
3930
3931                                 if (data->pcie_lane_power_saving.min >
3932                                                 ps->performance_levels[i].pcie_lane)
3933                                         data->pcie_lane_power_saving.min =
3934                                                         ps->performance_levels[i].pcie_lane;
3935                         }
3936                         break;
3937                 default:
3938                         break;
3939                 }
3940         }
3941         return 0;
3942 }
3943
3944 static void
3945 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3946 {
3947         uint32_t sclk, mclk, activity_percent;
3948         uint32_t offset;
3949         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3950
3951         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3952
3953         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3954
3955         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3956
3957         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3958         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3959                         mclk / 100, sclk / 100);
3960
3961         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3962         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3963         activity_percent += 0x80;
3964         activity_percent >>= 8;
3965
3966         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3967
3968         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3969
3970         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3971 }
3972
3973 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3974 {
3975         const struct phm_set_power_state_input *states =
3976                         (const struct phm_set_power_state_input *)input;
3977         const struct polaris10_power_state *polaris10_ps =
3978                         cast_const_phw_polaris10_power_state(states->pnew_state);
3979         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3980         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3981         uint32_t sclk = polaris10_ps->performance_levels
3982                         [polaris10_ps->performance_level_count - 1].engine_clock;
3983         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3984         uint32_t mclk = polaris10_ps->performance_levels
3985                         [polaris10_ps->performance_level_count - 1].memory_clock;
3986         struct PP_Clocks min_clocks = {0};
3987         uint32_t i;
3988         struct cgs_display_info info = {0};
3989
3990         data->need_update_smu7_dpm_table = 0;
3991
3992         for (i = 0; i < sclk_table->count; i++) {
3993                 if (sclk == sclk_table->dpm_levels[i].value)
3994                         break;
3995         }
3996
3997         if (i >= sclk_table->count)
3998                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3999         else {
4000         /* TODO: Check SCLK in DAL's minimum clocks
4001          * in case DeepSleep divider update is required.
4002          */
4003                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4004                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4005                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4006                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4007         }
4008
4009         for (i = 0; i < mclk_table->count; i++) {
4010                 if (mclk == mclk_table->dpm_levels[i].value)
4011                         break;
4012         }
4013
4014         if (i >= mclk_table->count)
4015                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4016
4017         cgs_get_active_displays_info(hwmgr->device, &info);
4018
4019         if (data->display_timing.num_existing_displays != info.display_count)
4020                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4021
4022         return 0;
4023 }
4024
4025 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4026                 const struct polaris10_power_state *polaris10_ps)
4027 {
4028         uint32_t i;
4029         uint32_t sclk, max_sclk = 0;
4030         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4031         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4032
4033         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4034                 sclk = polaris10_ps->performance_levels[i].engine_clock;
4035                 if (max_sclk < sclk)
4036                         max_sclk = sclk;
4037         }
4038
4039         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4040                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4041                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4042                                         dpm_table->pcie_speed_table.dpm_levels
4043                                         [dpm_table->pcie_speed_table.count - 1].value :
4044                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4045         }
4046
4047         return 0;
4048 }
4049
4050 static int polaris10_request_link_speed_change_before_state_change(
4051                 struct pp_hwmgr *hwmgr, const void *input)
4052 {
4053         const struct phm_set_power_state_input *states =
4054                         (const struct phm_set_power_state_input *)input;
4055         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4056         const struct polaris10_power_state *polaris10_nps =
4057                         cast_const_phw_polaris10_power_state(states->pnew_state);
4058         const struct polaris10_power_state *polaris10_cps =
4059                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4060
4061         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4062         uint16_t current_link_speed;
4063
4064         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4065                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4066         else
4067                 current_link_speed = data->force_pcie_gen;
4068
4069         data->force_pcie_gen = PP_PCIEGenInvalid;
4070         data->pspp_notify_required = false;
4071
4072         if (target_link_speed > current_link_speed) {
4073                 switch (target_link_speed) {
4074                 case PP_PCIEGen3:
4075                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4076                                 break;
4077                         data->force_pcie_gen = PP_PCIEGen2;
4078                         if (current_link_speed == PP_PCIEGen2)
4079                                 break;
4080                 case PP_PCIEGen2:
4081                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4082                                 break;
4083                 default:
4084                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4085                         break;
4086                 }
4087         } else {
4088                 if (target_link_speed < current_link_speed)
4089                         data->pspp_notify_required = true;
4090         }
4091
4092         return 0;
4093 }
4094
4095 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4096 {
4097         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4098
4099         if (0 == data->need_update_smu7_dpm_table)
4100                 return 0;
4101
4102         if ((0 == data->sclk_dpm_key_disabled) &&
4103                 (data->need_update_smu7_dpm_table &
4104                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4105                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4106                                 "Trying to freeze SCLK DPM when DPM is disabled",
4107                                 );
4108                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4109                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4110                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4111                                 return -1);
4112         }
4113
4114         if ((0 == data->mclk_dpm_key_disabled) &&
4115                 (data->need_update_smu7_dpm_table &
4116                  DPMTABLE_OD_UPDATE_MCLK)) {
4117                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4118                                 "Trying to freeze MCLK DPM when DPM is disabled",
4119                                 );
4120                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4121                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4122                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4123                                 return -1);
4124         }
4125
4126         return 0;
4127 }
4128
4129 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4130                 struct pp_hwmgr *hwmgr, const void *input)
4131 {
4132         int result = 0;
4133         const struct phm_set_power_state_input *states =
4134                         (const struct phm_set_power_state_input *)input;
4135         const struct polaris10_power_state *polaris10_ps =
4136                         cast_const_phw_polaris10_power_state(states->pnew_state);
4137         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4138         uint32_t sclk = polaris10_ps->performance_levels
4139                         [polaris10_ps->performance_level_count - 1].engine_clock;
4140         uint32_t mclk = polaris10_ps->performance_levels
4141                         [polaris10_ps->performance_level_count - 1].memory_clock;
4142         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4143
4144         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4145         uint32_t dpm_count, clock_percent;
4146         uint32_t i;
4147
4148         if (0 == data->need_update_smu7_dpm_table)
4149                 return 0;
4150
4151         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4152                 dpm_table->sclk_table.dpm_levels
4153                 [dpm_table->sclk_table.count - 1].value = sclk;
4154
4155                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4156                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4157                 /* Need to do calculation based on the golden DPM table
4158                  * as the Heatmap GPU Clock axis is also based on the default values
4159                  */
4160                         PP_ASSERT_WITH_CODE(
4161                                 (golden_dpm_table->sclk_table.dpm_levels
4162                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4163                                 "Divide by 0!",
4164                                 return -1);
4165                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4166
4167                         for (i = dpm_count; i > 1; i--) {
4168                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4169                                         clock_percent =
4170                                               ((sclk
4171                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4172                                                 ) * 100)
4173                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4174
4175                                         dpm_table->sclk_table.dpm_levels[i].value =
4176                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4177                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4178                                                                 clock_percent)/100;
4179
4180                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4181                                         clock_percent =
4182                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4183                                                 - sclk) * 100)
4184                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4185
4186                                         dpm_table->sclk_table.dpm_levels[i].value =
4187                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4188                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4189                                                                         clock_percent) / 100;
4190                                 } else
4191                                         dpm_table->sclk_table.dpm_levels[i].value =
4192                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4193                         }
4194                 }
4195         }
4196
4197         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4198                 dpm_table->mclk_table.dpm_levels
4199                         [dpm_table->mclk_table.count - 1].value = mclk;
4200
4201                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4202                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4203
4204                         PP_ASSERT_WITH_CODE(
4205                                         (golden_dpm_table->mclk_table.dpm_levels
4206                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4207                                         "Divide by 0!",
4208                                         return -1);
4209                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4210                         for (i = dpm_count; i > 1; i--) {
4211                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4212                                         clock_percent = ((mclk -
4213                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4214                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4215
4216                                         dpm_table->mclk_table.dpm_levels[i].value =
4217                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4218                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4219                                                         clock_percent) / 100;
4220
4221                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4222                                         clock_percent = (
4223                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4224                                         * 100)
4225                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4226
4227                                         dpm_table->mclk_table.dpm_levels[i].value =
4228                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4229                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4230                                                                         clock_percent) / 100;
4231                                 } else
4232                                         dpm_table->mclk_table.dpm_levels[i].value =
4233                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4234                         }
4235                 }
4236         }
4237
4238         if (data->need_update_smu7_dpm_table &
4239                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4240                 result = polaris10_populate_all_graphic_levels(hwmgr);
4241                 PP_ASSERT_WITH_CODE((0 == result),
4242                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4243                                 return result);
4244         }
4245
4246         if (data->need_update_smu7_dpm_table &
4247                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4248                 /*populate MCLK dpm table to SMU7 */
4249                 result = polaris10_populate_all_memory_levels(hwmgr);
4250                 PP_ASSERT_WITH_CODE((0 == result),
4251                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4252                                 return result);
4253         }
4254
4255         return result;
4256 }
4257
4258 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4259                           struct polaris10_single_dpm_table *dpm_table,
4260                         uint32_t low_limit, uint32_t high_limit)
4261 {
4262         uint32_t i;
4263
4264         for (i = 0; i < dpm_table->count; i++) {
4265                 if ((dpm_table->dpm_levels[i].value < low_limit)
4266                 || (dpm_table->dpm_levels[i].value > high_limit))
4267                         dpm_table->dpm_levels[i].enabled = false;
4268                 else
4269                         dpm_table->dpm_levels[i].enabled = true;
4270         }
4271
4272         return 0;
4273 }
4274
4275 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4276                 const struct polaris10_power_state *polaris10_ps)
4277 {
4278         int result = 0;
4279         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4280         uint32_t high_limit_count;
4281
4282         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4283                         "power state did not have any performance level",
4284                         return -1);
4285
4286         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4287
4288         polaris10_trim_single_dpm_states(hwmgr,
4289                         &(data->dpm_table.sclk_table),
4290                         polaris10_ps->performance_levels[0].engine_clock,
4291                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4292
4293         polaris10_trim_single_dpm_states(hwmgr,
4294                         &(data->dpm_table.mclk_table),
4295                         polaris10_ps->performance_levels[0].memory_clock,
4296                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4297
4298         return result;
4299 }
4300
4301 static int polaris10_generate_dpm_level_enable_mask(
4302                 struct pp_hwmgr *hwmgr, const void *input)
4303 {
4304         int result;
4305         const struct phm_set_power_state_input *states =
4306                         (const struct phm_set_power_state_input *)input;
4307         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4308         const struct polaris10_power_state *polaris10_ps =
4309                         cast_const_phw_polaris10_power_state(states->pnew_state);
4310
4311         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4312         if (result)
4313                 return result;
4314
4315         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4316                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4317         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4318                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4319         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4320                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4321
4322         return 0;
4323 }
4324
4325 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4326 {
4327         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4328                         PPSMC_MSG_UVDDPM_Enable :
4329                         PPSMC_MSG_UVDDPM_Disable);
4330 }
4331
4332 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4333 {
4334         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4335                         PPSMC_MSG_VCEDPM_Enable :
4336                         PPSMC_MSG_VCEDPM_Disable);
4337 }
4338
4339 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4340 {
4341         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4342                         PPSMC_MSG_SAMUDPM_Enable :
4343                         PPSMC_MSG_SAMUDPM_Disable);
4344 }
4345
4346 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4347 {
4348         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4349         uint32_t mm_boot_level_offset, mm_boot_level_value;
4350         struct phm_ppt_v1_information *table_info =
4351                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4352
4353         if (!bgate) {
4354                 data->smc_state_table.UvdBootLevel = 0;
4355                 if (table_info->mm_dep_table->count > 0)
4356                         data->smc_state_table.UvdBootLevel =
4357                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4358                 mm_boot_level_offset = data->dpm_table_start +
4359                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4360                 mm_boot_level_offset /= 4;
4361                 mm_boot_level_offset *= 4;
4362                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4363                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4364                 mm_boot_level_value &= 0x00FFFFFF;
4365                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4366                 cgs_write_ind_register(hwmgr->device,
4367                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4368
4369                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4370                                 PHM_PlatformCaps_UVDDPM) ||
4371                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4372                                 PHM_PlatformCaps_StablePState))
4373                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4374                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4375                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4376         }
4377
4378         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4379 }
4380
4381 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4382 {
4383         const struct phm_set_power_state_input *states =
4384                         (const struct phm_set_power_state_input *)input;
4385         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4386         const struct polaris10_power_state *polaris10_nps =
4387                         cast_const_phw_polaris10_power_state(states->pnew_state);
4388         const struct polaris10_power_state *polaris10_cps =
4389                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4390
4391         uint32_t mm_boot_level_offset, mm_boot_level_value;
4392         struct phm_ppt_v1_information *table_info =
4393                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4394
4395         if (polaris10_nps->vce_clks.evclk > 0 &&
4396         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4397
4398                 data->smc_state_table.VceBootLevel =
4399                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4400
4401                 mm_boot_level_offset = data->dpm_table_start +
4402                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4403                 mm_boot_level_offset /= 4;
4404                 mm_boot_level_offset *= 4;
4405                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4406                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4407                 mm_boot_level_value &= 0xFF00FFFF;
4408                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4409                 cgs_write_ind_register(hwmgr->device,
4410                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4411
4412                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4413                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4414                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4415                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4416
4417                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4418                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4419                                 polaris10_cps != NULL &&
4420                                 polaris10_cps->vce_clks.evclk > 0)
4421                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4422         }
4423
4424         return 0;
4425 }
4426
4427 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4428 {
4429         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4430         uint32_t mm_boot_level_offset, mm_boot_level_value;
4431
4432         if (!bgate) {
4433                 data->smc_state_table.SamuBootLevel = 0;
4434                 mm_boot_level_offset = data->dpm_table_start +
4435                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4436                 mm_boot_level_offset /= 4;
4437                 mm_boot_level_offset *= 4;
4438                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4439                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4440                 mm_boot_level_value &= 0xFFFFFF00;
4441                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4442                 cgs_write_ind_register(hwmgr->device,
4443                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4444
4445                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4446                                 PHM_PlatformCaps_StablePState))
4447                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4448                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4449                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4450         }
4451
4452         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4453 }
4454
4455 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4456 {
4457         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4458
4459         int result = 0;
4460         uint32_t low_sclk_interrupt_threshold = 0;
4461
4462         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4463                         PHM_PlatformCaps_SclkThrottleLowNotification)
4464                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4465                                 data->low_sclk_interrupt_threshold)) {
4466                 data->low_sclk_interrupt_threshold =
4467                                 hwmgr->gfx_arbiter.sclk_threshold;
4468                 low_sclk_interrupt_threshold =
4469                                 data->low_sclk_interrupt_threshold;
4470
4471                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4472
4473                 result = polaris10_copy_bytes_to_smc(
4474                                 hwmgr->smumgr,
4475                                 data->dpm_table_start +
4476                                 offsetof(SMU74_Discrete_DpmTable,
4477                                         LowSclkInterruptThreshold),
4478                                 (uint8_t *)&low_sclk_interrupt_threshold,
4479                                 sizeof(uint32_t),
4480                                 data->sram_end);
4481         }
4482
4483         return result;
4484 }
4485
4486 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4487 {
4488         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4489
4490         if (data->need_update_smu7_dpm_table &
4491                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4492                 return polaris10_program_memory_timing_parameters(hwmgr);
4493
4494         return 0;
4495 }
4496
4497 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4498 {
4499         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4500
4501         if (0 == data->need_update_smu7_dpm_table)
4502                 return 0;
4503
4504         if ((0 == data->sclk_dpm_key_disabled) &&
4505                 (data->need_update_smu7_dpm_table &
4506                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4507
4508                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4509                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4510                                 );
4511                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4512                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4513                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4514                         return -1);
4515         }
4516
4517         if ((0 == data->mclk_dpm_key_disabled) &&
4518                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4519
4520                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4521                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4522                                 );
4523                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4524                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4525                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4526                     return -1);
4527         }
4528
4529         data->need_update_smu7_dpm_table = 0;
4530
4531         return 0;
4532 }
4533
4534 static int polaris10_notify_link_speed_change_after_state_change(
4535                 struct pp_hwmgr *hwmgr, const void *input)
4536 {
4537         const struct phm_set_power_state_input *states =
4538                         (const struct phm_set_power_state_input *)input;
4539         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4540         const struct polaris10_power_state *polaris10_ps =
4541                         cast_const_phw_polaris10_power_state(states->pnew_state);
4542         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4543         uint8_t  request;
4544
4545         if (data->pspp_notify_required) {
4546                 if (target_link_speed == PP_PCIEGen3)
4547                         request = PCIE_PERF_REQ_GEN3;
4548                 else if (target_link_speed == PP_PCIEGen2)
4549                         request = PCIE_PERF_REQ_GEN2;
4550                 else
4551                         request = PCIE_PERF_REQ_GEN1;
4552
4553                 if (request == PCIE_PERF_REQ_GEN1 &&
4554                                 phm_get_current_pcie_speed(hwmgr) > 0)
4555                         return 0;
4556
4557                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4558                         if (PP_PCIEGen2 == target_link_speed)
4559                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4560                         else
4561                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4562                 }
4563         }
4564
4565         return 0;
4566 }
4567
4568 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4569 {
4570         int tmp_result, result = 0;
4571         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4572
4573         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4574         PP_ASSERT_WITH_CODE((0 == tmp_result),
4575                         "Failed to find DPM states clocks in DPM table!",
4576                         result = tmp_result);
4577
4578         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4579                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4580                 tmp_result =
4581                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4582                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4583                                 "Failed to request link speed change before state change!",
4584                                 result = tmp_result);
4585         }
4586
4587         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4588         PP_ASSERT_WITH_CODE((0 == tmp_result),
4589                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4590
4591         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4592         PP_ASSERT_WITH_CODE((0 == tmp_result),
4593                         "Failed to populate and upload SCLK MCLK DPM levels!",
4594                         result = tmp_result);
4595
4596         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4597         PP_ASSERT_WITH_CODE((0 == tmp_result),
4598                         "Failed to generate DPM level enabled mask!",
4599                         result = tmp_result);
4600
4601         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4602         PP_ASSERT_WITH_CODE((0 == tmp_result),
4603                         "Failed to update VCE DPM!",
4604                         result = tmp_result);
4605
4606         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4607         PP_ASSERT_WITH_CODE((0 == tmp_result),
4608                         "Failed to update SCLK threshold!",
4609                         result = tmp_result);
4610
4611         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4612         PP_ASSERT_WITH_CODE((0 == tmp_result),
4613                         "Failed to program memory timing parameters!",
4614                         result = tmp_result);
4615
4616         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4617         PP_ASSERT_WITH_CODE((0 == tmp_result),
4618                         "Failed to unfreeze SCLK MCLK DPM!",
4619                         result = tmp_result);
4620
4621         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4622         PP_ASSERT_WITH_CODE((0 == tmp_result),
4623                         "Failed to upload DPM level enabled mask!",
4624                         result = tmp_result);
4625
4626         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4627                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4628                 tmp_result =
4629                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4630                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4631                                 "Failed to notify link speed change after state change!",
4632                                 result = tmp_result);
4633         }
4634         data->apply_optimized_settings = false;
4635         return result;
4636 }
4637
4638 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4639 {
4640         hwmgr->thermal_controller.
4641         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4642
4643         if (phm_is_hw_access_blocked(hwmgr))
4644                 return 0;
4645
4646         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4647                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4648 }
4649
4650 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4651 {
4652         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4653
4654         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4655 }
4656
4657 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4658 {
4659         uint32_t num_active_displays = 0;
4660         struct cgs_display_info info = {0};
4661         info.mode_info = NULL;
4662
4663         cgs_get_active_displays_info(hwmgr->device, &info);
4664
4665         num_active_displays = info.display_count;
4666
4667         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4668                 polaris10_notify_smc_display_change(hwmgr, false);
4669         else
4670                 polaris10_notify_smc_display_change(hwmgr, true);
4671
4672         return 0;
4673 }
4674
4675 /**
4676 * Programs the display gap
4677 *
4678 * @param    hwmgr  the address of the powerplay hardware manager.
4679 * @return   always OK
4680 */
4681 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4682 {
4683         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4684         uint32_t num_active_displays = 0;
4685         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4686         uint32_t display_gap2;
4687         uint32_t pre_vbi_time_in_us;
4688         uint32_t frame_time_in_us;
4689         uint32_t ref_clock;
4690         uint32_t refresh_rate = 0;
4691         struct cgs_display_info info = {0};
4692         struct cgs_mode_info mode_info;
4693
4694         info.mode_info = &mode_info;
4695
4696         cgs_get_active_displays_info(hwmgr->device, &info);
4697         num_active_displays = info.display_count;
4698
4699         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4700         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4701
4702         ref_clock = mode_info.ref_clock;
4703         refresh_rate = mode_info.refresh_rate;
4704
4705         if (0 == refresh_rate)
4706                 refresh_rate = 60;
4707
4708         frame_time_in_us = 1000000 / refresh_rate;
4709
4710         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4711         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4712
4713         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4714
4715         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4716
4717         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4718
4719         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4720
4721         return 0;
4722 }
4723
4724
4725 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4726 {
4727         return polaris10_program_display_gap(hwmgr);
4728 }
4729
4730 /**
4731 *  Set maximum target operating fan output RPM
4732 *
4733 * @param    hwmgr:  the address of the powerplay hardware manager.
4734 * @param    usMaxFanRpm:  max operating fan RPM value.
4735 * @return   The response that came from the SMC.
4736 */
4737 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4738 {
4739         hwmgr->thermal_controller.
4740         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4741
4742         if (phm_is_hw_access_blocked(hwmgr))
4743                 return 0;
4744
4745         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4746                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4747 }
4748
4749 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4750                                         const void *thermal_interrupt_info)
4751 {
4752         return 0;
4753 }
4754
4755 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4756 {
4757         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4758         bool is_update_required = false;
4759         struct cgs_display_info info = {0, 0, NULL};
4760
4761         cgs_get_active_displays_info(hwmgr->device, &info);
4762
4763         if (data->display_timing.num_existing_displays != info.display_count)
4764                 is_update_required = true;
4765 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4766         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4767                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4768                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4769                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4770                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4771                         is_update_required = true;
4772 */
4773         return is_update_required;
4774 }
4775
4776 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4777                                                            const struct polaris10_performance_level *pl2)
4778 {
4779         return ((pl1->memory_clock == pl2->memory_clock) &&
4780                   (pl1->engine_clock == pl2->engine_clock) &&
4781                   (pl1->pcie_gen == pl2->pcie_gen) &&
4782                   (pl1->pcie_lane == pl2->pcie_lane));
4783 }
4784
4785 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4786 {
4787         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4788         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4789         int i;
4790
4791         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4792                 return -EINVAL;
4793
4794         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4795         if (psa->performance_level_count != psb->performance_level_count) {
4796                 *equal = false;
4797                 return 0;
4798         }
4799
4800         for (i = 0; i < psa->performance_level_count; i++) {
4801                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4802                         /* If we have found even one performance level pair that is different the states are different. */
4803                         *equal = false;
4804                         return 0;
4805                 }
4806         }
4807
4808         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4809         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4810         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4811         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4812
4813         return 0;
4814 }
4815
4816 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4817 {
4818         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4819
4820         uint32_t vbios_version;
4821
4822         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4823
4824         phm_get_mc_microcode_version(hwmgr);
4825         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4826         /*  Full version of MC ucode has already been loaded. */
4827         if (vbios_version == 0) {
4828                 data->need_long_memory_training = false;
4829                 return 0;
4830         }
4831
4832         data->need_long_memory_training = true;
4833
4834 /*
4835  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4836         pfd = &tonga_mcmeFirmware;
4837         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4838                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4839                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4840                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4841 */
4842         return 0;
4843 }
4844
4845 /**
4846  * Read clock related registers.
4847  *
4848  * @param    hwmgr  the address of the powerplay hardware manager.
4849  * @return   always 0
4850  */
4851 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4852 {
4853         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4854
4855         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4856                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4857                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4858
4859         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4860                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4861                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4862
4863         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4864                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4865                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4866
4867         return 0;
4868 }
4869
4870 /**
4871  * Find out if memory is GDDR5.
4872  *
4873  * @param    hwmgr  the address of the powerplay hardware manager.
4874  * @return   always 0
4875  */
4876 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4877 {
4878         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4879         uint32_t temp;
4880
4881         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4882
4883         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4884                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4885                          MC_SEQ_MISC0_GDDR5_SHIFT));
4886
4887         return 0;
4888 }
4889
4890 /**
4891  * Enables Dynamic Power Management by SMC
4892  *
4893  * @param    hwmgr  the address of the powerplay hardware manager.
4894  * @return   always 0
4895  */
4896 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4897 {
4898         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4899                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4900
4901         return 0;
4902 }
4903
4904 /**
4905  * Initialize PowerGating States for different engines
4906  *
4907  * @param    hwmgr  the address of the powerplay hardware manager.
4908  * @return   always 0
4909  */
4910 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4911 {
4912         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4913
4914         data->uvd_power_gated = false;
4915         data->vce_power_gated = false;
4916         data->samu_power_gated = false;
4917
4918         return 0;
4919 }
4920
4921 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4922 {
4923         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4924         data->low_sclk_interrupt_threshold = 0;
4925
4926         return 0;
4927 }
4928
4929 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4930 {
4931         int tmp_result, result = 0;
4932
4933         polaris10_upload_mc_firmware(hwmgr);
4934
4935         tmp_result = polaris10_read_clock_registers(hwmgr);
4936         PP_ASSERT_WITH_CODE((0 == tmp_result),
4937                         "Failed to read clock registers!", result = tmp_result);
4938
4939         tmp_result = polaris10_get_memory_type(hwmgr);
4940         PP_ASSERT_WITH_CODE((0 == tmp_result),
4941                         "Failed to get memory type!", result = tmp_result);
4942
4943         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4944         PP_ASSERT_WITH_CODE((0 == tmp_result),
4945                         "Failed to enable ACPI power management!", result = tmp_result);
4946
4947         tmp_result = polaris10_init_power_gate_state(hwmgr);
4948         PP_ASSERT_WITH_CODE((0 == tmp_result),
4949                         "Failed to init power gate state!", result = tmp_result);
4950
4951         tmp_result = phm_get_mc_microcode_version(hwmgr);
4952         PP_ASSERT_WITH_CODE((0 == tmp_result),
4953                         "Failed to get MC microcode version!", result = tmp_result);
4954
4955         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4956         PP_ASSERT_WITH_CODE((0 == tmp_result),
4957                         "Failed to init sclk threshold!", result = tmp_result);
4958
4959         return result;
4960 }
4961
4962 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4963 {
4964         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4965
4966         if (!data->soft_pp_table) {
4967                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4968                                               hwmgr->soft_pp_table_size,
4969                                               GFP_KERNEL);
4970                 if (!data->soft_pp_table)
4971                         return -ENOMEM;
4972         }
4973
4974         *table = (char *)&data->soft_pp_table;
4975
4976         return hwmgr->soft_pp_table_size;
4977 }
4978
4979 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4980 {
4981         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4982
4983         if (!data->soft_pp_table) {
4984                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4985                 if (!data->soft_pp_table)
4986                         return -ENOMEM;
4987         }
4988
4989         memcpy(data->soft_pp_table, buf, size);
4990
4991         hwmgr->soft_pp_table = data->soft_pp_table;
4992
4993         /* TODO: re-init powerplay to implement modified pptable */
4994
4995         return 0;
4996 }
4997
4998 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4999                 enum pp_clock_type type, uint32_t mask)
5000 {
5001         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5002
5003         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5004                 return -EINVAL;
5005
5006         switch (type) {
5007         case PP_SCLK:
5008                 if (!data->sclk_dpm_key_disabled)
5009                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5010                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5011                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5012                 break;
5013         case PP_MCLK:
5014                 if (!data->mclk_dpm_key_disabled)
5015                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5016                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5017                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5018                 break;
5019         case PP_PCIE:
5020         {
5021                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5022                 uint32_t level = 0;
5023
5024                 while (tmp >>= 1)
5025                         level++;
5026
5027                 if (!data->pcie_dpm_key_disabled)
5028                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5029                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5030                                         level);
5031                 break;
5032         }
5033         default:
5034                 break;
5035         }
5036
5037         return 0;
5038 }
5039
5040 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5041 {
5042         uint32_t speedCntl = 0;
5043
5044         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5045         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5046                         ixPCIE_LC_SPEED_CNTL);
5047         return((uint16_t)PHM_GET_FIELD(speedCntl,
5048                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5049 }
5050
5051 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5052                 enum pp_clock_type type, char *buf)
5053 {
5054         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5055         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5056         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5057         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5058         int i, now, size = 0;
5059         uint32_t clock, pcie_speed;
5060
5061         switch (type) {
5062         case PP_SCLK:
5063                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5064                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5065
5066                 for (i = 0; i < sclk_table->count; i++) {
5067                         if (clock > sclk_table->dpm_levels[i].value)
5068                                 continue;
5069                         break;
5070                 }
5071                 now = i;
5072
5073                 for (i = 0; i < sclk_table->count; i++)
5074                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5075                                         i, sclk_table->dpm_levels[i].value / 100,
5076                                         (i == now) ? "*" : "");
5077                 break;
5078         case PP_MCLK:
5079                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5080                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5081
5082                 for (i = 0; i < mclk_table->count; i++) {
5083                         if (clock > mclk_table->dpm_levels[i].value)
5084                                 continue;
5085                         break;
5086                 }
5087                 now = i;
5088
5089                 for (i = 0; i < mclk_table->count; i++)
5090                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5091                                         i, mclk_table->dpm_levels[i].value / 100,
5092                                         (i == now) ? "*" : "");
5093                 break;
5094         case PP_PCIE:
5095                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5096                 for (i = 0; i < pcie_table->count; i++) {
5097                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5098                                 continue;
5099                         break;
5100                 }
5101                 now = i;
5102
5103                 for (i = 0; i < pcie_table->count; i++)
5104                         size += sprintf(buf + size, "%d: %s %s\n", i,
5105                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5106                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5107                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5108                                         (i == now) ? "*" : "");
5109                 break;
5110         default:
5111                 break;
5112         }
5113         return size;
5114 }
5115
5116 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5117 {
5118         if (mode) {
5119                 /* stop auto-manage */
5120                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5121                                 PHM_PlatformCaps_MicrocodeFanControl))
5122                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5123                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5124         } else
5125                 /* restart auto-manage */
5126                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5127
5128         return 0;
5129 }
5130
5131 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5132 {
5133         if (hwmgr->fan_ctrl_is_in_default_mode)
5134                 return hwmgr->fan_ctrl_default_mode;
5135         else
5136                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5137                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5138 }
5139
5140 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5141 {
5142         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5143         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5144         struct polaris10_single_dpm_table *golden_sclk_table =
5145                         &(data->golden_dpm_table.sclk_table);
5146         int value;
5147
5148         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5149                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5150                         100 /
5151                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5152
5153         return value;
5154 }
5155
5156 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5157 {
5158         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5159         struct polaris10_single_dpm_table *golden_sclk_table =
5160                         &(data->golden_dpm_table.sclk_table);
5161         struct pp_power_state  *ps;
5162         struct polaris10_power_state  *polaris10_ps;
5163
5164         if (value > 20)
5165                 value = 20;
5166
5167         ps = hwmgr->request_ps;
5168
5169         if (ps == NULL)
5170                 return -EINVAL;
5171
5172         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5173
5174         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5175                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5176                         value / 100 +
5177                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5178
5179         return 0;
5180 }
5181
5182 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5183 {
5184         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5185         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5186         struct polaris10_single_dpm_table *golden_mclk_table =
5187                         &(data->golden_dpm_table.mclk_table);
5188         int value;
5189
5190         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5191                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5192                         100 /
5193                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5194
5195         return value;
5196 }
5197
5198 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5199 {
5200         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5201         struct polaris10_single_dpm_table *golden_mclk_table =
5202                         &(data->golden_dpm_table.mclk_table);
5203         struct pp_power_state  *ps;
5204         struct polaris10_power_state  *polaris10_ps;
5205
5206         if (value > 20)
5207                 value = 20;
5208
5209         ps = hwmgr->request_ps;
5210
5211         if (ps == NULL)
5212                 return -EINVAL;
5213
5214         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5215
5216         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5217                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5218                         value / 100 +
5219                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5220
5221         return 0;
5222 }
5223 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5224         .backend_init = &polaris10_hwmgr_backend_init,
5225         .backend_fini = &polaris10_hwmgr_backend_fini,
5226         .asic_setup = &polaris10_setup_asic_task,
5227         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5228         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5229         .force_dpm_level = &polaris10_force_dpm_level,
5230         .power_state_set = polaris10_set_power_state_tasks,
5231         .get_power_state_size = polaris10_get_power_state_size,
5232         .get_mclk = polaris10_dpm_get_mclk,
5233         .get_sclk = polaris10_dpm_get_sclk,
5234         .patch_boot_state = polaris10_dpm_patch_boot_state,
5235         .get_pp_table_entry = polaris10_get_pp_table_entry,
5236         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5237         .print_current_perforce_level = polaris10_print_current_perforce_level,
5238         .powerdown_uvd = polaris10_phm_powerdown_uvd,
5239         .powergate_uvd = polaris10_phm_powergate_uvd,
5240         .powergate_vce = polaris10_phm_powergate_vce,
5241         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5242         .update_clock_gatings = polaris10_phm_update_clock_gatings,
5243         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5244         .display_config_changed = polaris10_display_configuration_changed_task,
5245         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5246         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5247         .get_temperature = polaris10_thermal_get_temperature,
5248         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5249         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5250         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5251         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5252         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5253         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5254         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5255         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5256         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5257         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5258         .check_states_equal = polaris10_check_states_equal,
5259         .set_fan_control_mode = polaris10_set_fan_control_mode,
5260         .get_fan_control_mode = polaris10_get_fan_control_mode,
5261         .get_pp_table = polaris10_get_pp_table,
5262         .set_pp_table = polaris10_set_pp_table,
5263         .force_clock_level = polaris10_force_clock_level,
5264         .print_clock_levels = polaris10_print_clock_levels,
5265         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5266         .get_sclk_od = polaris10_get_sclk_od,
5267         .set_sclk_od = polaris10_set_sclk_od,
5268         .get_mclk_od = polaris10_get_mclk_od,
5269         .set_mclk_od = polaris10_set_mclk_od,
5270 };
5271
5272 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5273 {
5274         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5275         hwmgr->pptable_func = &tonga_pptable_funcs;
5276         pp_polaris10_thermal_initialize(hwmgr);
5277
5278         return 0;
5279 }