drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/delay.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29 #include <linux/pci.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "power_state.h"
  32 #include "hwmgr.h"
  33 #include "ppsmc.h"
  34 #include "amd_acpi.h"
  35 #include "pp_psm.h"
  36
  37 extern const struct pp_smumgr_func ci_smu_funcs;
  38 extern const struct pp_smumgr_func smu8_smu_funcs;
  39 extern const struct pp_smumgr_func iceland_smu_funcs;
  40 extern const struct pp_smumgr_func tonga_smu_funcs;
  41 extern const struct pp_smumgr_func fiji_smu_funcs;
  42 extern const struct pp_smumgr_func polaris10_smu_funcs;
  43 extern const struct pp_smumgr_func vegam_smu_funcs;
  44 extern const struct pp_smumgr_func vega10_smu_funcs;
  45 extern const struct pp_smumgr_func vega12_smu_funcs;
  46 extern const struct pp_smumgr_func smu10_smu_funcs;
  47
  48 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
  49 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
  50 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
  51 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
  52 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
  53
  54 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  55 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
  56 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
  57 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  58 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  59 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  60 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  61
  62
  63 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
  64 {
  65         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
  66         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
  67         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
  68         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
  69         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
  70
  71         hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
  72         hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
  73         hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
  74         hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
  75         hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
  76 }
  77
  78 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
  79 {
  80         if (!hwmgr)
  81                 return -EINVAL;
  82
  83         hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  84         hwmgr->power_source = PP_PowerSource_AC;
  85         hwmgr->pp_table_version = PP_TABLE_V1;
  86         hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  87         hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  88         hwmgr_init_default_caps(hwmgr);
  89         hwmgr_set_user_specify_caps(hwmgr);
  90         hwmgr->fan_ctrl_is_in_default_mode = true;
  91         hwmgr->reload_fw = 1;
  92         hwmgr_init_workload_prority(hwmgr);
  93
  94         switch (hwmgr->chip_family) {
  95         case AMDGPU_FAMILY_CI:
  96                 hwmgr->smumgr_funcs = &ci_smu_funcs;
  97                 ci_set_asic_special_caps(hwmgr);
  98                 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
  99                                          PP_ENABLE_GFX_CG_THRU_SMU |
 100                                          PP_GFXOFF_MASK);
 101                 hwmgr->pp_table_version = PP_TABLE_V0;
 102                 hwmgr->od_enabled = false;
 103                 smu7_init_function_pointers(hwmgr);
 104                 break;
 105         case AMDGPU_FAMILY_CZ:
 106                 hwmgr->od_enabled = false;
 107                 hwmgr->smumgr_funcs = &smu8_smu_funcs;
 108                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 109                 smu8_init_function_pointers(hwmgr);
 110                 break;
 111         case AMDGPU_FAMILY_VI:
 112                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 113                 switch (hwmgr->chip_id) {
 114                 case CHIP_TOPAZ:
 115                         hwmgr->smumgr_funcs = &iceland_smu_funcs;
 116                         topaz_set_asic_special_caps(hwmgr);
 117                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 118                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 119                         hwmgr->pp_table_version = PP_TABLE_V0;
 120                         hwmgr->od_enabled = false;
 121                         break;
 122                 case CHIP_TONGA:
 123                         hwmgr->smumgr_funcs = &tonga_smu_funcs;
 124                         tonga_set_asic_special_caps(hwmgr);
 125                         hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
 126                         break;
 127                 case CHIP_FIJI:
 128                         hwmgr->smumgr_funcs = &fiji_smu_funcs;
 129                         fiji_set_asic_special_caps(hwmgr);
 130                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 131                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 132                         break;
 133                 case CHIP_POLARIS11:
 134                 case CHIP_POLARIS10:
 135                 case CHIP_POLARIS12:
 136                         hwmgr->smumgr_funcs = &polaris10_smu_funcs;
 137                         polaris_set_asic_special_caps(hwmgr);
 138                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 139                         break;
 140                 case CHIP_VEGAM:
 141                         hwmgr->smumgr_funcs = &vegam_smu_funcs;
 142                         polaris_set_asic_special_caps(hwmgr);
 143                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 144                         break;
 145                 default:
 146                         return -EINVAL;
 147                 }
 148                 smu7_init_function_pointers(hwmgr);
 149                 break;
 150         case AMDGPU_FAMILY_AI:
 151                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 152                 switch (hwmgr->chip_id) {
 153                 case CHIP_VEGA10:
 154                         hwmgr->smumgr_funcs = &vega10_smu_funcs;
 155                         vega10_hwmgr_init(hwmgr);
 156                         break;
 157                 case CHIP_VEGA12:
 158                         hwmgr->smumgr_funcs = &vega12_smu_funcs;
 159                         vega12_hwmgr_init(hwmgr);
 160                         break;
 161                 default:
 162                         return -EINVAL;
 163                 }
 164                 break;
 165         case AMDGPU_FAMILY_RV:
 166                 switch (hwmgr->chip_id) {
 167                 case CHIP_RAVEN:
 168                         hwmgr->od_enabled = false;
 169                         hwmgr->smumgr_funcs = &smu10_smu_funcs;
 170                         smu10_init_function_pointers(hwmgr);
 171                         break;
 172                 default:
 173                         return -EINVAL;
 174                 }
 175                 break;
 176         default:
 177                 return -EINVAL;
 178         }
 179
 180         return 0;
 181 }
 182
 183 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
 184 {
 185         if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
 186                 return -EINVAL;
 187
 188         phm_register_irq_handlers(hwmgr);
 189
 190         return hwmgr->smumgr_funcs->smu_init(hwmgr);
 191 }
 192
 193
 194 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
 195 {
 196         if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
 197                 hwmgr->smumgr_funcs->smu_fini(hwmgr);
 198
 199         return 0;
 200 }
 201
 202 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
 203 {
 204         int ret = 0;
 205
 206         if (!hwmgr || !hwmgr->smumgr_funcs)
 207                 return -EINVAL;
 208
 209         if (hwmgr->smumgr_funcs->start_smu) {
 210                 ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
 211                 if (ret) {
 212                         pr_err("smc start failed\n");
 213                         return -EINVAL;
 214                 }
 215         }
 216
 217         if (!hwmgr->pm_en)
 218                 return 0;
 219
 220         if (!hwmgr->pptable_func ||
 221             !hwmgr->pptable_func->pptable_init ||
 222             !hwmgr->hwmgr_func->backend_init) {
 223                 hwmgr->pm_en = false;
 224                 pr_info("dpm not supported \n");
 225                 return 0;
 226         }
 227
 228         ret = hwmgr->pptable_func->pptable_init(hwmgr);
 229         if (ret)
 230                 goto err;
 231
 232         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 233         if (ret)
 234                 goto err1;
 235
 236         ret = psm_init_power_state_table(hwmgr);
 237         if (ret)
 238                 goto err2;
 239
 240         ret = phm_setup_asic(hwmgr);
 241         if (ret)
 242                 goto err2;
 243
 244         ret = phm_enable_dynamic_state_management(hwmgr);
 245         if (ret)
 246                 goto err2;
 247         ret = phm_start_thermal_controller(hwmgr);
 248         ret |= psm_set_performance_states(hwmgr);
 249         if (ret)
 250                 goto err2;
 251
 252         ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
 253
 254         return 0;
 255 err2:
 256         if (hwmgr->hwmgr_func->backend_fini)
 257                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 258 err1:
 259         if (hwmgr->pptable_func->pptable_fini)
 260                 hwmgr->pptable_func->pptable_fini(hwmgr);
 261 err:
 262         return ret;
 263 }
 264
 265 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 266 {
 267         if (!hwmgr || !hwmgr->pm_en)
 268                 return 0;
 269
 270         phm_stop_thermal_controller(hwmgr);
 271         psm_set_boot_states(hwmgr);
 272         psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 273         phm_disable_dynamic_state_management(hwmgr);
 274         phm_disable_clock_power_gatings(hwmgr);
 275
 276         if (hwmgr->hwmgr_func->backend_fini)
 277                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 278         if (hwmgr->pptable_func->pptable_fini)
 279                 hwmgr->pptable_func->pptable_fini(hwmgr);
 280         return psm_fini_power_state_table(hwmgr);
 281 }
 282
 283 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
 284 {
 285         int ret = 0;
 286
 287         if (!hwmgr || !hwmgr->pm_en)
 288                 return 0;
 289
 290         phm_disable_smc_firmware_ctf(hwmgr);
 291         ret = psm_set_boot_states(hwmgr);
 292         if (ret)
 293                 return ret;
 294         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 295         if (ret)
 296                 return ret;
 297         ret = phm_power_down_asic(hwmgr);
 298
 299         return ret;
 300 }
 301
 302 int hwmgr_resume(struct pp_hwmgr *hwmgr)
 303 {
 304         int ret = 0;
 305
 306         if (!hwmgr)
 307                 return -EINVAL;
 308
 309         if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
 310                 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
 311                         pr_err("smc start failed\n");
 312                         return -EINVAL;
 313                 }
 314         }
 315
 316         if (!hwmgr->pm_en)
 317                 return 0;
 318
 319         ret = phm_setup_asic(hwmgr);
 320         if (ret)
 321                 return ret;
 322
 323         ret = phm_enable_dynamic_state_management(hwmgr);
 324         if (ret)
 325                 return ret;
 326         ret = phm_start_thermal_controller(hwmgr);
 327         ret |= psm_set_performance_states(hwmgr);
 328         if (ret)
 329                 return ret;
 330
 331         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 332
 333         return ret;
 334 }
 335
 336 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 337 {
 338         switch (state) {
 339         case POWER_STATE_TYPE_BATTERY:
 340                 return PP_StateUILabel_Battery;
 341         case POWER_STATE_TYPE_BALANCED:
 342                 return PP_StateUILabel_Balanced;
 343         case POWER_STATE_TYPE_PERFORMANCE:
 344                 return PP_StateUILabel_Performance;
 345         default:
 346                 return PP_StateUILabel_None;
 347         }
 348 }
 349
 350 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
 351                 enum amd_pm_state_type *user_state)
 352 {
 353         int ret = 0;
 354
 355         if (hwmgr == NULL)
 356                 return -EINVAL;
 357
 358         switch (task_id) {
 359         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
 360                 ret = phm_set_cpu_power_state(hwmgr);
 361                 if (ret)
 362                         return ret;
 363                 ret = psm_set_performance_states(hwmgr);
 364                 if (ret)
 365                         return ret;
 366                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 367                 break;
 368         case AMD_PP_TASK_ENABLE_USER_STATE:
 369         {
 370                 enum PP_StateUILabel requested_ui_label;
 371                 struct pp_power_state *requested_ps = NULL;
 372
 373                 if (user_state == NULL) {
 374                         ret = -EINVAL;
 375                         break;
 376                 }
 377
 378                 requested_ui_label = power_state_convert(*user_state);
 379                 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
 380                 if (ret)
 381                         return ret;
 382                 ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
 383                 break;
 384         }
 385         case AMD_PP_TASK_COMPLETE_INIT:
 386         case AMD_PP_TASK_READJUST_POWER_STATE:
 387                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 388                 break;
 389         default:
 390                 break;
 391         }
 392         return ret;
 393 }
 394
 395 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 396 {
 397         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 398
 399         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
 400         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
 401
 402 #if defined(CONFIG_ACPI)
 403         if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
 404                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 405 #endif
 406
 407         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 408                 PHM_PlatformCaps_DynamicPatchPowerState);
 409
 410         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 411                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 412
 413         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 414                         PHM_PlatformCaps_DynamicPowerManagement);
 415
 416         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 417                                         PHM_PlatformCaps_SMC);
 418
 419         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 420                                         PHM_PlatformCaps_DynamicUVDState);
 421
 422         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 423                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 424         return;
 425 }
 426
 427 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 428 {
 429         if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
 430                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 431                         PHM_PlatformCaps_SclkDeepSleep);
 432         else
 433                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 434                         PHM_PlatformCaps_SclkDeepSleep);
 435
 436         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 437                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 438                             PHM_PlatformCaps_PowerContainment);
 439                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 440                         PHM_PlatformCaps_CAC);
 441         } else {
 442                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 443                             PHM_PlatformCaps_PowerContainment);
 444                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 445                         PHM_PlatformCaps_CAC);
 446         }
 447
 448         if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
 449                 hwmgr->od_enabled = true;
 450
 451         return 0;
 452 }
 453
 454 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 455 {
 456         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 457                                                 PHM_PlatformCaps_EVV);
 458         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 459                                                 PHM_PlatformCaps_SQRamping);
 460         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 461                                                 PHM_PlatformCaps_RegulatorHot);
 462
 463         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 464                                         PHM_PlatformCaps_AutomaticDCTransition);
 465
 466         if (hwmgr->chip_id != CHIP_POLARIS10)
 467                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 468                                         PHM_PlatformCaps_SPLLShutdownSupport);
 469
 470         if (hwmgr->chip_id != CHIP_POLARIS11) {
 471                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 472                                                         PHM_PlatformCaps_DBRamping);
 473                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 474                                                         PHM_PlatformCaps_TDRamping);
 475                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 476                                                         PHM_PlatformCaps_TCPRamping);
 477         }
 478         return 0;
 479 }
 480
 481 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 482 {
 483         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 484                                                 PHM_PlatformCaps_EVV);
 485         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 486                         PHM_PlatformCaps_SQRamping);
 487         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 488                         PHM_PlatformCaps_DBRamping);
 489         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 490                         PHM_PlatformCaps_TDRamping);
 491         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 492                         PHM_PlatformCaps_TCPRamping);
 493         return 0;
 494 }
 495
 496 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 497 {
 498         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 499                                                 PHM_PlatformCaps_EVV);
 500         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 501                         PHM_PlatformCaps_SQRamping);
 502         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 503                         PHM_PlatformCaps_DBRamping);
 504         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 505                         PHM_PlatformCaps_TDRamping);
 506         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 507                         PHM_PlatformCaps_TCPRamping);
 508
 509         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 510                       PHM_PlatformCaps_UVDPowerGating);
 511         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 512                       PHM_PlatformCaps_VCEPowerGating);
 513         return 0;
 514 }
 515
 516 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 517 {
 518         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 519                                                 PHM_PlatformCaps_EVV);
 520         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 521                         PHM_PlatformCaps_SQRamping);
 522         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 523                         PHM_PlatformCaps_DBRamping);
 524         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 525                         PHM_PlatformCaps_TDRamping);
 526         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 527                         PHM_PlatformCaps_TCPRamping);
 528         return 0;
 529 }
 530
 531 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 532 {
 533         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 534                         PHM_PlatformCaps_SQRamping);
 535         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 536                         PHM_PlatformCaps_DBRamping);
 537         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 538                         PHM_PlatformCaps_TDRamping);
 539         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 540                         PHM_PlatformCaps_TCPRamping);
 541         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 542                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 543         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 544                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
 545         return 0;
 546 }