drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41 #include "pp_thermal.h"
  42
  43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  44 #define CURRENT_NB_VID_MASK 0xff000000
  45 #define CURRENT_NB_VID__SHIFT 24
  46 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  47 #define CURRENT_GFX_VID_MASK 0xff000000
  48 #define CURRENT_GFX_VID__SHIFT 24
  49
  50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  51
  52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  53 {
  54         if (PhwCz_Magic != hw_ps->magic)
  55                 return NULL;
  56
  57         return (struct cz_power_state *)hw_ps;
  58 }
  59
  60 static const struct cz_power_state *cast_const_PhwCzPowerState(
  61                                 const struct pp_hw_power_state *hw_ps)
  62 {
  63         if (PhwCz_Magic != hw_ps->magic)
  64                 return NULL;
  65
  66         return (struct cz_power_state *)hw_ps;
  67 }
  68
  69 static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  70                                         uint32_t clock, uint32_t msg)
  71 {
  72         int i = 0;
  73         struct phm_vce_clock_voltage_dependency_table *ptable =
  74                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  75
  76         switch (msg) {
  77         case PPSMC_MSG_SetEclkSoftMin:
  78         case PPSMC_MSG_SetEclkHardMin:
  79                 for (i = 0; i < (int)ptable->count; i++) {
  80                         if (clock <= ptable->entries[i].ecclk)
  81                                 break;
  82                 }
  83                 break;
  84
  85         case PPSMC_MSG_SetEclkSoftMax:
  86         case PPSMC_MSG_SetEclkHardMax:
  87                 for (i = ptable->count - 1; i >= 0; i--) {
  88                         if (clock >= ptable->entries[i].ecclk)
  89                                 break;
  90                 }
  91                 break;
  92
  93         default:
  94                 break;
  95         }
  96
  97         return i;
  98 }
  99
 100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 101                                 uint32_t clock, uint32_t msg)
 102 {
 103         int i = 0;
 104         struct phm_clock_voltage_dependency_table *table =
 105                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 106
 107         switch (msg) {
 108         case PPSMC_MSG_SetSclkSoftMin:
 109         case PPSMC_MSG_SetSclkHardMin:
 110                 for (i = 0; i < (int)table->count; i++) {
 111                         if (clock <= table->entries[i].clk)
 112                                 break;
 113                 }
 114                 break;
 115
 116         case PPSMC_MSG_SetSclkSoftMax:
 117         case PPSMC_MSG_SetSclkHardMax:
 118                 for (i = table->count - 1; i >= 0; i--) {
 119                         if (clock >= table->entries[i].clk)
 120                                 break;
 121                 }
 122                 break;
 123
 124         default:
 125                 break;
 126         }
 127         return i;
 128 }
 129
 130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 131                                         uint32_t clock, uint32_t msg)
 132 {
 133         int i = 0;
 134         struct phm_uvd_clock_voltage_dependency_table *ptable =
 135                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 136
 137         switch (msg) {
 138         case PPSMC_MSG_SetUvdSoftMin:
 139         case PPSMC_MSG_SetUvdHardMin:
 140                 for (i = 0; i < (int)ptable->count; i++) {
 141                         if (clock <= ptable->entries[i].vclk)
 142                                 break;
 143                 }
 144                 break;
 145
 146         case PPSMC_MSG_SetUvdSoftMax:
 147         case PPSMC_MSG_SetUvdHardMax:
 148                 for (i = ptable->count - 1; i >= 0; i--) {
 149                         if (clock >= ptable->entries[i].vclk)
 150                                 break;
 151                 }
 152                 break;
 153
 154         default:
 155                 break;
 156         }
 157
 158         return i;
 159 }
 160
 161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 162 {
 163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 164
 165         if (cz_hwmgr->max_sclk_level == 0) {
 166                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
 167                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
 168         }
 169
 170         return cz_hwmgr->max_sclk_level;
 171 }
 172
 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 174 {
 175         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 176         uint32_t i;
 177         struct cgs_system_info sys_info = {0};
 178         int result;
 179
 180         cz_hwmgr->gfx_ramp_step = 256*25/100;
 181         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 182
 183         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 184                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 185
 186         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 187         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 188         cz_hwmgr->clock_slow_down_freq = 25000;
 189         cz_hwmgr->skip_clock_slow_down = 1;
 190         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 191         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 192         cz_hwmgr->voting_rights_clients = 0x00C00033;
 193         cz_hwmgr->static_screen_threshold = 8;
 194         cz_hwmgr->ddi_power_gating_disabled = 0;
 195         cz_hwmgr->bapm_enabled = 1;
 196         cz_hwmgr->voltage_drop_threshold = 0;
 197         cz_hwmgr->gfx_power_gating_threshold = 500;
 198         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 199         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 200         cz_hwmgr->disable_driver_thermal_policy = 1;
 201         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 202
 203         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 204                                                         PHM_PlatformCaps_ABM);
 205
 206         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 207                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 208
 209         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 210                                         PHM_PlatformCaps_DynamicM3Arbiter);
 211
 212         cz_hwmgr->override_dynamic_mgpg = 1;
 213
 214         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                                   PHM_PlatformCaps_DynamicPatchPowerState);
 216
 217         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 218         cz_hwmgr->tdr_clock = 0;
 219         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                                         PHM_PlatformCaps_DynamicUVDState);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_UVDDPM);
 226         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_VCEDPM);
 228
 229         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 230         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 231         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 232         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 233
 234         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 235                                    PHM_PlatformCaps_DisableVoltageIsland);
 236
 237         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 238                       PHM_PlatformCaps_UVDPowerGating);
 239         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 240                       PHM_PlatformCaps_VCEPowerGating);
 241         sys_info.size = sizeof(struct cgs_system_info);
 242         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 243         result = cgs_query_system_info(hwmgr->device, &sys_info);
 244         if (!result) {
 245                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 246                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 247                                       PHM_PlatformCaps_UVDPowerGating);
 248                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 250                                       PHM_PlatformCaps_VCEPowerGating);
 251         }
 252
 253         return 0;
 254 }
 255
 256 static uint32_t cz_convert_8Bit_index_to_voltage(
 257                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 258 {
 259         return 6200 - (voltage * 25);
 260 }
 261
 262 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 263                         struct phm_clock_and_voltage_limits *table)
 264 {
 265         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 266         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 267         struct phm_clock_voltage_dependency_table *dep_table =
 268                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 269
 270         if (dep_table->count > 0) {
 271                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 272                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 273                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 274         }
 275         table->mclk = sys_info->nbp_memory_clock[0];
 276         return 0;
 277 }
 278
 279 static int cz_init_dynamic_state_adjustment_rule_settings(
 280                         struct pp_hwmgr *hwmgr,
 281                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 282 {
 283         uint32_t table_size =
 284                 sizeof(struct phm_clock_voltage_dependency_table) +
 285                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 286
 287         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 288                                         kzalloc(table_size, GFP_KERNEL);
 289
 290         if (NULL == table_clk_vlt) {
 291                 pr_err("Can not allocate memory!\n");
 292                 return -ENOMEM;
 293         }
 294
 295         table_clk_vlt->count = 8;
 296         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 297         table_clk_vlt->entries[0].v = 0;
 298         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 299         table_clk_vlt->entries[1].v = 1;
 300         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 301         table_clk_vlt->entries[2].v = 2;
 302         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 303         table_clk_vlt->entries[3].v = 3;
 304         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 305         table_clk_vlt->entries[4].v = 4;
 306         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 307         table_clk_vlt->entries[5].v = 5;
 308         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 309         table_clk_vlt->entries[6].v = 6;
 310         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 311         table_clk_vlt->entries[7].v = 7;
 312         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 313
 314         return 0;
 315 }
 316
 317 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 318 {
 319         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 320         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 321         uint32_t i;
 322         int result = 0;
 323         uint8_t frev, crev;
 324         uint16_t size;
 325
 326         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 327                         hwmgr->device,
 328                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 329                         &size, &frev, &crev);
 330
 331         if (crev != 9) {
 332                 pr_err("Unsupported IGP table: %d %d\n", frev, crev);
 333                 return -EINVAL;
 334         }
 335
 336         if (info == NULL) {
 337                 pr_err("Could not retrieve the Integrated System Info Table!\n");
 338                 return -EINVAL;
 339         }
 340
 341         cz_hwmgr->sys_info.bootup_uma_clock =
 342                                    le32_to_cpu(info->ulBootUpUMAClock);
 343
 344         cz_hwmgr->sys_info.bootup_engine_clock =
 345                                 le32_to_cpu(info->ulBootUpEngineClock);
 346
 347         cz_hwmgr->sys_info.dentist_vco_freq =
 348                                    le32_to_cpu(info->ulDentistVCOFreq);
 349
 350         cz_hwmgr->sys_info.system_config =
 351                                      le32_to_cpu(info->ulSystemConfig);
 352
 353         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 354                                   le16_to_cpu(info->usBootUpNBVoltage);
 355
 356         cz_hwmgr->sys_info.htc_hyst_lmt =
 357                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 358
 359         cz_hwmgr->sys_info.htc_tmp_lmt =
 360                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 361
 362         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 363                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 364                 pr_err("The htcTmpLmt should be larger than htcHystLmt.\n");
 365                 return -EINVAL;
 366         }
 367
 368         cz_hwmgr->sys_info.nb_dpm_enable =
 369                                 cz_hwmgr->enable_nb_ps_policy &&
 370                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 371
 372         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 373                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 374                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 375                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 376                 }
 377                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 378                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 379         }
 380
 381         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 382                 cz_hwmgr->sys_info.display_clock[i] =
 383                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 384         }
 385
 386         /* Here use 4 levels, make sure not exceed */
 387         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 388                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 389                              le16_to_cpu(info->usNBPStateVoltage[i]);
 390         }
 391
 392         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 393                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 394                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 395                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 396                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 397                         }
 398                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 399                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 400                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 401                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 402                 }
 403         }
 404
 405         if (le32_to_cpu(info->ulGPUCapInfo) &
 406                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 407                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 408                                     PHM_PlatformCaps_EnableDFSBypass);
 409         }
 410
 411         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 412
 413         cz_construct_max_power_limits_table (hwmgr,
 414                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 415
 416         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 417                                     &info->sDISPCLK_Voltage[0]);
 418
 419         return result;
 420 }
 421
 422 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 423 {
 424         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 425
 426         cz_hwmgr->boot_power_level.engineClock =
 427                                 cz_hwmgr->sys_info.bootup_engine_clock;
 428
 429         cz_hwmgr->boot_power_level.vddcIndex =
 430                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 431
 432         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 433         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 434         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 435         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 436         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 437         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 438         cz_hwmgr->boot_power_level.display_wm = 0;
 439         cz_hwmgr->boot_power_level.vce_wm = 0;
 440
 441         return 0;
 442 }
 443
 444 static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
 445 {
 446         struct SMU8_Fusion_ClkTable *clock_table;
 447         int ret;
 448         uint32_t i;
 449         void *table = NULL;
 450         pp_atomctrl_clock_dividers_kong dividers;
 451
 452         struct phm_clock_voltage_dependency_table *vddc_table =
 453                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 454         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 455                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 456         struct phm_acp_clock_voltage_dependency_table *acp_table =
 457                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 458         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 459                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 460         struct phm_vce_clock_voltage_dependency_table *vce_table =
 461                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 462
 463         if (!hwmgr->need_pp_table_upload)
 464                 return 0;
 465
 466         ret = smum_download_powerplay_table(hwmgr, &table);
 467
 468         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 469                             "Fail to get clock table from SMU!", return -EINVAL;);
 470
 471         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 472
 473         /* patch clock table */
 474         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 475                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 476         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 477                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 478         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 479                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 480         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 481                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 482         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 483                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 484
 485         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 486
 487                 /* vddc_sclk */
 488                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 489                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 490                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 491                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 492
 493                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 494                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 495                                                       &dividers);
 496
 497                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 498                         (uint8_t)dividers.pll_post_divider;
 499
 500                 /* vddgfx_sclk */
 501                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 502                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 503
 504                 /* acp breakdown */
 505                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 506                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 507                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 508                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 509
 510                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 511                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 512                                                       &dividers);
 513
 514                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 515                         (uint8_t)dividers.pll_post_divider;
 516
 517
 518                 /* uvd breakdown */
 519                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 520                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 521                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 522                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 523
 524                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 525                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 526                                                       &dividers);
 527
 528                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 529                         (uint8_t)dividers.pll_post_divider;
 530
 531                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 532                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 533                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 534                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 535
 536                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 537                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 538                                                       &dividers);
 539
 540                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 541                         (uint8_t)dividers.pll_post_divider;
 542
 543                 /* vce breakdown */
 544                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 545                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 546                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 547                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 548
 549
 550                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 551                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 552                                                       &dividers);
 553
 554                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 555                         (uint8_t)dividers.pll_post_divider;
 556
 557         }
 558         ret = smum_upload_powerplay_table(hwmgr);
 559
 560         return ret;
 561 }
 562
 563 static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
 564 {
 565         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 566         struct phm_clock_voltage_dependency_table *table =
 567                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 568         unsigned long clock = 0, level;
 569
 570         if (NULL == table || table->count <= 0)
 571                 return -EINVAL;
 572
 573         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 574         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 575
 576         level = cz_get_max_sclk_level(hwmgr) - 1;
 577
 578         if (level < table->count)
 579                 clock = table->entries[level].clk;
 580         else
 581                 clock = table->entries[table->count - 1].clk;
 582
 583         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 584         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 585
 586         return 0;
 587 }
 588
 589 static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
 590 {
 591         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 592         struct phm_uvd_clock_voltage_dependency_table *table =
 593                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 594         unsigned long clock = 0, level;
 595
 596         if (NULL == table || table->count <= 0)
 597                 return -EINVAL;
 598
 599         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 600         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 601
 602         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
 603         level = smum_get_argument(hwmgr);
 604
 605         if (level < table->count)
 606                 clock = table->entries[level].vclk;
 607         else
 608                 clock = table->entries[table->count - 1].vclk;
 609
 610         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 611         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 612
 613         return 0;
 614 }
 615
 616 static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
 617 {
 618         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 619         struct phm_vce_clock_voltage_dependency_table *table =
 620                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 621         unsigned long clock = 0, level;
 622
 623         if (NULL == table || table->count <= 0)
 624                 return -EINVAL;
 625
 626         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 627         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 628
 629         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
 630         level = smum_get_argument(hwmgr);
 631
 632         if (level < table->count)
 633                 clock = table->entries[level].ecclk;
 634         else
 635                 clock = table->entries[table->count - 1].ecclk;
 636
 637         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 638         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 639
 640         return 0;
 641 }
 642
 643 static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
 644 {
 645         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 646         struct phm_acp_clock_voltage_dependency_table *table =
 647                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 648         unsigned long clock = 0, level;
 649
 650         if (NULL == table || table->count <= 0)
 651                 return -EINVAL;
 652
 653         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 654         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 655
 656         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
 657         level = smum_get_argument(hwmgr);
 658
 659         if (level < table->count)
 660                 clock = table->entries[level].acpclk;
 661         else
 662                 clock = table->entries[table->count - 1].acpclk;
 663
 664         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 665         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 666         return 0;
 667 }
 668
 669 static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
 670 {
 671         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 672
 673         cz_hwmgr->uvd_power_gated = false;
 674         cz_hwmgr->vce_power_gated = false;
 675         cz_hwmgr->samu_power_gated = false;
 676         cz_hwmgr->acp_power_gated = false;
 677         cz_hwmgr->pgacpinit = true;
 678 }
 679
 680 static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 681 {
 682         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 683
 684         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 685 }
 686
 687 static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
 688 {
 689         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 690         struct phm_clock_voltage_dependency_table *table =
 691                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 692
 693         unsigned long clock = 0;
 694         unsigned long level;
 695         unsigned long stable_pstate_sclk;
 696         unsigned long percentage;
 697
 698         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 699         level = cz_get_max_sclk_level(hwmgr) - 1;
 700
 701         if (level < table->count)
 702                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 703         else
 704                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 705
 706         clock = hwmgr->display_config.min_core_set_clock;
 707         if (clock == 0)
 708                 pr_debug("min_core_set_clock not set\n");
 709
 710         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 711                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 712
 713                 smum_send_msg_to_smc_with_parameter(hwmgr,
 714                                                 PPSMC_MSG_SetSclkHardMin,
 715                                                  cz_get_sclk_level(hwmgr,
 716                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 717                                              PPSMC_MSG_SetSclkHardMin));
 718         }
 719
 720         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 721
 722         /* update minimum clocks for Stable P-State feature */
 723         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 724                                      PHM_PlatformCaps_StablePState)) {
 725                 percentage = 75;
 726                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 727                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 728                                         percentage) / 100;
 729
 730                 if (clock < stable_pstate_sclk)
 731                         clock = stable_pstate_sclk;
 732         }
 733
 734         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 735                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 736                 smum_send_msg_to_smc_with_parameter(hwmgr,
 737                                                 PPSMC_MSG_SetSclkSoftMin,
 738                                                 cz_get_sclk_level(hwmgr,
 739                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 740                                              PPSMC_MSG_SetSclkSoftMin));
 741         }
 742
 743         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 744                                     PHM_PlatformCaps_StablePState) &&
 745                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 746                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 747                 smum_send_msg_to_smc_with_parameter(hwmgr,
 748                                                 PPSMC_MSG_SetSclkSoftMax,
 749                                                 cz_get_sclk_level(hwmgr,
 750                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 751                                         PPSMC_MSG_SetSclkSoftMax));
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
 758 {
 759         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 760                                 PHM_PlatformCaps_SclkDeepSleep)) {
 761                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 762                 if (clks == 0)
 763                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 764
 765                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 766
 767                 smum_send_msg_to_smc_with_parameter(hwmgr,
 768                                 PPSMC_MSG_SetMinDeepSleepSclk,
 769                                 clks);
 770         }
 771
 772         return 0;
 773 }
 774
 775 static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
 776 {
 777         struct cz_hwmgr *cz_hwmgr =
 778                                   (struct cz_hwmgr *)(hwmgr->backend);
 779
 780         smum_send_msg_to_smc_with_parameter(hwmgr,
 781                                         PPSMC_MSG_SetWatermarkFrequency,
 782                                         cz_hwmgr->sclk_dpm.soft_max_clk);
 783
 784         return 0;
 785 }
 786
 787 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 788 {
 789         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 790
 791         if (hw_data->is_nb_dpm_enabled) {
 792                 if (enable) {
 793                         PP_DBG_LOG("enable Low Memory PState.\n");
 794
 795                         return smum_send_msg_to_smc_with_parameter(hwmgr,
 796                                                 PPSMC_MSG_EnableLowMemoryPstate,
 797                                                 (lock ? 1 : 0));
 798                 } else {
 799                         PP_DBG_LOG("disable Low Memory PState.\n");
 800
 801                         return smum_send_msg_to_smc_with_parameter(hwmgr,
 802                                                 PPSMC_MSG_DisableLowMemoryPstate,
 803                                                 (lock ? 1 : 0));
 804                 }
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
 811 {
 812         int ret = 0;
 813
 814         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 815         unsigned long dpm_features = 0;
 816
 817         if (cz_hwmgr->is_nb_dpm_enabled) {
 818                 cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
 819                 dpm_features |= NB_DPM_MASK;
 820                 ret = smum_send_msg_to_smc_with_parameter(
 821                                                           hwmgr,
 822                                                           PPSMC_MSG_DisableAllSmuFeatures,
 823                                                           dpm_features);
 824                 if (ret == 0)
 825                         cz_hwmgr->is_nb_dpm_enabled = false;
 826         }
 827
 828         return ret;
 829 }
 830
 831 static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
 832 {
 833         int ret = 0;
 834
 835         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 836         unsigned long dpm_features = 0;
 837
 838         if (!cz_hwmgr->is_nb_dpm_enabled) {
 839                 PP_DBG_LOG("enabling ALL SMU features.\n");
 840                 dpm_features |= NB_DPM_MASK;
 841                 ret = smum_send_msg_to_smc_with_parameter(
 842                                                           hwmgr,
 843                                                           PPSMC_MSG_EnableAllSmuFeatures,
 844                                                           dpm_features);
 845                 if (ret == 0)
 846                         cz_hwmgr->is_nb_dpm_enabled = true;
 847         }
 848
 849         return ret;
 850 }
 851
 852 static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
 853 {
 854         bool disable_switch;
 855         bool enable_low_mem_state;
 856         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 857         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 858         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 859
 860         if (hw_data->sys_info.nb_dpm_enable) {
 861                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 862                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 863
 864                 if (pnew_state->action == FORCE_HIGH)
 865                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 866                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 867                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 868                 else
 869                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 870         }
 871         return 0;
 872 }
 873
 874 static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 875 {
 876         int ret = 0;
 877
 878         cz_update_sclk_limit(hwmgr);
 879         cz_set_deep_sleep_sclk_threshold(hwmgr);
 880         cz_set_watermark_threshold(hwmgr);
 881         ret = cz_enable_nb_dpm(hwmgr);
 882         if (ret)
 883                 return ret;
 884         cz_update_low_mem_pstate(hwmgr, input);
 885
 886         return 0;
 887 };
 888
 889
 890 static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
 891 {
 892         int ret;
 893
 894         ret = cz_upload_pptable_to_smu(hwmgr);
 895         if (ret)
 896                 return ret;
 897         ret = cz_init_sclk_limit(hwmgr);
 898         if (ret)
 899                 return ret;
 900         ret = cz_init_uvd_limit(hwmgr);
 901         if (ret)
 902                 return ret;
 903         ret = cz_init_vce_limit(hwmgr);
 904         if (ret)
 905                 return ret;
 906         ret = cz_init_acp_limit(hwmgr);
 907         if (ret)
 908                 return ret;
 909
 910         cz_init_power_gate_state(hwmgr);
 911         cz_init_sclk_threshold(hwmgr);
 912
 913         return 0;
 914 }
 915
 916 static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
 917 {
 918         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 919
 920         hw_data->disp_clk_bypass_pending = false;
 921         hw_data->disp_clk_bypass = false;
 922 }
 923
 924 static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
 925 {
 926         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 927
 928         hw_data->is_nb_dpm_enabled = false;
 929 }
 930
 931 static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
 932 {
 933         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 934
 935         hw_data->cc6_settings.cc6_setting_changed = false;
 936         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 937         hw_data->cc6_settings.cpu_cc6_disable = false;
 938         hw_data->cc6_settings.cpu_pstate_disable = false;
 939 }
 940
 941 static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
 942 {
 943         cz_power_up_display_clock_sys_pll(hwmgr);
 944         cz_clear_nb_dpm_flag(hwmgr);
 945         cz_reset_cc6_data(hwmgr);
 946         return 0;
 947 };
 948
 949 static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
 950 {
 951         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 952                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
 953 }
 954
 955 static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
 956 {
 957         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
 958 }
 959
 960 static int cz_start_dpm(struct pp_hwmgr *hwmgr)
 961 {
 962         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 963
 964         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
 965
 966         return smum_send_msg_to_smc_with_parameter(hwmgr,
 967                                 PPSMC_MSG_EnableAllSmuFeatures,
 968                                 SCLK_DPM_MASK);
 969 }
 970
 971 static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
 972 {
 973         int ret = 0;
 974         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 975         unsigned long dpm_features = 0;
 976
 977         if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
 978                 dpm_features |= SCLK_DPM_MASK;
 979                 cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
 980                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 981                                         PPSMC_MSG_DisableAllSmuFeatures,
 982                                         dpm_features);
 983         }
 984         return ret;
 985 }
 986
 987 static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
 988 {
 989         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 990
 991         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
 992         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
 993
 994         smum_send_msg_to_smc_with_parameter(hwmgr,
 995                                 PPSMC_MSG_SetSclkSoftMin,
 996                                 cz_get_sclk_level(hwmgr,
 997                                 cz_hwmgr->sclk_dpm.soft_min_clk,
 998                                 PPSMC_MSG_SetSclkSoftMin));
 999
1000         smum_send_msg_to_smc_with_parameter(hwmgr,
1001                                 PPSMC_MSG_SetSclkSoftMax,
1002                                 cz_get_sclk_level(hwmgr,
1003                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1004                                 PPSMC_MSG_SetSclkSoftMax));
1005
1006         return 0;
1007 }
1008
1009 static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
1010 {
1011         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1012
1013         cz_hwmgr->acp_boot_level = 0xff;
1014 }
1015
1016 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1017                                 unsigned long check_feature)
1018 {
1019         int result;
1020         unsigned long features;
1021
1022         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
1023         if (result == 0) {
1024                 features = smum_get_argument(hwmgr);
1025                 if (features & check_feature)
1026                         return true;
1027         }
1028
1029         return false;
1030 }
1031
1032 static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
1033 {
1034         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1035                 return true;
1036         return false;
1037 }
1038
1039 static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1040 {
1041         if (!cz_check_for_dpm_enabled(hwmgr)) {
1042                 pr_info("dpm has been disabled\n");
1043                 return 0;
1044         }
1045         cz_disable_nb_dpm(hwmgr);
1046
1047         cz_clear_voting_clients(hwmgr);
1048         if (cz_stop_dpm(hwmgr))
1049                 return -EINVAL;
1050
1051         return 0;
1052 };
1053
1054 static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1055 {
1056         if (cz_check_for_dpm_enabled(hwmgr)) {
1057                 pr_info("dpm has been enabled\n");
1058                 return 0;
1059         }
1060
1061         cz_program_voting_clients(hwmgr);
1062         if (cz_start_dpm(hwmgr))
1063                 return -EINVAL;
1064         cz_program_bootup_state(hwmgr);
1065         cz_reset_acp_boot_level(hwmgr);
1066
1067         return 0;
1068 };
1069
1070 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1071                                 struct pp_power_state  *prequest_ps,
1072                         const struct pp_power_state *pcurrent_ps)
1073 {
1074         struct cz_power_state *cz_ps =
1075                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1076
1077         const struct cz_power_state *cz_current_ps =
1078                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1079
1080         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1081         struct PP_Clocks clocks = {0, 0, 0, 0};
1082         bool force_high;
1083         uint32_t  num_of_active_displays = 0;
1084         struct cgs_display_info info = {0};
1085
1086         cz_ps->need_dfs_bypass = true;
1087
1088         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1089
1090         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1091                                 hwmgr->display_config.min_mem_set_clock :
1092                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1093
1094         cgs_get_active_displays_info(hwmgr->device, &info);
1095         num_of_active_displays = info.display_count;
1096
1097         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1098                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1099
1100         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1101                         || (num_of_active_displays >= 3);
1102
1103         cz_ps->action = cz_current_ps->action;
1104
1105         if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1106                 cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
1107         else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
1108                 cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
1109         else if (!force_high && (cz_ps->action == FORCE_HIGH))
1110                 cz_ps->action = CANCEL_FORCE_HIGH;
1111         else if (force_high && (cz_ps->action != FORCE_HIGH))
1112                 cz_ps->action = FORCE_HIGH;
1113         else
1114                 cz_ps->action = DO_NOTHING;
1115
1116         return 0;
1117 }
1118
1119 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1120 {
1121         int result = 0;
1122         struct cz_hwmgr *data;
1123
1124         data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1125         if (data == NULL)
1126                 return -ENOMEM;
1127
1128         hwmgr->backend = data;
1129
1130         result = cz_initialize_dpm_defaults(hwmgr);
1131         if (result != 0) {
1132                 pr_err("cz_initialize_dpm_defaults failed\n");
1133                 return result;
1134         }
1135
1136         result = cz_get_system_info_data(hwmgr);
1137         if (result != 0) {
1138                 pr_err("cz_get_system_info_data failed\n");
1139                 return result;
1140         }
1141
1142         cz_construct_boot_state(hwmgr);
1143
1144         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1145
1146         return result;
1147 }
1148
1149 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1150 {
1151         if (hwmgr != NULL) {
1152                 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
1153                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1154
1155                 kfree(hwmgr->backend);
1156                 hwmgr->backend = NULL;
1157         }
1158         return 0;
1159 }
1160
1161 static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1162 {
1163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1164
1165         smum_send_msg_to_smc_with_parameter(hwmgr,
1166                                         PPSMC_MSG_SetSclkSoftMin,
1167                                         cz_get_sclk_level(hwmgr,
1168                                         cz_hwmgr->sclk_dpm.soft_max_clk,
1169                                         PPSMC_MSG_SetSclkSoftMin));
1170
1171         smum_send_msg_to_smc_with_parameter(hwmgr,
1172                                 PPSMC_MSG_SetSclkSoftMax,
1173                                 cz_get_sclk_level(hwmgr,
1174                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1175                                 PPSMC_MSG_SetSclkSoftMax));
1176
1177         return 0;
1178 }
1179
1180 static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1181 {
1182         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1183         struct phm_clock_voltage_dependency_table *table =
1184                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1185         unsigned long clock = 0, level;
1186
1187         if (NULL == table || table->count <= 0)
1188                 return -EINVAL;
1189
1190         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1191         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1192
1193         level = cz_get_max_sclk_level(hwmgr) - 1;
1194
1195         if (level < table->count)
1196                 clock = table->entries[level].clk;
1197         else
1198                 clock = table->entries[table->count - 1].clk;
1199
1200         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1201         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1202
1203         smum_send_msg_to_smc_with_parameter(hwmgr,
1204                                 PPSMC_MSG_SetSclkSoftMin,
1205                                 cz_get_sclk_level(hwmgr,
1206                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1207                                 PPSMC_MSG_SetSclkSoftMin));
1208
1209         smum_send_msg_to_smc_with_parameter(hwmgr,
1210                                 PPSMC_MSG_SetSclkSoftMax,
1211                                 cz_get_sclk_level(hwmgr,
1212                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1213                                 PPSMC_MSG_SetSclkSoftMax));
1214
1215         return 0;
1216 }
1217
1218 static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1219 {
1220         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1221
1222         smum_send_msg_to_smc_with_parameter(hwmgr,
1223                         PPSMC_MSG_SetSclkSoftMax,
1224                         cz_get_sclk_level(hwmgr,
1225                         cz_hwmgr->sclk_dpm.soft_min_clk,
1226                         PPSMC_MSG_SetSclkSoftMax));
1227
1228         smum_send_msg_to_smc_with_parameter(hwmgr,
1229                                 PPSMC_MSG_SetSclkSoftMin,
1230                                 cz_get_sclk_level(hwmgr,
1231                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1232                                 PPSMC_MSG_SetSclkSoftMin));
1233
1234         return 0;
1235 }
1236
1237 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1238                                 enum amd_dpm_forced_level level)
1239 {
1240         int ret = 0;
1241
1242         switch (level) {
1243         case AMD_DPM_FORCED_LEVEL_HIGH:
1244         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1245                 ret = cz_phm_force_dpm_highest(hwmgr);
1246                 break;
1247         case AMD_DPM_FORCED_LEVEL_LOW:
1248         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1249         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1250                 ret = cz_phm_force_dpm_lowest(hwmgr);
1251                 break;
1252         case AMD_DPM_FORCED_LEVEL_AUTO:
1253                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1254                 break;
1255         case AMD_DPM_FORCED_LEVEL_MANUAL:
1256         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1257         default:
1258                 break;
1259         }
1260
1261         return ret;
1262 }
1263
1264 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1265 {
1266         if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
1267                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
1268         return 0;
1269 }
1270
1271 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1272 {
1273         if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
1274                 return smum_send_msg_to_smc_with_parameter(
1275                         hwmgr,
1276                         PPSMC_MSG_UVDPowerON,
1277                         PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0);
1278         }
1279
1280         return 0;
1281 }
1282
1283 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1284 {
1285         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1286         struct phm_uvd_clock_voltage_dependency_table *ptable =
1287                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1288
1289         if (!bgate) {
1290                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1291                 if (PP_CAP(PHM_PlatformCaps_StablePState) ||
1292                     hwmgr->en_umd_pstate) {
1293                         cz_hwmgr->uvd_dpm.hard_min_clk =
1294                                    ptable->entries[ptable->count - 1].vclk;
1295
1296                         smum_send_msg_to_smc_with_parameter(hwmgr,
1297                                 PPSMC_MSG_SetUvdHardMin,
1298                                 cz_get_uvd_level(hwmgr,
1299                                         cz_hwmgr->uvd_dpm.hard_min_clk,
1300                                         PPSMC_MSG_SetUvdHardMin));
1301
1302                         cz_enable_disable_uvd_dpm(hwmgr, true);
1303                 } else {
1304                         cz_enable_disable_uvd_dpm(hwmgr, true);
1305                 }
1306         } else {
1307                 cz_enable_disable_uvd_dpm(hwmgr, false);
1308         }
1309
1310         return 0;
1311 }
1312
1313 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1314 {
1315         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1316         struct phm_vce_clock_voltage_dependency_table *ptable =
1317                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1318
1319         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1320         if (PP_CAP(PHM_PlatformCaps_StablePState) ||
1321             hwmgr->en_umd_pstate) {
1322                 cz_hwmgr->vce_dpm.hard_min_clk =
1323                                   ptable->entries[ptable->count - 1].ecclk;
1324
1325                 smum_send_msg_to_smc_with_parameter(hwmgr,
1326                         PPSMC_MSG_SetEclkHardMin,
1327                         cz_get_eclk_level(hwmgr,
1328                                 cz_hwmgr->vce_dpm.hard_min_clk,
1329                                 PPSMC_MSG_SetEclkHardMin));
1330         } else {
1331
1332                 smum_send_msg_to_smc_with_parameter(hwmgr,
1333                                         PPSMC_MSG_SetEclkHardMin, 0);
1334                 /* disable ECLK DPM 0. Otherwise VCE could hang if
1335                  * switching SCLK from DPM 0 to 6/7 */
1336                 smum_send_msg_to_smc_with_parameter(hwmgr,
1337                                         PPSMC_MSG_SetEclkSoftMin, 1);
1338         }
1339         return 0;
1340 }
1341
1342 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1343 {
1344         if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
1345                 return smum_send_msg_to_smc(hwmgr,
1346                                                      PPSMC_MSG_VCEPowerOFF);
1347         return 0;
1348 }
1349
1350 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1351 {
1352         if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
1353                 return smum_send_msg_to_smc(hwmgr,
1354                                                      PPSMC_MSG_VCEPowerON);
1355         return 0;
1356 }
1357
1358 static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1359 {
1360         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1361
1362         return cz_hwmgr->sys_info.bootup_uma_clock;
1363 }
1364
1365 static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1366 {
1367         struct pp_power_state  *ps;
1368         struct cz_power_state  *cz_ps;
1369
1370         if (hwmgr == NULL)
1371                 return -EINVAL;
1372
1373         ps = hwmgr->request_ps;
1374
1375         if (ps == NULL)
1376                 return -EINVAL;
1377
1378         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1379
1380         if (low)
1381                 return cz_ps->levels[0].engineClock;
1382         else
1383                 return cz_ps->levels[cz_ps->level-1].engineClock;
1384 }
1385
1386 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1387                                         struct pp_hw_power_state *hw_ps)
1388 {
1389         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1390         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1391
1392         cz_ps->level = 1;
1393         cz_ps->nbps_flags = 0;
1394         cz_ps->bapm_flags = 0;
1395         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1396
1397         return 0;
1398 }
1399
1400 static int cz_dpm_get_pp_table_entry_callback(
1401                                                      struct pp_hwmgr *hwmgr,
1402                                            struct pp_hw_power_state *hw_ps,
1403                                                           unsigned int index,
1404                                                      const void *clock_info)
1405 {
1406         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1407
1408         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1409
1410         struct phm_clock_voltage_dependency_table *table =
1411                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1412         uint8_t clock_info_index = cz_clock_info->index;
1413
1414         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1415                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1416
1417         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1418         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1419
1420         cz_ps->level = index + 1;
1421
1422         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1423                 cz_ps->levels[index].dsDividerIndex = 5;
1424                 cz_ps->levels[index].ssDividerIndex = 5;
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1431 {
1432         int result;
1433         unsigned long ret = 0;
1434
1435         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1436
1437         return result ? 0 : ret;
1438 }
1439
1440 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1441                     unsigned long entry, struct pp_power_state *ps)
1442 {
1443         int result;
1444         struct cz_power_state *cz_ps;
1445
1446         ps->hardware.magic = PhwCz_Magic;
1447
1448         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1449
1450         result = pp_tables_get_entry(hwmgr, entry, ps,
1451                         cz_dpm_get_pp_table_entry_callback);
1452
1453         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1454         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1455
1456         return result;
1457 }
1458
1459 static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1460 {
1461         return sizeof(struct cz_power_state);
1462 }
1463
1464 static void cz_hw_print_display_cfg(
1465         const struct cc6_settings *cc6_settings)
1466 {
1467         PP_DBG_LOG("New Display Configuration:\n");
1468
1469         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1470                         cc6_settings->cpu_cc6_disable);
1471         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1472                         cc6_settings->cpu_pstate_disable);
1473         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1474                         cc6_settings->nb_pstate_switch_disable);
1475         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1476                         cc6_settings->cpu_pstate_separation_time);
1477 }
1478
1479  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1480 {
1481         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1482         uint32_t data = 0;
1483
1484         if (hw_data->cc6_settings.cc6_setting_changed) {
1485
1486                 hw_data->cc6_settings.cc6_setting_changed = false;
1487
1488                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1489
1490                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1491                         & PWRMGT_SEPARATION_TIME_MASK)
1492                         << PWRMGT_SEPARATION_TIME_SHIFT;
1493
1494                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1495                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1496
1497                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1498                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1499
1500                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1501                         data);
1502
1503                 smum_send_msg_to_smc_with_parameter(hwmgr,
1504                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1505                                                 data);
1506         }
1507
1508         return 0;
1509 }
1510
1511
1512 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1513                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1514 {
1515         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1516
1517         if (separation_time !=
1518             hw_data->cc6_settings.cpu_pstate_separation_time ||
1519             cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1520             pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1521             pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1522
1523                 hw_data->cc6_settings.cc6_setting_changed = true;
1524
1525                 hw_data->cc6_settings.cpu_pstate_separation_time =
1526                         separation_time;
1527                 hw_data->cc6_settings.cpu_cc6_disable =
1528                         cc6_disable;
1529                 hw_data->cc6_settings.cpu_pstate_disable =
1530                         pstate_disable;
1531                 hw_data->cc6_settings.nb_pstate_switch_disable =
1532                         pstate_switch_disable;
1533
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1540                 struct amd_pp_simple_clock_info *info)
1541 {
1542         uint32_t i;
1543         const struct phm_clock_voltage_dependency_table *table =
1544                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1545         const struct phm_clock_and_voltage_limits *limits =
1546                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1547
1548         info->engine_max_clock = limits->sclk;
1549         info->memory_max_clock = limits->mclk;
1550
1551         for (i = table->count - 1; i > 0; i--) {
1552                 if (limits->vddc >= table->entries[i].v) {
1553                         info->level = table->entries[i].clk;
1554                         return 0;
1555                 }
1556         }
1557         return -EINVAL;
1558 }
1559
1560 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1561                 enum pp_clock_type type, uint32_t mask)
1562 {
1563         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1564                 return -EINVAL;
1565
1566         switch (type) {
1567         case PP_SCLK:
1568                 smum_send_msg_to_smc_with_parameter(hwmgr,
1569                                 PPSMC_MSG_SetSclkSoftMin,
1570                                 mask);
1571                 smum_send_msg_to_smc_with_parameter(hwmgr,
1572                                 PPSMC_MSG_SetSclkSoftMax,
1573                                 mask);
1574                 break;
1575         default:
1576                 break;
1577         }
1578
1579         return 0;
1580 }
1581
1582 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1583                 enum pp_clock_type type, char *buf)
1584 {
1585         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1586         struct phm_clock_voltage_dependency_table *sclk_table =
1587                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1588         int i, now, size = 0;
1589
1590         switch (type) {
1591         case PP_SCLK:
1592                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1593                                 CGS_IND_REG__SMC,
1594                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1595                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1596                                 CURR_SCLK_INDEX);
1597
1598                 for (i = 0; i < sclk_table->count; i++)
1599                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1600                                         i, sclk_table->entries[i].clk / 100,
1601                                         (i == now) ? "*" : "");
1602                 break;
1603         case PP_MCLK:
1604                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1605                                 CGS_IND_REG__SMC,
1606                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1607                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1608                                 CURR_MCLK_INDEX);
1609
1610                 for (i = CZ_NUM_NBPMEMORYCLOCK; i > 0; i--)
1611                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1612                                         CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
1613                                         (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
1614                 break;
1615         default:
1616                 break;
1617         }
1618         return size;
1619 }
1620
1621 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1622                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1623                                 PHM_PerformanceLevel *level)
1624 {
1625         const struct cz_power_state *ps;
1626         struct cz_hwmgr *data;
1627         uint32_t level_index;
1628         uint32_t i;
1629
1630         if (level == NULL || hwmgr == NULL || state == NULL)
1631                 return -EINVAL;
1632
1633         data = (struct cz_hwmgr *)(hwmgr->backend);
1634         ps = cast_const_PhwCzPowerState(state);
1635
1636         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1637         level->coreClock = ps->levels[level_index].engineClock;
1638
1639         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1640                 for (i = 1; i < ps->level; i++) {
1641                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1642                                 level->coreClock = ps->levels[i].engineClock;
1643                                 break;
1644                         }
1645                 }
1646         }
1647
1648         if (level_index == 0)
1649                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1650         else
1651                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1652
1653         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1654         level->nonLocalMemoryFreq = 0;
1655         level->nonLocalMemoryWidth = 0;
1656
1657         return 0;
1658 }
1659
1660 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1661         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1662 {
1663         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1664
1665         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1666         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1667
1668         return 0;
1669 }
1670
1671 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1672                                                 struct amd_pp_clocks *clocks)
1673 {
1674         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1675         int i;
1676         struct phm_clock_voltage_dependency_table *table;
1677
1678         clocks->count = cz_get_max_sclk_level(hwmgr);
1679         switch (type) {
1680         case amd_pp_disp_clock:
1681                 for (i = 0; i < clocks->count; i++)
1682                         clocks->clock[i] = data->sys_info.display_clock[i];
1683                 break;
1684         case amd_pp_sys_clock:
1685                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1686                 for (i = 0; i < clocks->count; i++)
1687                         clocks->clock[i] = table->entries[i].clk;
1688                 break;
1689         case amd_pp_mem_clock:
1690                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1691                 for (i = 0; i < clocks->count; i++)
1692                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1693                 break;
1694         default:
1695                 return -1;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1702 {
1703         struct phm_clock_voltage_dependency_table *table =
1704                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1705         unsigned long level;
1706         const struct phm_clock_and_voltage_limits *limits =
1707                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1708
1709         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1710                 return -EINVAL;
1711
1712         level = cz_get_max_sclk_level(hwmgr) - 1;
1713
1714         if (level < table->count)
1715                 clocks->engine_max_clock = table->entries[level].clk;
1716         else
1717                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1718
1719         clocks->memory_max_clock = limits->mclk;
1720
1721         return 0;
1722 }
1723
1724 static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1725 {
1726         int actual_temp = 0;
1727         uint32_t val = cgs_read_ind_register(hwmgr->device,
1728                                              CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1729         uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1730
1731         if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1732                 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1733         else
1734                 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1735
1736         return actual_temp;
1737 }
1738
1739 static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1740                           void *value, int *size)
1741 {
1742         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1743
1744         struct phm_clock_voltage_dependency_table *table =
1745                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1746
1747         struct phm_vce_clock_voltage_dependency_table *vce_table =
1748                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1749
1750         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1751                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1752
1753         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1754                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1755         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1756                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1757         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1758                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1759
1760         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1761         uint16_t vddnb, vddgfx;
1762         int result;
1763
1764         /* size must be at least 4 bytes for all sensors */
1765         if (*size < 4)
1766                 return -EINVAL;
1767         *size = 4;
1768
1769         switch (idx) {
1770         case AMDGPU_PP_SENSOR_GFX_SCLK:
1771                 if (sclk_index < NUM_SCLK_LEVELS) {
1772                         sclk = table->entries[sclk_index].clk;
1773                         *((uint32_t *)value) = sclk;
1774                         return 0;
1775                 }
1776                 return -EINVAL;
1777         case AMDGPU_PP_SENSOR_VDDNB:
1778                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1779                         CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1780                 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1781                 *((uint32_t *)value) = vddnb;
1782                 return 0;
1783         case AMDGPU_PP_SENSOR_VDDGFX:
1784                 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1785                         CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1786                 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1787                 *((uint32_t *)value) = vddgfx;
1788                 return 0;
1789         case AMDGPU_PP_SENSOR_UVD_VCLK:
1790                 if (!cz_hwmgr->uvd_power_gated) {
1791                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1792                                 return -EINVAL;
1793                         } else {
1794                                 vclk = uvd_table->entries[uvd_index].vclk;
1795                                 *((uint32_t *)value) = vclk;
1796                                 return 0;
1797                         }
1798                 }
1799                 *((uint32_t *)value) = 0;
1800                 return 0;
1801         case AMDGPU_PP_SENSOR_UVD_DCLK:
1802                 if (!cz_hwmgr->uvd_power_gated) {
1803                         if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1804                                 return -EINVAL;
1805                         } else {
1806                                 dclk = uvd_table->entries[uvd_index].dclk;
1807                                 *((uint32_t *)value) = dclk;
1808                                 return 0;
1809                         }
1810                 }
1811                 *((uint32_t *)value) = 0;
1812                 return 0;
1813         case AMDGPU_PP_SENSOR_VCE_ECCLK:
1814                 if (!cz_hwmgr->vce_power_gated) {
1815                         if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1816                                 return -EINVAL;
1817                         } else {
1818                                 ecclk = vce_table->entries[vce_index].ecclk;
1819                                 *((uint32_t *)value) = ecclk;
1820                                 return 0;
1821                         }
1822                 }
1823                 *((uint32_t *)value) = 0;
1824                 return 0;
1825         case AMDGPU_PP_SENSOR_GPU_LOAD:
1826                 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
1827                 if (0 == result) {
1828                         activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1829                         activity_percent = activity_percent > 100 ? 100 : activity_percent;
1830                 } else {
1831                         activity_percent = 50;
1832                 }
1833                 *((uint32_t *)value) = activity_percent;
1834                 return 0;
1835         case AMDGPU_PP_SENSOR_UVD_POWER:
1836                 *((uint32_t *)value) = cz_hwmgr->uvd_power_gated ? 0 : 1;
1837                 return 0;
1838         case AMDGPU_PP_SENSOR_VCE_POWER:
1839                 *((uint32_t *)value) = cz_hwmgr->vce_power_gated ? 0 : 1;
1840                 return 0;
1841         case AMDGPU_PP_SENSOR_GPU_TEMP:
1842                 *((uint32_t *)value) = cz_thermal_get_temperature(hwmgr);
1843                 return 0;
1844         default:
1845                 return -EINVAL;
1846         }
1847 }
1848
1849 static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
1850                                         uint32_t virtual_addr_low,
1851                                         uint32_t virtual_addr_hi,
1852                                         uint32_t mc_addr_low,
1853                                         uint32_t mc_addr_hi,
1854                                         uint32_t size)
1855 {
1856         smum_send_msg_to_smc_with_parameter(hwmgr,
1857                                         PPSMC_MSG_DramAddrHiVirtual,
1858                                         mc_addr_hi);
1859         smum_send_msg_to_smc_with_parameter(hwmgr,
1860                                         PPSMC_MSG_DramAddrLoVirtual,
1861                                         mc_addr_low);
1862         smum_send_msg_to_smc_with_parameter(hwmgr,
1863                                         PPSMC_MSG_DramAddrHiPhysical,
1864                                         virtual_addr_hi);
1865         smum_send_msg_to_smc_with_parameter(hwmgr,
1866                                         PPSMC_MSG_DramAddrLoPhysical,
1867                                         virtual_addr_low);
1868
1869         smum_send_msg_to_smc_with_parameter(hwmgr,
1870                                         PPSMC_MSG_DramBufferSize,
1871                                         size);
1872         return 0;
1873 }
1874
1875 static int cz_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
1876                 struct PP_TemperatureRange *thermal_data)
1877 {
1878         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1879
1880         memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
1881
1882         thermal_data->max = (cz_hwmgr->thermal_auto_throttling_treshold +
1883                         cz_hwmgr->sys_info.htc_hyst_lmt) *
1884                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1885
1886         return 0;
1887 }
1888
1889 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1890         .backend_init = cz_hwmgr_backend_init,
1891         .backend_fini = cz_hwmgr_backend_fini,
1892         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1893         .force_dpm_level = cz_dpm_force_dpm_level,
1894         .get_power_state_size = cz_get_power_state_size,
1895         .powerdown_uvd = cz_dpm_powerdown_uvd,
1896         .powergate_uvd = cz_dpm_powergate_uvd,
1897         .powergate_vce = cz_dpm_powergate_vce,
1898         .get_mclk = cz_dpm_get_mclk,
1899         .get_sclk = cz_dpm_get_sclk,
1900         .patch_boot_state = cz_dpm_patch_boot_state,
1901         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1902         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1903         .set_cpu_power_state = cz_set_cpu_power_state,
1904         .store_cc6_data = cz_store_cc6_data,
1905         .force_clock_level = cz_force_clock_level,
1906         .print_clock_levels = cz_print_clock_levels,
1907         .get_dal_power_level = cz_get_dal_power_level,
1908         .get_performance_level = cz_get_performance_level,
1909         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1910         .get_clock_by_type = cz_get_clock_by_type,
1911         .get_max_high_clocks = cz_get_max_high_clocks,
1912         .get_temperature = cz_thermal_get_temperature,
1913         .read_sensor = cz_read_sensor,
1914         .power_off_asic = cz_power_off_asic,
1915         .asic_setup = cz_setup_asic_task,
1916         .dynamic_state_management_enable = cz_enable_dpm_tasks,
1917         .power_state_set = cz_set_power_state_tasks,
1918         .dynamic_state_management_disable = cz_disable_dpm_tasks,
1919         .notify_cac_buffer_info = cz_notify_cac_buffer_info,
1920         .get_thermal_temperature_range = cz_get_thermal_temperature_range,
1921 };
1922
1923 int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
1924 {
1925         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1926         hwmgr->pptable_func = &pptable_funcs;
1927         return 0;
1928 }