drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  85         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  86         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  87         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  88         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  89         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  90         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  91         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  92         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  93         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  94         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  95         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  96         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  97         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  98         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  99         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 100         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 101         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 102         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 103         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 104         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 105         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 108         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 109         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 110         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 111         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 112         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 113         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 114         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 115         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 116         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 117         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 118         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 119         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 120         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 121         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 122         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 123         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 124         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 125         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 126         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 127         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 128         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 129         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 130         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 131         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 132         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 133         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 134         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 135         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 136         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 137         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 138         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 139         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 140         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 141         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 142         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 143         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 144         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 145 };
 146
 147 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 148         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 149         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 150         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 151         CLK_MAP(FCLK, PPCLK_FCLK),
 152         CLK_MAP(UCLK, PPCLK_UCLK),
 153         CLK_MAP(MCLK, PPCLK_UCLK),
 154         CLK_MAP(DCLK, PPCLK_DCLK),
 155         CLK_MAP(VCLK, PPCLK_VCLK),
 156 };
 157
 158 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 159         FEA_MAP(DPM_PREFETCHER),
 160         FEA_MAP(DPM_GFXCLK),
 161         FEA_MAP(DPM_UCLK),
 162         FEA_MAP(DPM_SOCCLK),
 163         FEA_MAP(DPM_FCLK),
 164         FEA_MAP(DPM_MP0CLK),
 165         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 166         FEA_MAP(DS_GFXCLK),
 167         FEA_MAP(DS_SOCCLK),
 168         FEA_MAP(DS_LCLK),
 169         FEA_MAP(DS_FCLK),
 170         FEA_MAP(DS_UCLK),
 171         FEA_MAP(GFX_ULV),
 172         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 173         FEA_MAP(RSMU_SMN_CG),
 174         FEA_MAP(WAFL_CG),
 175         FEA_MAP(PPT),
 176         FEA_MAP(TDC),
 177         FEA_MAP(APCC_PLUS),
 178         FEA_MAP(VR0HOT),
 179         FEA_MAP(VR1HOT),
 180         FEA_MAP(FW_CTF),
 181         FEA_MAP(FAN_CONTROL),
 182         FEA_MAP(THERMAL),
 183         FEA_MAP(OUT_OF_BAND_MONITOR),
 184         FEA_MAP(TEMP_DEPENDENT_VMIN),
 185 };
 186
 187 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 188         TAB_MAP(PPTABLE),
 189         TAB_MAP(AVFS),
 190         TAB_MAP(AVFS_PSM_DEBUG),
 191         TAB_MAP(AVFS_FUSE_OVERRIDE),
 192         TAB_MAP(PMSTATUSLOG),
 193         TAB_MAP(SMU_METRICS),
 194         TAB_MAP(DRIVER_SMU_CONFIG),
 195         TAB_MAP(OVERDRIVE),
 196         TAB_MAP(I2C_COMMANDS),
 197         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 198 };
 199
 200 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 201         PWR_MAP(AC),
 202         PWR_MAP(DC),
 203 };
 204
 205 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 211 };
 212
 213 static int arcturus_tables_init(struct smu_context *smu)
 214 {
 215         struct smu_table_context *smu_table = &smu->smu_table;
 216         struct smu_table *tables = smu_table->tables;
 217
 218         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 219                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 220
 221         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 222                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 223
 224         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 225                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 226
 227         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 228                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 229
 230         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 231                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 232                        AMDGPU_GEM_DOMAIN_VRAM);
 233
 234         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 235         if (!smu_table->metrics_table)
 236                 return -ENOMEM;
 237         smu_table->metrics_time = 0;
 238
 239         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 240         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 241         if (!smu_table->gpu_metrics_table) {
 242                 kfree(smu_table->metrics_table);
 243                 return -ENOMEM;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 250 {
 251         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 252
 253         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 254                                        GFP_KERNEL);
 255         if (!smu_dpm->dpm_context)
 256                 return -ENOMEM;
 257         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 258
 259         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 260                                        GFP_KERNEL);
 261         if (!smu_dpm->dpm_current_power_state)
 262                 return -ENOMEM;
 263
 264         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 265                                        GFP_KERNEL);
 266         if (!smu_dpm->dpm_request_power_state)
 267                 return -ENOMEM;
 268
 269         return 0;
 270 }
 271
 272 static int arcturus_init_smc_tables(struct smu_context *smu)
 273 {
 274         int ret = 0;
 275
 276         ret = arcturus_tables_init(smu);
 277         if (ret)
 278                 return ret;
 279
 280         ret = arcturus_allocate_dpm_context(smu);
 281         if (ret)
 282                 return ret;
 283
 284         return smu_v11_0_init_smc_tables(smu);
 285 }
 286
 287 static int
 288 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 289                                   uint32_t *feature_mask, uint32_t num)
 290 {
 291         if (num > 2)
 292                 return -EINVAL;
 293
 294         /* pptable will handle the features to enable */
 295         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 296
 297         return 0;
 298 }
 299
 300 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 301 {
 302         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 303         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 304         struct smu_11_0_dpm_table *dpm_table = NULL;
 305         int ret = 0;
 306
 307         /* socclk dpm table setup */
 308         dpm_table = &dpm_context->dpm_tables.soc_table;
 309         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 310                 ret = smu_v11_0_set_single_dpm_table(smu,
 311                                                      SMU_SOCCLK,
 312                                                      dpm_table);
 313                 if (ret)
 314                         return ret;
 315                 dpm_table->is_fine_grained =
 316                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 317         } else {
 318                 dpm_table->count = 1;
 319                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 320                 dpm_table->dpm_levels[0].enabled = true;
 321                 dpm_table->min = dpm_table->dpm_levels[0].value;
 322                 dpm_table->max = dpm_table->dpm_levels[0].value;
 323         }
 324
 325         /* gfxclk dpm table setup */
 326         dpm_table = &dpm_context->dpm_tables.gfx_table;
 327         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 328                 ret = smu_v11_0_set_single_dpm_table(smu,
 329                                                      SMU_GFXCLK,
 330                                                      dpm_table);
 331                 if (ret)
 332                         return ret;
 333                 dpm_table->is_fine_grained =
 334                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 335         } else {
 336                 dpm_table->count = 1;
 337                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 338                 dpm_table->dpm_levels[0].enabled = true;
 339                 dpm_table->min = dpm_table->dpm_levels[0].value;
 340                 dpm_table->max = dpm_table->dpm_levels[0].value;
 341         }
 342
 343         /* memclk dpm table setup */
 344         dpm_table = &dpm_context->dpm_tables.uclk_table;
 345         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 346                 ret = smu_v11_0_set_single_dpm_table(smu,
 347                                                      SMU_UCLK,
 348                                                      dpm_table);
 349                 if (ret)
 350                         return ret;
 351                 dpm_table->is_fine_grained =
 352                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 353         } else {
 354                 dpm_table->count = 1;
 355                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 356                 dpm_table->dpm_levels[0].enabled = true;
 357                 dpm_table->min = dpm_table->dpm_levels[0].value;
 358                 dpm_table->max = dpm_table->dpm_levels[0].value;
 359         }
 360
 361         /* fclk dpm table setup */
 362         dpm_table = &dpm_context->dpm_tables.fclk_table;
 363         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 364                 ret = smu_v11_0_set_single_dpm_table(smu,
 365                                                      SMU_FCLK,
 366                                                      dpm_table);
 367                 if (ret)
 368                         return ret;
 369                 dpm_table->is_fine_grained =
 370                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 371         } else {
 372                 dpm_table->count = 1;
 373                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 374                 dpm_table->dpm_levels[0].enabled = true;
 375                 dpm_table->min = dpm_table->dpm_levels[0].value;
 376                 dpm_table->max = dpm_table->dpm_levels[0].value;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int arcturus_check_powerplay_table(struct smu_context *smu)
 383 {
 384         struct smu_table_context *table_context = &smu->smu_table;
 385         struct smu_11_0_powerplay_table *powerplay_table =
 386                 table_context->power_play_table;
 387         struct smu_baco_context *smu_baco = &smu->smu_baco;
 388
 389         mutex_lock(&smu_baco->mutex);
 390         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 391             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 392                 smu_baco->platform_support = true;
 393         mutex_unlock(&smu_baco->mutex);
 394
 395         table_context->thermal_controller_type =
 396                 powerplay_table->thermal_controller_type;
 397
 398         return 0;
 399 }
 400
 401 static int arcturus_store_powerplay_table(struct smu_context *smu)
 402 {
 403         struct smu_table_context *table_context = &smu->smu_table;
 404         struct smu_11_0_powerplay_table *powerplay_table =
 405                 table_context->power_play_table;
 406
 407         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 408                sizeof(PPTable_t));
 409
 410         return 0;
 411 }
 412
 413 static int arcturus_append_powerplay_table(struct smu_context *smu)
 414 {
 415         struct smu_table_context *table_context = &smu->smu_table;
 416         PPTable_t *smc_pptable = table_context->driver_pptable;
 417         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 418         int index, ret;
 419
 420         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 421                                            smc_dpm_info);
 422
 423         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 424                                       (uint8_t **)&smc_dpm_table);
 425         if (ret)
 426                 return ret;
 427
 428         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 429                         smc_dpm_table->table_header.format_revision,
 430                         smc_dpm_table->table_header.content_revision);
 431
 432         if ((smc_dpm_table->table_header.format_revision == 4) &&
 433             (smc_dpm_table->table_header.content_revision == 6))
 434                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 435                        &smc_dpm_table->maxvoltagestepgfx,
 436                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 437
 438         return 0;
 439 }
 440
 441 static int arcturus_setup_pptable(struct smu_context *smu)
 442 {
 443         int ret = 0;
 444
 445         ret = smu_v11_0_setup_pptable(smu);
 446         if (ret)
 447                 return ret;
 448
 449         ret = arcturus_store_powerplay_table(smu);
 450         if (ret)
 451                 return ret;
 452
 453         ret = arcturus_append_powerplay_table(smu);
 454         if (ret)
 455                 return ret;
 456
 457         ret = arcturus_check_powerplay_table(smu);
 458         if (ret)
 459                 return ret;
 460
 461         return ret;
 462 }
 463
 464 static int arcturus_run_btc(struct smu_context *smu)
 465 {
 466         int ret = 0;
 467
 468         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 469         if (ret) {
 470                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 471                 return ret;
 472         }
 473
 474         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 475 }
 476
 477 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 478 {
 479         struct smu_11_0_dpm_context *dpm_context =
 480                                 smu->smu_dpm.dpm_context;
 481         struct smu_11_0_dpm_table *gfx_table =
 482                                 &dpm_context->dpm_tables.gfx_table;
 483         struct smu_11_0_dpm_table *mem_table =
 484                                 &dpm_context->dpm_tables.uclk_table;
 485         struct smu_11_0_dpm_table *soc_table =
 486                                 &dpm_context->dpm_tables.soc_table;
 487         struct smu_umd_pstate_table *pstate_table =
 488                                 &smu->pstate_table;
 489
 490         pstate_table->gfxclk_pstate.min = gfx_table->min;
 491         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 492
 493         pstate_table->uclk_pstate.min = mem_table->min;
 494         pstate_table->uclk_pstate.peak = mem_table->max;
 495
 496         pstate_table->socclk_pstate.min = soc_table->min;
 497         pstate_table->socclk_pstate.peak = soc_table->max;
 498
 499         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 500             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 501             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 502                 pstate_table->gfxclk_pstate.standard =
 503                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 504                 pstate_table->uclk_pstate.standard =
 505                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 506                 pstate_table->socclk_pstate.standard =
 507                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 508         } else {
 509                 pstate_table->gfxclk_pstate.standard =
 510                         pstate_table->gfxclk_pstate.min;
 511                 pstate_table->uclk_pstate.standard =
 512                         pstate_table->uclk_pstate.min;
 513                 pstate_table->socclk_pstate.standard =
 514                         pstate_table->socclk_pstate.min;
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int arcturus_get_clk_table(struct smu_context *smu,
 521                         struct pp_clock_levels_with_latency *clocks,
 522                         struct smu_11_0_dpm_table *dpm_table)
 523 {
 524         int i, count;
 525
 526         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 527         clocks->num_levels = count;
 528
 529         for (i = 0; i < count; i++) {
 530                 clocks->data[i].clocks_in_khz =
 531                         dpm_table->dpm_levels[i].value * 1000;
 532                 clocks->data[i].latency_in_us = 0;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int arcturus_freqs_in_same_level(int32_t frequency1,
 539                                         int32_t frequency2)
 540 {
 541         return (abs(frequency1 - frequency2) <= EPSILON);
 542 }
 543
 544 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 545                                          MetricsMember_t member,
 546                                          uint32_t *value)
 547 {
 548         struct smu_table_context *smu_table= &smu->smu_table;
 549         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 550         int ret = 0;
 551
 552         mutex_lock(&smu->metrics_lock);
 553
 554         ret = smu_cmn_get_metrics_table_locked(smu,
 555                                                NULL,
 556                                                false);
 557         if (ret) {
 558                 mutex_unlock(&smu->metrics_lock);
 559                 return ret;
 560         }
 561
 562         switch (member) {
 563         case METRICS_CURR_GFXCLK:
 564                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 565                 break;
 566         case METRICS_CURR_SOCCLK:
 567                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 568                 break;
 569         case METRICS_CURR_UCLK:
 570                 *value = metrics->CurrClock[PPCLK_UCLK];
 571                 break;
 572         case METRICS_CURR_VCLK:
 573                 *value = metrics->CurrClock[PPCLK_VCLK];
 574                 break;
 575         case METRICS_CURR_DCLK:
 576                 *value = metrics->CurrClock[PPCLK_DCLK];
 577                 break;
 578         case METRICS_CURR_FCLK:
 579                 *value = metrics->CurrClock[PPCLK_FCLK];
 580                 break;
 581         case METRICS_AVERAGE_GFXCLK:
 582                 *value = metrics->AverageGfxclkFrequency;
 583                 break;
 584         case METRICS_AVERAGE_SOCCLK:
 585                 *value = metrics->AverageSocclkFrequency;
 586                 break;
 587         case METRICS_AVERAGE_UCLK:
 588                 *value = metrics->AverageUclkFrequency;
 589                 break;
 590         case METRICS_AVERAGE_VCLK:
 591                 *value = metrics->AverageVclkFrequency;
 592                 break;
 593         case METRICS_AVERAGE_DCLK:
 594                 *value = metrics->AverageDclkFrequency;
 595                 break;
 596         case METRICS_AVERAGE_GFXACTIVITY:
 597                 *value = metrics->AverageGfxActivity;
 598                 break;
 599         case METRICS_AVERAGE_MEMACTIVITY:
 600                 *value = metrics->AverageUclkActivity;
 601                 break;
 602         case METRICS_AVERAGE_VCNACTIVITY:
 603                 *value = metrics->VcnActivityPercentage;
 604                 break;
 605         case METRICS_AVERAGE_SOCKETPOWER:
 606                 *value = metrics->AverageSocketPower << 8;
 607                 break;
 608         case METRICS_TEMPERATURE_EDGE:
 609                 *value = metrics->TemperatureEdge *
 610                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 611                 break;
 612         case METRICS_TEMPERATURE_HOTSPOT:
 613                 *value = metrics->TemperatureHotspot *
 614                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 615                 break;
 616         case METRICS_TEMPERATURE_MEM:
 617                 *value = metrics->TemperatureHBM *
 618                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 619                 break;
 620         case METRICS_TEMPERATURE_VRGFX:
 621                 *value = metrics->TemperatureVrGfx *
 622                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 623                 break;
 624         case METRICS_TEMPERATURE_VRSOC:
 625                 *value = metrics->TemperatureVrSoc *
 626                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 627                 break;
 628         case METRICS_TEMPERATURE_VRMEM:
 629                 *value = metrics->TemperatureVrMem *
 630                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 631                 break;
 632         case METRICS_THROTTLER_STATUS:
 633                 *value = metrics->ThrottlerStatus;
 634                 break;
 635         case METRICS_CURR_FANSPEED:
 636                 *value = metrics->CurrFanSpeed;
 637                 break;
 638         default:
 639                 *value = UINT_MAX;
 640                 break;
 641         }
 642
 643         mutex_unlock(&smu->metrics_lock);
 644
 645         return ret;
 646 }
 647
 648 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 649                                        enum smu_clk_type clk_type,
 650                                        uint32_t *value)
 651 {
 652         MetricsMember_t member_type;
 653         int clk_id = 0;
 654
 655         if (!value)
 656                 return -EINVAL;
 657
 658         clk_id = smu_cmn_to_asic_specific_index(smu,
 659                                                 CMN2ASIC_MAPPING_CLK,
 660                                                 clk_type);
 661         if (clk_id < 0)
 662                 return -EINVAL;
 663
 664         switch (clk_id) {
 665         case PPCLK_GFXCLK:
 666                 /*
 667                  * CurrClock[clk_id] can provide accurate
 668                  *   output only when the dpm feature is enabled.
 669                  * We can use Average_* for dpm disabled case.
 670                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 671                  */
 672                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 673                         member_type = METRICS_CURR_GFXCLK;
 674                 else
 675                         member_type = METRICS_AVERAGE_GFXCLK;
 676                 break;
 677         case PPCLK_UCLK:
 678                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 679                         member_type = METRICS_CURR_UCLK;
 680                 else
 681                         member_type = METRICS_AVERAGE_UCLK;
 682                 break;
 683         case PPCLK_SOCCLK:
 684                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 685                         member_type = METRICS_CURR_SOCCLK;
 686                 else
 687                         member_type = METRICS_AVERAGE_SOCCLK;
 688                 break;
 689         case PPCLK_VCLK:
 690                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 691                         member_type = METRICS_CURR_VCLK;
 692                 else
 693                         member_type = METRICS_AVERAGE_VCLK;
 694                 break;
 695         case PPCLK_DCLK:
 696                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 697                         member_type = METRICS_CURR_DCLK;
 698                 else
 699                         member_type = METRICS_AVERAGE_DCLK;
 700                 break;
 701         case PPCLK_FCLK:
 702                 member_type = METRICS_CURR_FCLK;
 703                 break;
 704         default:
 705                 return -EINVAL;
 706         }
 707
 708         return arcturus_get_smu_metrics_data(smu,
 709                                              member_type,
 710                                              value);
 711 }
 712
 713 static int arcturus_print_clk_levels(struct smu_context *smu,
 714                         enum smu_clk_type type, char *buf)
 715 {
 716         int i, now, size = 0;
 717         int ret = 0;
 718         struct pp_clock_levels_with_latency clocks;
 719         struct smu_11_0_dpm_table *single_dpm_table;
 720         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 721         struct smu_11_0_dpm_context *dpm_context = NULL;
 722
 723         if (amdgpu_ras_intr_triggered())
 724                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 725
 726         dpm_context = smu_dpm->dpm_context;
 727
 728         switch (type) {
 729         case SMU_SCLK:
 730                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 731                 if (ret) {
 732                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 733                         return ret;
 734                 }
 735
 736                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 737                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 738                 if (ret) {
 739                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 740                         return ret;
 741                 }
 742
 743                 /*
 744                  * For DPM disabled case, there will be only one clock level.
 745                  * And it's safe to assume that is always the current clock.
 746                  */
 747                 for (i = 0; i < clocks.num_levels; i++)
 748                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 749                                         clocks.data[i].clocks_in_khz / 1000,
 750                                         (clocks.num_levels == 1) ? "*" :
 751                                         (arcturus_freqs_in_same_level(
 752                                         clocks.data[i].clocks_in_khz / 1000,
 753                                         now) ? "*" : ""));
 754                 break;
 755
 756         case SMU_MCLK:
 757                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 758                 if (ret) {
 759                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 760                         return ret;
 761                 }
 762
 763                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 764                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 765                 if (ret) {
 766                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 767                         return ret;
 768                 }
 769
 770                 for (i = 0; i < clocks.num_levels; i++)
 771                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 772                                 i, clocks.data[i].clocks_in_khz / 1000,
 773                                 (clocks.num_levels == 1) ? "*" :
 774                                 (arcturus_freqs_in_same_level(
 775                                 clocks.data[i].clocks_in_khz / 1000,
 776                                 now) ? "*" : ""));
 777                 break;
 778
 779         case SMU_SOCCLK:
 780                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 781                 if (ret) {
 782                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 783                         return ret;
 784                 }
 785
 786                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 787                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 788                 if (ret) {
 789                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 790                         return ret;
 791                 }
 792
 793                 for (i = 0; i < clocks.num_levels; i++)
 794                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 795                                 i, clocks.data[i].clocks_in_khz / 1000,
 796                                 (clocks.num_levels == 1) ? "*" :
 797                                 (arcturus_freqs_in_same_level(
 798                                 clocks.data[i].clocks_in_khz / 1000,
 799                                 now) ? "*" : ""));
 800                 break;
 801
 802         case SMU_FCLK:
 803                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 804                 if (ret) {
 805                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 806                         return ret;
 807                 }
 808
 809                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 810                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 811                 if (ret) {
 812                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 813                         return ret;
 814                 }
 815
 816                 for (i = 0; i < single_dpm_table->count; i++)
 817                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 818                                 i, single_dpm_table->dpm_levels[i].value,
 819                                 (clocks.num_levels == 1) ? "*" :
 820                                 (arcturus_freqs_in_same_level(
 821                                 clocks.data[i].clocks_in_khz / 1000,
 822                                 now) ? "*" : ""));
 823                 break;
 824
 825         default:
 826                 break;
 827         }
 828
 829         return size;
 830 }
 831
 832 static int arcturus_upload_dpm_level(struct smu_context *smu,
 833                                      bool max,
 834                                      uint32_t feature_mask,
 835                                      uint32_t level)
 836 {
 837         struct smu_11_0_dpm_context *dpm_context =
 838                         smu->smu_dpm.dpm_context;
 839         uint32_t freq;
 840         int ret = 0;
 841
 842         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 843             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 844                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 845                 ret = smu_cmn_send_smc_msg_with_param(smu,
 846                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 847                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 848                         NULL);
 849                 if (ret) {
 850                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 851                                                 max ? "max" : "min");
 852                         return ret;
 853                 }
 854         }
 855
 856         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 857             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 858                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 859                 ret = smu_cmn_send_smc_msg_with_param(smu,
 860                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 861                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 862                         NULL);
 863                 if (ret) {
 864                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 865                                                 max ? "max" : "min");
 866                         return ret;
 867                 }
 868         }
 869
 870         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 871             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 872                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 873                 ret = smu_cmn_send_smc_msg_with_param(smu,
 874                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 875                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 876                         NULL);
 877                 if (ret) {
 878                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 879                                                 max ? "max" : "min");
 880                         return ret;
 881                 }
 882         }
 883
 884         return ret;
 885 }
 886
 887 static int arcturus_force_clk_levels(struct smu_context *smu,
 888                         enum smu_clk_type type, uint32_t mask)
 889 {
 890         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 891         struct smu_11_0_dpm_table *single_dpm_table = NULL;
 892         uint32_t soft_min_level, soft_max_level;
 893         uint32_t smu_version;
 894         int ret = 0;
 895
 896         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 897         if (ret) {
 898                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 899                 return ret;
 900         }
 901
 902         if ((smu_version >= 0x361200) &&
 903             (smu_version <= 0x361a00)) {
 904                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
 905                        "54.18 - 54.26(included) SMU firmwares\n");
 906                 return -EOPNOTSUPP;
 907         }
 908
 909         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 910         soft_max_level = mask ? (fls(mask) - 1) : 0;
 911
 912         switch (type) {
 913         case SMU_SCLK:
 914                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 915                 if (soft_max_level >= single_dpm_table->count) {
 916                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 917                                         soft_max_level, single_dpm_table->count - 1);
 918                         ret = -EINVAL;
 919                         break;
 920                 }
 921
 922                 ret = arcturus_upload_dpm_level(smu,
 923                                                 false,
 924                                                 FEATURE_DPM_GFXCLK_MASK,
 925                                                 soft_min_level);
 926                 if (ret) {
 927                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 928                         break;
 929                 }
 930
 931                 ret = arcturus_upload_dpm_level(smu,
 932                                                 true,
 933                                                 FEATURE_DPM_GFXCLK_MASK,
 934                                                 soft_max_level);
 935                 if (ret)
 936                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 937
 938                 break;
 939
 940         case SMU_MCLK:
 941         case SMU_SOCCLK:
 942         case SMU_FCLK:
 943                 /*
 944                  * Should not arrive here since Arcturus does not
 945                  * support mclk/socclk/fclk softmin/softmax settings
 946                  */
 947                 ret = -EINVAL;
 948                 break;
 949
 950         default:
 951                 break;
 952         }
 953
 954         return ret;
 955 }
 956
 957 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 958                                                 struct smu_temperature_range *range)
 959 {
 960         struct smu_table_context *table_context = &smu->smu_table;
 961         struct smu_11_0_powerplay_table *powerplay_table =
 962                                 table_context->power_play_table;
 963         PPTable_t *pptable = smu->smu_table.driver_pptable;
 964
 965         if (!range)
 966                 return -EINVAL;
 967
 968         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
 969
 970         range->max = pptable->TedgeLimit *
 971                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 972         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 973                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 974         range->hotspot_crit_max = pptable->ThotspotLimit *
 975                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 976         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 977                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 978         range->mem_crit_max = pptable->TmemLimit *
 979                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 980         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
 981                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 982         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
 983
 984         return 0;
 985 }
 986
 987 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 988                                                  enum amd_pp_sensors sensor,
 989                                                  uint32_t *value)
 990 {
 991         int ret = 0;
 992
 993         if (!value)
 994                 return -EINVAL;
 995
 996         switch (sensor) {
 997         case AMDGPU_PP_SENSOR_GPU_LOAD:
 998                 ret = arcturus_get_smu_metrics_data(smu,
 999                                                     METRICS_AVERAGE_GFXACTIVITY,
1000                                                     value);
1001                 break;
1002         case AMDGPU_PP_SENSOR_MEM_LOAD:
1003                 ret = arcturus_get_smu_metrics_data(smu,
1004                                                     METRICS_AVERAGE_MEMACTIVITY,
1005                                                     value);
1006                 break;
1007         default:
1008                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1009                 return -EINVAL;
1010         }
1011
1012         return ret;
1013 }
1014
1015 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
1016 {
1017         if (!value)
1018                 return -EINVAL;
1019
1020         return arcturus_get_smu_metrics_data(smu,
1021                                              METRICS_AVERAGE_SOCKETPOWER,
1022                                              value);
1023 }
1024
1025 static int arcturus_thermal_get_temperature(struct smu_context *smu,
1026                                             enum amd_pp_sensors sensor,
1027                                             uint32_t *value)
1028 {
1029         int ret = 0;
1030
1031         if (!value)
1032                 return -EINVAL;
1033
1034         switch (sensor) {
1035         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1036                 ret = arcturus_get_smu_metrics_data(smu,
1037                                                     METRICS_TEMPERATURE_HOTSPOT,
1038                                                     value);
1039                 break;
1040         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1041                 ret = arcturus_get_smu_metrics_data(smu,
1042                                                     METRICS_TEMPERATURE_EDGE,
1043                                                     value);
1044                 break;
1045         case AMDGPU_PP_SENSOR_MEM_TEMP:
1046                 ret = arcturus_get_smu_metrics_data(smu,
1047                                                     METRICS_TEMPERATURE_MEM,
1048                                                     value);
1049                 break;
1050         default:
1051                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1052                 return -EINVAL;
1053         }
1054
1055         return ret;
1056 }
1057
1058 static int arcturus_read_sensor(struct smu_context *smu,
1059                                 enum amd_pp_sensors sensor,
1060                                 void *data, uint32_t *size)
1061 {
1062         struct smu_table_context *table_context = &smu->smu_table;
1063         PPTable_t *pptable = table_context->driver_pptable;
1064         int ret = 0;
1065
1066         if (amdgpu_ras_intr_triggered())
1067                 return 0;
1068
1069         if (!data || !size)
1070                 return -EINVAL;
1071
1072         mutex_lock(&smu->sensor_lock);
1073         switch (sensor) {
1074         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1075                 *(uint32_t *)data = pptable->FanMaximumRpm;
1076                 *size = 4;
1077                 break;
1078         case AMDGPU_PP_SENSOR_MEM_LOAD:
1079         case AMDGPU_PP_SENSOR_GPU_LOAD:
1080                 ret = arcturus_get_current_activity_percent(smu,
1081                                                             sensor,
1082                                                 (uint32_t *)data);
1083                 *size = 4;
1084                 break;
1085         case AMDGPU_PP_SENSOR_GPU_POWER:
1086                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1087                 *size = 4;
1088                 break;
1089         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1090         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1091         case AMDGPU_PP_SENSOR_MEM_TEMP:
1092                 ret = arcturus_thermal_get_temperature(smu, sensor,
1093                                                 (uint32_t *)data);
1094                 *size = 4;
1095                 break;
1096         case AMDGPU_PP_SENSOR_GFX_MCLK:
1097                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1098                 /* the output clock frequency in 10K unit */
1099                 *(uint32_t *)data *= 100;
1100                 *size = 4;
1101                 break;
1102         case AMDGPU_PP_SENSOR_GFX_SCLK:
1103                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1104                 *(uint32_t *)data *= 100;
1105                 *size = 4;
1106                 break;
1107         case AMDGPU_PP_SENSOR_VDDGFX:
1108                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1109                 *size = 4;
1110                 break;
1111         default:
1112                 ret = -EOPNOTSUPP;
1113                 break;
1114         }
1115         mutex_unlock(&smu->sensor_lock);
1116
1117         return ret;
1118 }
1119
1120 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1121                                       uint32_t *speed)
1122 {
1123         if (!speed)
1124                 return -EINVAL;
1125
1126         return arcturus_get_smu_metrics_data(smu,
1127                                              METRICS_CURR_FANSPEED,
1128                                              speed);
1129 }
1130
1131 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1132                                           uint32_t *speed)
1133 {
1134         PPTable_t *pptable = smu->smu_table.driver_pptable;
1135         uint32_t percent, current_rpm;
1136         int ret = 0;
1137
1138         if (!speed)
1139                 return -EINVAL;
1140
1141         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1142         if (ret)
1143                 return ret;
1144
1145         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1146         *speed = percent > 100 ? 100 : percent;
1147
1148         return ret;
1149 }
1150
1151 static int arcturus_get_power_limit(struct smu_context *smu)
1152 {
1153         struct smu_11_0_powerplay_table *powerplay_table =
1154                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1155         PPTable_t *pptable = smu->smu_table.driver_pptable;
1156         uint32_t power_limit, od_percent;
1157
1158         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1159                 /* the last hope to figure out the ppt limit */
1160                 if (!pptable) {
1161                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1162                         return -EINVAL;
1163                 }
1164                 power_limit =
1165                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1166         }
1167         smu->current_power_limit = power_limit;
1168
1169         if (smu->od_enabled) {
1170                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1171
1172                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1173
1174                 power_limit *= (100 + od_percent);
1175                 power_limit /= 100;
1176         }
1177         smu->max_power_limit = power_limit;
1178
1179         return 0;
1180 }
1181
1182 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1183                                            char *buf)
1184 {
1185         DpmActivityMonitorCoeffInt_t activity_monitor;
1186         static const char *profile_name[] = {
1187                                         "BOOTUP_DEFAULT",
1188                                         "3D_FULL_SCREEN",
1189                                         "POWER_SAVING",
1190                                         "VIDEO",
1191                                         "VR",
1192                                         "COMPUTE",
1193                                         "CUSTOM"};
1194         static const char *title[] = {
1195                         "PROFILE_INDEX(NAME)",
1196                         "CLOCK_TYPE(NAME)",
1197                         "FPS",
1198                         "UseRlcBusy",
1199                         "MinActiveFreqType",
1200                         "MinActiveFreq",
1201                         "BoosterFreqType",
1202                         "BoosterFreq",
1203                         "PD_Data_limit_c",
1204                         "PD_Data_error_coeff",
1205                         "PD_Data_error_rate_coeff"};
1206         uint32_t i, size = 0;
1207         int16_t workload_type = 0;
1208         int result = 0;
1209         uint32_t smu_version;
1210
1211         if (!buf)
1212                 return -EINVAL;
1213
1214         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1215         if (result)
1216                 return result;
1217
1218         if (smu_version >= 0x360d00)
1219                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1220                         title[0], title[1], title[2], title[3], title[4], title[5],
1221                         title[6], title[7], title[8], title[9], title[10]);
1222         else
1223                 size += sprintf(buf + size, "%16s\n",
1224                         title[0]);
1225
1226         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1227                 /*
1228                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1229                  * Not all profile modes are supported on arcturus.
1230                  */
1231                 workload_type = smu_cmn_to_asic_specific_index(smu,
1232                                                                CMN2ASIC_MAPPING_WORKLOAD,
1233                                                                i);
1234                 if (workload_type < 0)
1235                         continue;
1236
1237                 if (smu_version >= 0x360d00) {
1238                         result = smu_cmn_update_table(smu,
1239                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1240                                                   workload_type,
1241                                                   (void *)(&activity_monitor),
1242                                                   false);
1243                         if (result) {
1244                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1245                                 return result;
1246                         }
1247                 }
1248
1249                 size += sprintf(buf + size, "%2d %14s%s\n",
1250                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1251
1252                 if (smu_version >= 0x360d00) {
1253                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1254                                 " ",
1255                                 0,
1256                                 "GFXCLK",
1257                                 activity_monitor.Gfx_FPS,
1258                                 activity_monitor.Gfx_UseRlcBusy,
1259                                 activity_monitor.Gfx_MinActiveFreqType,
1260                                 activity_monitor.Gfx_MinActiveFreq,
1261                                 activity_monitor.Gfx_BoosterFreqType,
1262                                 activity_monitor.Gfx_BoosterFreq,
1263                                 activity_monitor.Gfx_PD_Data_limit_c,
1264                                 activity_monitor.Gfx_PD_Data_error_coeff,
1265                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1266
1267                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1268                                 " ",
1269                                 1,
1270                                 "UCLK",
1271                                 activity_monitor.Mem_FPS,
1272                                 activity_monitor.Mem_UseRlcBusy,
1273                                 activity_monitor.Mem_MinActiveFreqType,
1274                                 activity_monitor.Mem_MinActiveFreq,
1275                                 activity_monitor.Mem_BoosterFreqType,
1276                                 activity_monitor.Mem_BoosterFreq,
1277                                 activity_monitor.Mem_PD_Data_limit_c,
1278                                 activity_monitor.Mem_PD_Data_error_coeff,
1279                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1280                 }
1281         }
1282
1283         return size;
1284 }
1285
1286 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1287                                            long *input,
1288                                            uint32_t size)
1289 {
1290         DpmActivityMonitorCoeffInt_t activity_monitor;
1291         int workload_type = 0;
1292         uint32_t profile_mode = input[size];
1293         int ret = 0;
1294         uint32_t smu_version;
1295
1296         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1297                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1298                 return -EINVAL;
1299         }
1300
1301         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1302         if (ret)
1303                 return ret;
1304
1305         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1306              (smu_version >=0x360d00)) {
1307                 ret = smu_cmn_update_table(smu,
1308                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1309                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1310                                        (void *)(&activity_monitor),
1311                                        false);
1312                 if (ret) {
1313                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1314                         return ret;
1315                 }
1316
1317                 switch (input[0]) {
1318                 case 0: /* Gfxclk */
1319                         activity_monitor.Gfx_FPS = input[1];
1320                         activity_monitor.Gfx_UseRlcBusy = input[2];
1321                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1322                         activity_monitor.Gfx_MinActiveFreq = input[4];
1323                         activity_monitor.Gfx_BoosterFreqType = input[5];
1324                         activity_monitor.Gfx_BoosterFreq = input[6];
1325                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1326                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1327                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1328                         break;
1329                 case 1: /* Uclk */
1330                         activity_monitor.Mem_FPS = input[1];
1331                         activity_monitor.Mem_UseRlcBusy = input[2];
1332                         activity_monitor.Mem_MinActiveFreqType = input[3];
1333                         activity_monitor.Mem_MinActiveFreq = input[4];
1334                         activity_monitor.Mem_BoosterFreqType = input[5];
1335                         activity_monitor.Mem_BoosterFreq = input[6];
1336                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1337                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1338                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1339                         break;
1340                 }
1341
1342                 ret = smu_cmn_update_table(smu,
1343                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1344                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1345                                        (void *)(&activity_monitor),
1346                                        true);
1347                 if (ret) {
1348                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1349                         return ret;
1350                 }
1351         }
1352
1353         /*
1354          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1355          * Not all profile modes are supported on arcturus.
1356          */
1357         workload_type = smu_cmn_to_asic_specific_index(smu,
1358                                                        CMN2ASIC_MAPPING_WORKLOAD,
1359                                                        profile_mode);
1360         if (workload_type < 0) {
1361                 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1362                 return -EINVAL;
1363         }
1364
1365         ret = smu_cmn_send_smc_msg_with_param(smu,
1366                                           SMU_MSG_SetWorkloadMask,
1367                                           1 << workload_type,
1368                                           NULL);
1369         if (ret) {
1370                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1371                 return ret;
1372         }
1373
1374         smu->power_profile_mode = profile_mode;
1375
1376         return 0;
1377 }
1378
1379 static int arcturus_set_performance_level(struct smu_context *smu,
1380                                           enum amd_dpm_forced_level level)
1381 {
1382         uint32_t smu_version;
1383         int ret;
1384
1385         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1386         if (ret) {
1387                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1388                 return ret;
1389         }
1390
1391         switch (level) {
1392         case AMD_DPM_FORCED_LEVEL_HIGH:
1393         case AMD_DPM_FORCED_LEVEL_LOW:
1394         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1395         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1396         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1397         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1398                 if ((smu_version >= 0x361200) &&
1399                     (smu_version <= 0x361a00)) {
1400                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1401                                "54.18 - 54.26(included) SMU firmwares\n");
1402                         return -EOPNOTSUPP;
1403                 }
1404                 break;
1405         default:
1406                 break;
1407         }
1408
1409         return smu_v11_0_set_performance_level(smu, level);
1410 }
1411
1412 static void arcturus_dump_pptable(struct smu_context *smu)
1413 {
1414         struct smu_table_context *table_context = &smu->smu_table;
1415         PPTable_t *pptable = table_context->driver_pptable;
1416         int i;
1417
1418         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1419
1420         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1421
1422         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1423         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1424
1425         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1426                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1427                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1428         }
1429
1430         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1431         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1432         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1433         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1434
1435         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1436         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1437         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1438         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1439         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1440         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1441         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1442
1443         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1444         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1445
1446         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1447
1448         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1449         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1450
1451         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1452         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1453         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1454         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1455
1456         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1457         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1458         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1459         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1460
1461         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1462         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1463
1464         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1465                         "  .VoltageMode          = 0x%02x\n"
1466                         "  .SnapToDiscrete       = 0x%02x\n"
1467                         "  .NumDiscreteLevels    = 0x%02x\n"
1468                         "  .padding              = 0x%02x\n"
1469                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1470                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1471                         "  .SsFmin               = 0x%04x\n"
1472                         "  .Padding_16           = 0x%04x\n",
1473                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1474                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1475                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1476                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1477                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1478                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1479                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1480                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1481                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1482                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1483                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1484
1485         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1486                         "  .VoltageMode          = 0x%02x\n"
1487                         "  .SnapToDiscrete       = 0x%02x\n"
1488                         "  .NumDiscreteLevels    = 0x%02x\n"
1489                         "  .padding              = 0x%02x\n"
1490                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1491                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1492                         "  .SsFmin               = 0x%04x\n"
1493                         "  .Padding_16           = 0x%04x\n",
1494                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1495                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1496                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1497                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1498                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1499                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1500                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1501                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1502                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1503                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1504                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1505
1506         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1507                         "  .VoltageMode          = 0x%02x\n"
1508                         "  .SnapToDiscrete       = 0x%02x\n"
1509                         "  .NumDiscreteLevels    = 0x%02x\n"
1510                         "  .padding              = 0x%02x\n"
1511                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1512                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1513                         "  .SsFmin               = 0x%04x\n"
1514                         "  .Padding_16           = 0x%04x\n",
1515                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1516                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1517                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1518                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1519                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1520                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1521                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1522                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1523                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1524                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1525                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1526
1527         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1528                         "  .VoltageMode          = 0x%02x\n"
1529                         "  .SnapToDiscrete       = 0x%02x\n"
1530                         "  .NumDiscreteLevels    = 0x%02x\n"
1531                         "  .padding              = 0x%02x\n"
1532                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1533                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1534                         "  .SsFmin               = 0x%04x\n"
1535                         "  .Padding_16           = 0x%04x\n",
1536                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1537                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1538                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1539                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1540                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1541                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1542                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1543                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1544                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1545                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1546                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1547
1548         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1549                         "  .VoltageMode          = 0x%02x\n"
1550                         "  .SnapToDiscrete       = 0x%02x\n"
1551                         "  .NumDiscreteLevels    = 0x%02x\n"
1552                         "  .padding              = 0x%02x\n"
1553                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1554                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1555                         "  .SsFmin               = 0x%04x\n"
1556                         "  .Padding_16           = 0x%04x\n",
1557                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1558                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1559                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1560                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1561                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1562                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1563                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1564                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1565                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1566                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1567                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1568
1569         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1570                         "  .VoltageMode          = 0x%02x\n"
1571                         "  .SnapToDiscrete       = 0x%02x\n"
1572                         "  .NumDiscreteLevels    = 0x%02x\n"
1573                         "  .padding              = 0x%02x\n"
1574                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1575                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1576                         "  .SsFmin               = 0x%04x\n"
1577                         "  .Padding_16           = 0x%04x\n",
1578                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1579                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1580                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1581                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1582                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1583                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1584                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1585                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1586                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1587                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1588                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1589
1590
1591         dev_info(smu->adev->dev, "FreqTableGfx\n");
1592         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1593                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1594
1595         dev_info(smu->adev->dev, "FreqTableVclk\n");
1596         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1597                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1598
1599         dev_info(smu->adev->dev, "FreqTableDclk\n");
1600         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1601                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1602
1603         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1604         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1605                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1606
1607         dev_info(smu->adev->dev, "FreqTableUclk\n");
1608         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1609                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1610
1611         dev_info(smu->adev->dev, "FreqTableFclk\n");
1612         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1613                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1614
1615         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1616         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1617                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1618
1619         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1620         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1621                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1622
1623         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1624         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1625         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1626         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1627         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1628         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1629         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1630         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1631         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1632
1633         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1634         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1635         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1636         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1637
1638         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1639         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1640
1641         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1642         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1643         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1644         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1645         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1646         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1647
1648         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1649         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1650         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1651         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1652         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1653         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1654         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1655         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1656         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1657
1658         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1659         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1660         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1661         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1662
1663         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1664         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1665         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1666         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1667
1668         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1669                         pptable->dBtcGbGfxPll.a,
1670                         pptable->dBtcGbGfxPll.b,
1671                         pptable->dBtcGbGfxPll.c);
1672         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1673                         pptable->dBtcGbGfxAfll.a,
1674                         pptable->dBtcGbGfxAfll.b,
1675                         pptable->dBtcGbGfxAfll.c);
1676         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1677                         pptable->dBtcGbSoc.a,
1678                         pptable->dBtcGbSoc.b,
1679                         pptable->dBtcGbSoc.c);
1680
1681         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1682                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1683                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1684         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1685                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1686                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1687
1688         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1689                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1690                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1691                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1692         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1693                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1694                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1695                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1696
1697         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1698         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1699
1700         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1701         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1702         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1703         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1704
1705         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1706         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1707         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1708         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1709
1710         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1711         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1712
1713         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1714         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1715                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1716         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1717         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1718
1719         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1720         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1721         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1722         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1723         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1724         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1725         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1726         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1727
1728         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1729         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1730                         pptable->ReservedEquation0.a,
1731                         pptable->ReservedEquation0.b,
1732                         pptable->ReservedEquation0.c);
1733         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1734                         pptable->ReservedEquation1.a,
1735                         pptable->ReservedEquation1.b,
1736                         pptable->ReservedEquation1.c);
1737         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1738                         pptable->ReservedEquation2.a,
1739                         pptable->ReservedEquation2.b,
1740                         pptable->ReservedEquation2.c);
1741         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1742                         pptable->ReservedEquation3.a,
1743                         pptable->ReservedEquation3.b,
1744                         pptable->ReservedEquation3.c);
1745
1746         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1747         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1748
1749         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1750         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1751         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1752
1753         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1754         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1755
1756         dev_info(smu->adev->dev, "Board Parameters:\n");
1757         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1758         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1759
1760         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1761         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1762         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1763         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1764
1765         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1766         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1767
1768         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1769         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1770         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1771
1772         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1773         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1774         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1775
1776         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1777         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1778         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1779
1780         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1781         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1782         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1783
1784         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1785         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1786         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1787         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1788
1789         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1790         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1791         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1792
1793         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1794         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1795         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1796
1797         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1798         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1799         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1800
1801         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1802         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1803         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1804
1805         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1806                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1807                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1808                                 pptable->I2cControllers[i].Enabled);
1809                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1810                                 pptable->I2cControllers[i].SlaveAddress);
1811                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1812                                 pptable->I2cControllers[i].ControllerPort);
1813                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1814                                 pptable->I2cControllers[i].ControllerName);
1815                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1816                                 pptable->I2cControllers[i].ThermalThrotter);
1817                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1818                                 pptable->I2cControllers[i].I2cProtocol);
1819                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
1820                                 pptable->I2cControllers[i].Speed);
1821         }
1822
1823         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1824         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1825
1826         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1827
1828         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1829         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1830                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1831         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1832         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1833                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1834         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1835         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1836                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1837         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1838         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1839                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1840
1841 }
1842
1843 static bool arcturus_is_dpm_running(struct smu_context *smu)
1844 {
1845         int ret = 0;
1846         uint32_t feature_mask[2];
1847         unsigned long feature_enabled;
1848         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1849         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1850                            ((uint64_t)feature_mask[1] << 32));
1851         return !!(feature_enabled & SMC_DPM_FEATURE);
1852 }
1853
1854 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1855 {
1856         int ret = 0;
1857
1858         if (enable) {
1859                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1860                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1861                         if (ret) {
1862                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1863                                 return ret;
1864                         }
1865                 }
1866         } else {
1867                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1868                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1869                         if (ret) {
1870                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1871                                 return ret;
1872                         }
1873                 }
1874         }
1875
1876         return ret;
1877 }
1878
1879 static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1880                                   uint8_t address, uint32_t numbytes,
1881                                   uint8_t *data)
1882 {
1883         int i;
1884
1885         req->I2CcontrollerPort = 0;
1886         req->I2CSpeed = 2;
1887         req->SlaveAddress = address;
1888         req->NumCmds = numbytes;
1889
1890         for (i = 0; i < numbytes; i++) {
1891                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1892
1893                 /* First 2 bytes are always write for lower 2b EEPROM address */
1894                 if (i < 2)
1895                         cmd->Cmd = 1;
1896                 else
1897                         cmd->Cmd = write;
1898
1899
1900                 /* Add RESTART for read  after address filled */
1901                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1902
1903                 /* Add STOP in the end */
1904                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1905
1906                 /* Fill with data regardless if read or write to simplify code */
1907                 cmd->RegisterAddr = data[i];
1908         }
1909 }
1910
1911 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1912                                                uint8_t address,
1913                                                uint8_t *data,
1914                                                uint32_t numbytes)
1915 {
1916         uint32_t  i, ret = 0;
1917         SwI2cRequest_t req;
1918         struct amdgpu_device *adev = to_amdgpu_device(control);
1919         struct smu_table_context *smu_table = &adev->smu.smu_table;
1920         struct smu_table *table = &smu_table->driver_table;
1921
1922         if (numbytes > MAX_SW_I2C_COMMANDS) {
1923                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1924                         numbytes, MAX_SW_I2C_COMMANDS);
1925                 return -EINVAL;
1926         }
1927
1928         memset(&req, 0, sizeof(req));
1929         arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1930
1931         mutex_lock(&adev->smu.mutex);
1932         /* Now read data starting with that address */
1933         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1934                                         true);
1935         mutex_unlock(&adev->smu.mutex);
1936
1937         if (!ret) {
1938                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1939
1940                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1941                 for (i = 0; i < numbytes; i++)
1942                         data[i] = res->SwI2cCmds[i].Data;
1943
1944                 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1945                                   (uint16_t)address, numbytes);
1946
1947                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1948                                8, 1, data, numbytes, false);
1949         } else
1950                 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1951
1952         return ret;
1953 }
1954
1955 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1956                                                 uint8_t address,
1957                                                 uint8_t *data,
1958                                                 uint32_t numbytes)
1959 {
1960         uint32_t ret;
1961         SwI2cRequest_t req;
1962         struct amdgpu_device *adev = to_amdgpu_device(control);
1963
1964         if (numbytes > MAX_SW_I2C_COMMANDS) {
1965                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1966                         numbytes, MAX_SW_I2C_COMMANDS);
1967                 return -EINVAL;
1968         }
1969
1970         memset(&req, 0, sizeof(req));
1971         arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1972
1973         mutex_lock(&adev->smu.mutex);
1974         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1975         mutex_unlock(&adev->smu.mutex);
1976
1977         if (!ret) {
1978                 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1979                                          (uint16_t)address, numbytes);
1980
1981                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1982                                8, 1, data, numbytes, false);
1983                 /*
1984                  * According to EEPROM spec there is a MAX of 10 ms required for
1985                  * EEPROM to flush internal RX buffer after STOP was issued at the
1986                  * end of write transaction. During this time the EEPROM will not be
1987                  * responsive to any more commands - so wait a bit more.
1988                  */
1989                 msleep(10);
1990
1991         } else
1992                 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1993
1994         return ret;
1995 }
1996
1997 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1998                               struct i2c_msg *msgs, int num)
1999 {
2000         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2001         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2002
2003         for (i = 0; i < num; i++) {
2004                 /*
2005                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2006                  * once and hence the data needs to be spliced into chunks and sent each
2007                  * chunk separately
2008                  */
2009                 data_size = msgs[i].len - 2;
2010                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2011                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2012                 data_ptr = msgs[i].buf + 2;
2013
2014                 for (j = 0; j < data_size / data_chunk_size; j++) {
2015                         /* Insert the EEPROM dest addess, bits 0-15 */
2016                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2017                         data_chunk[1] = (next_eeprom_addr & 0xff);
2018
2019                         if (msgs[i].flags & I2C_M_RD) {
2020                                 ret = arcturus_i2c_read_data(i2c_adap,
2021                                                              (uint8_t)msgs[i].addr,
2022                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2023
2024                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2025                         } else {
2026
2027                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2028
2029                                 ret = arcturus_i2c_write_data(i2c_adap,
2030                                                               (uint8_t)msgs[i].addr,
2031                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2032                         }
2033
2034                         if (ret) {
2035                                 num = -EIO;
2036                                 goto fail;
2037                         }
2038
2039                         next_eeprom_addr += data_chunk_size;
2040                         data_ptr += data_chunk_size;
2041                 }
2042
2043                 if (data_size % data_chunk_size) {
2044                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2045                         data_chunk[1] = (next_eeprom_addr & 0xff);
2046
2047                         if (msgs[i].flags & I2C_M_RD) {
2048                                 ret = arcturus_i2c_read_data(i2c_adap,
2049                                                              (uint8_t)msgs[i].addr,
2050                                                              data_chunk, (data_size % data_chunk_size) + 2);
2051
2052                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2053                         } else {
2054                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2055
2056                                 ret = arcturus_i2c_write_data(i2c_adap,
2057                                                               (uint8_t)msgs[i].addr,
2058                                                               data_chunk, (data_size % data_chunk_size) + 2);
2059                         }
2060
2061                         if (ret) {
2062                                 num = -EIO;
2063                                 goto fail;
2064                         }
2065                 }
2066         }
2067
2068 fail:
2069         return num;
2070 }
2071
2072 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2073 {
2074         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2075 }
2076
2077
2078 static const struct i2c_algorithm arcturus_i2c_algo = {
2079         .master_xfer = arcturus_i2c_xfer,
2080         .functionality = arcturus_i2c_func,
2081 };
2082
2083 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2084 {
2085         struct amdgpu_device *adev = to_amdgpu_device(control);
2086         int res;
2087
2088         control->owner = THIS_MODULE;
2089         control->class = I2C_CLASS_SPD;
2090         control->dev.parent = &adev->pdev->dev;
2091         control->algo = &arcturus_i2c_algo;
2092         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2093
2094         res = i2c_add_adapter(control);
2095         if (res)
2096                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2097
2098         return res;
2099 }
2100
2101 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2102 {
2103         i2c_del_adapter(control);
2104 }
2105
2106 static void arcturus_get_unique_id(struct smu_context *smu)
2107 {
2108         struct amdgpu_device *adev = smu->adev;
2109         uint32_t top32 = 0, bottom32 = 0, smu_version;
2110         uint64_t id;
2111
2112         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2113                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2114                 return;
2115         }
2116
2117         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2118         if (smu_version < 0x361700) {
2119                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2120                 return;
2121         }
2122
2123         /* Get the SN to turn into a Unique ID */
2124         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2125         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2126
2127         id = ((uint64_t)bottom32 << 32) | top32;
2128         adev->unique_id = id;
2129         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2130          * 16-digit HEX string for convenience and backwards-compatibility
2131          */
2132         sprintf(adev->serial, "%llx", id);
2133 }
2134
2135 static bool arcturus_is_baco_supported(struct smu_context *smu)
2136 {
2137         struct amdgpu_device *adev = smu->adev;
2138         uint32_t val;
2139
2140         if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2141                 return false;
2142
2143         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2144         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2145 }
2146
2147 static int arcturus_set_df_cstate(struct smu_context *smu,
2148                                   enum pp_df_cstate state)
2149 {
2150         uint32_t smu_version;
2151         int ret;
2152
2153         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2154         if (ret) {
2155                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2156                 return ret;
2157         }
2158
2159         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2160         if (smu_version < 0x360F00) {
2161                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2162                 return -EINVAL;
2163         }
2164
2165         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2166 }
2167
2168 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2169 {
2170         uint32_t smu_version;
2171         int ret;
2172
2173         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2174         if (ret) {
2175                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2176                 return ret;
2177         }
2178
2179         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2180         if (smu_version < 0x00361700) {
2181                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2182                 return -EINVAL;
2183         }
2184
2185         if (en)
2186                 return smu_cmn_send_smc_msg_with_param(smu,
2187                                                    SMU_MSG_GmiPwrDnControl,
2188                                                    1,
2189                                                    NULL);
2190
2191         return smu_cmn_send_smc_msg_with_param(smu,
2192                                            SMU_MSG_GmiPwrDnControl,
2193                                            0,
2194                                            NULL);
2195 }
2196
2197 static const struct throttling_logging_label {
2198         uint32_t feature_mask;
2199         const char *label;
2200 } logging_label[] = {
2201         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2202         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2203         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2204         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2205         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2206         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2207         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2208 };
2209 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2210 {
2211         int ret;
2212         int throttler_idx, throtting_events = 0, buf_idx = 0;
2213         struct amdgpu_device *adev = smu->adev;
2214         uint32_t throttler_status;
2215         char log_buf[256];
2216
2217         ret = arcturus_get_smu_metrics_data(smu,
2218                                             METRICS_THROTTLER_STATUS,
2219                                             &throttler_status);
2220         if (ret)
2221                 return;
2222
2223         memset(log_buf, 0, sizeof(log_buf));
2224         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2225              throttler_idx++) {
2226                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2227                         throtting_events++;
2228                         buf_idx += snprintf(log_buf + buf_idx,
2229                                             sizeof(log_buf) - buf_idx,
2230                                             "%s%s",
2231                                             throtting_events > 1 ? " and " : "",
2232                                             logging_label[throttler_idx].label);
2233                         if (buf_idx >= sizeof(log_buf)) {
2234                                 dev_err(adev->dev, "buffer overflow!\n");
2235                                 log_buf[sizeof(log_buf) - 1] = '\0';
2236                                 break;
2237                         }
2238                 }
2239         }
2240
2241         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2242                         log_buf);
2243         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2244 }
2245
2246 static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2247 {
2248         struct amdgpu_device *adev = smu->adev;
2249         uint32_t esm_ctrl;
2250
2251         /* TODO: confirm this on real target */
2252         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2253         if ((esm_ctrl >> 15) & 0x1FFFF)
2254                 return (((esm_ctrl >> 8) & 0x3F) + 128);
2255
2256         return smu_v11_0_get_current_pcie_link_speed(smu);
2257 }
2258
2259 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2260                                         void **table)
2261 {
2262         struct smu_table_context *smu_table = &smu->smu_table;
2263         struct gpu_metrics_v1_0 *gpu_metrics =
2264                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2265         SmuMetrics_t metrics;
2266         int ret = 0;
2267
2268         ret = smu_cmn_get_metrics_table(smu,
2269                                         &metrics,
2270                                         true);
2271         if (ret)
2272                 return ret;
2273
2274         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2275
2276         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2277         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2278         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2279         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2280         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2281         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2282
2283         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2284         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2285         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2286
2287         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2288         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2289
2290         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2291         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2292         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2293         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2294         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2295
2296         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2297         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2298         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2299         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2300         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2301
2302         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2303
2304         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2305
2306         gpu_metrics->pcie_link_width =
2307                         smu_v11_0_get_current_pcie_link_width(smu);
2308         gpu_metrics->pcie_link_speed =
2309                         arcturus_get_current_pcie_link_speed(smu);
2310
2311         *table = (void *)gpu_metrics;
2312
2313         return sizeof(struct gpu_metrics_v1_0);
2314 }
2315
2316 static const struct pptable_funcs arcturus_ppt_funcs = {
2317         /* init dpm */
2318         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2319         /* btc */
2320         .run_btc = arcturus_run_btc,
2321         /* dpm/clk tables */
2322         .set_default_dpm_table = arcturus_set_default_dpm_table,
2323         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2324         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2325         .print_clk_levels = arcturus_print_clk_levels,
2326         .force_clk_levels = arcturus_force_clk_levels,
2327         .read_sensor = arcturus_read_sensor,
2328         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2329         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2330         .get_power_profile_mode = arcturus_get_power_profile_mode,
2331         .set_power_profile_mode = arcturus_set_power_profile_mode,
2332         .set_performance_level = arcturus_set_performance_level,
2333         /* debug (internal used) */
2334         .dump_pptable = arcturus_dump_pptable,
2335         .get_power_limit = arcturus_get_power_limit,
2336         .is_dpm_running = arcturus_is_dpm_running,
2337         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2338         .i2c_init = arcturus_i2c_control_init,
2339         .i2c_fini = arcturus_i2c_control_fini,
2340         .get_unique_id = arcturus_get_unique_id,
2341         .init_microcode = smu_v11_0_init_microcode,
2342         .load_microcode = smu_v11_0_load_microcode,
2343         .fini_microcode = smu_v11_0_fini_microcode,
2344         .init_smc_tables = arcturus_init_smc_tables,
2345         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2346         .init_power = smu_v11_0_init_power,
2347         .fini_power = smu_v11_0_fini_power,
2348         .check_fw_status = smu_v11_0_check_fw_status,
2349         /* pptable related */
2350         .setup_pptable = arcturus_setup_pptable,
2351         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2352         .check_fw_version = smu_v11_0_check_fw_version,
2353         .write_pptable = smu_cmn_write_pptable,
2354         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2355         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2356         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2357         .system_features_control = smu_v11_0_system_features_control,
2358         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2359         .send_smc_msg = smu_cmn_send_smc_msg,
2360         .init_display_count = NULL,
2361         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2362         .get_enabled_mask = smu_cmn_get_enabled_mask,
2363         .feature_is_enabled = smu_cmn_feature_is_enabled,
2364         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2365         .notify_display_change = NULL,
2366         .set_power_limit = smu_v11_0_set_power_limit,
2367         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2368         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2369         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2370         .set_min_dcef_deep_sleep = NULL,
2371         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2372         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2373         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2374         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2375         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2376         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2377         .gfx_off_control = smu_v11_0_gfx_off_control,
2378         .register_irq_handler = smu_v11_0_register_irq_handler,
2379         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2380         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2381         .baco_is_support= arcturus_is_baco_supported,
2382         .baco_get_state = smu_v11_0_baco_get_state,
2383         .baco_set_state = smu_v11_0_baco_set_state,
2384         .baco_enter = smu_v11_0_baco_enter,
2385         .baco_exit = smu_v11_0_baco_exit,
2386         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2387         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2388         .set_df_cstate = arcturus_set_df_cstate,
2389         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2390         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2391         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2392         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2393         .get_gpu_metrics = arcturus_get_gpu_metrics,
2394 };
2395
2396 void arcturus_set_ppt_funcs(struct smu_context *smu)
2397 {
2398         smu->ppt_funcs = &arcturus_ppt_funcs;
2399         smu->message_map = arcturus_message_map;
2400         smu->clock_map = arcturus_clk_map;
2401         smu->feature_map = arcturus_feature_mask_map;
2402         smu->table_map = arcturus_table_map;
2403         smu->pwr_src_map = arcturus_pwr_src_map;
2404         smu->workload_map = arcturus_workload_map;
2405 }