drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39
  40 #define CTF_OFFSET_EDGE                 5
  41 #define CTF_OFFSET_HOTSPOT              5
  42 #define CTF_OFFSET_HBM                  5
  43
  44 #define MSG_MAP(msg, index) \
  45         [SMU_MSG_##msg] = {1, (index)}
  46 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  47         [smu_feature] = {1, (arcturus_feature)}
  48
  49 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  50 #define SMU_FEATURES_LOW_SHIFT       0
  51 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  52 #define SMU_FEATURES_HIGH_SHIFT      32
  53
  54 #define SMC_DPM_FEATURE ( \
  55         FEATURE_DPM_PREFETCHER_MASK | \
  56         FEATURE_DPM_GFXCLK_MASK | \
  57         FEATURE_DPM_UCLK_MASK | \
  58         FEATURE_DPM_SOCCLK_MASK | \
  59         FEATURE_DPM_MP0CLK_MASK | \
  60         FEATURE_DPM_FCLK_MASK | \
  61         FEATURE_DPM_XGMI_MASK)
  62
  63 /* possible frequency drift (1Mhz) */
  64 #define EPSILON                         1
  65
  66 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  67         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  68         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  69         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  70         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  71         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  72         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  73         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  74         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  75         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  76         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  77         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  78         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  79         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  80         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  81         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  82         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  83         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  84         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  85         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  86         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  87         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  88         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  89         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  90         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  91         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  92         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
  93         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
  94         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
  95         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
  96         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
  97         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
  98         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
  99         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 100         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 101         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 102         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 103         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 104         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 105         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 106         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 107         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 108         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 109         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 110         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 111         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 112         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 113         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 114         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 115         MSG_MAP(RunGfxDcBtc,                         PPSMC_MSG_RunGfxDcBtc),
 116         MSG_MAP(RunSocDcBtc,                         PPSMC_MSG_RunSocDcBtc),
 117         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 118         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 119         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 120         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 121         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 122         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 123         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 124 };
 125
 126 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 127         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 128         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 129         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 130         CLK_MAP(FCLK, PPCLK_FCLK),
 131         CLK_MAP(UCLK, PPCLK_UCLK),
 132         CLK_MAP(MCLK, PPCLK_UCLK),
 133         CLK_MAP(DCLK, PPCLK_DCLK),
 134         CLK_MAP(VCLK, PPCLK_VCLK),
 135 };
 136
 137 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 138         FEA_MAP(DPM_PREFETCHER),
 139         FEA_MAP(DPM_GFXCLK),
 140         FEA_MAP(DPM_UCLK),
 141         FEA_MAP(DPM_SOCCLK),
 142         FEA_MAP(DPM_FCLK),
 143         FEA_MAP(DPM_MP0CLK),
 144         FEA_MAP(DS_GFXCLK),
 145         FEA_MAP(DS_SOCCLK),
 146         FEA_MAP(DS_LCLK),
 147         FEA_MAP(DS_FCLK),
 148         FEA_MAP(DS_UCLK),
 149         FEA_MAP(GFX_ULV),
 150         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 151         FEA_MAP(RSMU_SMN_CG),
 152         FEA_MAP(PPT),
 153         FEA_MAP(TDC),
 154         FEA_MAP(APCC_PLUS),
 155         FEA_MAP(VR0HOT),
 156         FEA_MAP(VR1HOT),
 157         FEA_MAP(FW_CTF),
 158         FEA_MAP(FAN_CONTROL),
 159         FEA_MAP(THERMAL),
 160         FEA_MAP(OUT_OF_BAND_MONITOR),
 161         FEA_MAP(TEMP_DEPENDENT_VMIN),
 162 };
 163
 164 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 165         TAB_MAP(PPTABLE),
 166         TAB_MAP(AVFS),
 167         TAB_MAP(AVFS_PSM_DEBUG),
 168         TAB_MAP(AVFS_FUSE_OVERRIDE),
 169         TAB_MAP(PMSTATUSLOG),
 170         TAB_MAP(SMU_METRICS),
 171         TAB_MAP(DRIVER_SMU_CONFIG),
 172         TAB_MAP(OVERDRIVE),
 173 };
 174
 175 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 176         PWR_MAP(AC),
 177         PWR_MAP(DC),
 178 };
 179
 180 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 181         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 182         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 183         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 184         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 185         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 186 };
 187
 188 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 189 {
 190         struct smu_11_0_cmn2aisc_mapping mapping;
 191
 192         if (index >= SMU_MSG_MAX_COUNT)
 193                 return -EINVAL;
 194
 195         mapping = arcturus_message_map[index];
 196         if (!(mapping.valid_mapping))
 197                 return -EINVAL;
 198
 199         return mapping.map_to;
 200 }
 201
 202 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 203 {
 204         struct smu_11_0_cmn2aisc_mapping mapping;
 205
 206         if (index >= SMU_CLK_COUNT)
 207                 return -EINVAL;
 208
 209         mapping = arcturus_clk_map[index];
 210         if (!(mapping.valid_mapping)) {
 211                 pr_warn("Unsupported SMU clk: %d\n", index);
 212                 return -EINVAL;
 213         }
 214
 215         return mapping.map_to;
 216 }
 217
 218 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 219 {
 220         struct smu_11_0_cmn2aisc_mapping mapping;
 221
 222         if (index >= SMU_FEATURE_COUNT)
 223                 return -EINVAL;
 224
 225         mapping = arcturus_feature_mask_map[index];
 226         if (!(mapping.valid_mapping)) {
 227                 return -EINVAL;
 228         }
 229
 230         return mapping.map_to;
 231 }
 232
 233 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 234 {
 235         struct smu_11_0_cmn2aisc_mapping mapping;
 236
 237         if (index >= SMU_TABLE_COUNT)
 238                 return -EINVAL;
 239
 240         mapping = arcturus_table_map[index];
 241         if (!(mapping.valid_mapping)) {
 242                 pr_warn("Unsupported SMU table: %d\n", index);
 243                 return -EINVAL;
 244         }
 245
 246         return mapping.map_to;
 247 }
 248
 249 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 250 {
 251         struct smu_11_0_cmn2aisc_mapping mapping;
 252
 253         if (index >= SMU_POWER_SOURCE_COUNT)
 254                 return -EINVAL;
 255
 256         mapping = arcturus_pwr_src_map[index];
 257         if (!(mapping.valid_mapping)) {
 258                 pr_warn("Unsupported SMU power source: %d\n", index);
 259                 return -EINVAL;
 260         }
 261
 262         return mapping.map_to;
 263 }
 264
 265
 266 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 267 {
 268         struct smu_11_0_cmn2aisc_mapping mapping;
 269
 270         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 271                 return -EINVAL;
 272
 273         mapping = arcturus_workload_map[profile];
 274         if (!(mapping.valid_mapping)) {
 275                 pr_warn("Unsupported SMU power source: %d\n", profile);
 276                 return -EINVAL;
 277         }
 278
 279         return mapping.map_to;
 280 }
 281
 282 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 283 {
 284         struct smu_table_context *smu_table = &smu->smu_table;
 285
 286         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 287                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 288
 289         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 290                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 291
 292         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 293                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 294
 295         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 296         if (!smu_table->metrics_table)
 297                 return -ENOMEM;
 298         smu_table->metrics_time = 0;
 299
 300         return 0;
 301 }
 302
 303 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 304 {
 305         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 306
 307         if (smu_dpm->dpm_context)
 308                 return -EINVAL;
 309
 310         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 311                                        GFP_KERNEL);
 312         if (!smu_dpm->dpm_context)
 313                 return -ENOMEM;
 314
 315         if (smu_dpm->golden_dpm_context)
 316                 return -EINVAL;
 317
 318         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 319                                               GFP_KERNEL);
 320         if (!smu_dpm->golden_dpm_context)
 321                 return -ENOMEM;
 322
 323         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 324
 325         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 326                                        GFP_KERNEL);
 327         if (!smu_dpm->dpm_current_power_state)
 328                 return -ENOMEM;
 329
 330         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 331                                        GFP_KERNEL);
 332         if (!smu_dpm->dpm_request_power_state)
 333                 return -ENOMEM;
 334
 335         return 0;
 336 }
 337
 338 static int
 339 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 340                                   uint32_t *feature_mask, uint32_t num)
 341 {
 342         if (num > 2)
 343                 return -EINVAL;
 344
 345         /* pptable will handle the features to enable */
 346         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 347
 348         return 0;
 349 }
 350
 351 static int
 352 arcturus_set_single_dpm_table(struct smu_context *smu,
 353                             struct arcturus_single_dpm_table *single_dpm_table,
 354                             PPCLK_e clk_id)
 355 {
 356         int ret = 0;
 357         uint32_t i, num_of_levels = 0, clk;
 358
 359         ret = smu_send_smc_msg_with_param(smu,
 360                         SMU_MSG_GetDpmFreqByIndex,
 361                         (clk_id << 16 | 0xFF));
 362         if (ret) {
 363                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 364                 return ret;
 365         }
 366
 367         smu_read_smc_arg(smu, &num_of_levels);
 368         if (!num_of_levels) {
 369                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 370                 return -EINVAL;
 371         }
 372
 373         single_dpm_table->count = num_of_levels;
 374         for (i = 0; i < num_of_levels; i++) {
 375                 ret = smu_send_smc_msg_with_param(smu,
 376                                 SMU_MSG_GetDpmFreqByIndex,
 377                                 (clk_id << 16 | i));
 378                 if (ret) {
 379                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 380                         return ret;
 381                 }
 382                 smu_read_smc_arg(smu, &clk);
 383                 if (!clk) {
 384                         pr_err("[%s] clk value is invalid!\n", __func__);
 385                         return -EINVAL;
 386                 }
 387                 single_dpm_table->dpm_levels[i].value = clk;
 388                 single_dpm_table->dpm_levels[i].enabled = true;
 389         }
 390         return 0;
 391 }
 392
 393 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 394 {
 395         dpm_state->soft_min_level = 0x0;
 396         dpm_state->soft_max_level = 0xffff;
 397         dpm_state->hard_min_level = 0x0;
 398         dpm_state->hard_max_level = 0xffff;
 399 }
 400
 401 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 402 {
 403         int ret;
 404
 405         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 406         struct arcturus_dpm_table *dpm_table = NULL;
 407         struct arcturus_single_dpm_table *single_dpm_table;
 408
 409         dpm_table = smu_dpm->dpm_context;
 410
 411         /* socclk */
 412         single_dpm_table = &(dpm_table->soc_table);
 413         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 414                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 415                                                   PPCLK_SOCCLK);
 416                 if (ret) {
 417                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 418                         return ret;
 419                 }
 420         } else {
 421                 single_dpm_table->count = 1;
 422                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 423         }
 424         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 425
 426         /* gfxclk */
 427         single_dpm_table = &(dpm_table->gfx_table);
 428         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 429                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 430                                                   PPCLK_GFXCLK);
 431                 if (ret) {
 432                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 433                         return ret;
 434                 }
 435         } else {
 436                 single_dpm_table->count = 1;
 437                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 438         }
 439         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 440
 441         /* memclk */
 442         single_dpm_table = &(dpm_table->mem_table);
 443         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 444                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 445                                                   PPCLK_UCLK);
 446                 if (ret) {
 447                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 448                         return ret;
 449                 }
 450         } else {
 451                 single_dpm_table->count = 1;
 452                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 453         }
 454         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 455
 456         /* fclk */
 457         single_dpm_table = &(dpm_table->fclk_table);
 458         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 459                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 460                                                   PPCLK_FCLK);
 461                 if (ret) {
 462                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 463                         return ret;
 464                 }
 465         } else {
 466                 single_dpm_table->count = 0;
 467         }
 468         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 469
 470         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 471                sizeof(struct arcturus_dpm_table));
 472
 473         return 0;
 474 }
 475
 476 static int arcturus_check_powerplay_table(struct smu_context *smu)
 477 {
 478         return 0;
 479 }
 480
 481 static int arcturus_store_powerplay_table(struct smu_context *smu)
 482 {
 483         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 484         struct smu_table_context *table_context = &smu->smu_table;
 485         int ret = 0;
 486
 487         if (!table_context->power_play_table)
 488                 return -EINVAL;
 489
 490         powerplay_table = table_context->power_play_table;
 491
 492         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 493                sizeof(PPTable_t));
 494
 495         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 496
 497         return ret;
 498 }
 499
 500 static int arcturus_append_powerplay_table(struct smu_context *smu)
 501 {
 502         struct smu_table_context *table_context = &smu->smu_table;
 503         PPTable_t *smc_pptable = table_context->driver_pptable;
 504         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 505         int index, ret;
 506
 507         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 508                                            smc_dpm_info);
 509
 510         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 511                                       (uint8_t **)&smc_dpm_table);
 512         if (ret)
 513                 return ret;
 514
 515         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 516                         smc_dpm_table->table_header.format_revision,
 517                         smc_dpm_table->table_header.content_revision);
 518
 519         if ((smc_dpm_table->table_header.format_revision == 4) &&
 520             (smc_dpm_table->table_header.content_revision == 6))
 521                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 522                        &smc_dpm_table->maxvoltagestepgfx,
 523                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 524
 525         return 0;
 526 }
 527
 528 static int arcturus_run_btc_afll(struct smu_context *smu)
 529 {
 530         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 531 }
 532
 533 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 534 {
 535         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 536         struct arcturus_dpm_table *dpm_table = NULL;
 537         struct arcturus_single_dpm_table *gfx_table = NULL;
 538         struct arcturus_single_dpm_table *mem_table = NULL;
 539
 540         dpm_table = smu_dpm->dpm_context;
 541         gfx_table = &(dpm_table->gfx_table);
 542         mem_table = &(dpm_table->mem_table);
 543
 544         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 545         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 546
 547         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 548             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 549                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 550                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 551         }
 552
 553         smu->pstate_sclk = smu->pstate_sclk * 100;
 554         smu->pstate_mclk = smu->pstate_mclk * 100;
 555
 556         return 0;
 557 }
 558
 559 static int arcturus_get_clk_table(struct smu_context *smu,
 560                         struct pp_clock_levels_with_latency *clocks,
 561                         struct arcturus_single_dpm_table *dpm_table)
 562 {
 563         int i, count;
 564
 565         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 566         clocks->num_levels = count;
 567
 568         for (i = 0; i < count; i++) {
 569                 clocks->data[i].clocks_in_khz =
 570                         dpm_table->dpm_levels[i].value * 1000;
 571                 clocks->data[i].latency_in_us = 0;
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int arcturus_freqs_in_same_level(int32_t frequency1,
 578                                         int32_t frequency2)
 579 {
 580         return (abs(frequency1 - frequency2) <= EPSILON);
 581 }
 582
 583 static int arcturus_print_clk_levels(struct smu_context *smu,
 584                         enum smu_clk_type type, char *buf)
 585 {
 586         int i, now, size = 0;
 587         int ret = 0;
 588         struct pp_clock_levels_with_latency clocks;
 589         struct arcturus_single_dpm_table *single_dpm_table;
 590         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 591         struct arcturus_dpm_table *dpm_table = NULL;
 592
 593         dpm_table = smu_dpm->dpm_context;
 594
 595         switch (type) {
 596         case SMU_SCLK:
 597                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 598                 if (ret) {
 599                         pr_err("Attempt to get current gfx clk Failed!");
 600                         return ret;
 601                 }
 602
 603                 single_dpm_table = &(dpm_table->gfx_table);
 604                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 605                 if (ret) {
 606                         pr_err("Attempt to get gfx clk levels Failed!");
 607                         return ret;
 608                 }
 609
 610                 for (i = 0; i < clocks.num_levels; i++)
 611                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 612                                         clocks.data[i].clocks_in_khz / 1000,
 613                                         arcturus_freqs_in_same_level(
 614                                         clocks.data[i].clocks_in_khz / 1000,
 615                                         now / 100) ? "*" : "");
 616                 break;
 617
 618         case SMU_MCLK:
 619                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 620                 if (ret) {
 621                         pr_err("Attempt to get current mclk Failed!");
 622                         return ret;
 623                 }
 624
 625                 single_dpm_table = &(dpm_table->mem_table);
 626                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 627                 if (ret) {
 628                         pr_err("Attempt to get memory clk levels Failed!");
 629                         return ret;
 630                 }
 631
 632                 for (i = 0; i < clocks.num_levels; i++)
 633                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 634                                 i, clocks.data[i].clocks_in_khz / 1000,
 635                                 arcturus_freqs_in_same_level(
 636                                 clocks.data[i].clocks_in_khz / 1000,
 637                                 now / 100) ? "*" : "");
 638                 break;
 639
 640         case SMU_SOCCLK:
 641                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 642                 if (ret) {
 643                         pr_err("Attempt to get current socclk Failed!");
 644                         return ret;
 645                 }
 646
 647                 single_dpm_table = &(dpm_table->soc_table);
 648                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 649                 if (ret) {
 650                         pr_err("Attempt to get socclk levels Failed!");
 651                         return ret;
 652                 }
 653
 654                 for (i = 0; i < clocks.num_levels; i++)
 655                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 656                                 i, clocks.data[i].clocks_in_khz / 1000,
 657                                 arcturus_freqs_in_same_level(
 658                                 clocks.data[i].clocks_in_khz / 1000,
 659                                 now / 100) ? "*" : "");
 660                 break;
 661
 662         case SMU_FCLK:
 663                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 664                 if (ret) {
 665                         pr_err("Attempt to get current fclk Failed!");
 666                         return ret;
 667                 }
 668
 669                 single_dpm_table = &(dpm_table->fclk_table);
 670                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 671                 if (ret) {
 672                         pr_err("Attempt to get fclk levels Failed!");
 673                         return ret;
 674                 }
 675
 676                 for (i = 0; i < single_dpm_table->count; i++)
 677                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 678                                 i, single_dpm_table->dpm_levels[i].value,
 679                                 arcturus_freqs_in_same_level(
 680                                 clocks.data[i].clocks_in_khz / 1000,
 681                                 now / 100) ? "*" : "");
 682                 break;
 683
 684         default:
 685                 break;
 686         }
 687
 688         return size;
 689 }
 690
 691 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 692                                      uint32_t feature_mask)
 693 {
 694         struct arcturus_single_dpm_table *single_dpm_table;
 695         struct arcturus_dpm_table *dpm_table =
 696                         smu->smu_dpm.dpm_context;
 697         uint32_t freq;
 698         int ret = 0;
 699
 700         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 701             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 702                 single_dpm_table = &(dpm_table->gfx_table);
 703                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 704                         single_dpm_table->dpm_state.soft_min_level;
 705                 ret = smu_send_smc_msg_with_param(smu,
 706                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 707                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 708                 if (ret) {
 709                         pr_err("Failed to set soft %s gfxclk !\n",
 710                                                 max ? "max" : "min");
 711                         return ret;
 712                 }
 713         }
 714
 715         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 716             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 717                 single_dpm_table = &(dpm_table->mem_table);
 718                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 719                         single_dpm_table->dpm_state.soft_min_level;
 720                 ret = smu_send_smc_msg_with_param(smu,
 721                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 722                         (PPCLK_UCLK << 16) | (freq & 0xffff));
 723                 if (ret) {
 724                         pr_err("Failed to set soft %s memclk !\n",
 725                                                 max ? "max" : "min");
 726                         return ret;
 727                 }
 728         }
 729
 730         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 731             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 732                 single_dpm_table = &(dpm_table->soc_table);
 733                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 734                         single_dpm_table->dpm_state.soft_min_level;
 735                 ret = smu_send_smc_msg_with_param(smu,
 736                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 737                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
 738                 if (ret) {
 739                         pr_err("Failed to set soft %s socclk !\n",
 740                                                 max ? "max" : "min");
 741                         return ret;
 742                 }
 743         }
 744
 745         return ret;
 746 }
 747
 748 static int arcturus_force_clk_levels(struct smu_context *smu,
 749                         enum smu_clk_type type, uint32_t mask)
 750 {
 751         struct arcturus_dpm_table *dpm_table;
 752         struct arcturus_single_dpm_table *single_dpm_table;
 753         uint32_t soft_min_level, soft_max_level;
 754         int ret = 0;
 755
 756         mutex_lock(&(smu->mutex));
 757
 758         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 759         soft_max_level = mask ? (fls(mask) - 1) : 0;
 760
 761         dpm_table = smu->smu_dpm.dpm_context;
 762
 763         switch (type) {
 764         case SMU_SCLK:
 765                 single_dpm_table = &(dpm_table->gfx_table);
 766
 767                 if (soft_max_level >= single_dpm_table->count) {
 768                         pr_err("Clock level specified %d is over max allowed %d\n",
 769                                         soft_max_level, single_dpm_table->count - 1);
 770                         ret = -EINVAL;
 771                         break;
 772                 }
 773
 774                 single_dpm_table->dpm_state.soft_min_level =
 775                         single_dpm_table->dpm_levels[soft_min_level].value;
 776                 single_dpm_table->dpm_state.soft_max_level =
 777                         single_dpm_table->dpm_levels[soft_max_level].value;
 778
 779                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 780                 if (ret) {
 781                         pr_err("Failed to upload boot level to lowest!\n");
 782                         break;
 783                 }
 784
 785                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 786                 if (ret)
 787                         pr_err("Failed to upload dpm max level to highest!\n");
 788
 789                 break;
 790
 791         case SMU_MCLK:
 792                 single_dpm_table = &(dpm_table->mem_table);
 793
 794                 if (soft_max_level >= single_dpm_table->count) {
 795                         pr_err("Clock level specified %d is over max allowed %d\n",
 796                                         soft_max_level, single_dpm_table->count - 1);
 797                         ret = -EINVAL;
 798                         break;
 799                 }
 800
 801                 single_dpm_table->dpm_state.soft_min_level =
 802                         single_dpm_table->dpm_levels[soft_min_level].value;
 803                 single_dpm_table->dpm_state.soft_max_level =
 804                         single_dpm_table->dpm_levels[soft_max_level].value;
 805
 806                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
 807                 if (ret) {
 808                         pr_err("Failed to upload boot level to lowest!\n");
 809                         break;
 810                 }
 811
 812                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
 813                 if (ret)
 814                         pr_err("Failed to upload dpm max level to highest!\n");
 815
 816                 break;
 817
 818         case SMU_SOCCLK:
 819                 single_dpm_table = &(dpm_table->soc_table);
 820
 821                 if (soft_max_level >= single_dpm_table->count) {
 822                         pr_err("Clock level specified %d is over max allowed %d\n",
 823                                         soft_max_level, single_dpm_table->count - 1);
 824                         ret = -EINVAL;
 825                         break;
 826                 }
 827
 828                 single_dpm_table->dpm_state.soft_min_level =
 829                         single_dpm_table->dpm_levels[soft_min_level].value;
 830                 single_dpm_table->dpm_state.soft_max_level =
 831                         single_dpm_table->dpm_levels[soft_max_level].value;
 832
 833                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
 834                 if (ret) {
 835                         pr_err("Failed to upload boot level to lowest!\n");
 836                         break;
 837                 }
 838
 839                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
 840                 if (ret)
 841                         pr_err("Failed to upload dpm max level to highest!\n");
 842
 843                 break;
 844
 845         case SMU_FCLK:
 846                 single_dpm_table = &(dpm_table->fclk_table);
 847
 848                 if (soft_max_level >= single_dpm_table->count) {
 849                         pr_err("Clock level specified %d is over max allowed %d\n",
 850                                         soft_max_level, single_dpm_table->count - 1);
 851                         ret = -EINVAL;
 852                         break;
 853                 }
 854
 855                 single_dpm_table->dpm_state.soft_min_level =
 856                         single_dpm_table->dpm_levels[soft_min_level].value;
 857                 single_dpm_table->dpm_state.soft_max_level =
 858                         single_dpm_table->dpm_levels[soft_max_level].value;
 859
 860                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
 861                 if (ret) {
 862                         pr_err("Failed to upload boot level to lowest!\n");
 863                         break;
 864                 }
 865
 866                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
 867                 if (ret)
 868                         pr_err("Failed to upload dpm max level to highest!\n");
 869
 870                 break;
 871
 872         default:
 873                 break;
 874         }
 875
 876         mutex_unlock(&(smu->mutex));
 877         return ret;
 878 }
 879
 880 static const struct smu_temperature_range arcturus_thermal_policy[] =
 881 {
 882         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
 883         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
 884 };
 885
 886 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 887                                                 struct smu_temperature_range *range)
 888 {
 889
 890         PPTable_t *pptable = smu->smu_table.driver_pptable;
 891
 892         if (!range)
 893                 return -EINVAL;
 894
 895         memcpy(range, &arcturus_thermal_policy[0], sizeof(struct smu_temperature_range));
 896
 897         range->max = pptable->TedgeLimit *
 898                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 899         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 900                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 901         range->hotspot_crit_max = pptable->ThotspotLimit *
 902                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 903         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 904                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 905         range->mem_crit_max = pptable->TmemLimit *
 906                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 907         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 908                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 909
 910
 911         return 0;
 912 }
 913
 914 static int arcturus_get_metrics_table(struct smu_context *smu,
 915                                       SmuMetrics_t *metrics_table)
 916 {
 917         struct smu_table_context *smu_table= &smu->smu_table;
 918         int ret = 0;
 919
 920         if (!smu_table->metrics_time ||
 921              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 922                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 923                                 (void *)smu_table->metrics_table, false);
 924                 if (ret) {
 925                         pr_info("Failed to export SMU metrics table!\n");
 926                         return ret;
 927                 }
 928                 smu_table->metrics_time = jiffies;
 929         }
 930
 931         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 932
 933         return ret;
 934 }
 935
 936 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 937                                                  enum amd_pp_sensors sensor,
 938                                                  uint32_t *value)
 939 {
 940         SmuMetrics_t metrics;
 941         int ret = 0;
 942
 943         if (!value)
 944                 return -EINVAL;
 945
 946         ret = arcturus_get_metrics_table(smu, &metrics);
 947         if (ret)
 948                 return ret;
 949
 950         switch (sensor) {
 951         case AMDGPU_PP_SENSOR_GPU_LOAD:
 952                 *value = metrics.AverageGfxActivity;
 953                 break;
 954         case AMDGPU_PP_SENSOR_MEM_LOAD:
 955                 *value = metrics.AverageUclkActivity;
 956                 break;
 957         default:
 958                 pr_err("Invalid sensor for retrieving clock activity\n");
 959                 return -EINVAL;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 966 {
 967         SmuMetrics_t metrics;
 968         int ret = 0;
 969
 970         if (!value)
 971                 return -EINVAL;
 972
 973         ret = arcturus_get_metrics_table(smu, &metrics);
 974         if (ret)
 975                 return ret;
 976
 977         *value = metrics.AverageSocketPower << 8;
 978
 979         return 0;
 980 }
 981
 982 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 983                                             enum amd_pp_sensors sensor,
 984                                             uint32_t *value)
 985 {
 986         SmuMetrics_t metrics;
 987         int ret = 0;
 988
 989         if (!value)
 990                 return -EINVAL;
 991
 992         ret = arcturus_get_metrics_table(smu, &metrics);
 993         if (ret)
 994                 return ret;
 995
 996         switch (sensor) {
 997         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 998                 *value = metrics.TemperatureHotspot *
 999                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1000                 break;
1001         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1002                 *value = metrics.TemperatureEdge *
1003                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1004                 break;
1005         case AMDGPU_PP_SENSOR_MEM_TEMP:
1006                 *value = metrics.TemperatureHBM *
1007                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1008                 break;
1009         default:
1010                 pr_err("Invalid sensor for retrieving temp\n");
1011                 return -EINVAL;
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int arcturus_read_sensor(struct smu_context *smu,
1018                                 enum amd_pp_sensors sensor,
1019                                 void *data, uint32_t *size)
1020 {
1021         struct smu_table_context *table_context = &smu->smu_table;
1022         PPTable_t *pptable = table_context->driver_pptable;
1023         int ret = 0;
1024
1025         if (!data || !size)
1026                 return -EINVAL;
1027
1028         switch (sensor) {
1029         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1030                 *(uint32_t *)data = pptable->FanMaximumRpm;
1031                 *size = 4;
1032                 break;
1033         case AMDGPU_PP_SENSOR_MEM_LOAD:
1034         case AMDGPU_PP_SENSOR_GPU_LOAD:
1035                 ret = arcturus_get_current_activity_percent(smu,
1036                                                             sensor,
1037                                                 (uint32_t *)data);
1038                 *size = 4;
1039                 break;
1040         case AMDGPU_PP_SENSOR_GPU_POWER:
1041                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1042                 *size = 4;
1043                 break;
1044         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1045         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1046         case AMDGPU_PP_SENSOR_MEM_TEMP:
1047                 ret = arcturus_thermal_get_temperature(smu, sensor,
1048                                                 (uint32_t *)data);
1049                 *size = 4;
1050                 break;
1051         default:
1052                 ret = smu_smc_read_sensor(smu, sensor, data, size);
1053         }
1054
1055         return ret;
1056 }
1057
1058 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1059                                       uint32_t *speed)
1060 {
1061         SmuMetrics_t metrics;
1062         int ret = 0;
1063
1064         if (!speed)
1065                 return -EINVAL;
1066
1067         ret = arcturus_get_metrics_table(smu, &metrics);
1068         if (ret)
1069                 return ret;
1070
1071         *speed = metrics.CurrFanSpeed;
1072
1073         return ret;
1074 }
1075
1076 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1077                                           uint32_t *speed)
1078 {
1079         PPTable_t *pptable = smu->smu_table.driver_pptable;
1080         uint32_t percent, current_rpm;
1081         int ret = 0;
1082
1083         if (!speed)
1084                 return -EINVAL;
1085
1086         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1087         if (ret)
1088                 return ret;
1089
1090         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1091         *speed = percent > 100 ? 100 : percent;
1092
1093         return ret;
1094 }
1095
1096 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1097                                        enum smu_clk_type clk_type,
1098                                        uint32_t *value)
1099 {
1100         static SmuMetrics_t metrics;
1101         int ret = 0, clk_id = 0;
1102
1103         if (!value)
1104                 return -EINVAL;
1105
1106         clk_id = smu_clk_get_index(smu, clk_type);
1107         if (clk_id < 0)
1108                 return -EINVAL;
1109
1110         ret = arcturus_get_metrics_table(smu, &metrics);
1111         if (ret)
1112                 return ret;
1113
1114         switch (clk_id) {
1115         case PPCLK_GFXCLK:
1116                 /*
1117                  * CurrClock[clk_id] can provide accurate
1118                  *   output only when the dpm feature is enabled.
1119                  * We can use Average_* for dpm disabled case.
1120                  *   But this is available for gfxclk/uclk/socclk.
1121                  */
1122                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1123                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1124                 else
1125                         *value = metrics.AverageGfxclkFrequency;
1126                 break;
1127         case PPCLK_UCLK:
1128                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1129                         *value = metrics.CurrClock[PPCLK_UCLK];
1130                 else
1131                         *value = metrics.AverageUclkFrequency;
1132                 break;
1133         case PPCLK_SOCCLK:
1134                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1135                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1136                 else
1137                         *value = metrics.AverageSocclkFrequency;
1138                 break;
1139         default:
1140                 *value = metrics.CurrClock[clk_id];
1141                 break;
1142         }
1143
1144         return ret;
1145 }
1146
1147 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1148 {
1149         uint32_t i;
1150
1151         for (i = 0; i < table->count; i++) {
1152                 if (table->dpm_levels[i].enabled)
1153                         break;
1154         }
1155         if (i >= table->count) {
1156                 i = 0;
1157                 table->dpm_levels[i].enabled = true;
1158         }
1159
1160         return i;
1161 }
1162
1163 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1164 {
1165         int i = 0;
1166
1167         if (table->count <= 0) {
1168                 pr_err("[%s] DPM Table has no entry!", __func__);
1169                 return 0;
1170         }
1171         if (table->count > MAX_DPM_NUMBER) {
1172                 pr_err("[%s] DPM Table has too many entries!", __func__);
1173                 return MAX_DPM_NUMBER - 1;
1174         }
1175
1176         for (i = table->count - 1; i >= 0; i--) {
1177                 if (table->dpm_levels[i].enabled)
1178                         break;
1179         }
1180         if (i < 0) {
1181                 i = 0;
1182                 table->dpm_levels[i].enabled = true;
1183         }
1184
1185         return i;
1186 }
1187
1188
1189
1190 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1191 {
1192         struct arcturus_dpm_table *dpm_table =
1193                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1194         uint32_t soft_level;
1195         int ret = 0;
1196
1197         /* gfxclk */
1198         if (highest)
1199                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1200         else
1201                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1202
1203         dpm_table->gfx_table.dpm_state.soft_min_level =
1204                 dpm_table->gfx_table.dpm_state.soft_max_level =
1205                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1206
1207         /* uclk */
1208         if (highest)
1209                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1210         else
1211                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1212
1213         dpm_table->mem_table.dpm_state.soft_min_level =
1214                 dpm_table->mem_table.dpm_state.soft_max_level =
1215                 dpm_table->mem_table.dpm_levels[soft_level].value;
1216
1217         /* socclk */
1218         if (highest)
1219                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1220         else
1221                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1222
1223         dpm_table->soc_table.dpm_state.soft_min_level =
1224                 dpm_table->soc_table.dpm_state.soft_max_level =
1225                 dpm_table->soc_table.dpm_levels[soft_level].value;
1226
1227         ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1228         if (ret) {
1229                 pr_err("Failed to upload boot level to %s!\n",
1230                                 highest ? "highest" : "lowest");
1231                 return ret;
1232         }
1233
1234         ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1235         if (ret) {
1236                 pr_err("Failed to upload dpm max level to %s!\n!",
1237                                 highest ? "highest" : "lowest");
1238                 return ret;
1239         }
1240
1241         return ret;
1242 }
1243
1244 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1245 {
1246         struct arcturus_dpm_table *dpm_table =
1247                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1248         uint32_t soft_min_level, soft_max_level;
1249         int ret = 0;
1250
1251         /* gfxclk */
1252         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1253         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1254         dpm_table->gfx_table.dpm_state.soft_min_level =
1255                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1256         dpm_table->gfx_table.dpm_state.soft_max_level =
1257                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1258
1259         /* uclk */
1260         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1261         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1262         dpm_table->mem_table.dpm_state.soft_min_level =
1263                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1264         dpm_table->mem_table.dpm_state.soft_max_level =
1265                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1266
1267         /* socclk */
1268         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1269         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1270         dpm_table->soc_table.dpm_state.soft_min_level =
1271                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
1272         dpm_table->soc_table.dpm_state.soft_max_level =
1273                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
1274
1275         ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1276         if (ret) {
1277                 pr_err("Failed to upload DPM Bootup Levels!");
1278                 return ret;
1279         }
1280
1281         ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1282         if (ret) {
1283                 pr_err("Failed to upload DPM Max Levels!");
1284                 return ret;
1285         }
1286
1287         return ret;
1288 }
1289
1290 static int
1291 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1292                                 enum amd_dpm_forced_level level,
1293                                 uint32_t *sclk_mask,
1294                                 uint32_t *mclk_mask,
1295                                 uint32_t *soc_mask)
1296 {
1297         struct arcturus_dpm_table *dpm_table =
1298                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1299         struct arcturus_single_dpm_table *gfx_dpm_table;
1300         struct arcturus_single_dpm_table *mem_dpm_table;
1301         struct arcturus_single_dpm_table *soc_dpm_table;
1302
1303         if (!smu->smu_dpm.dpm_context)
1304                 return -EINVAL;
1305
1306         gfx_dpm_table = &dpm_table->gfx_table;
1307         mem_dpm_table = &dpm_table->mem_table;
1308         soc_dpm_table = &dpm_table->soc_table;
1309
1310         *sclk_mask = 0;
1311         *mclk_mask = 0;
1312         *soc_mask  = 0;
1313
1314         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1315             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1316             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1317                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1318                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1319                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1320         }
1321
1322         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1323                 *sclk_mask = 0;
1324         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1325                 *mclk_mask = 0;
1326         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1327                 *sclk_mask = gfx_dpm_table->count - 1;
1328                 *mclk_mask = mem_dpm_table->count - 1;
1329                 *soc_mask  = soc_dpm_table->count - 1;
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int arcturus_get_power_limit(struct smu_context *smu,
1336                                      uint32_t *limit,
1337                                      bool asic_default)
1338 {
1339         PPTable_t *pptable = smu->smu_table.driver_pptable;
1340         uint32_t asic_default_power_limit = 0;
1341         int ret = 0;
1342         int power_src;
1343
1344         if (!smu->default_power_limit ||
1345             !smu->power_limit) {
1346                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1347                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1348                         if (power_src < 0)
1349                                 return -EINVAL;
1350
1351                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1352                                 power_src << 16);
1353                         if (ret) {
1354                                 pr_err("[%s] get PPT limit failed!", __func__);
1355                                 return ret;
1356                         }
1357                         smu_read_smc_arg(smu, &asic_default_power_limit);
1358                 } else {
1359                         /* the last hope to figure out the ppt limit */
1360                         if (!pptable) {
1361                                 pr_err("Cannot get PPT limit due to pptable missing!");
1362                                 return -EINVAL;
1363                         }
1364                         asic_default_power_limit =
1365                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1366                 }
1367
1368                 if (smu->od_enabled) {
1369                         asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1370                         asic_default_power_limit /= 100;
1371                 }
1372
1373                 smu->default_power_limit = asic_default_power_limit;
1374                 smu->power_limit = asic_default_power_limit;
1375         }
1376
1377         if (asic_default)
1378                 *limit = smu->default_power_limit;
1379         else
1380                 *limit = smu->power_limit;
1381
1382         return 0;
1383 }
1384
1385 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1386                                            char *buf)
1387 {
1388         static const char *profile_name[] = {
1389                                         "BOOTUP_DEFAULT",
1390                                         "3D_FULL_SCREEN",
1391                                         "POWER_SAVING",
1392                                         "VIDEO",
1393                                         "VR",
1394                                         "COMPUTE",
1395                                         "CUSTOM"};
1396         uint32_t i, size = 0;
1397         int16_t workload_type = 0;
1398
1399         if (!smu->pm_enabled || !buf)
1400                 return -EINVAL;
1401
1402         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1403                 /*
1404                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1405                  * Not all profile modes are supported on arcturus.
1406                  */
1407                 workload_type = smu_workload_get_type(smu, i);
1408                 if (workload_type < 0)
1409                         continue;
1410
1411                 size += sprintf(buf + size, "%2d %14s%s\n",
1412                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1413         }
1414
1415         return size;
1416 }
1417
1418 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1419                                            long *input,
1420                                            uint32_t size)
1421 {
1422         int workload_type = 0;
1423         uint32_t profile_mode = input[size];
1424         int ret = 0;
1425
1426         if (!smu->pm_enabled)
1427                 return -EINVAL;
1428
1429         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1430                 pr_err("Invalid power profile mode %d\n", profile_mode);
1431                 return -EINVAL;
1432         }
1433
1434         /*
1435          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1436          * Not all profile modes are supported on arcturus.
1437          */
1438         workload_type = smu_workload_get_type(smu, profile_mode);
1439         if (workload_type < 0) {
1440                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1441                 return -EINVAL;
1442         }
1443
1444         ret = smu_send_smc_msg_with_param(smu,
1445                                           SMU_MSG_SetWorkloadMask,
1446                                           1 << workload_type);
1447         if (ret) {
1448                 pr_err("Fail to set workload type %d\n", workload_type);
1449                 return ret;
1450         }
1451
1452         smu->power_profile_mode = profile_mode;
1453
1454         return 0;
1455 }
1456
1457 static void arcturus_dump_pptable(struct smu_context *smu)
1458 {
1459         struct smu_table_context *table_context = &smu->smu_table;
1460         PPTable_t *pptable = table_context->driver_pptable;
1461         int i;
1462
1463         pr_info("Dumped PPTable:\n");
1464
1465         pr_info("Version = 0x%08x\n", pptable->Version);
1466
1467         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1468         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1469
1470         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1471                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1472                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1473         }
1474
1475         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1476         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1477         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1478         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1479
1480         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1481         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1482         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1483         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1484         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1485         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1486         pr_info("FitLimit = %d\n", pptable->FitLimit);
1487
1488         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1489         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1490
1491         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1492
1493         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1494         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1495
1496         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1497         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1498         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1499         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1500
1501         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1502         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1503         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1504         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1505
1506         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1507         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1508
1509         pr_info("[PPCLK_GFXCLK]\n"
1510                         "  .VoltageMode          = 0x%02x\n"
1511                         "  .SnapToDiscrete       = 0x%02x\n"
1512                         "  .NumDiscreteLevels    = 0x%02x\n"
1513                         "  .padding              = 0x%02x\n"
1514                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1515                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1516                         "  .SsFmin               = 0x%04x\n"
1517                         "  .Padding_16           = 0x%04x\n",
1518                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1519                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1520                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1521                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1522                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1523                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1524                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1525                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1526                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1527                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1528                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1529
1530         pr_info("[PPCLK_VCLK]\n"
1531                         "  .VoltageMode          = 0x%02x\n"
1532                         "  .SnapToDiscrete       = 0x%02x\n"
1533                         "  .NumDiscreteLevels    = 0x%02x\n"
1534                         "  .padding              = 0x%02x\n"
1535                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1536                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1537                         "  .SsFmin               = 0x%04x\n"
1538                         "  .Padding_16           = 0x%04x\n",
1539                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1540                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1541                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1542                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1543                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1544                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1545                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1546                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1547                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1548                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1549                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1550
1551         pr_info("[PPCLK_DCLK]\n"
1552                         "  .VoltageMode          = 0x%02x\n"
1553                         "  .SnapToDiscrete       = 0x%02x\n"
1554                         "  .NumDiscreteLevels    = 0x%02x\n"
1555                         "  .padding              = 0x%02x\n"
1556                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1557                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1558                         "  .SsFmin               = 0x%04x\n"
1559                         "  .Padding_16           = 0x%04x\n",
1560                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1561                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1562                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1563                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1564                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1565                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1566                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1567                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1568                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1569                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1570                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1571
1572         pr_info("[PPCLK_SOCCLK]\n"
1573                         "  .VoltageMode          = 0x%02x\n"
1574                         "  .SnapToDiscrete       = 0x%02x\n"
1575                         "  .NumDiscreteLevels    = 0x%02x\n"
1576                         "  .padding              = 0x%02x\n"
1577                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1578                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1579                         "  .SsFmin               = 0x%04x\n"
1580                         "  .Padding_16           = 0x%04x\n",
1581                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1582                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1583                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1584                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1585                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1586                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1587                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1588                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1589                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1590                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1591                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1592
1593         pr_info("[PPCLK_UCLK]\n"
1594                         "  .VoltageMode          = 0x%02x\n"
1595                         "  .SnapToDiscrete       = 0x%02x\n"
1596                         "  .NumDiscreteLevels    = 0x%02x\n"
1597                         "  .padding              = 0x%02x\n"
1598                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1599                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1600                         "  .SsFmin               = 0x%04x\n"
1601                         "  .Padding_16           = 0x%04x\n",
1602                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1603                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1604                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1605                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1606                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1607                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1608                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1609                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1610                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1611                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1612                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1613
1614         pr_info("[PPCLK_FCLK]\n"
1615                         "  .VoltageMode          = 0x%02x\n"
1616                         "  .SnapToDiscrete       = 0x%02x\n"
1617                         "  .NumDiscreteLevels    = 0x%02x\n"
1618                         "  .padding              = 0x%02x\n"
1619                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1620                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1621                         "  .SsFmin               = 0x%04x\n"
1622                         "  .Padding_16           = 0x%04x\n",
1623                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1624                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1625                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1626                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1627                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1628                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1629                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1630                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1631                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1632                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1633                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1634
1635
1636         pr_info("FreqTableGfx\n");
1637         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1638                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1639
1640         pr_info("FreqTableVclk\n");
1641         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1642                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1643
1644         pr_info("FreqTableDclk\n");
1645         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1646                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1647
1648         pr_info("FreqTableSocclk\n");
1649         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1650                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1651
1652         pr_info("FreqTableUclk\n");
1653         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1654                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1655
1656         pr_info("FreqTableFclk\n");
1657         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1658                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1659
1660         pr_info("Mp0clkFreq\n");
1661         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1662                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1663
1664         pr_info("Mp0DpmVoltage\n");
1665         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1666                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1667
1668         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1669         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1670         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1671         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1672         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1673         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1674         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1675         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1676         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1677
1678         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1679         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1680         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1681         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1682
1683         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1684         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1685
1686         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1687         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1688         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1689         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1690         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1691         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1692
1693         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1694         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1695         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1696         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1697         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1698         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1699         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1700         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1701         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1702
1703         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1704         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1705         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1706         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1707
1708         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1709         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1710         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1711         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1712
1713         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1714                         pptable->dBtcGbGfxPll.a,
1715                         pptable->dBtcGbGfxPll.b,
1716                         pptable->dBtcGbGfxPll.c);
1717         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1718                         pptable->dBtcGbGfxAfll.a,
1719                         pptable->dBtcGbGfxAfll.b,
1720                         pptable->dBtcGbGfxAfll.c);
1721         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1722                         pptable->dBtcGbSoc.a,
1723                         pptable->dBtcGbSoc.b,
1724                         pptable->dBtcGbSoc.c);
1725
1726         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1727                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1728                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1729         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1730                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1731                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1732
1733         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1734                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1735                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1736                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1737         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1738                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1739                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1740                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1741
1742         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1743         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1744
1745         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1746         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1747         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1748         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1749
1750         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1751         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1752         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1753         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1754
1755         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1756         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1757
1758         pr_info("XgmiDpmPstates\n");
1759         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1760                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1761         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1762         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1763
1764         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1765         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1766         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1767         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1768         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1769         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1770         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1771         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1772
1773         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1774         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1775                         pptable->ReservedEquation0.a,
1776                         pptable->ReservedEquation0.b,
1777                         pptable->ReservedEquation0.c);
1778         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1779                         pptable->ReservedEquation1.a,
1780                         pptable->ReservedEquation1.b,
1781                         pptable->ReservedEquation1.c);
1782         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1783                         pptable->ReservedEquation2.a,
1784                         pptable->ReservedEquation2.b,
1785                         pptable->ReservedEquation2.c);
1786         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1787                         pptable->ReservedEquation3.a,
1788                         pptable->ReservedEquation3.b,
1789                         pptable->ReservedEquation3.c);
1790
1791         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1792         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1793
1794         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1795         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1796         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1797
1798         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1799         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1800
1801         pr_info("Board Parameters:\n");
1802         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1803         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1804
1805         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1806         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1807         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1808         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1809
1810         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1811         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1812
1813         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1814         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1815         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1816
1817         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1818         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1819         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1820
1821         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1822         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1823         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1824
1825         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1826         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1827         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1828
1829         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1830         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1831         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1832         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1833
1834         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1835         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1836         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1837
1838         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1839         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1840         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1841
1842         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1843         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1844         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1845
1846         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1847         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1848         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1849
1850         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1851                 pr_info("I2cControllers[%d]:\n", i);
1852                 pr_info("                   .Enabled = %d\n",
1853                                 pptable->I2cControllers[i].Enabled);
1854                 pr_info("                   .SlaveAddress = 0x%x\n",
1855                                 pptable->I2cControllers[i].SlaveAddress);
1856                 pr_info("                   .ControllerPort = %d\n",
1857                                 pptable->I2cControllers[i].ControllerPort);
1858                 pr_info("                   .ControllerName = %d\n",
1859                                 pptable->I2cControllers[i].ControllerName);
1860                 pr_info("                   .ThermalThrottler = %d\n",
1861                                 pptable->I2cControllers[i].ThermalThrotter);
1862                 pr_info("                   .I2cProtocol = %d\n",
1863                                 pptable->I2cControllers[i].I2cProtocol);
1864                 pr_info("                   .Speed = %d\n",
1865                                 pptable->I2cControllers[i].Speed);
1866         }
1867
1868         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1869         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1870
1871         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1872
1873         pr_info("XgmiLinkSpeed\n");
1874         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1875                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1876         pr_info("XgmiLinkWidth\n");
1877         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1878                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1879         pr_info("XgmiFclkFreq\n");
1880         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1881                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1882         pr_info("XgmiSocVoltage\n");
1883         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1884                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1885
1886 }
1887
1888 static bool arcturus_is_dpm_running(struct smu_context *smu)
1889 {
1890         int ret = 0;
1891         uint32_t feature_mask[2];
1892         unsigned long feature_enabled;
1893         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1894         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1895                            ((uint64_t)feature_mask[1] << 32));
1896         return !!(feature_enabled & SMC_DPM_FEATURE);
1897 }
1898
1899 static const struct pptable_funcs arcturus_ppt_funcs = {
1900         /* translate smu index into arcturus specific index */
1901         .get_smu_msg_index = arcturus_get_smu_msg_index,
1902         .get_smu_clk_index = arcturus_get_smu_clk_index,
1903         .get_smu_feature_index = arcturus_get_smu_feature_index,
1904         .get_smu_table_index = arcturus_get_smu_table_index,
1905         .get_smu_power_index= arcturus_get_pwr_src_index,
1906         .get_workload_type = arcturus_get_workload_type,
1907         /* internal structurs allocations */
1908         .tables_init = arcturus_tables_init,
1909         .alloc_dpm_context = arcturus_allocate_dpm_context,
1910         /* pptable related */
1911         .check_powerplay_table = arcturus_check_powerplay_table,
1912         .store_powerplay_table = arcturus_store_powerplay_table,
1913         .append_powerplay_table = arcturus_append_powerplay_table,
1914         /* init dpm */
1915         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1916         /* btc */
1917         .run_afll_btc = arcturus_run_btc_afll,
1918         /* dpm/clk tables */
1919         .set_default_dpm_table = arcturus_set_default_dpm_table,
1920         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1921         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1922         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1923         .print_clk_levels = arcturus_print_clk_levels,
1924         .force_clk_levels = arcturus_force_clk_levels,
1925         .read_sensor = arcturus_read_sensor,
1926         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1927         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1928         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
1929         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
1930         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
1931         .get_power_profile_mode = arcturus_get_power_profile_mode,
1932         .set_power_profile_mode = arcturus_set_power_profile_mode,
1933         /* debug (internal used) */
1934         .dump_pptable = arcturus_dump_pptable,
1935         .get_power_limit = arcturus_get_power_limit,
1936         .is_dpm_running = arcturus_is_dpm_running,
1937 };
1938
1939 void arcturus_set_ppt_funcs(struct smu_context *smu)
1940 {
1941         struct smu_table_context *smu_table = &smu->smu_table;
1942
1943         smu->ppt_funcs = &arcturus_ppt_funcs;
1944         smu_table->table_count = TABLE_COUNT;
1945 }