drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "atom.h"
  31
  32 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
  33                            bool gate)
  34 {
  35         int ret = 0;
  36
  37         switch (block_type) {
  38         case AMD_IP_BLOCK_TYPE_UVD:
  39                 ret = smu_dpm_set_uvd_enable(smu, gate);
  40                 break;
  41         case AMD_IP_BLOCK_TYPE_VCE:
  42                 ret = smu_dpm_set_vce_enable(smu, gate);
  43                 break;
  44         default:
  45                 break;
  46         }
  47
  48         return ret;
  49 }
  50
  51 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
  52 {
  53         /* not support power state */
  54         return POWER_STATE_TYPE_DEFAULT;
  55 }
  56
  57 int smu_get_power_num_states(struct smu_context *smu,
  58                              struct pp_states_info *state_info)
  59 {
  60         if (!state_info)
  61                 return -EINVAL;
  62
  63         /* not support power state */
  64         memset(state_info, 0, sizeof(struct pp_states_info));
  65         state_info->nums = 0;
  66
  67         return 0;
  68 }
  69
  70 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
  71                            void *data, uint32_t *size)
  72 {
  73         int ret = 0;
  74
  75         switch (sensor) {
  76         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
  77                 *((uint32_t *)data) = smu->pstate_sclk;
  78                 *size = 4;
  79                 break;
  80         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
  81                 *((uint32_t *)data) = smu->pstate_mclk;
  82                 *size = 4;
  83                 break;
  84         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
  85                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
  86                 *size = 8;
  87                 break;
  88         default:
  89                 ret = -EINVAL;
  90                 break;
  91         }
  92
  93         if (ret)
  94                 *size = 0;
  95
  96         return ret;
  97 }
  98
  99 int smu_update_table(struct smu_context *smu, uint32_t table_id,
 100                      void *table_data, bool drv2smu)
 101 {
 102         struct smu_table_context *smu_table = &smu->smu_table;
 103         struct smu_table *table = NULL;
 104         int ret = 0;
 105
 106         if (!table_data || table_id >= smu_table->table_count)
 107                 return -EINVAL;
 108
 109         table = &smu_table->tables[table_id];
 110
 111         if (drv2smu)
 112                 memcpy(table->cpu_addr, table_data, table->size);
 113
 114         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 115                                           upper_32_bits(table->mc_address));
 116         if (ret)
 117                 return ret;
 118         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 119                                           lower_32_bits(table->mc_address));
 120         if (ret)
 121                 return ret;
 122         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 123                                           SMU_MSG_TransferTableDram2Smu :
 124                                           SMU_MSG_TransferTableSmu2Dram,
 125                                           table_id);
 126         if (ret)
 127                 return ret;
 128
 129         if (!drv2smu)
 130                 memcpy(table_data, table->cpu_addr, table->size);
 131
 132         return ret;
 133 }
 134
 135 bool is_support_sw_smu(struct amdgpu_device *adev)
 136 {
 137         if (amdgpu_dpm != 1)
 138                 return false;
 139
 140         if (adev->asic_type >= CHIP_VEGA20)
 141                 return true;
 142
 143         return false;
 144 }
 145
 146 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 147 {
 148         struct smu_table_context *smu_table = &smu->smu_table;
 149
 150         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 151                 return -EINVAL;
 152
 153         if (smu_table->hardcode_pptable)
 154                 *table = smu_table->hardcode_pptable;
 155         else
 156                 *table = smu_table->power_play_table;
 157
 158         return smu_table->power_play_table_size;
 159 }
 160
 161 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 162 {
 163         struct smu_table_context *smu_table = &smu->smu_table;
 164         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 165         int ret = 0;
 166
 167         if (header->usStructureSize != size) {
 168                 pr_err("pp table size not matched !\n");
 169                 return -EIO;
 170         }
 171
 172         mutex_lock(&smu->mutex);
 173         if (!smu_table->hardcode_pptable)
 174                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 175         if (!smu_table->hardcode_pptable) {
 176                 ret = -ENOMEM;
 177                 goto failed;
 178         }
 179
 180         memcpy(smu_table->hardcode_pptable, buf, size);
 181         smu_table->power_play_table = smu_table->hardcode_pptable;
 182         smu_table->power_play_table_size = size;
 183         mutex_unlock(&smu->mutex);
 184
 185         ret = smu_reset(smu);
 186         if (ret)
 187                 pr_info("smu reset failed, ret = %d\n", ret);
 188
 189 failed:
 190         mutex_unlock(&smu->mutex);
 191         return ret;
 192 }
 193
 194 int smu_feature_init_dpm(struct smu_context *smu)
 195 {
 196         struct smu_feature *feature = &smu->smu_feature;
 197         int ret = 0;
 198         uint32_t unallowed_feature_mask[SMU_FEATURE_MAX/32];
 199
 200         mutex_lock(&feature->mutex);
 201         bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
 202         mutex_unlock(&feature->mutex);
 203
 204         ret = smu_get_unallowed_feature_mask(smu, unallowed_feature_mask,
 205                                              SMU_FEATURE_MAX/32);
 206         if (ret)
 207                 return ret;
 208
 209         mutex_lock(&feature->mutex);
 210         bitmap_andnot(feature->allowed, feature->allowed,
 211                       (unsigned long *)unallowed_feature_mask,
 212                       feature->feature_num);
 213         mutex_unlock(&feature->mutex);
 214
 215         return ret;
 216 }
 217
 218 int smu_feature_is_enabled(struct smu_context *smu, int feature_id)
 219 {
 220         struct smu_feature *feature = &smu->smu_feature;
 221         int ret = 0;
 222
 223         WARN_ON(feature_id > feature->feature_num);
 224
 225         mutex_lock(&feature->mutex);
 226         ret = test_bit(feature_id, feature->enabled);
 227         mutex_unlock(&feature->mutex);
 228
 229         return ret;
 230 }
 231
 232 int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable)
 233 {
 234         struct smu_feature *feature = &smu->smu_feature;
 235         int ret = 0;
 236
 237         WARN_ON(feature_id > feature->feature_num);
 238
 239         mutex_lock(&feature->mutex);
 240         ret = smu_feature_update_enable_state(smu, feature_id, enable);
 241         if (ret)
 242                 goto failed;
 243
 244         if (enable)
 245                 test_and_set_bit(feature_id, feature->enabled);
 246         else
 247                 test_and_clear_bit(feature_id, feature->enabled);
 248
 249 failed:
 250         mutex_unlock(&feature->mutex);
 251
 252         return ret;
 253 }
 254
 255 int smu_feature_is_supported(struct smu_context *smu, int feature_id)
 256 {
 257         struct smu_feature *feature = &smu->smu_feature;
 258         int ret = 0;
 259
 260         WARN_ON(feature_id > feature->feature_num);
 261
 262         mutex_lock(&feature->mutex);
 263         ret = test_bit(feature_id, feature->supported);
 264         mutex_unlock(&feature->mutex);
 265
 266         return ret;
 267 }
 268
 269 int smu_feature_set_supported(struct smu_context *smu, int feature_id,
 270                               bool enable)
 271 {
 272         struct smu_feature *feature = &smu->smu_feature;
 273         int ret = 0;
 274
 275         WARN_ON(feature_id > feature->feature_num);
 276
 277         mutex_unlock(&feature->mutex);
 278         if (enable)
 279                 test_and_set_bit(feature_id, feature->supported);
 280         else
 281                 test_and_clear_bit(feature_id, feature->supported);
 282         mutex_unlock(&feature->mutex);
 283
 284         return ret;
 285 }
 286
 287 static int smu_set_funcs(struct amdgpu_device *adev)
 288 {
 289         struct smu_context *smu = &adev->smu;
 290
 291         switch (adev->asic_type) {
 292         case CHIP_VEGA20:
 293                 smu_v11_0_set_smu_funcs(smu);
 294                 break;
 295         default:
 296                 return -EINVAL;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int smu_early_init(void *handle)
 303 {
 304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 305         struct smu_context *smu = &adev->smu;
 306
 307         smu->adev = adev;
 308         mutex_init(&smu->mutex);
 309
 310         return smu_set_funcs(adev);
 311 }
 312
 313 static int smu_late_init(void *handle)
 314 {
 315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 316         struct smu_context *smu = &adev->smu;
 317         mutex_lock(&smu->mutex);
 318         smu_handle_task(&adev->smu,
 319                         smu->smu_dpm.dpm_level,
 320                         AMD_PP_TASK_COMPLETE_INIT);
 321         mutex_unlock(&smu->mutex);
 322
 323         return 0;
 324 }
 325
 326 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 327                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 328                             uint8_t **addr)
 329 {
 330         struct amdgpu_device *adev = smu->adev;
 331         uint16_t data_start;
 332
 333         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 334                                            size, frev, crev, &data_start))
 335                 return -EINVAL;
 336
 337         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 338
 339         return 0;
 340 }
 341
 342 static int smu_initialize_pptable(struct smu_context *smu)
 343 {
 344         /* TODO */
 345         return 0;
 346 }
 347
 348 static int smu_smc_table_sw_init(struct smu_context *smu)
 349 {
 350         int ret;
 351
 352         ret = smu_initialize_pptable(smu);
 353         if (ret) {
 354                 pr_err("Failed to init smu_initialize_pptable!\n");
 355                 return ret;
 356         }
 357
 358         /**
 359          * Create smu_table structure, and init smc tables such as
 360          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 361          */
 362         ret = smu_init_smc_tables(smu);
 363         if (ret) {
 364                 pr_err("Failed to init smc tables!\n");
 365                 return ret;
 366         }
 367
 368         /**
 369          * Create smu_power_context structure, and allocate smu_dpm_context and
 370          * context size to fill the smu_power_context data.
 371          */
 372         ret = smu_init_power(smu);
 373         if (ret) {
 374                 pr_err("Failed to init smu_init_power!\n");
 375                 return ret;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int smu_smc_table_sw_fini(struct smu_context *smu)
 382 {
 383         int ret;
 384
 385         ret = smu_fini_smc_tables(smu);
 386         if (ret) {
 387                 pr_err("Failed to smu_fini_smc_tables!\n");
 388                 return ret;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int smu_sw_init(void *handle)
 395 {
 396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 397         struct smu_context *smu = &adev->smu;
 398         int ret;
 399
 400         if (!is_support_sw_smu(adev))
 401                 return -EINVAL;
 402
 403         smu->pool_size = adev->pm.smu_prv_buffer_size;
 404         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 405         mutex_init(&smu->smu_feature.mutex);
 406         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 407         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 408         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 409         smu->watermarks_bitmap = 0;
 410         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 411         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 412
 413         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 414         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 415         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 416         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 417         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 418         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 419         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 420         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 421
 422         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 423         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 424         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 425         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 426         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 427         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 428         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 429         smu->display_config = &adev->pm.pm_display_cfg;
 430
 431         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 432         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 433         ret = smu_init_microcode(smu);
 434         if (ret) {
 435                 pr_err("Failed to load smu firmware!\n");
 436                 return ret;
 437         }
 438
 439         ret = smu_smc_table_sw_init(smu);
 440         if (ret) {
 441                 pr_err("Failed to sw init smc table!\n");
 442                 return ret;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int smu_sw_fini(void *handle)
 449 {
 450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 451         struct smu_context *smu = &adev->smu;
 452         int ret;
 453
 454         if (!is_support_sw_smu(adev))
 455                 return -EINVAL;
 456
 457         ret = smu_smc_table_sw_fini(smu);
 458         if (ret) {
 459                 pr_err("Failed to sw fini smc table!\n");
 460                 return ret;
 461         }
 462
 463         ret = smu_fini_power(smu);
 464         if (ret) {
 465                 pr_err("Failed to init smu_fini_power!\n");
 466                 return ret;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int smu_init_fb_allocations(struct smu_context *smu)
 473 {
 474         struct amdgpu_device *adev = smu->adev;
 475         struct smu_table_context *smu_table = &smu->smu_table;
 476         struct smu_table *tables = smu_table->tables;
 477         uint32_t table_count = smu_table->table_count;
 478         uint32_t i = 0;
 479         int32_t ret = 0;
 480
 481         if (table_count <= 0)
 482                 return -EINVAL;
 483
 484         for (i = 0 ; i < table_count; i++) {
 485                 if (tables[i].size == 0)
 486                         continue;
 487                 ret = amdgpu_bo_create_kernel(adev,
 488                                               tables[i].size,
 489                                               tables[i].align,
 490                                               tables[i].domain,
 491                                               &tables[i].bo,
 492                                               &tables[i].mc_address,
 493                                               &tables[i].cpu_addr);
 494                 if (ret)
 495                         goto failed;
 496         }
 497
 498         return 0;
 499 failed:
 500         for (; i > 0; i--) {
 501                 if (tables[i].size == 0)
 502                         continue;
 503                 amdgpu_bo_free_kernel(&tables[i].bo,
 504                                       &tables[i].mc_address,
 505                                       &tables[i].cpu_addr);
 506
 507         }
 508         return ret;
 509 }
 510
 511 static int smu_fini_fb_allocations(struct smu_context *smu)
 512 {
 513         struct smu_table_context *smu_table = &smu->smu_table;
 514         struct smu_table *tables = smu_table->tables;
 515         uint32_t table_count = smu_table->table_count;
 516         uint32_t i = 0;
 517
 518         if (table_count == 0 || tables == NULL)
 519                 return 0;
 520
 521         for (i = 0 ; i < table_count; i++) {
 522                 if (tables[i].size == 0)
 523                         continue;
 524                 amdgpu_bo_free_kernel(&tables[i].bo,
 525                                       &tables[i].mc_address,
 526                                       &tables[i].cpu_addr);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static int smu_smc_table_hw_init(struct smu_context *smu)
 533 {
 534         int ret;
 535
 536         ret = smu_init_display(smu);
 537         if (ret)
 538                 return ret;
 539
 540         ret = smu_feature_set_allowed_mask(smu);
 541         if (ret)
 542                 return ret;
 543
 544         ret = smu_read_pptable_from_vbios(smu);
 545         if (ret)
 546                 return ret;
 547
 548         /* get boot_values from vbios to set revision, gfxclk, and etc. */
 549         ret = smu_get_vbios_bootup_values(smu);
 550         if (ret)
 551                 return ret;
 552
 553         ret = smu_get_clk_info_from_vbios(smu);
 554         if (ret)
 555                 return ret;
 556
 557         /*
 558          * check if the format_revision in vbios is up to pptable header
 559          * version, and the structure size is not 0.
 560          */
 561         ret = smu_get_clk_info_from_vbios(smu);
 562         if (ret)
 563                 return ret;
 564
 565         ret = smu_check_pptable(smu);
 566         if (ret)
 567                 return ret;
 568
 569         /*
 570          * allocate vram bos to store smc table contents.
 571          */
 572         ret = smu_init_fb_allocations(smu);
 573         if (ret)
 574                 return ret;
 575
 576         /*
 577          * Parse pptable format and fill PPTable_t smc_pptable to
 578          * smu_table_context structure. And read the smc_dpm_table from vbios,
 579          * then fill it into smc_pptable.
 580          */
 581         ret = smu_parse_pptable(smu);
 582         if (ret)
 583                 return ret;
 584
 585         /*
 586          * Send msg GetDriverIfVersion to check if the return value is equal
 587          * with DRIVER_IF_VERSION of smc header.
 588          */
 589         ret = smu_check_fw_version(smu);
 590         if (ret)
 591                 return ret;
 592
 593         /*
 594          * Copy pptable bo in the vram to smc with SMU MSGs such as
 595          * SetDriverDramAddr and TransferTableDram2Smu.
 596          */
 597         ret = smu_write_pptable(smu);
 598         if (ret)
 599                 return ret;
 600
 601         /* issue RunAfllBtc msg */
 602         ret = smu_run_afll_btc(smu);
 603         if (ret)
 604                 return ret;
 605
 606         ret = smu_feature_enable_all(smu);
 607         if (ret)
 608                 return ret;
 609
 610         ret = smu_notify_display_change(smu);
 611         if (ret)
 612                 return ret;
 613
 614         /*
 615          * Set min deep sleep dce fclk with bootup value from vbios via
 616          * SetMinDeepSleepDcefclk MSG.
 617          */
 618         ret = smu_set_min_dcef_deep_sleep(smu);
 619         if (ret)
 620                 return ret;
 621
 622         /*
 623          * Set initialized values (get from vbios) to dpm tables context such as
 624          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 625          * type of clks.
 626          */
 627         ret = smu_populate_smc_pptable(smu);
 628         if (ret)
 629                 return ret;
 630
 631         ret = smu_init_max_sustainable_clocks(smu);
 632         if (ret)
 633                 return ret;
 634
 635         ret = smu_set_od8_default_settings(smu);
 636         if (ret)
 637                 return ret;
 638
 639         ret = smu_populate_umd_state_clk(smu);
 640         if (ret)
 641                 return ret;
 642
 643         ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 644         if (ret)
 645                 return ret;
 646
 647         /*
 648          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 649          */
 650         ret = smu_set_tool_table_location(smu);
 651
 652         return ret;
 653 }
 654
 655 /**
 656  * smu_alloc_memory_pool - allocate memory pool in the system memory
 657  *
 658  * @smu: amdgpu_device pointer
 659  *
 660  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 661  * and DramLogSetDramAddr can notify it changed.
 662  *
 663  * Returns 0 on success, error on failure.
 664  */
 665 static int smu_alloc_memory_pool(struct smu_context *smu)
 666 {
 667         struct amdgpu_device *adev = smu->adev;
 668         struct smu_table_context *smu_table = &smu->smu_table;
 669         struct smu_table *memory_pool = &smu_table->memory_pool;
 670         uint64_t pool_size = smu->pool_size;
 671         int ret = 0;
 672
 673         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 674                 return ret;
 675
 676         memory_pool->size = pool_size;
 677         memory_pool->align = PAGE_SIZE;
 678         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 679
 680         switch (pool_size) {
 681         case SMU_MEMORY_POOL_SIZE_256_MB:
 682         case SMU_MEMORY_POOL_SIZE_512_MB:
 683         case SMU_MEMORY_POOL_SIZE_1_GB:
 684         case SMU_MEMORY_POOL_SIZE_2_GB:
 685                 ret = amdgpu_bo_create_kernel(adev,
 686                                               memory_pool->size,
 687                                               memory_pool->align,
 688                                               memory_pool->domain,
 689                                               &memory_pool->bo,
 690                                               &memory_pool->mc_address,
 691                                               &memory_pool->cpu_addr);
 692                 break;
 693         default:
 694                 break;
 695         }
 696
 697         return ret;
 698 }
 699
 700 static int smu_free_memory_pool(struct smu_context *smu)
 701 {
 702         struct smu_table_context *smu_table = &smu->smu_table;
 703         struct smu_table *memory_pool = &smu_table->memory_pool;
 704         int ret = 0;
 705
 706         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 707                 return ret;
 708
 709         amdgpu_bo_free_kernel(&memory_pool->bo,
 710                               &memory_pool->mc_address,
 711                               &memory_pool->cpu_addr);
 712
 713         memset(memory_pool, 0, sizeof(struct smu_table));
 714
 715         return ret;
 716 }
 717 static int smu_hw_init(void *handle)
 718 {
 719         int ret;
 720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 721         struct smu_context *smu = &adev->smu;
 722
 723         if (!is_support_sw_smu(adev))
 724                 return -EINVAL;
 725
 726         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 727                 ret = smu_load_microcode(smu);
 728                 if (ret)
 729                         return ret;
 730         }
 731
 732         ret = smu_check_fw_status(smu);
 733         if (ret) {
 734                 pr_err("SMC firmware status is not correct\n");
 735                 return ret;
 736         }
 737
 738         mutex_lock(&smu->mutex);
 739
 740         ret = smu_feature_init_dpm(smu);
 741         if (ret)
 742                 goto failed;
 743
 744         ret = smu_smc_table_hw_init(smu);
 745         if (ret)
 746                 goto failed;
 747
 748         ret = smu_alloc_memory_pool(smu);
 749         if (ret)
 750                 goto failed;
 751
 752         /*
 753          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 754          * pool location.
 755          */
 756         ret = smu_notify_memory_pool_location(smu);
 757         if (ret)
 758                 goto failed;
 759
 760         ret = smu_start_thermal_control(smu);
 761         if (ret)
 762                 goto failed;
 763
 764         mutex_unlock(&smu->mutex);
 765
 766         adev->pm.dpm_enabled = true;
 767
 768         pr_info("SMU is initialized successfully!\n");
 769
 770         return 0;
 771
 772 failed:
 773         mutex_unlock(&smu->mutex);
 774         return ret;
 775 }
 776
 777 static int smu_hw_fini(void *handle)
 778 {
 779         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 780         struct smu_context *smu = &adev->smu;
 781         struct smu_table_context *table_context = &smu->smu_table;
 782         int ret = 0;
 783
 784         if (!is_support_sw_smu(adev))
 785                 return -EINVAL;
 786
 787         kfree(table_context->driver_pptable);
 788         table_context->driver_pptable = NULL;
 789
 790         kfree(table_context->max_sustainable_clocks);
 791         table_context->max_sustainable_clocks = NULL;
 792
 793         kfree(table_context->od_feature_capabilities);
 794         table_context->od_feature_capabilities = NULL;
 795
 796         kfree(table_context->od_settings_max);
 797         table_context->od_settings_max = NULL;
 798
 799         kfree(table_context->od_settings_min);
 800         table_context->od_settings_min = NULL;
 801
 802         kfree(table_context->overdrive_table);
 803         table_context->overdrive_table = NULL;
 804
 805         kfree(table_context->od8_settings);
 806         table_context->od8_settings = NULL;
 807
 808         ret = smu_fini_fb_allocations(smu);
 809         if (ret)
 810                 return ret;
 811
 812         ret = smu_free_memory_pool(smu);
 813         if (ret)
 814                 return ret;
 815
 816         return 0;
 817 }
 818
 819 int smu_reset(struct smu_context *smu)
 820 {
 821         struct amdgpu_device *adev = smu->adev;
 822         int ret = 0;
 823
 824         ret = smu_hw_fini(adev);
 825         if (ret)
 826                 return ret;
 827
 828         ret = smu_hw_init(adev);
 829         if (ret)
 830                 return ret;
 831
 832         return ret;
 833 }
 834
 835 static int smu_suspend(void *handle)
 836 {
 837         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 838
 839         if (!is_support_sw_smu(adev))
 840                 return -EINVAL;
 841
 842         return 0;
 843 }
 844
 845 static int smu_resume(void *handle)
 846 {
 847         int ret;
 848         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 849         struct smu_context *smu = &adev->smu;
 850
 851         if (!is_support_sw_smu(adev))
 852                 return -EINVAL;
 853
 854         pr_info("SMU is resuming...\n");
 855
 856         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 857                 ret = smu_load_microcode(smu);
 858                 if (ret)
 859                         return ret;
 860         }
 861
 862         ret = smu_check_fw_status(smu);
 863         if (ret) {
 864                 pr_err("SMC firmware status is not correct\n");
 865                 return ret;
 866         }
 867
 868         mutex_lock(&smu->mutex);
 869
 870         ret = smu_set_tool_table_location(smu);
 871         if (ret)
 872                 goto failed;
 873
 874         ret = smu_write_pptable(smu);
 875         if (ret)
 876                 goto failed;
 877
 878         ret = smu_write_watermarks_table(smu);
 879         if (ret)
 880                 goto failed;
 881
 882         ret = smu_set_last_dcef_min_deep_sleep_clk(smu);
 883         if (ret)
 884                 goto failed;
 885
 886         ret = smu_system_features_control(smu, true);
 887         if (ret)
 888                 goto failed;
 889
 890         mutex_unlock(&smu->mutex);
 891
 892         pr_info("SMU is resumed successfully!\n");
 893
 894         return 0;
 895 failed:
 896         mutex_unlock(&smu->mutex);
 897         return ret;
 898 }
 899
 900 int smu_display_configuration_change(struct smu_context *smu,
 901                                      const struct amd_pp_display_configuration *display_config)
 902 {
 903         int index = 0;
 904         int num_of_active_display = 0;
 905
 906         if (!is_support_sw_smu(smu->adev))
 907                 return -EINVAL;
 908
 909         if (!display_config)
 910                 return -EINVAL;
 911
 912         mutex_lock(&smu->mutex);
 913
 914         smu_set_deep_sleep_dcefclk(smu,
 915                                    display_config->min_dcef_deep_sleep_set_clk / 100);
 916
 917         for (index = 0; index < display_config->num_path_including_non_display; index++) {
 918                 if (display_config->displays[index].controller_id != 0)
 919                         num_of_active_display++;
 920         }
 921
 922         smu_set_active_display_count(smu, num_of_active_display);
 923
 924         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
 925                            display_config->cpu_cc6_disable,
 926                            display_config->cpu_pstate_disable,
 927                            display_config->nb_pstate_switch_disable);
 928
 929         mutex_unlock(&smu->mutex);
 930
 931         return 0;
 932 }
 933
 934 static int smu_get_clock_info(struct smu_context *smu,
 935                               struct smu_clock_info *clk_info,
 936                               enum smu_perf_level_designation designation)
 937 {
 938         int ret;
 939         struct smu_performance_level level = {0};
 940
 941         if (!clk_info)
 942                 return -EINVAL;
 943
 944         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
 945         if (ret)
 946                 return -EINVAL;
 947
 948         clk_info->min_mem_clk = level.memory_clock;
 949         clk_info->min_eng_clk = level.core_clock;
 950         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
 951
 952         ret = smu_get_perf_level(smu, designation, &level);
 953         if (ret)
 954                 return -EINVAL;
 955
 956         clk_info->min_mem_clk = level.memory_clock;
 957         clk_info->min_eng_clk = level.core_clock;
 958         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
 959
 960         return 0;
 961 }
 962
 963 int smu_get_current_clocks(struct smu_context *smu,
 964                            struct amd_pp_clock_info *clocks)
 965 {
 966         struct amd_pp_simple_clock_info simple_clocks = {0};
 967         struct smu_clock_info hw_clocks;
 968         int ret = 0;
 969
 970         if (!is_support_sw_smu(smu->adev))
 971                 return -EINVAL;
 972
 973         mutex_lock(&smu->mutex);
 974
 975         smu_get_dal_power_level(smu, &simple_clocks);
 976
 977         if (smu->support_power_containment)
 978                 ret = smu_get_clock_info(smu, &hw_clocks,
 979                                          PERF_LEVEL_POWER_CONTAINMENT);
 980         else
 981                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
 982
 983         if (ret) {
 984                 pr_err("Error in smu_get_clock_info\n");
 985                 goto failed;
 986         }
 987
 988         clocks->min_engine_clock = hw_clocks.min_eng_clk;
 989         clocks->max_engine_clock = hw_clocks.max_eng_clk;
 990         clocks->min_memory_clock = hw_clocks.min_mem_clk;
 991         clocks->max_memory_clock = hw_clocks.max_mem_clk;
 992         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
 993         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
 994         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 995         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 996
 997         if (simple_clocks.level == 0)
 998                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
 999         else
1000                 clocks->max_clocks_state = simple_clocks.level;
1001
1002         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1003                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1004                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1005         }
1006
1007 failed:
1008         mutex_unlock(&smu->mutex);
1009         return ret;
1010 }
1011
1012 static int smu_set_clockgating_state(void *handle,
1013                                      enum amd_clockgating_state state)
1014 {
1015         return 0;
1016 }
1017
1018 static int smu_set_powergating_state(void *handle,
1019                                      enum amd_powergating_state state)
1020 {
1021         return 0;
1022 }
1023
1024 static int smu_enable_umd_pstate(void *handle,
1025                       enum amd_dpm_forced_level *level)
1026 {
1027         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1028                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1029                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1030                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1031
1032         struct smu_context *smu = (struct smu_context*)(handle);
1033         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1034         if (!smu_dpm_ctx->dpm_context)
1035                 return -EINVAL;
1036
1037         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1038                 /* enter umd pstate, save current level, disable gfx cg*/
1039                 if (*level & profile_mode_mask) {
1040                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1041                         smu_dpm_ctx->enable_umd_pstate = true;
1042                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1043                                                                AMD_IP_BLOCK_TYPE_GFX,
1044                                                                AMD_CG_STATE_UNGATE);
1045                         amdgpu_device_ip_set_powergating_state(smu->adev,
1046                                                                AMD_IP_BLOCK_TYPE_GFX,
1047                                                                AMD_PG_STATE_UNGATE);
1048                 }
1049         } else {
1050                 /* exit umd pstate, restore level, enable gfx cg*/
1051                 if (!(*level & profile_mode_mask)) {
1052                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1053                                 *level = smu_dpm_ctx->saved_dpm_level;
1054                         smu_dpm_ctx->enable_umd_pstate = false;
1055                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1056                                                                AMD_IP_BLOCK_TYPE_GFX,
1057                                                                AMD_CG_STATE_GATE);
1058                         amdgpu_device_ip_set_powergating_state(smu->adev,
1059                                                                AMD_IP_BLOCK_TYPE_GFX,
1060                                                                AMD_PG_STATE_GATE);
1061                 }
1062         }
1063
1064         return 0;
1065 }
1066
1067 int smu_unforce_dpm_levels(struct smu_context *smu)
1068 {
1069         int ret = 0;
1070
1071         ret = smu_upload_dpm_level(smu, false);
1072         if (ret) {
1073                 pr_err("Failed to upload DPM Bootup Levels!");
1074                 return ret;
1075         }
1076
1077         ret = smu_upload_dpm_level(smu, true);
1078         if (ret) {
1079                 pr_err("Failed to upload DPM Max Levels!");
1080                 return ret;
1081         }
1082
1083         return ret;
1084 }
1085
1086 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1087                                    enum amd_dpm_forced_level level,
1088                                    bool skip_display_settings)
1089 {
1090         int ret = 0;
1091         int index = 0;
1092         uint32_t sclk_mask, mclk_mask, soc_mask;
1093         long workload;
1094         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1095
1096         if (!skip_display_settings) {
1097                 ret = smu_display_config_changed(smu);
1098                 if (ret) {
1099                         pr_err("Failed to change display config!");
1100                         return ret;
1101                 }
1102         }
1103
1104         ret = smu_apply_clocks_adjust_rules(smu);
1105         if (ret) {
1106                 pr_err("Failed to apply clocks adjust rules!");
1107                 return ret;
1108         }
1109
1110         if (!skip_display_settings) {
1111                 ret = smu_notify_smc_dispaly_config(smu);
1112                 if (ret) {
1113                         pr_err("Failed to notify smc display config!");
1114                         return ret;
1115                 }
1116         }
1117
1118         if (smu_dpm_ctx->dpm_level != level) {
1119                 switch (level) {
1120                 case AMD_DPM_FORCED_LEVEL_HIGH:
1121                         ret = smu_force_dpm_limit_value(smu, true);
1122                         break;
1123                 case AMD_DPM_FORCED_LEVEL_LOW:
1124                         ret = smu_force_dpm_limit_value(smu, false);
1125                         break;
1126
1127                 case AMD_DPM_FORCED_LEVEL_AUTO:
1128                         ret = smu_unforce_dpm_levels(smu);
1129                         break;
1130
1131                 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1132                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1133                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1134                 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1135                         ret = smu_get_profiling_clk_mask(smu, level,
1136                                                          &sclk_mask,
1137                                                          &mclk_mask,
1138                                                          &soc_mask);
1139                         if (ret)
1140                                 return ret;
1141                         smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
1142                         smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
1143                         break;
1144
1145                 case AMD_DPM_FORCED_LEVEL_MANUAL:
1146                 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1147                 default:
1148                         break;
1149                 }
1150
1151                 if (!ret)
1152                         smu_dpm_ctx->dpm_level = level;
1153         }
1154
1155         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1156                 index = fls(smu->workload_mask);
1157                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1158                 workload = smu->workload_setting[index];
1159
1160                 if (smu->power_profile_mode != workload)
1161                         smu_set_power_profile_mode(smu, &workload, 0);
1162         }
1163
1164         return ret;
1165 }
1166
1167 int smu_handle_task(struct smu_context *smu,
1168                     enum amd_dpm_forced_level level,
1169                     enum amd_pp_task task_id)
1170 {
1171         int ret = 0;
1172
1173         switch (task_id) {
1174         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1175                 ret = smu_pre_display_config_changed(smu);
1176                 if (ret)
1177                         return ret;
1178                 ret = smu_set_cpu_power_state(smu);
1179                 if (ret)
1180                         return ret;
1181                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1182                 break;
1183         case AMD_PP_TASK_COMPLETE_INIT:
1184         case AMD_PP_TASK_READJUST_POWER_STATE:
1185                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1186                 break;
1187         default:
1188                 break;
1189         }
1190
1191         return ret;
1192 }
1193
1194 const struct amd_ip_funcs smu_ip_funcs = {
1195         .name = "smu",
1196         .early_init = smu_early_init,
1197         .late_init = smu_late_init,
1198         .sw_init = smu_sw_init,
1199         .sw_fini = smu_sw_fini,
1200         .hw_init = smu_hw_init,
1201         .hw_fini = smu_hw_fini,
1202         .suspend = smu_suspend,
1203         .resume = smu_resume,
1204         .is_idle = NULL,
1205         .check_soft_reset = NULL,
1206         .wait_for_idle = NULL,
1207         .soft_reset = NULL,
1208         .set_clockgating_state = smu_set_clockgating_state,
1209         .set_powergating_state = smu_set_powergating_state,
1210         .enable_umd_pstate = smu_enable_umd_pstate,
1211 };
1212
1213 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1214 {
1215         .type = AMD_IP_BLOCK_TYPE_SMC,
1216         .major = 11,
1217         .minor = 0,
1218         .rev = 0,
1219         .funcs = &smu_ip_funcs,
1220 };