drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         mutex_lock(&feature->mutex);
 365         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 366         mutex_unlock(&feature->mutex);
 367
 368         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 369                                              SMU_FEATURE_MAX/32);
 370         if (ret)
 371                 return ret;
 372
 373         mutex_lock(&feature->mutex);
 374         bitmap_or(feature->allowed, feature->allowed,
 375                       (unsigned long *)allowed_feature_mask,
 376                       feature->feature_num);
 377         mutex_unlock(&feature->mutex);
 378
 379         return ret;
 380 }
 381
 382 static int smu_set_funcs(struct amdgpu_device *adev)
 383 {
 384         struct smu_context *smu = &adev->smu;
 385
 386         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 387                 smu->od_enabled = true;
 388
 389         switch (adev->asic_type) {
 390         case CHIP_NAVI10:
 391         case CHIP_NAVI14:
 392         case CHIP_NAVI12:
 393                 navi10_set_ppt_funcs(smu);
 394                 break;
 395         case CHIP_ARCTURUS:
 396                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 397                 arcturus_set_ppt_funcs(smu);
 398                 /* OD is not supported on Arcturus */
 399                 smu->od_enabled =false;
 400                 break;
 401         case CHIP_SIENNA_CICHLID:
 402         case CHIP_NAVY_FLOUNDER:
 403                 sienna_cichlid_set_ppt_funcs(smu);
 404                 break;
 405         case CHIP_RENOIR:
 406                 renoir_set_ppt_funcs(smu);
 407                 break;
 408         default:
 409                 return -EINVAL;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int smu_early_init(void *handle)
 416 {
 417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 418         struct smu_context *smu = &adev->smu;
 419
 420         smu->adev = adev;
 421         smu->pm_enabled = !!amdgpu_dpm;
 422         smu->is_apu = false;
 423         mutex_init(&smu->mutex);
 424
 425         return smu_set_funcs(adev);
 426 }
 427
 428 static int smu_set_default_dpm_table(struct smu_context *smu)
 429 {
 430         struct smu_power_context *smu_power = &smu->smu_power;
 431         struct smu_power_gate *power_gate = &smu_power->power_gate;
 432         int vcn_gate, jpeg_gate;
 433         int ret = 0;
 434
 435         if (!smu->ppt_funcs->set_default_dpm_table)
 436                 return 0;
 437
 438         mutex_lock(&power_gate->vcn_gate_lock);
 439         mutex_lock(&power_gate->jpeg_gate_lock);
 440
 441         vcn_gate = atomic_read(&power_gate->vcn_gated);
 442         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 443
 444         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 445         if (ret)
 446                 goto err0_out;
 447
 448         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 449         if (ret)
 450                 goto err1_out;
 451
 452         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 453         if (ret)
 454                 dev_err(smu->adev->dev,
 455                         "Failed to setup default dpm clock tables!\n");
 456
 457         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 458 err1_out:
 459         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 460 err0_out:
 461         mutex_unlock(&power_gate->jpeg_gate_lock);
 462         mutex_unlock(&power_gate->vcn_gate_lock);
 463
 464         return ret;
 465 }
 466
 467 static int smu_late_init(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470         struct smu_context *smu = &adev->smu;
 471         int ret = 0;
 472
 473         if (!smu->pm_enabled)
 474                 return 0;
 475
 476         ret = smu_set_default_od_settings(smu);
 477         if (ret) {
 478                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 479                 return ret;
 480         }
 481
 482         ret = smu_populate_umd_state_clk(smu);
 483         if (ret) {
 484                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 485                 return ret;
 486         }
 487
 488         ret = smu_get_asic_power_limits(smu);
 489         if (ret) {
 490                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 491                 return ret;
 492         }
 493
 494         smu_get_unique_id(smu);
 495
 496         smu_handle_task(&adev->smu,
 497                         smu->smu_dpm.dpm_level,
 498                         AMD_PP_TASK_COMPLETE_INIT,
 499                         false);
 500
 501         return 0;
 502 }
 503
 504 static int smu_init_fb_allocations(struct smu_context *smu)
 505 {
 506         struct amdgpu_device *adev = smu->adev;
 507         struct smu_table_context *smu_table = &smu->smu_table;
 508         struct smu_table *tables = smu_table->tables;
 509         struct smu_table *driver_table = &(smu_table->driver_table);
 510         uint32_t max_table_size = 0;
 511         int ret, i;
 512
 513         /* VRAM allocation for tool table */
 514         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 515                 ret = amdgpu_bo_create_kernel(adev,
 516                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 517                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 518                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 519                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 520                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 521                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 522                 if (ret) {
 523                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 524                         return ret;
 525                 }
 526         }
 527
 528         /* VRAM allocation for driver table */
 529         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 530                 if (tables[i].size == 0)
 531                         continue;
 532
 533                 if (i == SMU_TABLE_PMSTATUSLOG)
 534                         continue;
 535
 536                 if (max_table_size < tables[i].size)
 537                         max_table_size = tables[i].size;
 538         }
 539
 540         driver_table->size = max_table_size;
 541         driver_table->align = PAGE_SIZE;
 542         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 543
 544         ret = amdgpu_bo_create_kernel(adev,
 545                                       driver_table->size,
 546                                       driver_table->align,
 547                                       driver_table->domain,
 548                                       &driver_table->bo,
 549                                       &driver_table->mc_address,
 550                                       &driver_table->cpu_addr);
 551         if (ret) {
 552                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 553                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 554                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 555                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 556                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 557         }
 558
 559         return ret;
 560 }
 561
 562 static int smu_fini_fb_allocations(struct smu_context *smu)
 563 {
 564         struct smu_table_context *smu_table = &smu->smu_table;
 565         struct smu_table *tables = smu_table->tables;
 566         struct smu_table *driver_table = &(smu_table->driver_table);
 567
 568         if (!tables)
 569                 return 0;
 570
 571         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 572                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 573                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 574                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 575
 576         amdgpu_bo_free_kernel(&driver_table->bo,
 577                               &driver_table->mc_address,
 578                               &driver_table->cpu_addr);
 579
 580         return 0;
 581 }
 582
 583 /**
 584  * smu_alloc_memory_pool - allocate memory pool in the system memory
 585  *
 586  * @smu: amdgpu_device pointer
 587  *
 588  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 589  * and DramLogSetDramAddr can notify it changed.
 590  *
 591  * Returns 0 on success, error on failure.
 592  */
 593 static int smu_alloc_memory_pool(struct smu_context *smu)
 594 {
 595         struct amdgpu_device *adev = smu->adev;
 596         struct smu_table_context *smu_table = &smu->smu_table;
 597         struct smu_table *memory_pool = &smu_table->memory_pool;
 598         uint64_t pool_size = smu->pool_size;
 599         int ret = 0;
 600
 601         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 602                 return ret;
 603
 604         memory_pool->size = pool_size;
 605         memory_pool->align = PAGE_SIZE;
 606         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 607
 608         switch (pool_size) {
 609         case SMU_MEMORY_POOL_SIZE_256_MB:
 610         case SMU_MEMORY_POOL_SIZE_512_MB:
 611         case SMU_MEMORY_POOL_SIZE_1_GB:
 612         case SMU_MEMORY_POOL_SIZE_2_GB:
 613                 ret = amdgpu_bo_create_kernel(adev,
 614                                               memory_pool->size,
 615                                               memory_pool->align,
 616                                               memory_pool->domain,
 617                                               &memory_pool->bo,
 618                                               &memory_pool->mc_address,
 619                                               &memory_pool->cpu_addr);
 620                 if (ret)
 621                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 622                 break;
 623         default:
 624                 break;
 625         }
 626
 627         return ret;
 628 }
 629
 630 static int smu_free_memory_pool(struct smu_context *smu)
 631 {
 632         struct smu_table_context *smu_table = &smu->smu_table;
 633         struct smu_table *memory_pool = &smu_table->memory_pool;
 634
 635         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 636                 return 0;
 637
 638         amdgpu_bo_free_kernel(&memory_pool->bo,
 639                               &memory_pool->mc_address,
 640                               &memory_pool->cpu_addr);
 641
 642         memset(memory_pool, 0, sizeof(struct smu_table));
 643
 644         return 0;
 645 }
 646
 647 static int smu_smc_table_sw_init(struct smu_context *smu)
 648 {
 649         int ret;
 650
 651         /**
 652          * Create smu_table structure, and init smc tables such as
 653          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 654          */
 655         ret = smu_init_smc_tables(smu);
 656         if (ret) {
 657                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 658                 return ret;
 659         }
 660
 661         /**
 662          * Create smu_power_context structure, and allocate smu_dpm_context and
 663          * context size to fill the smu_power_context data.
 664          */
 665         ret = smu_init_power(smu);
 666         if (ret) {
 667                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 668                 return ret;
 669         }
 670
 671         /*
 672          * allocate vram bos to store smc table contents.
 673          */
 674         ret = smu_init_fb_allocations(smu);
 675         if (ret)
 676                 return ret;
 677
 678         ret = smu_alloc_memory_pool(smu);
 679         if (ret)
 680                 return ret;
 681
 682         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 683         if (ret)
 684                 return ret;
 685
 686         return 0;
 687 }
 688
 689 static int smu_smc_table_sw_fini(struct smu_context *smu)
 690 {
 691         int ret;
 692
 693         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 694
 695         ret = smu_free_memory_pool(smu);
 696         if (ret)
 697                 return ret;
 698
 699         ret = smu_fini_fb_allocations(smu);
 700         if (ret)
 701                 return ret;
 702
 703         ret = smu_fini_power(smu);
 704         if (ret) {
 705                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 706                 return ret;
 707         }
 708
 709         ret = smu_fini_smc_tables(smu);
 710         if (ret) {
 711                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 712                 return ret;
 713         }
 714
 715         return 0;
 716 }
 717
 718 static void smu_throttling_logging_work_fn(struct work_struct *work)
 719 {
 720         struct smu_context *smu = container_of(work, struct smu_context,
 721                                                throttling_logging_work);
 722
 723         smu_log_thermal_throttling(smu);
 724 }
 725
 726 static int smu_sw_init(void *handle)
 727 {
 728         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 729         struct smu_context *smu = &adev->smu;
 730         int ret;
 731
 732         smu->pool_size = adev->pm.smu_prv_buffer_size;
 733         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 734         mutex_init(&smu->smu_feature.mutex);
 735         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 736         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 737         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 738
 739         mutex_init(&smu->smu_baco.mutex);
 740         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 741         smu->smu_baco.platform_support = false;
 742
 743         mutex_init(&smu->sensor_lock);
 744         mutex_init(&smu->metrics_lock);
 745         mutex_init(&smu->message_lock);
 746
 747         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 748         smu->watermarks_bitmap = 0;
 749         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 750         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 751
 752         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 753         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 754         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 755         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 756
 757         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 758         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 759         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 760         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 761         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 762         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 763         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 764         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 765
 766         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 767         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 768         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 769         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 770         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 771         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 772         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 773         smu->display_config = &adev->pm.pm_display_cfg;
 774
 775         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 776         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 777         ret = smu_init_microcode(smu);
 778         if (ret) {
 779                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 780                 return ret;
 781         }
 782
 783         ret = smu_smc_table_sw_init(smu);
 784         if (ret) {
 785                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 786                 return ret;
 787         }
 788
 789         ret = smu_register_irq_handler(smu);
 790         if (ret) {
 791                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 792                 return ret;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int smu_sw_fini(void *handle)
 799 {
 800         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 801         struct smu_context *smu = &adev->smu;
 802         int ret;
 803
 804         ret = smu_smc_table_sw_fini(smu);
 805         if (ret) {
 806                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 807                 return ret;
 808         }
 809
 810         smu_fini_microcode(smu);
 811
 812         return 0;
 813 }
 814
 815 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 816 {
 817         struct amdgpu_device *adev = smu->adev;
 818         struct smu_temperature_range *range =
 819                                 &smu->thermal_range;
 820         int ret = 0;
 821
 822         if (!smu->ppt_funcs->get_thermal_temperature_range)
 823                 return 0;
 824
 825         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 826         if (ret)
 827                 return ret;
 828
 829         adev->pm.dpm.thermal.min_temp = range->min;
 830         adev->pm.dpm.thermal.max_temp = range->max;
 831         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 832         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 833         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 834         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 835         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 836         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 837         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 838
 839         return ret;
 840 }
 841
 842 static int smu_smc_hw_setup(struct smu_context *smu)
 843 {
 844         struct amdgpu_device *adev = smu->adev;
 845         uint32_t pcie_gen = 0, pcie_width = 0;
 846         int ret;
 847
 848         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 849                 dev_info(adev->dev, "dpm has been enabled\n");
 850                 return 0;
 851         }
 852
 853         ret = smu_init_display_count(smu, 0);
 854         if (ret) {
 855                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 856                 return ret;
 857         }
 858
 859         ret = smu_set_driver_table_location(smu);
 860         if (ret) {
 861                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 862                 return ret;
 863         }
 864
 865         /*
 866          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 867          */
 868         ret = smu_set_tool_table_location(smu);
 869         if (ret) {
 870                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 871                 return ret;
 872         }
 873
 874         /*
 875          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 876          * pool location.
 877          */
 878         ret = smu_notify_memory_pool_location(smu);
 879         if (ret) {
 880                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 881                 return ret;
 882         }
 883
 884         /* smu_dump_pptable(smu); */
 885         /*
 886          * Copy pptable bo in the vram to smc with SMU MSGs such as
 887          * SetDriverDramAddr and TransferTableDram2Smu.
 888          */
 889         ret = smu_write_pptable(smu);
 890         if (ret) {
 891                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 892                 return ret;
 893         }
 894
 895         /* issue Run*Btc msg */
 896         ret = smu_run_btc(smu);
 897         if (ret)
 898                 return ret;
 899
 900         ret = smu_feature_set_allowed_mask(smu);
 901         if (ret) {
 902                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 903                 return ret;
 904         }
 905
 906         ret = smu_system_features_control(smu, true);
 907         if (ret) {
 908                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 909                 return ret;
 910         }
 911
 912         if (!smu_is_dpm_running(smu))
 913                 dev_info(adev->dev, "dpm has been disabled\n");
 914
 915         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 916                 pcie_gen = 3;
 917         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 918                 pcie_gen = 2;
 919         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 920                 pcie_gen = 1;
 921         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 922                 pcie_gen = 0;
 923
 924         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 925          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 926          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 927          */
 928         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 929                 pcie_width = 6;
 930         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 931                 pcie_width = 5;
 932         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 933                 pcie_width = 4;
 934         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 935                 pcie_width = 3;
 936         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 937                 pcie_width = 2;
 938         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 939                 pcie_width = 1;
 940         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 941         if (ret) {
 942                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
 943                 return ret;
 944         }
 945
 946         ret = smu_get_thermal_temperature_range(smu);
 947         if (ret) {
 948                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
 949                 return ret;
 950         }
 951
 952         ret = smu_enable_thermal_alert(smu);
 953         if (ret) {
 954                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
 955                 return ret;
 956         }
 957
 958         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
 959         if (ret) {
 960                 dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
 961                 return ret;
 962         }
 963
 964         /*
 965          * For Navi1X, manually switch it to AC mode as PMFW
 966          * may boot it with DC mode.
 967          */
 968         ret = smu_set_power_source(smu,
 969                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
 970                                    SMU_POWER_SOURCE_DC);
 971         if (ret) {
 972                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
 973                 return ret;
 974         }
 975
 976         /*
 977          * Set initialized values (get from vbios) to dpm tables context such as
 978          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 979          * type of clks.
 980          */
 981         ret = smu_set_default_dpm_table(smu);
 982         if (ret) {
 983                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 984                 return ret;
 985         }
 986
 987         ret = smu_notify_display_change(smu);
 988         if (ret)
 989                 return ret;
 990
 991         /*
 992          * Set min deep sleep dce fclk with bootup value from vbios via
 993          * SetMinDeepSleepDcefclk MSG.
 994          */
 995         ret = smu_set_min_dcef_deep_sleep(smu,
 996                                           smu->smu_table.boot_values.dcefclk / 100);
 997         if (ret)
 998                 return ret;
 999
1000         return ret;
1001 }
1002
1003 static int smu_start_smc_engine(struct smu_context *smu)
1004 {
1005         struct amdgpu_device *adev = smu->adev;
1006         int ret = 0;
1007
1008         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1009                 if (adev->asic_type < CHIP_NAVI10) {
1010                         if (smu->ppt_funcs->load_microcode) {
1011                                 ret = smu->ppt_funcs->load_microcode(smu);
1012                                 if (ret)
1013                                         return ret;
1014                         }
1015                 }
1016         }
1017
1018         if (smu->ppt_funcs->check_fw_status) {
1019                 ret = smu->ppt_funcs->check_fw_status(smu);
1020                 if (ret) {
1021                         dev_err(adev->dev, "SMC is not ready\n");
1022                         return ret;
1023                 }
1024         }
1025
1026         /*
1027          * Send msg GetDriverIfVersion to check if the return value is equal
1028          * with DRIVER_IF_VERSION of smc header.
1029          */
1030         ret = smu_check_fw_version(smu);
1031         if (ret)
1032                 return ret;
1033
1034         return ret;
1035 }
1036
1037 static int smu_hw_init(void *handle)
1038 {
1039         int ret;
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041         struct smu_context *smu = &adev->smu;
1042
1043         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1044                 smu->pm_enabled = false;
1045                 return 0;
1046         }
1047
1048         ret = smu_start_smc_engine(smu);
1049         if (ret) {
1050                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1051                 return ret;
1052         }
1053
1054         if (smu->is_apu) {
1055                 smu_powergate_sdma(&adev->smu, false);
1056                 smu_dpm_set_vcn_enable(smu, true);
1057                 smu_dpm_set_jpeg_enable(smu, true);
1058                 smu_set_gfx_cgpg(&adev->smu, true);
1059         }
1060
1061         if (!smu->pm_enabled)
1062                 return 0;
1063
1064         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1065         ret = smu_get_vbios_bootup_values(smu);
1066         if (ret) {
1067                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1068                 return ret;
1069         }
1070
1071         ret = smu_setup_pptable(smu);
1072         if (ret) {
1073                 dev_err(adev->dev, "Failed to setup pptable!\n");
1074                 return ret;
1075         }
1076
1077         ret = smu_get_driver_allowed_feature_mask(smu);
1078         if (ret)
1079                 return ret;
1080
1081         ret = smu_smc_hw_setup(smu);
1082         if (ret) {
1083                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1084                 return ret;
1085         }
1086
1087         /*
1088          * Move maximum sustainable clock retrieving here considering
1089          * 1. It is not needed on resume(from S3).
1090          * 2. DAL settings come between .hw_init and .late_init of SMU.
1091          *    And DAL needs to know the maximum sustainable clocks. Thus
1092          *    it cannot be put in .late_init().
1093          */
1094         ret = smu_init_max_sustainable_clocks(smu);
1095         if (ret) {
1096                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1097                 return ret;
1098         }
1099
1100         adev->pm.dpm_enabled = true;
1101
1102         dev_info(adev->dev, "SMU is initialized successfully!\n");
1103
1104         return 0;
1105 }
1106
1107 static int smu_disable_dpms(struct smu_context *smu)
1108 {
1109         struct amdgpu_device *adev = smu->adev;
1110         int ret = 0;
1111         bool use_baco = !smu->is_apu &&
1112                 ((adev->in_gpu_reset &&
1113                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1114                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1115
1116         /*
1117          * For custom pptable uploading, skip the DPM features
1118          * disable process on Navi1x ASICs.
1119          *   - As the gfx related features are under control of
1120          *     RLC on those ASICs. RLC reinitialization will be
1121          *     needed to reenable them. That will cost much more
1122          *     efforts.
1123          *
1124          *   - SMU firmware can handle the DPM reenablement
1125          *     properly.
1126          */
1127         if (smu->uploading_custom_pp_table &&
1128             (adev->asic_type >= CHIP_NAVI10) &&
1129             (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1130                 return 0;
1131
1132         /*
1133          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1134          * on BACO in. Driver involvement is unnecessary.
1135          */
1136         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1137              use_baco)
1138                 return 0;
1139
1140         /*
1141          * For gpu reset, runpm and hibernation through BACO,
1142          * BACO feature has to be kept enabled.
1143          */
1144         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1145                 ret = smu_disable_all_features_with_exception(smu,
1146                                                               SMU_FEATURE_BACO_BIT);
1147                 if (ret)
1148                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1149         } else {
1150                 ret = smu_system_features_control(smu, false);
1151                 if (ret)
1152                         dev_err(adev->dev, "Failed to disable smu features.\n");
1153         }
1154
1155         if (adev->asic_type >= CHIP_NAVI10 &&
1156             adev->gfx.rlc.funcs->stop)
1157                 adev->gfx.rlc.funcs->stop(adev);
1158
1159         return ret;
1160 }
1161
1162 static int smu_smc_hw_cleanup(struct smu_context *smu)
1163 {
1164         struct amdgpu_device *adev = smu->adev;
1165         int ret = 0;
1166
1167         cancel_work_sync(&smu->throttling_logging_work);
1168
1169         ret = smu_disable_thermal_alert(smu);
1170         if (ret) {
1171                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1172                 return ret;
1173         }
1174
1175         ret = smu_disable_dpms(smu);
1176         if (ret) {
1177                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1178                 return ret;
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int smu_hw_fini(void *handle)
1185 {
1186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187         struct smu_context *smu = &adev->smu;
1188         int ret = 0;
1189
1190         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1191                 return 0;
1192
1193         if (smu->is_apu) {
1194                 smu_powergate_sdma(&adev->smu, true);
1195                 smu_dpm_set_vcn_enable(smu, false);
1196                 smu_dpm_set_jpeg_enable(smu, false);
1197         }
1198
1199         if (!smu->pm_enabled)
1200                 return 0;
1201
1202         adev->pm.dpm_enabled = false;
1203
1204         ret = smu_smc_hw_cleanup(smu);
1205         if (ret)
1206                 return ret;
1207
1208         return 0;
1209 }
1210
1211 int smu_reset(struct smu_context *smu)
1212 {
1213         struct amdgpu_device *adev = smu->adev;
1214         int ret;
1215
1216         amdgpu_gfx_off_ctrl(smu->adev, false);
1217
1218         ret = smu_hw_fini(adev);
1219         if (ret)
1220                 return ret;
1221
1222         ret = smu_hw_init(adev);
1223         if (ret)
1224                 return ret;
1225
1226         ret = smu_late_init(adev);
1227         if (ret)
1228                 return ret;
1229
1230         amdgpu_gfx_off_ctrl(smu->adev, true);
1231
1232         return 0;
1233 }
1234
1235 static int smu_suspend(void *handle)
1236 {
1237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238         struct smu_context *smu = &adev->smu;
1239         int ret;
1240
1241         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1242                 return 0;
1243
1244         if (!smu->pm_enabled)
1245                 return 0;
1246
1247         adev->pm.dpm_enabled = false;
1248
1249         ret = smu_smc_hw_cleanup(smu);
1250         if (ret)
1251                 return ret;
1252
1253         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1254
1255         if (smu->is_apu)
1256                 smu_set_gfx_cgpg(&adev->smu, false);
1257
1258         return 0;
1259 }
1260
1261 static int smu_resume(void *handle)
1262 {
1263         int ret;
1264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265         struct smu_context *smu = &adev->smu;
1266
1267         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1268                 return 0;
1269
1270         if (!smu->pm_enabled)
1271                 return 0;
1272
1273         dev_info(adev->dev, "SMU is resuming...\n");
1274
1275         ret = smu_start_smc_engine(smu);
1276         if (ret) {
1277                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1278                 return ret;
1279         }
1280
1281         ret = smu_smc_hw_setup(smu);
1282         if (ret) {
1283                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1284                 return ret;
1285         }
1286
1287         if (smu->is_apu)
1288                 smu_set_gfx_cgpg(&adev->smu, true);
1289
1290         smu->disable_uclk_switch = 0;
1291
1292         adev->pm.dpm_enabled = true;
1293
1294         dev_info(adev->dev, "SMU is resumed successfully!\n");
1295
1296         return 0;
1297 }
1298
1299 int smu_display_configuration_change(struct smu_context *smu,
1300                                      const struct amd_pp_display_configuration *display_config)
1301 {
1302         int index = 0;
1303         int num_of_active_display = 0;
1304
1305         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1306                 return -EOPNOTSUPP;
1307
1308         if (!display_config)
1309                 return -EINVAL;
1310
1311         mutex_lock(&smu->mutex);
1312
1313         smu_set_min_dcef_deep_sleep(smu,
1314                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1315
1316         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1317                 if (display_config->displays[index].controller_id != 0)
1318                         num_of_active_display++;
1319         }
1320
1321         smu_set_active_display_count(smu, num_of_active_display);
1322
1323         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1324                            display_config->cpu_cc6_disable,
1325                            display_config->cpu_pstate_disable,
1326                            display_config->nb_pstate_switch_disable);
1327
1328         mutex_unlock(&smu->mutex);
1329
1330         return 0;
1331 }
1332
1333 static int smu_get_clock_info(struct smu_context *smu,
1334                               struct smu_clock_info *clk_info,
1335                               enum smu_perf_level_designation designation)
1336 {
1337         int ret;
1338         struct smu_performance_level level = {0};
1339
1340         if (!clk_info)
1341                 return -EINVAL;
1342
1343         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1344         if (ret)
1345                 return -EINVAL;
1346
1347         clk_info->min_mem_clk = level.memory_clock;
1348         clk_info->min_eng_clk = level.core_clock;
1349         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1350
1351         ret = smu_get_perf_level(smu, designation, &level);
1352         if (ret)
1353                 return -EINVAL;
1354
1355         clk_info->min_mem_clk = level.memory_clock;
1356         clk_info->min_eng_clk = level.core_clock;
1357         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1358
1359         return 0;
1360 }
1361
1362 int smu_get_current_clocks(struct smu_context *smu,
1363                            struct amd_pp_clock_info *clocks)
1364 {
1365         struct amd_pp_simple_clock_info simple_clocks = {0};
1366         struct smu_clock_info hw_clocks;
1367         int ret = 0;
1368
1369         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1370                 return -EOPNOTSUPP;
1371
1372         mutex_lock(&smu->mutex);
1373
1374         smu_get_dal_power_level(smu, &simple_clocks);
1375
1376         if (smu->support_power_containment)
1377                 ret = smu_get_clock_info(smu, &hw_clocks,
1378                                          PERF_LEVEL_POWER_CONTAINMENT);
1379         else
1380                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1381
1382         if (ret) {
1383                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1384                 goto failed;
1385         }
1386
1387         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1388         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1389         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1390         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1391         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1392         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1393         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1394         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1395
1396         if (simple_clocks.level == 0)
1397                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1398         else
1399                 clocks->max_clocks_state = simple_clocks.level;
1400
1401         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1402                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1403                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1404         }
1405
1406 failed:
1407         mutex_unlock(&smu->mutex);
1408         return ret;
1409 }
1410
1411 static int smu_set_clockgating_state(void *handle,
1412                                      enum amd_clockgating_state state)
1413 {
1414         return 0;
1415 }
1416
1417 static int smu_set_powergating_state(void *handle,
1418                                      enum amd_powergating_state state)
1419 {
1420         return 0;
1421 }
1422
1423 static int smu_enable_umd_pstate(void *handle,
1424                       enum amd_dpm_forced_level *level)
1425 {
1426         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1427                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1428                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1429                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1430
1431         struct smu_context *smu = (struct smu_context*)(handle);
1432         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1433
1434         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1435                 return -EINVAL;
1436
1437         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1438                 /* enter umd pstate, save current level, disable gfx cg*/
1439                 if (*level & profile_mode_mask) {
1440                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1441                         smu_dpm_ctx->enable_umd_pstate = true;
1442                         amdgpu_device_ip_set_powergating_state(smu->adev,
1443                                                                AMD_IP_BLOCK_TYPE_GFX,
1444                                                                AMD_PG_STATE_UNGATE);
1445                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1446                                                                AMD_IP_BLOCK_TYPE_GFX,
1447                                                                AMD_CG_STATE_UNGATE);
1448                 }
1449         } else {
1450                 /* exit umd pstate, restore level, enable gfx cg*/
1451                 if (!(*level & profile_mode_mask)) {
1452                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1453                                 *level = smu_dpm_ctx->saved_dpm_level;
1454                         smu_dpm_ctx->enable_umd_pstate = false;
1455                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1456                                                                AMD_IP_BLOCK_TYPE_GFX,
1457                                                                AMD_CG_STATE_GATE);
1458                         amdgpu_device_ip_set_powergating_state(smu->adev,
1459                                                                AMD_IP_BLOCK_TYPE_GFX,
1460                                                                AMD_PG_STATE_GATE);
1461                 }
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1468                                    enum amd_dpm_forced_level level,
1469                                    bool skip_display_settings)
1470 {
1471         int ret = 0;
1472         int index = 0;
1473         long workload;
1474         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1475
1476         if (!skip_display_settings) {
1477                 ret = smu_display_config_changed(smu);
1478                 if (ret) {
1479                         dev_err(smu->adev->dev, "Failed to change display config!");
1480                         return ret;
1481                 }
1482         }
1483
1484         ret = smu_apply_clocks_adjust_rules(smu);
1485         if (ret) {
1486                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1487                 return ret;
1488         }
1489
1490         if (!skip_display_settings) {
1491                 ret = smu_notify_smc_display_config(smu);
1492                 if (ret) {
1493                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1494                         return ret;
1495                 }
1496         }
1497
1498         if (smu_dpm_ctx->dpm_level != level) {
1499                 ret = smu_asic_set_performance_level(smu, level);
1500                 if (ret) {
1501                         dev_err(smu->adev->dev, "Failed to set performance level!");
1502                         return ret;
1503                 }
1504
1505                 /* update the saved copy */
1506                 smu_dpm_ctx->dpm_level = level;
1507         }
1508
1509         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1510                 index = fls(smu->workload_mask);
1511                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1512                 workload = smu->workload_setting[index];
1513
1514                 if (smu->power_profile_mode != workload)
1515                         smu_set_power_profile_mode(smu, &workload, 0, false);
1516         }
1517
1518         return ret;
1519 }
1520
1521 int smu_handle_task(struct smu_context *smu,
1522                     enum amd_dpm_forced_level level,
1523                     enum amd_pp_task task_id,
1524                     bool lock_needed)
1525 {
1526         int ret = 0;
1527
1528         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1529                 return -EOPNOTSUPP;
1530
1531         if (lock_needed)
1532                 mutex_lock(&smu->mutex);
1533
1534         switch (task_id) {
1535         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1536                 ret = smu_pre_display_config_changed(smu);
1537                 if (ret)
1538                         goto out;
1539                 ret = smu_set_cpu_power_state(smu);
1540                 if (ret)
1541                         goto out;
1542                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1543                 break;
1544         case AMD_PP_TASK_COMPLETE_INIT:
1545         case AMD_PP_TASK_READJUST_POWER_STATE:
1546                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1547                 break;
1548         default:
1549                 break;
1550         }
1551
1552 out:
1553         if (lock_needed)
1554                 mutex_unlock(&smu->mutex);
1555
1556         return ret;
1557 }
1558
1559 int smu_switch_power_profile(struct smu_context *smu,
1560                              enum PP_SMC_POWER_PROFILE type,
1561                              bool en)
1562 {
1563         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1564         long workload;
1565         uint32_t index;
1566
1567         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1568                 return -EOPNOTSUPP;
1569
1570         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1571                 return -EINVAL;
1572
1573         mutex_lock(&smu->mutex);
1574
1575         if (!en) {
1576                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1577                 index = fls(smu->workload_mask);
1578                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1579                 workload = smu->workload_setting[index];
1580         } else {
1581                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1582                 index = fls(smu->workload_mask);
1583                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1584                 workload = smu->workload_setting[index];
1585         }
1586
1587         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1588                 smu_set_power_profile_mode(smu, &workload, 0, false);
1589
1590         mutex_unlock(&smu->mutex);
1591
1592         return 0;
1593 }
1594
1595 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1596 {
1597         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1598         enum amd_dpm_forced_level level;
1599
1600         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1601                 return -EOPNOTSUPP;
1602
1603         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1604                 return -EINVAL;
1605
1606         mutex_lock(&(smu->mutex));
1607         level = smu_dpm_ctx->dpm_level;
1608         mutex_unlock(&(smu->mutex));
1609
1610         return level;
1611 }
1612
1613 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1614 {
1615         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1616         int ret = 0;
1617
1618         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1619                 return -EOPNOTSUPP;
1620
1621         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1622                 return -EINVAL;
1623
1624         mutex_lock(&smu->mutex);
1625
1626         ret = smu_enable_umd_pstate(smu, &level);
1627         if (ret) {
1628                 mutex_unlock(&smu->mutex);
1629                 return ret;
1630         }
1631
1632         ret = smu_handle_task(smu, level,
1633                               AMD_PP_TASK_READJUST_POWER_STATE,
1634                               false);
1635
1636         mutex_unlock(&smu->mutex);
1637
1638         return ret;
1639 }
1640
1641 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1642 {
1643         int ret = 0;
1644
1645         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1646                 return -EOPNOTSUPP;
1647
1648         mutex_lock(&smu->mutex);
1649         ret = smu_init_display_count(smu, count);
1650         mutex_unlock(&smu->mutex);
1651
1652         return ret;
1653 }
1654
1655 int smu_force_clk_levels(struct smu_context *smu,
1656                          enum smu_clk_type clk_type,
1657                          uint32_t mask)
1658 {
1659         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1660         int ret = 0;
1661
1662         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1663                 return -EOPNOTSUPP;
1664
1665         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1666                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1667                 return -EINVAL;
1668         }
1669
1670         mutex_lock(&smu->mutex);
1671
1672         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1673                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1674
1675         mutex_unlock(&smu->mutex);
1676
1677         return ret;
1678 }
1679
1680 /*
1681  * On system suspending or resetting, the dpm_enabled
1682  * flag will be cleared. So that those SMU services which
1683  * are not supported will be gated.
1684  * However, the mp1 state setting should still be granted
1685  * even if the dpm_enabled cleared.
1686  */
1687 int smu_set_mp1_state(struct smu_context *smu,
1688                       enum pp_mp1_state mp1_state)
1689 {
1690         uint16_t msg;
1691         int ret;
1692
1693         if (!smu->pm_enabled)
1694                 return -EOPNOTSUPP;
1695
1696         mutex_lock(&smu->mutex);
1697
1698         switch (mp1_state) {
1699         case PP_MP1_STATE_SHUTDOWN:
1700                 msg = SMU_MSG_PrepareMp1ForShutdown;
1701                 break;
1702         case PP_MP1_STATE_UNLOAD:
1703                 msg = SMU_MSG_PrepareMp1ForUnload;
1704                 break;
1705         case PP_MP1_STATE_RESET:
1706                 msg = SMU_MSG_PrepareMp1ForReset;
1707                 break;
1708         case PP_MP1_STATE_NONE:
1709         default:
1710                 mutex_unlock(&smu->mutex);
1711                 return 0;
1712         }
1713
1714         ret = smu_send_smc_msg(smu, msg, NULL);
1715         /* some asics may not support those messages */
1716         if (ret == -EINVAL)
1717                 ret = 0;
1718         if (ret)
1719                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1720
1721         mutex_unlock(&smu->mutex);
1722
1723         return ret;
1724 }
1725
1726 int smu_set_df_cstate(struct smu_context *smu,
1727                       enum pp_df_cstate state)
1728 {
1729         int ret = 0;
1730
1731         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1732                 return -EOPNOTSUPP;
1733
1734         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1735                 return 0;
1736
1737         mutex_lock(&smu->mutex);
1738
1739         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1740         if (ret)
1741                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1742
1743         mutex_unlock(&smu->mutex);
1744
1745         return ret;
1746 }
1747
1748 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1749 {
1750         int ret = 0;
1751
1752         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1753                 return -EOPNOTSUPP;
1754
1755         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1756                 return 0;
1757
1758         mutex_lock(&smu->mutex);
1759
1760         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1761         if (ret)
1762                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1763
1764         mutex_unlock(&smu->mutex);
1765
1766         return ret;
1767 }
1768
1769 int smu_write_watermarks_table(struct smu_context *smu)
1770 {
1771         int ret = 0;
1772
1773         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1774                 return -EOPNOTSUPP;
1775
1776         mutex_lock(&smu->mutex);
1777
1778         ret = smu_set_watermarks_table(smu, NULL);
1779
1780         mutex_unlock(&smu->mutex);
1781
1782         return ret;
1783 }
1784
1785 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1786                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1787 {
1788         int ret = 0;
1789
1790         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1791                 return -EOPNOTSUPP;
1792
1793         mutex_lock(&smu->mutex);
1794
1795         if (!smu->disable_watermark &&
1796                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1797                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1798                 ret = smu_set_watermarks_table(smu, clock_ranges);
1799
1800                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1801                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1802                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1803                 }
1804         }
1805
1806         mutex_unlock(&smu->mutex);
1807
1808         return ret;
1809 }
1810
1811 int smu_set_ac_dc(struct smu_context *smu)
1812 {
1813         int ret = 0;
1814
1815         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1816                 return -EOPNOTSUPP;
1817
1818         /* controlled by firmware */
1819         if (smu->dc_controlled_by_gpio)
1820                 return 0;
1821
1822         mutex_lock(&smu->mutex);
1823         ret = smu_set_power_source(smu,
1824                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1825                                    SMU_POWER_SOURCE_DC);
1826         if (ret)
1827                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1828                        smu->adev->pm.ac_power ? "AC" : "DC");
1829         mutex_unlock(&smu->mutex);
1830
1831         return ret;
1832 }
1833
1834 const struct amd_ip_funcs smu_ip_funcs = {
1835         .name = "smu",
1836         .early_init = smu_early_init,
1837         .late_init = smu_late_init,
1838         .sw_init = smu_sw_init,
1839         .sw_fini = smu_sw_fini,
1840         .hw_init = smu_hw_init,
1841         .hw_fini = smu_hw_fini,
1842         .suspend = smu_suspend,
1843         .resume = smu_resume,
1844         .is_idle = NULL,
1845         .check_soft_reset = NULL,
1846         .wait_for_idle = NULL,
1847         .soft_reset = NULL,
1848         .set_clockgating_state = smu_set_clockgating_state,
1849         .set_powergating_state = smu_set_powergating_state,
1850         .enable_umd_pstate = smu_enable_umd_pstate,
1851 };
1852
1853 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1854 {
1855         .type = AMD_IP_BLOCK_TYPE_SMC,
1856         .major = 11,
1857         .minor = 0,
1858         .rev = 0,
1859         .funcs = &smu_ip_funcs,
1860 };
1861
1862 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1863 {
1864         .type = AMD_IP_BLOCK_TYPE_SMC,
1865         .major = 12,
1866         .minor = 0,
1867         .rev = 0,
1868         .funcs = &smu_ip_funcs,
1869 };
1870
1871 int smu_load_microcode(struct smu_context *smu)
1872 {
1873         int ret = 0;
1874
1875         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1876                 return -EOPNOTSUPP;
1877
1878         mutex_lock(&smu->mutex);
1879
1880         if (smu->ppt_funcs->load_microcode)
1881                 ret = smu->ppt_funcs->load_microcode(smu);
1882
1883         mutex_unlock(&smu->mutex);
1884
1885         return ret;
1886 }
1887
1888 int smu_check_fw_status(struct smu_context *smu)
1889 {
1890         int ret = 0;
1891
1892         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1893                 return -EOPNOTSUPP;
1894
1895         mutex_lock(&smu->mutex);
1896
1897         if (smu->ppt_funcs->check_fw_status)
1898                 ret = smu->ppt_funcs->check_fw_status(smu);
1899
1900         mutex_unlock(&smu->mutex);
1901
1902         return ret;
1903 }
1904
1905 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1906 {
1907         int ret = 0;
1908
1909         mutex_lock(&smu->mutex);
1910
1911         if (smu->ppt_funcs->set_gfx_cgpg)
1912                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1913
1914         mutex_unlock(&smu->mutex);
1915
1916         return ret;
1917 }
1918
1919 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1920 {
1921         int ret = 0;
1922
1923         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1924                 return -EOPNOTSUPP;
1925
1926         mutex_lock(&smu->mutex);
1927
1928         if (smu->ppt_funcs->set_fan_speed_rpm)
1929                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1930
1931         mutex_unlock(&smu->mutex);
1932
1933         return ret;
1934 }
1935
1936 int smu_get_power_limit(struct smu_context *smu,
1937                         uint32_t *limit,
1938                         bool max_setting)
1939 {
1940         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1941                 return -EOPNOTSUPP;
1942
1943         mutex_lock(&smu->mutex);
1944
1945         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1946
1947         mutex_unlock(&smu->mutex);
1948
1949         return 0;
1950 }
1951
1952 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1953 {
1954         int ret = 0;
1955
1956         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1957                 return -EOPNOTSUPP;
1958
1959         mutex_lock(&smu->mutex);
1960
1961         if (limit > smu->max_power_limit) {
1962                 dev_err(smu->adev->dev,
1963                         "New power limit (%d) is over the max allowed %d\n",
1964                         limit, smu->max_power_limit);
1965                 goto out;
1966         }
1967
1968         if (!limit)
1969                 limit = smu->current_power_limit;
1970
1971         if (smu->ppt_funcs->set_power_limit)
1972                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
1973
1974 out:
1975         mutex_unlock(&smu->mutex);
1976
1977         return ret;
1978 }
1979
1980 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
1981 {
1982         int ret = 0;
1983
1984         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1985                 return -EOPNOTSUPP;
1986
1987         mutex_lock(&smu->mutex);
1988
1989         if (smu->ppt_funcs->print_clk_levels)
1990                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
1991
1992         mutex_unlock(&smu->mutex);
1993
1994         return ret;
1995 }
1996
1997 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
1998 {
1999         int ret = 0;
2000
2001         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2002                 return -EOPNOTSUPP;
2003
2004         mutex_lock(&smu->mutex);
2005
2006         if (smu->ppt_funcs->get_od_percentage)
2007                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2008
2009         mutex_unlock(&smu->mutex);
2010
2011         return ret;
2012 }
2013
2014 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2015 {
2016         int ret = 0;
2017
2018         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2019                 return -EOPNOTSUPP;
2020
2021         mutex_lock(&smu->mutex);
2022
2023         if (smu->ppt_funcs->set_od_percentage)
2024                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2025
2026         mutex_unlock(&smu->mutex);
2027
2028         return ret;
2029 }
2030
2031 int smu_od_edit_dpm_table(struct smu_context *smu,
2032                           enum PP_OD_DPM_TABLE_COMMAND type,
2033                           long *input, uint32_t size)
2034 {
2035         int ret = 0;
2036
2037         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2038                 return -EOPNOTSUPP;
2039
2040         mutex_lock(&smu->mutex);
2041
2042         if (smu->ppt_funcs->od_edit_dpm_table) {
2043                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2044                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2045                         ret = smu_handle_task(smu,
2046                                               smu->smu_dpm.dpm_level,
2047                                               AMD_PP_TASK_READJUST_POWER_STATE,
2048                                               false);
2049         }
2050
2051         mutex_unlock(&smu->mutex);
2052
2053         return ret;
2054 }
2055
2056 int smu_read_sensor(struct smu_context *smu,
2057                     enum amd_pp_sensors sensor,
2058                     void *data, uint32_t *size)
2059 {
2060         struct smu_umd_pstate_table *pstate_table =
2061                                 &smu->pstate_table;
2062         int ret = 0;
2063
2064         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2065                 return -EOPNOTSUPP;
2066
2067         if (!data || !size)
2068                 return -EINVAL;
2069
2070         mutex_lock(&smu->mutex);
2071
2072         if (smu->ppt_funcs->read_sensor)
2073                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2074                         goto unlock;
2075
2076         switch (sensor) {
2077         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2078                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2079                 *size = 4;
2080                 break;
2081         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2082                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2083                 *size = 4;
2084                 break;
2085         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2086                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2087                 *size = 8;
2088                 break;
2089         case AMDGPU_PP_SENSOR_UVD_POWER:
2090                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2091                 *size = 4;
2092                 break;
2093         case AMDGPU_PP_SENSOR_VCE_POWER:
2094                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2095                 *size = 4;
2096                 break;
2097         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2098                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2099                 *size = 4;
2100                 break;
2101         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2102                 *(uint32_t *)data = 0;
2103                 *size = 4;
2104                 break;
2105         default:
2106                 *size = 0;
2107                 ret = -EOPNOTSUPP;
2108                 break;
2109         }
2110
2111 unlock:
2112         mutex_unlock(&smu->mutex);
2113
2114         return ret;
2115 }
2116
2117 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2118 {
2119         int ret = 0;
2120
2121         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2122                 return -EOPNOTSUPP;
2123
2124         mutex_lock(&smu->mutex);
2125
2126         if (smu->ppt_funcs->get_power_profile_mode)
2127                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2128
2129         mutex_unlock(&smu->mutex);
2130
2131         return ret;
2132 }
2133
2134 int smu_set_power_profile_mode(struct smu_context *smu,
2135                                long *param,
2136                                uint32_t param_size,
2137                                bool lock_needed)
2138 {
2139         int ret = 0;
2140
2141         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2142                 return -EOPNOTSUPP;
2143
2144         if (lock_needed)
2145                 mutex_lock(&smu->mutex);
2146
2147         if (smu->ppt_funcs->set_power_profile_mode)
2148                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2149
2150         if (lock_needed)
2151                 mutex_unlock(&smu->mutex);
2152
2153         return ret;
2154 }
2155
2156
2157 int smu_get_fan_control_mode(struct smu_context *smu)
2158 {
2159         int ret = 0;
2160
2161         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2162                 return -EOPNOTSUPP;
2163
2164         mutex_lock(&smu->mutex);
2165
2166         if (smu->ppt_funcs->get_fan_control_mode)
2167                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2168
2169         mutex_unlock(&smu->mutex);
2170
2171         return ret;
2172 }
2173
2174 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2175 {
2176         int ret = 0;
2177
2178         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2179                 return -EOPNOTSUPP;
2180
2181         mutex_lock(&smu->mutex);
2182
2183         if (smu->ppt_funcs->set_fan_control_mode)
2184                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2185
2186         mutex_unlock(&smu->mutex);
2187
2188         return ret;
2189 }
2190
2191 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2192 {
2193         int ret = 0;
2194
2195         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2196                 return -EOPNOTSUPP;
2197
2198         mutex_lock(&smu->mutex);
2199
2200         if (smu->ppt_funcs->get_fan_speed_percent)
2201                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2202
2203         mutex_unlock(&smu->mutex);
2204
2205         return ret;
2206 }
2207
2208 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2209 {
2210         int ret = 0;
2211
2212         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2213                 return -EOPNOTSUPP;
2214
2215         mutex_lock(&smu->mutex);
2216
2217         if (smu->ppt_funcs->set_fan_speed_percent)
2218                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2219
2220         mutex_unlock(&smu->mutex);
2221
2222         return ret;
2223 }
2224
2225 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2226 {
2227         int ret = 0;
2228
2229         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2230                 return -EOPNOTSUPP;
2231
2232         mutex_lock(&smu->mutex);
2233
2234         if (smu->ppt_funcs->get_fan_speed_rpm)
2235                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2236
2237         mutex_unlock(&smu->mutex);
2238
2239         return ret;
2240 }
2241
2242 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2243 {
2244         int ret = 0;
2245
2246         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2247                 return -EOPNOTSUPP;
2248
2249         mutex_lock(&smu->mutex);
2250
2251         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2252
2253         mutex_unlock(&smu->mutex);
2254
2255         return ret;
2256 }
2257
2258 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2259 {
2260         int ret = 0;
2261
2262         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2263                 return -EOPNOTSUPP;
2264
2265         if (smu->ppt_funcs->set_active_display_count)
2266                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2267
2268         return ret;
2269 }
2270
2271 int smu_get_clock_by_type(struct smu_context *smu,
2272                           enum amd_pp_clock_type type,
2273                           struct amd_pp_clocks *clocks)
2274 {
2275         int ret = 0;
2276
2277         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2278                 return -EOPNOTSUPP;
2279
2280         mutex_lock(&smu->mutex);
2281
2282         if (smu->ppt_funcs->get_clock_by_type)
2283                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2284
2285         mutex_unlock(&smu->mutex);
2286
2287         return ret;
2288 }
2289
2290 int smu_get_max_high_clocks(struct smu_context *smu,
2291                             struct amd_pp_simple_clock_info *clocks)
2292 {
2293         int ret = 0;
2294
2295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2296                 return -EOPNOTSUPP;
2297
2298         mutex_lock(&smu->mutex);
2299
2300         if (smu->ppt_funcs->get_max_high_clocks)
2301                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2302
2303         mutex_unlock(&smu->mutex);
2304
2305         return ret;
2306 }
2307
2308 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2309                                        enum smu_clk_type clk_type,
2310                                        struct pp_clock_levels_with_latency *clocks)
2311 {
2312         int ret = 0;
2313
2314         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2315                 return -EOPNOTSUPP;
2316
2317         mutex_lock(&smu->mutex);
2318
2319         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2320                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2321
2322         mutex_unlock(&smu->mutex);
2323
2324         return ret;
2325 }
2326
2327 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2328                                        enum amd_pp_clock_type type,
2329                                        struct pp_clock_levels_with_voltage *clocks)
2330 {
2331         int ret = 0;
2332
2333         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2334                 return -EOPNOTSUPP;
2335
2336         mutex_lock(&smu->mutex);
2337
2338         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2339                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2340
2341         mutex_unlock(&smu->mutex);
2342
2343         return ret;
2344 }
2345
2346
2347 int smu_display_clock_voltage_request(struct smu_context *smu,
2348                                       struct pp_display_clock_request *clock_req)
2349 {
2350         int ret = 0;
2351
2352         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2353                 return -EOPNOTSUPP;
2354
2355         mutex_lock(&smu->mutex);
2356
2357         if (smu->ppt_funcs->display_clock_voltage_request)
2358                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2359
2360         mutex_unlock(&smu->mutex);
2361
2362         return ret;
2363 }
2364
2365
2366 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2367 {
2368         int ret = -EINVAL;
2369
2370         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2371                 return -EOPNOTSUPP;
2372
2373         mutex_lock(&smu->mutex);
2374
2375         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2376                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2377
2378         mutex_unlock(&smu->mutex);
2379
2380         return ret;
2381 }
2382
2383 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2384 {
2385         int ret = 0;
2386
2387         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2388                 return -EOPNOTSUPP;
2389
2390         mutex_lock(&smu->mutex);
2391
2392         if (smu->ppt_funcs->notify_smu_enable_pwe)
2393                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2394
2395         mutex_unlock(&smu->mutex);
2396
2397         return ret;
2398 }
2399
2400 int smu_set_xgmi_pstate(struct smu_context *smu,
2401                         uint32_t pstate)
2402 {
2403         int ret = 0;
2404
2405         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2406                 return -EOPNOTSUPP;
2407
2408         mutex_lock(&smu->mutex);
2409
2410         if (smu->ppt_funcs->set_xgmi_pstate)
2411                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2412
2413         mutex_unlock(&smu->mutex);
2414
2415         if(ret)
2416                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2417
2418         return ret;
2419 }
2420
2421 int smu_set_azalia_d3_pme(struct smu_context *smu)
2422 {
2423         int ret = 0;
2424
2425         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2426                 return -EOPNOTSUPP;
2427
2428         mutex_lock(&smu->mutex);
2429
2430         if (smu->ppt_funcs->set_azalia_d3_pme)
2431                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2432
2433         mutex_unlock(&smu->mutex);
2434
2435         return ret;
2436 }
2437
2438 /*
2439  * On system suspending or resetting, the dpm_enabled
2440  * flag will be cleared. So that those SMU services which
2441  * are not supported will be gated.
2442  *
2443  * However, the baco/mode1 reset should still be granted
2444  * as they are still supported and necessary.
2445  */
2446 bool smu_baco_is_support(struct smu_context *smu)
2447 {
2448         bool ret = false;
2449
2450         if (!smu->pm_enabled)
2451                 return false;
2452
2453         mutex_lock(&smu->mutex);
2454
2455         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2456                 ret = smu->ppt_funcs->baco_is_support(smu);
2457
2458         mutex_unlock(&smu->mutex);
2459
2460         return ret;
2461 }
2462
2463 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2464 {
2465         if (smu->ppt_funcs->baco_get_state)
2466                 return -EINVAL;
2467
2468         mutex_lock(&smu->mutex);
2469         *state = smu->ppt_funcs->baco_get_state(smu);
2470         mutex_unlock(&smu->mutex);
2471
2472         return 0;
2473 }
2474
2475 int smu_baco_enter(struct smu_context *smu)
2476 {
2477         int ret = 0;
2478
2479         if (!smu->pm_enabled)
2480                 return -EOPNOTSUPP;
2481
2482         mutex_lock(&smu->mutex);
2483
2484         if (smu->ppt_funcs->baco_enter)
2485                 ret = smu->ppt_funcs->baco_enter(smu);
2486
2487         mutex_unlock(&smu->mutex);
2488
2489         if (ret)
2490                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2491
2492         return ret;
2493 }
2494
2495 int smu_baco_exit(struct smu_context *smu)
2496 {
2497         int ret = 0;
2498
2499         if (!smu->pm_enabled)
2500                 return -EOPNOTSUPP;
2501
2502         mutex_lock(&smu->mutex);
2503
2504         if (smu->ppt_funcs->baco_exit)
2505                 ret = smu->ppt_funcs->baco_exit(smu);
2506
2507         mutex_unlock(&smu->mutex);
2508
2509         if (ret)
2510                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2511
2512         return ret;
2513 }
2514
2515 bool smu_mode1_reset_is_support(struct smu_context *smu)
2516 {
2517         bool ret = false;
2518
2519         if (!smu->pm_enabled)
2520                 return false;
2521
2522         mutex_lock(&smu->mutex);
2523
2524         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2525                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2526
2527         mutex_unlock(&smu->mutex);
2528
2529         return ret;
2530 }
2531
2532 int smu_mode1_reset(struct smu_context *smu)
2533 {
2534         int ret = 0;
2535
2536         if (!smu->pm_enabled)
2537                 return -EOPNOTSUPP;
2538
2539         mutex_lock(&smu->mutex);
2540
2541         if (smu->ppt_funcs->mode1_reset)
2542                 ret = smu->ppt_funcs->mode1_reset(smu);
2543
2544         mutex_unlock(&smu->mutex);
2545
2546         return ret;
2547 }
2548
2549 int smu_mode2_reset(struct smu_context *smu)
2550 {
2551         int ret = 0;
2552
2553         if (!smu->pm_enabled)
2554                 return -EOPNOTSUPP;
2555
2556         mutex_lock(&smu->mutex);
2557
2558         if (smu->ppt_funcs->mode2_reset)
2559                 ret = smu->ppt_funcs->mode2_reset(smu);
2560
2561         mutex_unlock(&smu->mutex);
2562
2563         if (ret)
2564                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2565
2566         return ret;
2567 }
2568
2569 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2570                                          struct pp_smu_nv_clock_table *max_clocks)
2571 {
2572         int ret = 0;
2573
2574         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2575                 return -EOPNOTSUPP;
2576
2577         mutex_lock(&smu->mutex);
2578
2579         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2580                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2581
2582         mutex_unlock(&smu->mutex);
2583
2584         return ret;
2585 }
2586
2587 int smu_get_uclk_dpm_states(struct smu_context *smu,
2588                             unsigned int *clock_values_in_khz,
2589                             unsigned int *num_states)
2590 {
2591         int ret = 0;
2592
2593         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2594                 return -EOPNOTSUPP;
2595
2596         mutex_lock(&smu->mutex);
2597
2598         if (smu->ppt_funcs->get_uclk_dpm_states)
2599                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2600
2601         mutex_unlock(&smu->mutex);
2602
2603         return ret;
2604 }
2605
2606 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2607 {
2608         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2609
2610         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2611                 return -EOPNOTSUPP;
2612
2613         mutex_lock(&smu->mutex);
2614
2615         if (smu->ppt_funcs->get_current_power_state)
2616                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2617
2618         mutex_unlock(&smu->mutex);
2619
2620         return pm_state;
2621 }
2622
2623 int smu_get_dpm_clock_table(struct smu_context *smu,
2624                             struct dpm_clocks *clock_table)
2625 {
2626         int ret = 0;
2627
2628         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2629                 return -EOPNOTSUPP;
2630
2631         mutex_lock(&smu->mutex);
2632
2633         if (smu->ppt_funcs->get_dpm_clock_table)
2634                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2635
2636         mutex_unlock(&smu->mutex);
2637
2638         return ret;
2639 }