drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "atom.h"
  31 #include "amd_pcie.h"
  32
  33 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
  34 {
  35         int ret = 0;
  36
  37         if (!if_version && !smu_version)
  38                 return -EINVAL;
  39
  40         if (if_version) {
  41                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
  42                 if (ret)
  43                         return ret;
  44
  45                 ret = smu_read_smc_arg(smu, if_version);
  46                 if (ret)
  47                         return ret;
  48         }
  49
  50         if (smu_version) {
  51                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
  52                 if (ret)
  53                         return ret;
  54
  55                 ret = smu_read_smc_arg(smu, smu_version);
  56                 if (ret)
  57                         return ret;
  58         }
  59
  60         return ret;
  61 }
  62
  63 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
  64                             uint32_t min, uint32_t max)
  65 {
  66         int ret = 0, clk_id = 0;
  67         uint32_t param;
  68
  69         if (min <= 0 && max <= 0)
  70                 return -EINVAL;
  71
  72         clk_id = smu_clk_get_index(smu, clk_type);
  73         if (clk_id < 0)
  74                 return clk_id;
  75
  76         if (max > 0) {
  77                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
  78                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
  79                                                   param);
  80                 if (ret)
  81                         return ret;
  82         }
  83
  84         if (min > 0) {
  85                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
  86                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
  87                                                   param);
  88                 if (ret)
  89                         return ret;
  90         }
  91
  92
  93         return ret;
  94 }
  95
  96 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
  97                             uint32_t min, uint32_t max)
  98 {
  99         int ret = 0, clk_id = 0;
 100         uint32_t param;
 101
 102         if (min <= 0 && max <= 0)
 103                 return -EINVAL;
 104
 105         clk_id = smu_clk_get_index(smu, clk_type);
 106         if (clk_id < 0)
 107                 return clk_id;
 108
 109         if (max > 0) {
 110                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 111                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 112                                                   param);
 113                 if (ret)
 114                         return ret;
 115         }
 116
 117         if (min > 0) {
 118                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 119                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 120                                                   param);
 121                 if (ret)
 122                         return ret;
 123         }
 124
 125
 126         return ret;
 127 }
 128
 129 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 130                            uint32_t *min, uint32_t *max)
 131 {
 132         int ret = 0, clk_id = 0;
 133         uint32_t param = 0;
 134
 135         if (!min && !max)
 136                 return -EINVAL;
 137
 138         switch (clk_type) {
 139         case SMU_MCLK:
 140         case SMU_UCLK:
 141                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 142                         pr_warn("uclk dpm is not enabled\n");
 143                         return 0;
 144                 }
 145                 break;
 146         case SMU_GFXCLK:
 147         case SMU_SCLK:
 148                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 149                         pr_warn("gfxclk dpm is not enabled\n");
 150                         return 0;
 151                 }
 152                 break;
 153         default:
 154                 break;
 155         }
 156
 157         mutex_lock(&smu->mutex);
 158         clk_id = smu_clk_get_index(smu, clk_type);
 159         if (clk_id < 0) {
 160                 ret = -EINVAL;
 161                 goto failed;
 162         }
 163
 164         param = (clk_id & 0xffff) << 16;
 165
 166         if (max) {
 167                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
 168                 if (ret)
 169                         goto failed;
 170                 ret = smu_read_smc_arg(smu, max);
 171                 if (ret)
 172                         goto failed;
 173         }
 174
 175         if (min) {
 176                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
 177                 if (ret)
 178                         goto failed;
 179                 ret = smu_read_smc_arg(smu, min);
 180                 if (ret)
 181                         goto failed;
 182         }
 183
 184 failed:
 185         mutex_unlock(&smu->mutex);
 186         return ret;
 187 }
 188
 189 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 190                               uint16_t level, uint32_t *value)
 191 {
 192         int ret = 0, clk_id = 0;
 193         uint32_t param;
 194
 195         if (!value)
 196                 return -EINVAL;
 197
 198         clk_id = smu_clk_get_index(smu, clk_type);
 199         if (clk_id < 0)
 200                 return clk_id;
 201
 202         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 203
 204         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 205                                           param);
 206         if (ret)
 207                 return ret;
 208
 209         ret = smu_read_smc_arg(smu, &param);
 210         if (ret)
 211                 return ret;
 212
 213         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 214          * now, we un-support it */
 215         *value = param & 0x7fffffff;
 216
 217         return ret;
 218 }
 219
 220 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 221                             uint32_t *value)
 222 {
 223         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 224 }
 225
 226 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 227                            bool gate)
 228 {
 229         int ret = 0;
 230
 231         switch (block_type) {
 232         case AMD_IP_BLOCK_TYPE_UVD:
 233                 ret = smu_dpm_set_uvd_enable(smu, gate);
 234                 break;
 235         case AMD_IP_BLOCK_TYPE_VCE:
 236                 ret = smu_dpm_set_vce_enable(smu, gate);
 237                 break;
 238         case AMD_IP_BLOCK_TYPE_GFX:
 239                 ret = smu_gfx_off_control(smu, gate);
 240                 break;
 241         default:
 242                 break;
 243         }
 244
 245         return ret;
 246 }
 247
 248 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 249 {
 250         /* not support power state */
 251         return POWER_STATE_TYPE_DEFAULT;
 252 }
 253
 254 int smu_get_power_num_states(struct smu_context *smu,
 255                              struct pp_states_info *state_info)
 256 {
 257         if (!state_info)
 258                 return -EINVAL;
 259
 260         /* not support power state */
 261         memset(state_info, 0, sizeof(struct pp_states_info));
 262         state_info->nums = 0;
 263
 264         return 0;
 265 }
 266
 267 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 268                            void *data, uint32_t *size)
 269 {
 270         int ret = 0;
 271
 272         switch (sensor) {
 273         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 274                 *((uint32_t *)data) = smu->pstate_sclk;
 275                 *size = 4;
 276                 break;
 277         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 278                 *((uint32_t *)data) = smu->pstate_mclk;
 279                 *size = 4;
 280                 break;
 281         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 282                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 283                 *size = 8;
 284                 break;
 285         case AMDGPU_PP_SENSOR_UVD_POWER:
 286                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 287                 *size = 4;
 288                 break;
 289         case AMDGPU_PP_SENSOR_VCE_POWER:
 290                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 291                 *size = 4;
 292                 break;
 293         default:
 294                 ret = -EINVAL;
 295                 break;
 296         }
 297
 298         if (ret)
 299                 *size = 0;
 300
 301         return ret;
 302 }
 303
 304 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
 305                      void *table_data, bool drv2smu)
 306 {
 307         struct smu_table_context *smu_table = &smu->smu_table;
 308         struct smu_table *table = NULL;
 309         int ret = 0;
 310         int table_id = smu_table_get_index(smu, table_index);
 311
 312         if (!table_data || table_id >= smu_table->table_count)
 313                 return -EINVAL;
 314
 315         table = &smu_table->tables[table_index];
 316
 317         if (drv2smu)
 318                 memcpy(table->cpu_addr, table_data, table->size);
 319
 320         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 321                                           upper_32_bits(table->mc_address));
 322         if (ret)
 323                 return ret;
 324         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 325                                           lower_32_bits(table->mc_address));
 326         if (ret)
 327                 return ret;
 328         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 329                                           SMU_MSG_TransferTableDram2Smu :
 330                                           SMU_MSG_TransferTableSmu2Dram,
 331                                           table_id);
 332         if (ret)
 333                 return ret;
 334
 335         if (!drv2smu)
 336                 memcpy(table_data, table->cpu_addr, table->size);
 337
 338         return ret;
 339 }
 340
 341 bool is_support_sw_smu(struct amdgpu_device *adev)
 342 {
 343         if (adev->asic_type == CHIP_VEGA20)
 344                 return (amdgpu_dpm == 2) ? true : false;
 345         else if (adev->asic_type >= CHIP_NAVI10)
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 352 {
 353         struct smu_table_context *smu_table = &smu->smu_table;
 354
 355         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 356                 return -EINVAL;
 357
 358         if (smu_table->hardcode_pptable)
 359                 *table = smu_table->hardcode_pptable;
 360         else
 361                 *table = smu_table->power_play_table;
 362
 363         return smu_table->power_play_table_size;
 364 }
 365
 366 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 367 {
 368         struct smu_table_context *smu_table = &smu->smu_table;
 369         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 370         int ret = 0;
 371
 372         if (!smu->pm_enabled)
 373                 return -EINVAL;
 374         if (header->usStructureSize != size) {
 375                 pr_err("pp table size not matched !\n");
 376                 return -EIO;
 377         }
 378
 379         mutex_lock(&smu->mutex);
 380         if (!smu_table->hardcode_pptable)
 381                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 382         if (!smu_table->hardcode_pptable) {
 383                 ret = -ENOMEM;
 384                 goto failed;
 385         }
 386
 387         memcpy(smu_table->hardcode_pptable, buf, size);
 388         smu_table->power_play_table = smu_table->hardcode_pptable;
 389         smu_table->power_play_table_size = size;
 390         mutex_unlock(&smu->mutex);
 391
 392         ret = smu_reset(smu);
 393         if (ret)
 394                 pr_info("smu reset failed, ret = %d\n", ret);
 395
 396         return ret;
 397
 398 failed:
 399         mutex_unlock(&smu->mutex);
 400         return ret;
 401 }
 402
 403 int smu_feature_init_dpm(struct smu_context *smu)
 404 {
 405         struct smu_feature *feature = &smu->smu_feature;
 406         int ret = 0;
 407         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 408
 409         if (!smu->pm_enabled)
 410                 return ret;
 411         mutex_lock(&feature->mutex);
 412         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 413         mutex_unlock(&feature->mutex);
 414
 415         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 416                                              SMU_FEATURE_MAX/32);
 417         if (ret)
 418                 return ret;
 419
 420         mutex_lock(&feature->mutex);
 421         bitmap_or(feature->allowed, feature->allowed,
 422                       (unsigned long *)allowed_feature_mask,
 423                       feature->feature_num);
 424         mutex_unlock(&feature->mutex);
 425
 426         return ret;
 427 }
 428
 429 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 430 {
 431         struct smu_feature *feature = &smu->smu_feature;
 432         uint32_t feature_id;
 433         int ret = 0;
 434
 435         feature_id = smu_feature_get_index(smu, mask);
 436
 437         WARN_ON(feature_id > feature->feature_num);
 438
 439         mutex_lock(&feature->mutex);
 440         ret = test_bit(feature_id, feature->enabled);
 441         mutex_unlock(&feature->mutex);
 442
 443         return ret;
 444 }
 445
 446 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 447                             bool enable)
 448 {
 449         struct smu_feature *feature = &smu->smu_feature;
 450         uint32_t feature_id;
 451         int ret = 0;
 452
 453         feature_id = smu_feature_get_index(smu, mask);
 454
 455         WARN_ON(feature_id > feature->feature_num);
 456
 457         mutex_lock(&feature->mutex);
 458         ret = smu_feature_update_enable_state(smu, feature_id, enable);
 459         if (ret)
 460                 goto failed;
 461
 462         if (enable)
 463                 test_and_set_bit(feature_id, feature->enabled);
 464         else
 465                 test_and_clear_bit(feature_id, feature->enabled);
 466
 467 failed:
 468         mutex_unlock(&feature->mutex);
 469
 470         return ret;
 471 }
 472
 473 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 474 {
 475         struct smu_feature *feature = &smu->smu_feature;
 476         uint32_t feature_id;
 477         int ret = 0;
 478
 479         feature_id = smu_feature_get_index(smu, mask);
 480
 481         WARN_ON(feature_id > feature->feature_num);
 482
 483         mutex_lock(&feature->mutex);
 484         ret = test_bit(feature_id, feature->supported);
 485         mutex_unlock(&feature->mutex);
 486
 487         return ret;
 488 }
 489
 490 int smu_feature_set_supported(struct smu_context *smu,
 491                               enum smu_feature_mask mask,
 492                               bool enable)
 493 {
 494         struct smu_feature *feature = &smu->smu_feature;
 495         uint32_t feature_id;
 496         int ret = 0;
 497
 498         feature_id = smu_feature_get_index(smu, mask);
 499
 500         WARN_ON(feature_id > feature->feature_num);
 501
 502         mutex_lock(&feature->mutex);
 503         if (enable)
 504                 test_and_set_bit(feature_id, feature->supported);
 505         else
 506                 test_and_clear_bit(feature_id, feature->supported);
 507         mutex_unlock(&feature->mutex);
 508
 509         return ret;
 510 }
 511
 512 static int smu_set_funcs(struct amdgpu_device *adev)
 513 {
 514         struct smu_context *smu = &adev->smu;
 515
 516         switch (adev->asic_type) {
 517         case CHIP_VEGA20:
 518         case CHIP_NAVI10:
 519                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 520                         smu->od_enabled = true;
 521                 smu_v11_0_set_smu_funcs(smu);
 522                 break;
 523         default:
 524                 return -EINVAL;
 525         }
 526
 527         return 0;
 528 }
 529
 530 static int smu_early_init(void *handle)
 531 {
 532         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 533         struct smu_context *smu = &adev->smu;
 534
 535         smu->adev = adev;
 536         smu->pm_enabled = !!amdgpu_dpm;
 537         mutex_init(&smu->mutex);
 538
 539         return smu_set_funcs(adev);
 540 }
 541
 542 static int smu_late_init(void *handle)
 543 {
 544         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 545         struct smu_context *smu = &adev->smu;
 546
 547         if (!smu->pm_enabled)
 548                 return 0;
 549         mutex_lock(&smu->mutex);
 550         smu_handle_task(&adev->smu,
 551                         smu->smu_dpm.dpm_level,
 552                         AMD_PP_TASK_COMPLETE_INIT);
 553         mutex_unlock(&smu->mutex);
 554
 555         return 0;
 556 }
 557
 558 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 559                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 560                             uint8_t **addr)
 561 {
 562         struct amdgpu_device *adev = smu->adev;
 563         uint16_t data_start;
 564
 565         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 566                                            size, frev, crev, &data_start))
 567                 return -EINVAL;
 568
 569         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 570
 571         return 0;
 572 }
 573
 574 static int smu_initialize_pptable(struct smu_context *smu)
 575 {
 576         /* TODO */
 577         return 0;
 578 }
 579
 580 static int smu_smc_table_sw_init(struct smu_context *smu)
 581 {
 582         int ret;
 583
 584         ret = smu_initialize_pptable(smu);
 585         if (ret) {
 586                 pr_err("Failed to init smu_initialize_pptable!\n");
 587                 return ret;
 588         }
 589
 590         /**
 591          * Create smu_table structure, and init smc tables such as
 592          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 593          */
 594         ret = smu_init_smc_tables(smu);
 595         if (ret) {
 596                 pr_err("Failed to init smc tables!\n");
 597                 return ret;
 598         }
 599
 600         /**
 601          * Create smu_power_context structure, and allocate smu_dpm_context and
 602          * context size to fill the smu_power_context data.
 603          */
 604         ret = smu_init_power(smu);
 605         if (ret) {
 606                 pr_err("Failed to init smu_init_power!\n");
 607                 return ret;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int smu_smc_table_sw_fini(struct smu_context *smu)
 614 {
 615         int ret;
 616
 617         ret = smu_fini_smc_tables(smu);
 618         if (ret) {
 619                 pr_err("Failed to smu_fini_smc_tables!\n");
 620                 return ret;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int smu_sw_init(void *handle)
 627 {
 628         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 629         struct smu_context *smu = &adev->smu;
 630         int ret;
 631
 632         smu->pool_size = adev->pm.smu_prv_buffer_size;
 633         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 634         mutex_init(&smu->smu_feature.mutex);
 635         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 636         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 637         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 638
 639         mutex_init(&smu->smu_baco.mutex);
 640         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 641         smu->smu_baco.platform_support = false;
 642
 643         smu->watermarks_bitmap = 0;
 644         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 645         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 646
 647         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 648         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 649         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 650         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 651         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 652         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 653         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 654         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 655
 656         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 657         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 658         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 659         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 660         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 661         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 662         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 663         smu->display_config = &adev->pm.pm_display_cfg;
 664
 665         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 666         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 667         ret = smu_init_microcode(smu);
 668         if (ret) {
 669                 pr_err("Failed to load smu firmware!\n");
 670                 return ret;
 671         }
 672
 673         ret = smu_smc_table_sw_init(smu);
 674         if (ret) {
 675                 pr_err("Failed to sw init smc table!\n");
 676                 return ret;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int smu_sw_fini(void *handle)
 683 {
 684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 685         struct smu_context *smu = &adev->smu;
 686         int ret;
 687
 688         ret = smu_smc_table_sw_fini(smu);
 689         if (ret) {
 690                 pr_err("Failed to sw fini smc table!\n");
 691                 return ret;
 692         }
 693
 694         ret = smu_fini_power(smu);
 695         if (ret) {
 696                 pr_err("Failed to init smu_fini_power!\n");
 697                 return ret;
 698         }
 699
 700         return 0;
 701 }
 702
 703 static int smu_init_fb_allocations(struct smu_context *smu)
 704 {
 705         struct amdgpu_device *adev = smu->adev;
 706         struct smu_table_context *smu_table = &smu->smu_table;
 707         struct smu_table *tables = smu_table->tables;
 708         uint32_t table_count = smu_table->table_count;
 709         uint32_t i = 0;
 710         int32_t ret = 0;
 711
 712         if (table_count <= 0)
 713                 return -EINVAL;
 714
 715         for (i = 0 ; i < table_count; i++) {
 716                 if (tables[i].size == 0)
 717                         continue;
 718                 ret = amdgpu_bo_create_kernel(adev,
 719                                               tables[i].size,
 720                                               tables[i].align,
 721                                               tables[i].domain,
 722                                               &tables[i].bo,
 723                                               &tables[i].mc_address,
 724                                               &tables[i].cpu_addr);
 725                 if (ret)
 726                         goto failed;
 727         }
 728
 729         return 0;
 730 failed:
 731         for (; i > 0; i--) {
 732                 if (tables[i].size == 0)
 733                         continue;
 734                 amdgpu_bo_free_kernel(&tables[i].bo,
 735                                       &tables[i].mc_address,
 736                                       &tables[i].cpu_addr);
 737
 738         }
 739         return ret;
 740 }
 741
 742 static int smu_fini_fb_allocations(struct smu_context *smu)
 743 {
 744         struct smu_table_context *smu_table = &smu->smu_table;
 745         struct smu_table *tables = smu_table->tables;
 746         uint32_t table_count = smu_table->table_count;
 747         uint32_t i = 0;
 748
 749         if (table_count == 0 || tables == NULL)
 750                 return 0;
 751
 752         for (i = 0 ; i < table_count; i++) {
 753                 if (tables[i].size == 0)
 754                         continue;
 755                 amdgpu_bo_free_kernel(&tables[i].bo,
 756                                       &tables[i].mc_address,
 757                                       &tables[i].cpu_addr);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int smu_override_pcie_parameters(struct smu_context *smu)
 764 {
 765         struct amdgpu_device *adev = smu->adev;
 766         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 767         int ret;
 768
 769         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 770                 pcie_gen = 3;
 771         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 772                 pcie_gen = 2;
 773         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 774                 pcie_gen = 1;
 775         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 776                 pcie_gen = 0;
 777
 778         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 779          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 780          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 781          */
 782         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 783                 pcie_width = 6;
 784         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 785                 pcie_width = 5;
 786         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 787                 pcie_width = 4;
 788         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 789                 pcie_width = 3;
 790         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 791                 pcie_width = 2;
 792         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 793                 pcie_width = 1;
 794
 795         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 796         ret = smu_send_smc_msg_with_param(smu,
 797                                           SMU_MSG_OverridePcieParameters,
 798                                           smu_pcie_arg);
 799         if (ret)
 800                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
 801         return ret;
 802 }
 803
 804 static int smu_smc_table_hw_init(struct smu_context *smu,
 805                                  bool initialize)
 806 {
 807         struct amdgpu_device *adev = smu->adev;
 808         int ret;
 809
 810         if (smu_is_dpm_running(smu) && adev->in_suspend) {
 811                 pr_info("dpm has been enabled\n");
 812                 return 0;
 813         }
 814
 815         ret = smu_init_display_count(smu, 0);
 816         if (ret)
 817                 return ret;
 818
 819         if (initialize) {
 820                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
 821                 ret = smu_get_vbios_bootup_values(smu);
 822                 if (ret)
 823                         return ret;
 824
 825                 ret = smu_setup_pptable(smu);
 826                 if (ret)
 827                         return ret;
 828
 829                 ret = smu_get_clk_info_from_vbios(smu);
 830                 if (ret)
 831                         return ret;
 832
 833                 /*
 834                  * check if the format_revision in vbios is up to pptable header
 835                  * version, and the structure size is not 0.
 836                  */
 837                 ret = smu_check_pptable(smu);
 838                 if (ret)
 839                         return ret;
 840
 841                 /*
 842                  * allocate vram bos to store smc table contents.
 843                  */
 844                 ret = smu_init_fb_allocations(smu);
 845                 if (ret)
 846                         return ret;
 847
 848                 /*
 849                  * Parse pptable format and fill PPTable_t smc_pptable to
 850                  * smu_table_context structure. And read the smc_dpm_table from vbios,
 851                  * then fill it into smc_pptable.
 852                  */
 853                 ret = smu_parse_pptable(smu);
 854                 if (ret)
 855                         return ret;
 856
 857                 /*
 858                  * Send msg GetDriverIfVersion to check if the return value is equal
 859                  * with DRIVER_IF_VERSION of smc header.
 860                  */
 861                 ret = smu_check_fw_version(smu);
 862                 if (ret)
 863                         return ret;
 864         }
 865
 866         /*
 867          * Copy pptable bo in the vram to smc with SMU MSGs such as
 868          * SetDriverDramAddr and TransferTableDram2Smu.
 869          */
 870         ret = smu_write_pptable(smu);
 871         if (ret)
 872                 return ret;
 873
 874         /* issue RunAfllBtc msg */
 875         ret = smu_run_afll_btc(smu);
 876         if (ret)
 877                 return ret;
 878
 879         ret = smu_feature_set_allowed_mask(smu);
 880         if (ret)
 881                 return ret;
 882
 883         ret = smu_system_features_control(smu, true);
 884         if (ret)
 885                 return ret;
 886
 887         ret = smu_override_pcie_parameters(smu);
 888         if (ret)
 889                 return ret;
 890
 891         ret = smu_notify_display_change(smu);
 892         if (ret)
 893                 return ret;
 894
 895         /*
 896          * Set min deep sleep dce fclk with bootup value from vbios via
 897          * SetMinDeepSleepDcefclk MSG.
 898          */
 899         ret = smu_set_min_dcef_deep_sleep(smu);
 900         if (ret)
 901                 return ret;
 902
 903         /*
 904          * Set initialized values (get from vbios) to dpm tables context such as
 905          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 906          * type of clks.
 907          */
 908         if (initialize) {
 909                 ret = smu_populate_smc_pptable(smu);
 910                 if (ret)
 911                         return ret;
 912
 913                 ret = smu_init_max_sustainable_clocks(smu);
 914                 if (ret)
 915                         return ret;
 916         }
 917
 918         ret = smu_set_default_od_settings(smu, initialize);
 919         if (ret)
 920                 return ret;
 921
 922         if (initialize) {
 923                 ret = smu_populate_umd_state_clk(smu);
 924                 if (ret)
 925                         return ret;
 926
 927                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 928                 if (ret)
 929                         return ret;
 930         }
 931
 932         /*
 933          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 934          */
 935         ret = smu_set_tool_table_location(smu);
 936
 937         if (!smu_is_dpm_running(smu))
 938                 pr_info("dpm has been disabled\n");
 939
 940         return ret;
 941 }
 942
 943 /**
 944  * smu_alloc_memory_pool - allocate memory pool in the system memory
 945  *
 946  * @smu: amdgpu_device pointer
 947  *
 948  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 949  * and DramLogSetDramAddr can notify it changed.
 950  *
 951  * Returns 0 on success, error on failure.
 952  */
 953 static int smu_alloc_memory_pool(struct smu_context *smu)
 954 {
 955         struct amdgpu_device *adev = smu->adev;
 956         struct smu_table_context *smu_table = &smu->smu_table;
 957         struct smu_table *memory_pool = &smu_table->memory_pool;
 958         uint64_t pool_size = smu->pool_size;
 959         int ret = 0;
 960
 961         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 962                 return ret;
 963
 964         memory_pool->size = pool_size;
 965         memory_pool->align = PAGE_SIZE;
 966         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 967
 968         switch (pool_size) {
 969         case SMU_MEMORY_POOL_SIZE_256_MB:
 970         case SMU_MEMORY_POOL_SIZE_512_MB:
 971         case SMU_MEMORY_POOL_SIZE_1_GB:
 972         case SMU_MEMORY_POOL_SIZE_2_GB:
 973                 ret = amdgpu_bo_create_kernel(adev,
 974                                               memory_pool->size,
 975                                               memory_pool->align,
 976                                               memory_pool->domain,
 977                                               &memory_pool->bo,
 978                                               &memory_pool->mc_address,
 979                                               &memory_pool->cpu_addr);
 980                 break;
 981         default:
 982                 break;
 983         }
 984
 985         return ret;
 986 }
 987
 988 static int smu_free_memory_pool(struct smu_context *smu)
 989 {
 990         struct smu_table_context *smu_table = &smu->smu_table;
 991         struct smu_table *memory_pool = &smu_table->memory_pool;
 992         int ret = 0;
 993
 994         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 995                 return ret;
 996
 997         amdgpu_bo_free_kernel(&memory_pool->bo,
 998                               &memory_pool->mc_address,
 999                               &memory_pool->cpu_addr);
1000
1001         memset(memory_pool, 0, sizeof(struct smu_table));
1002
1003         return ret;
1004 }
1005
1006 static int smu_hw_init(void *handle)
1007 {
1008         int ret;
1009         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1010         struct smu_context *smu = &adev->smu;
1011
1012         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1013                 ret = smu_check_fw_status(smu);
1014                 if (ret) {
1015                         pr_err("SMC firmware status is not correct\n");
1016                         return ret;
1017                 }
1018         }
1019
1020         ret = smu_feature_init_dpm(smu);
1021         if (ret)
1022                 goto failed;
1023
1024         ret = smu_smc_table_hw_init(smu, true);
1025         if (ret)
1026                 goto failed;
1027
1028         ret = smu_alloc_memory_pool(smu);
1029         if (ret)
1030                 goto failed;
1031
1032         /*
1033          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1034          * pool location.
1035          */
1036         ret = smu_notify_memory_pool_location(smu);
1037         if (ret)
1038                 goto failed;
1039
1040         ret = smu_start_thermal_control(smu);
1041         if (ret)
1042                 goto failed;
1043
1044         ret = smu_register_irq_handler(smu);
1045         if (ret)
1046                 goto failed;
1047
1048         if (!smu->pm_enabled)
1049                 adev->pm.dpm_enabled = false;
1050         else
1051                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1052
1053         pr_info("SMU is initialized successfully!\n");
1054
1055         return 0;
1056
1057 failed:
1058         return ret;
1059 }
1060
1061 static int smu_hw_fini(void *handle)
1062 {
1063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064         struct smu_context *smu = &adev->smu;
1065         struct smu_table_context *table_context = &smu->smu_table;
1066         int ret = 0;
1067
1068         kfree(table_context->driver_pptable);
1069         table_context->driver_pptable = NULL;
1070
1071         kfree(table_context->max_sustainable_clocks);
1072         table_context->max_sustainable_clocks = NULL;
1073
1074         kfree(table_context->overdrive_table);
1075         table_context->overdrive_table = NULL;
1076
1077         kfree(smu->irq_source);
1078         smu->irq_source = NULL;
1079
1080         ret = smu_fini_fb_allocations(smu);
1081         if (ret)
1082                 return ret;
1083
1084         ret = smu_free_memory_pool(smu);
1085         if (ret)
1086                 return ret;
1087
1088         return 0;
1089 }
1090
1091 int smu_reset(struct smu_context *smu)
1092 {
1093         struct amdgpu_device *adev = smu->adev;
1094         int ret = 0;
1095
1096         ret = smu_hw_fini(adev);
1097         if (ret)
1098                 return ret;
1099
1100         ret = smu_hw_init(adev);
1101         if (ret)
1102                 return ret;
1103
1104         return ret;
1105 }
1106
1107 static int smu_suspend(void *handle)
1108 {
1109         int ret;
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111         struct smu_context *smu = &adev->smu;
1112         bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1113
1114         ret = smu_system_features_control(smu, false);
1115         if (ret)
1116                 return ret;
1117
1118         if (adev->in_gpu_reset && baco_feature_is_enabled) {
1119                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1120                 if (ret) {
1121                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1122                         return ret;
1123                 }
1124         }
1125
1126         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1127
1128         if (adev->asic_type >= CHIP_NAVI10 &&
1129             adev->gfx.rlc.funcs->stop)
1130                 adev->gfx.rlc.funcs->stop(adev);
1131
1132         return 0;
1133 }
1134
1135 static int smu_resume(void *handle)
1136 {
1137         int ret;
1138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139         struct smu_context *smu = &adev->smu;
1140
1141         pr_info("SMU is resuming...\n");
1142
1143         mutex_lock(&smu->mutex);
1144
1145         ret = smu_smc_table_hw_init(smu, false);
1146         if (ret)
1147                 goto failed;
1148
1149         ret = smu_start_thermal_control(smu);
1150         if (ret)
1151                 goto failed;
1152
1153         mutex_unlock(&smu->mutex);
1154
1155         pr_info("SMU is resumed successfully!\n");
1156
1157         return 0;
1158 failed:
1159         mutex_unlock(&smu->mutex);
1160         return ret;
1161 }
1162
1163 int smu_display_configuration_change(struct smu_context *smu,
1164                                      const struct amd_pp_display_configuration *display_config)
1165 {
1166         int index = 0;
1167         int num_of_active_display = 0;
1168
1169         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1170                 return -EINVAL;
1171
1172         if (!display_config)
1173                 return -EINVAL;
1174
1175         mutex_lock(&smu->mutex);
1176
1177         smu_set_deep_sleep_dcefclk(smu,
1178                                    display_config->min_dcef_deep_sleep_set_clk / 100);
1179
1180         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1181                 if (display_config->displays[index].controller_id != 0)
1182                         num_of_active_display++;
1183         }
1184
1185         smu_set_active_display_count(smu, num_of_active_display);
1186
1187         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1188                            display_config->cpu_cc6_disable,
1189                            display_config->cpu_pstate_disable,
1190                            display_config->nb_pstate_switch_disable);
1191
1192         mutex_unlock(&smu->mutex);
1193
1194         return 0;
1195 }
1196
1197 static int smu_get_clock_info(struct smu_context *smu,
1198                               struct smu_clock_info *clk_info,
1199                               enum smu_perf_level_designation designation)
1200 {
1201         int ret;
1202         struct smu_performance_level level = {0};
1203
1204         if (!clk_info)
1205                 return -EINVAL;
1206
1207         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1208         if (ret)
1209                 return -EINVAL;
1210
1211         clk_info->min_mem_clk = level.memory_clock;
1212         clk_info->min_eng_clk = level.core_clock;
1213         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1214
1215         ret = smu_get_perf_level(smu, designation, &level);
1216         if (ret)
1217                 return -EINVAL;
1218
1219         clk_info->min_mem_clk = level.memory_clock;
1220         clk_info->min_eng_clk = level.core_clock;
1221         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1222
1223         return 0;
1224 }
1225
1226 int smu_get_current_clocks(struct smu_context *smu,
1227                            struct amd_pp_clock_info *clocks)
1228 {
1229         struct amd_pp_simple_clock_info simple_clocks = {0};
1230         struct smu_clock_info hw_clocks;
1231         int ret = 0;
1232
1233         if (!is_support_sw_smu(smu->adev))
1234                 return -EINVAL;
1235
1236         mutex_lock(&smu->mutex);
1237
1238         smu_get_dal_power_level(smu, &simple_clocks);
1239
1240         if (smu->support_power_containment)
1241                 ret = smu_get_clock_info(smu, &hw_clocks,
1242                                          PERF_LEVEL_POWER_CONTAINMENT);
1243         else
1244                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1245
1246         if (ret) {
1247                 pr_err("Error in smu_get_clock_info\n");
1248                 goto failed;
1249         }
1250
1251         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1252         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1253         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1254         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1255         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1256         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1257         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1258         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1259
1260         if (simple_clocks.level == 0)
1261                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1262         else
1263                 clocks->max_clocks_state = simple_clocks.level;
1264
1265         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1266                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1267                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1268         }
1269
1270 failed:
1271         mutex_unlock(&smu->mutex);
1272         return ret;
1273 }
1274
1275 static int smu_set_clockgating_state(void *handle,
1276                                      enum amd_clockgating_state state)
1277 {
1278         return 0;
1279 }
1280
1281 static int smu_set_powergating_state(void *handle,
1282                                      enum amd_powergating_state state)
1283 {
1284         return 0;
1285 }
1286
1287 static int smu_enable_umd_pstate(void *handle,
1288                       enum amd_dpm_forced_level *level)
1289 {
1290         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1291                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1292                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1293                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1294
1295         struct smu_context *smu = (struct smu_context*)(handle);
1296         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1297         if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1298                 return -EINVAL;
1299
1300         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1301                 /* enter umd pstate, save current level, disable gfx cg*/
1302                 if (*level & profile_mode_mask) {
1303                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1304                         smu_dpm_ctx->enable_umd_pstate = true;
1305                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1306                                                                AMD_IP_BLOCK_TYPE_GFX,
1307                                                                AMD_CG_STATE_UNGATE);
1308                         amdgpu_device_ip_set_powergating_state(smu->adev,
1309                                                                AMD_IP_BLOCK_TYPE_GFX,
1310                                                                AMD_PG_STATE_UNGATE);
1311                 }
1312         } else {
1313                 /* exit umd pstate, restore level, enable gfx cg*/
1314                 if (!(*level & profile_mode_mask)) {
1315                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1316                                 *level = smu_dpm_ctx->saved_dpm_level;
1317                         smu_dpm_ctx->enable_umd_pstate = false;
1318                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1319                                                                AMD_IP_BLOCK_TYPE_GFX,
1320                                                                AMD_CG_STATE_GATE);
1321                         amdgpu_device_ip_set_powergating_state(smu->adev,
1322                                                                AMD_IP_BLOCK_TYPE_GFX,
1323                                                                AMD_PG_STATE_GATE);
1324                 }
1325         }
1326
1327         return 0;
1328 }
1329
1330 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1331                                    enum amd_dpm_forced_level level,
1332                                    bool skip_display_settings)
1333 {
1334         int ret = 0;
1335         int index = 0;
1336         uint32_t sclk_mask, mclk_mask, soc_mask;
1337         long workload;
1338         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1339
1340         if (!smu->pm_enabled)
1341                 return -EINVAL;
1342         if (!skip_display_settings) {
1343                 ret = smu_display_config_changed(smu);
1344                 if (ret) {
1345                         pr_err("Failed to change display config!");
1346                         return ret;
1347                 }
1348         }
1349
1350         if (!smu->pm_enabled)
1351                 return -EINVAL;
1352         ret = smu_apply_clocks_adjust_rules(smu);
1353         if (ret) {
1354                 pr_err("Failed to apply clocks adjust rules!");
1355                 return ret;
1356         }
1357
1358         if (!skip_display_settings) {
1359                 ret = smu_notify_smc_dispaly_config(smu);
1360                 if (ret) {
1361                         pr_err("Failed to notify smc display config!");
1362                         return ret;
1363                 }
1364         }
1365
1366         if (smu_dpm_ctx->dpm_level != level) {
1367                 switch (level) {
1368                 case AMD_DPM_FORCED_LEVEL_HIGH:
1369                         ret = smu_force_dpm_limit_value(smu, true);
1370                         break;
1371                 case AMD_DPM_FORCED_LEVEL_LOW:
1372                         ret = smu_force_dpm_limit_value(smu, false);
1373                         break;
1374
1375                 case AMD_DPM_FORCED_LEVEL_AUTO:
1376                         ret = smu_unforce_dpm_levels(smu);
1377                         break;
1378
1379                 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1380                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1381                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1382                 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1383                         ret = smu_get_profiling_clk_mask(smu, level,
1384                                                          &sclk_mask,
1385                                                          &mclk_mask,
1386                                                          &soc_mask);
1387                         if (ret)
1388                                 return ret;
1389                         smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1390                         smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1391                         break;
1392
1393                 case AMD_DPM_FORCED_LEVEL_MANUAL:
1394                 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1395                 default:
1396                         break;
1397                 }
1398
1399                 if (!ret)
1400                         smu_dpm_ctx->dpm_level = level;
1401         }
1402
1403         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1404                 index = fls(smu->workload_mask);
1405                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1406                 workload = smu->workload_setting[index];
1407
1408                 if (smu->power_profile_mode != workload)
1409                         smu_set_power_profile_mode(smu, &workload, 0);
1410         }
1411
1412         return ret;
1413 }
1414
1415 int smu_handle_task(struct smu_context *smu,
1416                     enum amd_dpm_forced_level level,
1417                     enum amd_pp_task task_id)
1418 {
1419         int ret = 0;
1420
1421         switch (task_id) {
1422         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1423                 ret = smu_pre_display_config_changed(smu);
1424                 if (ret)
1425                         return ret;
1426                 ret = smu_set_cpu_power_state(smu);
1427                 if (ret)
1428                         return ret;
1429                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1430                 break;
1431         case AMD_PP_TASK_COMPLETE_INIT:
1432         case AMD_PP_TASK_READJUST_POWER_STATE:
1433                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1434                 break;
1435         default:
1436                 break;
1437         }
1438
1439         return ret;
1440 }
1441
1442 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1443 {
1444         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1445
1446         if (!smu_dpm_ctx->dpm_context)
1447                 return -EINVAL;
1448
1449         mutex_lock(&(smu->mutex));
1450         if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
1451                 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1452         }
1453         mutex_unlock(&(smu->mutex));
1454
1455         return smu_dpm_ctx->dpm_level;
1456 }
1457
1458 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1459 {
1460         int ret = 0;
1461         int i;
1462         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1463
1464         if (!smu_dpm_ctx->dpm_context)
1465                 return -EINVAL;
1466
1467         for (i = 0; i < smu->adev->num_ip_blocks; i++) {
1468                 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
1469                         break;
1470         }
1471
1472
1473         smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
1474         ret = smu_handle_task(smu, level,
1475                               AMD_PP_TASK_READJUST_POWER_STATE);
1476         if (ret)
1477                 return ret;
1478
1479         mutex_lock(&smu->mutex);
1480         smu_dpm_ctx->dpm_level = level;
1481         mutex_unlock(&smu->mutex);
1482
1483         return ret;
1484 }
1485
1486 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1487 {
1488         int ret = 0;
1489
1490         mutex_lock(&smu->mutex);
1491         ret = smu_init_display_count(smu, count);
1492         mutex_unlock(&smu->mutex);
1493
1494         return ret;
1495 }
1496
1497 const struct amd_ip_funcs smu_ip_funcs = {
1498         .name = "smu",
1499         .early_init = smu_early_init,
1500         .late_init = smu_late_init,
1501         .sw_init = smu_sw_init,
1502         .sw_fini = smu_sw_fini,
1503         .hw_init = smu_hw_init,
1504         .hw_fini = smu_hw_fini,
1505         .suspend = smu_suspend,
1506         .resume = smu_resume,
1507         .is_idle = NULL,
1508         .check_soft_reset = NULL,
1509         .wait_for_idle = NULL,
1510         .soft_reset = NULL,
1511         .set_clockgating_state = smu_set_clockgating_state,
1512         .set_powergating_state = smu_set_powergating_state,
1513         .enable_umd_pstate = smu_enable_umd_pstate,
1514 };
1515
1516 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1517 {
1518         .type = AMD_IP_BLOCK_TYPE_SMC,
1519         .major = 11,
1520         .minor = 0,
1521         .rev = 0,
1522         .funcs = &smu_ip_funcs,
1523 };