2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L4
26 #include "amdgpu_smu.h"
28 #include "soc15_common.h"
31 * DO NOT use these for err/warn/info/debug messages.
32 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
33 * They are more MGPU friendly.
41 * Although these are defined in each ASIC's specific header file.
42 * They share the same definitions and values. That makes common
43 * APIs for SMC messages issuing for all ASICs possible.
45 #define mmMP1_SMN_C2PMSG_66 0x0282
46 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
48 #define mmMP1_SMN_C2PMSG_82 0x0292
49 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
51 #define mmMP1_SMN_C2PMSG_90 0x029a
52 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
54 /* SMU 13.0.5 has its specific mailbox messaging registers */
56 #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
57 #define mmMP1_C2PMSG_2_BASE_IDX 0
59 #define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
60 #define mmMP1_C2PMSG_34_BASE_IDX 0
62 #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
63 #define mmMP1_C2PMSG_33_BASE_IDX 0
65 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
67 #undef __SMU_DUMMY_MAP
68 #define __SMU_DUMMY_MAP(type) #type
69 static const char * const __smu_message_names[] = {
73 #define smu_cmn_call_asic_func(intf, smu, args...) \
74 ((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? \
75 (smu)->ppt_funcs->intf(smu, ##args) : \
79 static const char *smu_get_message_name(struct smu_context *smu,
80 enum smu_message_type type)
82 if (type < 0 || type >= SMU_MSG_MAX_COUNT)
83 return "unknown smu message";
85 return __smu_message_names[type];
88 static void smu_cmn_read_arg(struct smu_context *smu,
91 struct amdgpu_device *adev = smu->adev;
93 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
94 *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
96 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
99 /* Redefine the SMU error codes here.
101 * Note that these definitions are redundant and should be removed
102 * when the SMU has exported a unified header file containing these
103 * macros, which header file we can just include and use the SMU's
104 * macros. At the moment, these error codes are defined by the SMU
105 * per-ASIC unfortunately, yet we're a one driver for all ASICs.
107 #define SMU_RESP_NONE 0
108 #define SMU_RESP_OK 1
109 #define SMU_RESP_CMD_FAIL 0xFF
110 #define SMU_RESP_CMD_UNKNOWN 0xFE
111 #define SMU_RESP_CMD_BAD_PREREQ 0xFD
112 #define SMU_RESP_BUSY_OTHER 0xFC
113 #define SMU_RESP_DEBUG_END 0xFB
116 * __smu_cmn_poll_stat -- poll for a status from the SMU
117 * @smu: a pointer to SMU context
119 * Returns the status of the SMU, which could be,
120 * 0, the SMU is busy with your command;
121 * 1, execution status: success, execution result: success;
122 * 0xFF, execution status: success, execution result: failure;
123 * 0xFE, unknown command;
124 * 0xFD, valid command, but bad (command) prerequisites;
125 * 0xFC, the command was rejected as the SMU is busy;
126 * 0xFB, "SMC_Result_DebugDataDumpEnd".
128 * The values here are not defined by macros, because I'd rather we
129 * include a single header file which defines them, which is
130 * maintained by the SMU FW team, so that we're impervious to firmware
131 * changes. At the moment those values are defined in various header
132 * files, one for each ASIC, yet here we're a single ASIC-agnostic
133 * interface. Such a change can be followed-up by a subsequent patch.
135 static u32 __smu_cmn_poll_stat(struct smu_context *smu)
137 struct amdgpu_device *adev = smu->adev;
138 int timeout = adev->usec_timeout * 20;
141 for ( ; timeout > 0; timeout--) {
142 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
143 reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
145 reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
146 if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
155 static void __smu_cmn_reg_print_error(struct smu_context *smu,
159 enum smu_message_type msg)
161 struct amdgpu_device *adev = smu->adev;
162 const char *message = smu_get_message_name(smu, msg);
165 switch (reg_c2pmsg_90) {
166 case SMU_RESP_NONE: {
167 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
168 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
169 prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
171 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
172 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
174 dev_err_ratelimited(adev->dev,
175 "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
180 /* The SMU executed the command. It completed with a
184 case SMU_RESP_CMD_FAIL:
185 /* The SMU executed the command. It completed with an
186 * unsuccessful result.
189 case SMU_RESP_CMD_UNKNOWN:
190 dev_err_ratelimited(adev->dev,
191 "SMU: unknown command: index:%d param:0x%08X message:%s",
192 msg_index, param, message);
194 case SMU_RESP_CMD_BAD_PREREQ:
195 dev_err_ratelimited(adev->dev,
196 "SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s",
197 msg_index, param, message);
199 case SMU_RESP_BUSY_OTHER:
200 dev_err_ratelimited(adev->dev,
201 "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s",
202 msg_index, param, message);
204 case SMU_RESP_DEBUG_END:
205 dev_err_ratelimited(adev->dev,
206 "SMU: I'm debugging!");
209 dev_err_ratelimited(adev->dev,
210 "SMU: response:0x%08X for index:%d param:0x%08X message:%s?",
211 reg_c2pmsg_90, msg_index, param, message);
216 static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)
220 switch (reg_c2pmsg_90) {
222 /* The SMU is busy--still executing your command.
229 case SMU_RESP_CMD_FAIL:
230 /* Command completed successfully, but the command
231 * status was failure.
235 case SMU_RESP_CMD_UNKNOWN:
236 /* Unknown command--ignored by the SMU.
240 case SMU_RESP_CMD_BAD_PREREQ:
241 /* Valid command--bad prerequisites.
245 case SMU_RESP_BUSY_OTHER:
246 /* The SMU is busy with other commands. The client
247 * should retry in 10 us.
252 /* Unknown or debug response from the SMU.
261 static void __smu_cmn_send_msg(struct smu_context *smu,
265 struct amdgpu_device *adev = smu->adev;
267 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
268 WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
269 WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
270 WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
272 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
273 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
274 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
280 * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status
281 * @smu: pointer to an SMU context
282 * @msg_index: message index
283 * @param: message parameter to send to the SMU
285 * Send a message to the SMU with the parameter passed. Do not wait
286 * for status/result of the message, thus the "without_waiting".
288 * Return 0 on success, -errno on error if we weren't able to _send_
289 * the message for some reason. See __smu_cmn_reg2errno() for details
292 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
296 struct amdgpu_device *adev = smu->adev;
300 if (adev->no_hw_access)
303 reg = __smu_cmn_poll_stat(smu);
304 res = __smu_cmn_reg2errno(smu, reg);
305 if (reg == SMU_RESP_NONE ||
308 __smu_cmn_send_msg(smu, msg_index, param);
311 if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
312 res && (res != -ETIME)) {
313 amdgpu_device_halt(adev);
321 * smu_cmn_wait_for_response -- wait for response from the SMU
322 * @smu: pointer to an SMU context
324 * Wait for status from the SMU.
326 * Return 0 on success, -errno on error, indicating the execution
327 * status and result of the message being waited for. See
328 * __smu_cmn_reg2errno() for details of the -errno.
330 int smu_cmn_wait_for_response(struct smu_context *smu)
335 reg = __smu_cmn_poll_stat(smu);
336 res = __smu_cmn_reg2errno(smu, reg);
338 if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
339 res && (res != -ETIME)) {
340 amdgpu_device_halt(smu->adev);
348 * smu_cmn_send_smc_msg_with_param -- send a message with parameter
349 * @smu: pointer to an SMU context
350 * @msg: message to send
351 * @param: parameter to send to the SMU
352 * @read_arg: pointer to u32 to return a value from the SMU back
355 * Send the message @msg with parameter @param to the SMU, wait for
356 * completion of the command, and return back a value from the SMU in
359 * Return 0 on success, -errno on error, if we weren't able to send
360 * the message or if the message completed with some kind of
361 * error. See __smu_cmn_reg2errno() for details of the -errno.
363 * If we weren't able to send the message to the SMU, we also print
364 * the error to the standard log.
366 * Command completion status is printed only if the -errno is
367 * -EREMOTEIO, indicating that the SMU returned back an
368 * undefined/unknown/unspecified result. All other cases are
369 * well-defined, not printed, but instead given back to the client to
370 * decide what further to do.
372 * The return value, @read_arg is read back regardless, to give back
373 * more information to the client, which on error would most likely be
374 * @param, but we can't assume that. This also eliminates more
377 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
378 enum smu_message_type msg,
382 struct amdgpu_device *adev = smu->adev;
386 if (adev->no_hw_access)
389 index = smu_cmn_to_asic_specific_index(smu,
390 CMN2ASIC_MAPPING_MSG,
393 return index == -EACCES ? 0 : index;
395 mutex_lock(&smu->message_lock);
396 reg = __smu_cmn_poll_stat(smu);
397 res = __smu_cmn_reg2errno(smu, reg);
398 if (reg == SMU_RESP_NONE ||
400 __smu_cmn_reg_print_error(smu, reg, index, param, msg);
403 __smu_cmn_send_msg(smu, (uint16_t) index, param);
404 reg = __smu_cmn_poll_stat(smu);
405 res = __smu_cmn_reg2errno(smu, reg);
407 __smu_cmn_reg_print_error(smu, reg, index, param, msg);
409 smu_cmn_read_arg(smu, read_arg);
411 if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) {
412 amdgpu_device_halt(adev);
416 mutex_unlock(&smu->message_lock);
420 int smu_cmn_send_smc_msg(struct smu_context *smu,
421 enum smu_message_type msg,
424 return smu_cmn_send_smc_msg_with_param(smu,
430 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
431 enum smu_cmn2asic_mapping_type type,
434 struct cmn2asic_msg_mapping msg_mapping;
435 struct cmn2asic_mapping mapping;
438 case CMN2ASIC_MAPPING_MSG:
439 if (index >= SMU_MSG_MAX_COUNT ||
443 msg_mapping = smu->message_map[index];
444 if (!msg_mapping.valid_mapping)
447 if (amdgpu_sriov_vf(smu->adev) &&
448 !msg_mapping.valid_in_vf)
451 return msg_mapping.map_to;
453 case CMN2ASIC_MAPPING_CLK:
454 if (index >= SMU_CLK_COUNT ||
458 mapping = smu->clock_map[index];
459 if (!mapping.valid_mapping)
462 return mapping.map_to;
464 case CMN2ASIC_MAPPING_FEATURE:
465 if (index >= SMU_FEATURE_COUNT ||
469 mapping = smu->feature_map[index];
470 if (!mapping.valid_mapping)
473 return mapping.map_to;
475 case CMN2ASIC_MAPPING_TABLE:
476 if (index >= SMU_TABLE_COUNT ||
480 mapping = smu->table_map[index];
481 if (!mapping.valid_mapping)
484 return mapping.map_to;
486 case CMN2ASIC_MAPPING_PWR:
487 if (index >= SMU_POWER_SOURCE_COUNT ||
491 mapping = smu->pwr_src_map[index];
492 if (!mapping.valid_mapping)
495 return mapping.map_to;
497 case CMN2ASIC_MAPPING_WORKLOAD:
498 if (index > PP_SMC_POWER_PROFILE_CUSTOM ||
502 mapping = smu->workload_map[index];
503 if (!mapping.valid_mapping)
506 return mapping.map_to;
513 int smu_cmn_feature_is_supported(struct smu_context *smu,
514 enum smu_feature_mask mask)
516 struct smu_feature *feature = &smu->smu_feature;
519 feature_id = smu_cmn_to_asic_specific_index(smu,
520 CMN2ASIC_MAPPING_FEATURE,
525 WARN_ON(feature_id > feature->feature_num);
527 return test_bit(feature_id, feature->supported);
530 static int __smu_get_enabled_features(struct smu_context *smu,
531 uint64_t *enabled_features)
533 return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
536 int smu_cmn_feature_is_enabled(struct smu_context *smu,
537 enum smu_feature_mask mask)
539 struct amdgpu_device *adev = smu->adev;
540 uint64_t enabled_features;
543 if (__smu_get_enabled_features(smu, &enabled_features)) {
544 dev_err(adev->dev, "Failed to retrieve enabled ppfeatures!\n");
549 * For Renoir and Cyan Skillfish, they are assumed to have all features
550 * enabled. Also considering they have no feature_map available, the
551 * check here can avoid unwanted feature_map check below.
553 if (enabled_features == ULLONG_MAX)
556 feature_id = smu_cmn_to_asic_specific_index(smu,
557 CMN2ASIC_MAPPING_FEATURE,
562 return test_bit(feature_id, (unsigned long *)&enabled_features);
565 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
566 enum smu_clk_type clk_type)
568 enum smu_feature_mask feature_id = 0;
573 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
577 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
580 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
586 if (!smu_cmn_feature_is_enabled(smu, feature_id))
592 int smu_cmn_get_enabled_mask(struct smu_context *smu,
593 uint64_t *feature_mask)
595 uint32_t *feature_mask_high;
596 uint32_t *feature_mask_low;
597 int ret = 0, index = 0;
602 feature_mask_low = &((uint32_t *)feature_mask)[0];
603 feature_mask_high = &((uint32_t *)feature_mask)[1];
605 index = smu_cmn_to_asic_specific_index(smu,
606 CMN2ASIC_MAPPING_MSG,
607 SMU_MSG_GetEnabledSmuFeatures);
609 ret = smu_cmn_send_smc_msg_with_param(smu,
610 SMU_MSG_GetEnabledSmuFeatures,
616 ret = smu_cmn_send_smc_msg_with_param(smu,
617 SMU_MSG_GetEnabledSmuFeatures,
621 ret = smu_cmn_send_smc_msg(smu,
622 SMU_MSG_GetEnabledSmuFeaturesHigh,
627 ret = smu_cmn_send_smc_msg(smu,
628 SMU_MSG_GetEnabledSmuFeaturesLow,
635 uint64_t smu_cmn_get_indep_throttler_status(
636 const unsigned long dep_status,
637 const uint8_t *throttler_map)
639 uint64_t indep_status = 0;
642 for_each_set_bit(dep_bit, &dep_status, 32)
643 indep_status |= 1ULL << throttler_map[dep_bit];
648 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
649 uint64_t feature_mask,
655 ret = smu_cmn_send_smc_msg_with_param(smu,
656 SMU_MSG_EnableSmuFeaturesLow,
657 lower_32_bits(feature_mask),
661 ret = smu_cmn_send_smc_msg_with_param(smu,
662 SMU_MSG_EnableSmuFeaturesHigh,
663 upper_32_bits(feature_mask),
666 ret = smu_cmn_send_smc_msg_with_param(smu,
667 SMU_MSG_DisableSmuFeaturesLow,
668 lower_32_bits(feature_mask),
672 ret = smu_cmn_send_smc_msg_with_param(smu,
673 SMU_MSG_DisableSmuFeaturesHigh,
674 upper_32_bits(feature_mask),
681 int smu_cmn_feature_set_enabled(struct smu_context *smu,
682 enum smu_feature_mask mask,
687 feature_id = smu_cmn_to_asic_specific_index(smu,
688 CMN2ASIC_MAPPING_FEATURE,
693 return smu_cmn_feature_update_enable_state(smu,
698 #undef __SMU_DUMMY_MAP
699 #define __SMU_DUMMY_MAP(fea) #fea
700 static const char* __smu_feature_names[] = {
704 static const char *smu_get_feature_name(struct smu_context *smu,
705 enum smu_feature_mask feature)
707 if (feature < 0 || feature >= SMU_FEATURE_COUNT)
708 return "unknown smu feature";
709 return __smu_feature_names[feature];
712 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
715 uint64_t feature_mask;
716 int feature_index = 0;
718 int8_t sort_feature[SMU_FEATURE_COUNT];
723 ret = __smu_get_enabled_features(smu, &feature_mask);
727 size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
728 upper_32_bits(feature_mask), lower_32_bits(feature_mask));
730 memset(sort_feature, -1, sizeof(sort_feature));
732 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
733 feature_index = smu_cmn_to_asic_specific_index(smu,
734 CMN2ASIC_MAPPING_FEATURE,
736 if (feature_index < 0)
739 sort_feature[feature_index] = i;
742 size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n",
743 "No", "Feature", "Bit", "State");
745 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
746 if (sort_feature[i] < 0)
749 /* convert to asic spcific feature ID */
750 feature_id = smu_cmn_to_asic_specific_index(smu,
751 CMN2ASIC_MAPPING_FEATURE,
756 size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
758 smu_get_feature_name(smu, sort_feature[i]),
760 !!test_bit(feature_id, (unsigned long *)&feature_mask) ?
761 "enabled" : "disabled");
767 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
771 uint64_t feature_mask;
772 uint64_t feature_2_enabled = 0;
773 uint64_t feature_2_disabled = 0;
775 ret = __smu_get_enabled_features(smu, &feature_mask);
779 feature_2_enabled = ~feature_mask & new_mask;
780 feature_2_disabled = feature_mask & ~new_mask;
782 if (feature_2_enabled) {
783 ret = smu_cmn_feature_update_enable_state(smu,
789 if (feature_2_disabled) {
790 ret = smu_cmn_feature_update_enable_state(smu,
801 * smu_cmn_disable_all_features_with_exception - disable all dpm features
802 * except this specified by
805 * @smu: smu_context pointer
806 * @mask: the dpm feature which should not be disabled
807 * SMU_FEATURE_COUNT: no exception, all dpm features
811 * 0 on success or a negative error code on failure.
813 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
814 enum smu_feature_mask mask)
816 uint64_t features_to_disable = U64_MAX;
817 int skipped_feature_id;
819 if (mask != SMU_FEATURE_COUNT) {
820 skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
821 CMN2ASIC_MAPPING_FEATURE,
823 if (skipped_feature_id < 0)
826 features_to_disable &= ~(1ULL << skipped_feature_id);
829 return smu_cmn_feature_update_enable_state(smu,
834 int smu_cmn_get_smc_version(struct smu_context *smu,
835 uint32_t *if_version,
836 uint32_t *smu_version)
840 if (!if_version && !smu_version)
843 if (smu->smc_fw_if_version && smu->smc_fw_version)
846 *if_version = smu->smc_fw_if_version;
849 *smu_version = smu->smc_fw_version;
855 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
859 smu->smc_fw_if_version = *if_version;
863 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
867 smu->smc_fw_version = *smu_version;
873 int smu_cmn_update_table(struct smu_context *smu,
874 enum smu_table_id table_index,
879 struct smu_table_context *smu_table = &smu->smu_table;
880 struct amdgpu_device *adev = smu->adev;
881 struct smu_table *table = &smu_table->driver_table;
882 int table_id = smu_cmn_to_asic_specific_index(smu,
883 CMN2ASIC_MAPPING_TABLE,
887 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
890 table_size = smu_table->tables[table_index].size;
893 memcpy(table->cpu_addr, table_data, table_size);
895 * Flush hdp cache: to guard the content seen by
896 * GPU is consitent with CPU.
898 amdgpu_asic_flush_hdp(adev, NULL);
901 ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
902 SMU_MSG_TransferTableDram2Smu :
903 SMU_MSG_TransferTableSmu2Dram,
904 table_id | ((argument & 0xFFFF) << 16),
910 amdgpu_asic_invalidate_hdp(adev, NULL);
911 memcpy(table_data, table->cpu_addr, table_size);
917 int smu_cmn_write_watermarks_table(struct smu_context *smu)
919 void *watermarks_table = smu->smu_table.watermarks_table;
921 if (!watermarks_table)
924 return smu_cmn_update_table(smu,
925 SMU_TABLE_WATERMARKS,
931 int smu_cmn_write_pptable(struct smu_context *smu)
933 void *pptable = smu->smu_table.driver_pptable;
935 return smu_cmn_update_table(smu,
942 int smu_cmn_get_metrics_table(struct smu_context *smu,
946 struct smu_table_context *smu_table= &smu->smu_table;
947 uint32_t table_size =
948 smu_table->tables[SMU_TABLE_SMU_METRICS].size;
952 !smu_table->metrics_time ||
953 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
954 ret = smu_cmn_update_table(smu,
955 SMU_TABLE_SMU_METRICS,
957 smu_table->metrics_table,
960 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
963 smu_table->metrics_time = jiffies;
967 memcpy(metrics_table, smu_table->metrics_table, table_size);
972 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
974 struct metrics_table_header *header = (struct metrics_table_header *)table;
975 uint16_t structure_size;
977 #define METRICS_VERSION(a, b) ((a << 16) | b )
979 switch (METRICS_VERSION(frev, crev)) {
980 case METRICS_VERSION(1, 0):
981 structure_size = sizeof(struct gpu_metrics_v1_0);
983 case METRICS_VERSION(1, 1):
984 structure_size = sizeof(struct gpu_metrics_v1_1);
986 case METRICS_VERSION(1, 2):
987 structure_size = sizeof(struct gpu_metrics_v1_2);
989 case METRICS_VERSION(1, 3):
990 structure_size = sizeof(struct gpu_metrics_v1_3);
992 case METRICS_VERSION(2, 0):
993 structure_size = sizeof(struct gpu_metrics_v2_0);
995 case METRICS_VERSION(2, 1):
996 structure_size = sizeof(struct gpu_metrics_v2_1);
998 case METRICS_VERSION(2, 2):
999 structure_size = sizeof(struct gpu_metrics_v2_2);
1005 #undef METRICS_VERSION
1007 memset(header, 0xFF, structure_size);
1009 header->format_revision = frev;
1010 header->content_revision = crev;
1011 header->structure_size = structure_size;
1015 int smu_cmn_set_mp1_state(struct smu_context *smu,
1016 enum pp_mp1_state mp1_state)
1018 enum smu_message_type msg;
1021 switch (mp1_state) {
1022 case PP_MP1_STATE_SHUTDOWN:
1023 msg = SMU_MSG_PrepareMp1ForShutdown;
1025 case PP_MP1_STATE_UNLOAD:
1026 msg = SMU_MSG_PrepareMp1ForUnload;
1028 case PP_MP1_STATE_RESET:
1029 msg = SMU_MSG_PrepareMp1ForReset;
1031 case PP_MP1_STATE_NONE:
1036 ret = smu_cmn_send_smc_msg(smu, msg, NULL);
1038 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1043 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
1045 struct pci_dev *p = NULL;
1046 bool snd_driver_loaded;
1049 * If the ASIC comes with no audio function, we always assume
1052 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1053 adev->pdev->bus->number, 1);
1057 snd_driver_loaded = pci_is_enabled(p) ? true : false;
1061 return snd_driver_loaded;