drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L4
  24
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "smu_cmn.h"
  28 #include "soc15_common.h"
  29
  30 /*
  31  * DO NOT use these for err/warn/info/debug messages.
  32  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  33  * They are more MGPU friendly.
  34  */
  35 #undef pr_err
  36 #undef pr_warn
  37 #undef pr_info
  38 #undef pr_debug
  39
  40 /*
  41  * Although these are defined in each ASIC's specific header file.
  42  * They share the same definitions and values. That makes common
  43  * APIs for SMC messages issuing for all ASICs possible.
  44  */
  45 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  46 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  47
  48 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  49 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  50
  51 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  52 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  53
  54 #define MP1_C2PMSG_90__CONTENT_MASK                                                                    0xFFFFFFFFL
  55
  56 #undef __SMU_DUMMY_MAP
  57 #define __SMU_DUMMY_MAP(type)   #type
  58 static const char* __smu_message_names[] = {
  59         SMU_MESSAGE_TYPES
  60 };
  61
  62 static const char *smu_get_message_name(struct smu_context *smu,
  63                                         enum smu_message_type type)
  64 {
  65         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  66                 return "unknown smu message";
  67
  68         return __smu_message_names[type];
  69 }
  70
  71 static void smu_cmn_read_arg(struct smu_context *smu,
  72                              uint32_t *arg)
  73 {
  74         struct amdgpu_device *adev = smu->adev;
  75
  76         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  77 }
  78
  79 int smu_cmn_wait_for_response(struct smu_context *smu)
  80 {
  81         struct amdgpu_device *adev = smu->adev;
  82         uint32_t cur_value, i, timeout = adev->usec_timeout * 20;
  83
  84         for (i = 0; i < timeout; i++) {
  85                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  86                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  87                         return cur_value;
  88
  89                 udelay(1);
  90         }
  91
  92         /* timeout means wrong logic */
  93         if (i == timeout)
  94                 return -ETIME;
  95
  96         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  97 }
  98
  99 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
 100                                      uint16_t msg, uint32_t param)
 101 {
 102         struct amdgpu_device *adev = smu->adev;
 103         int ret;
 104
 105         ret = smu_cmn_wait_for_response(smu);
 106         if (ret != 0x1) {
 107                 dev_err(adev->dev, "Msg issuing pre-check failed and "
 108                        "SMU may be not in the right state!\n");
 109                 if (ret != -ETIME)
 110                         ret = -EIO;
 111                 return ret;
 112         }
 113
 114         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 115         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 116         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
 117
 118         return 0;
 119 }
 120
 121 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 122                                     enum smu_message_type msg,
 123                                     uint32_t param,
 124                                     uint32_t *read_arg)
 125 {
 126         struct amdgpu_device *adev = smu->adev;
 127         int ret = 0, index = 0;
 128
 129         if (smu->adev->in_pci_err_recovery)
 130                 return 0;
 131
 132         index = smu_cmn_to_asic_specific_index(smu,
 133                                                CMN2ASIC_MAPPING_MSG,
 134                                                msg);
 135         if (index < 0)
 136                 return index == -EACCES ? 0 : index;
 137
 138         mutex_lock(&smu->message_lock);
 139         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, param);
 140         if (ret)
 141                 goto out;
 142
 143         ret = smu_cmn_wait_for_response(smu);
 144         if (ret != 0x1) {
 145                 if (ret == -ETIME) {
 146                         dev_err(adev->dev, "message: %15s (%d) \tparam: 0x%08x is timeout (no response)\n",
 147                                 smu_get_message_name(smu, msg), index, param);
 148                 } else {
 149                         dev_err(adev->dev, "failed send message: %15s (%d) \tparam: 0x%08x response %#x\n",
 150                                 smu_get_message_name(smu, msg), index, param,
 151                                 ret);
 152                         ret = -EIO;
 153                 }
 154                 goto out;
 155         }
 156
 157         if (read_arg)
 158                 smu_cmn_read_arg(smu, read_arg);
 159
 160         ret = 0; /* 0 as driver return value */
 161 out:
 162         mutex_unlock(&smu->message_lock);
 163         return ret;
 164 }
 165
 166 int smu_cmn_send_smc_msg(struct smu_context *smu,
 167                          enum smu_message_type msg,
 168                          uint32_t *read_arg)
 169 {
 170         return smu_cmn_send_smc_msg_with_param(smu,
 171                                                msg,
 172                                                0,
 173                                                read_arg);
 174 }
 175
 176 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
 177                                    enum smu_cmn2asic_mapping_type type,
 178                                    uint32_t index)
 179 {
 180         struct cmn2asic_msg_mapping msg_mapping;
 181         struct cmn2asic_mapping mapping;
 182
 183         switch (type) {
 184         case CMN2ASIC_MAPPING_MSG:
 185                 if (index >= SMU_MSG_MAX_COUNT ||
 186                     !smu->message_map)
 187                         return -EINVAL;
 188
 189                 msg_mapping = smu->message_map[index];
 190                 if (!msg_mapping.valid_mapping)
 191                         return -EINVAL;
 192
 193                 if (amdgpu_sriov_vf(smu->adev) &&
 194                     !msg_mapping.valid_in_vf)
 195                         return -EACCES;
 196
 197                 return msg_mapping.map_to;
 198
 199         case CMN2ASIC_MAPPING_CLK:
 200                 if (index >= SMU_CLK_COUNT ||
 201                     !smu->clock_map)
 202                         return -EINVAL;
 203
 204                 mapping = smu->clock_map[index];
 205                 if (!mapping.valid_mapping)
 206                         return -EINVAL;
 207
 208                 return mapping.map_to;
 209
 210         case CMN2ASIC_MAPPING_FEATURE:
 211                 if (index >= SMU_FEATURE_COUNT ||
 212                     !smu->feature_map)
 213                         return -EINVAL;
 214
 215                 mapping = smu->feature_map[index];
 216                 if (!mapping.valid_mapping)
 217                         return -EINVAL;
 218
 219                 return mapping.map_to;
 220
 221         case CMN2ASIC_MAPPING_TABLE:
 222                 if (index >= SMU_TABLE_COUNT ||
 223                     !smu->table_map)
 224                         return -EINVAL;
 225
 226                 mapping = smu->table_map[index];
 227                 if (!mapping.valid_mapping)
 228                         return -EINVAL;
 229
 230                 return mapping.map_to;
 231
 232         case CMN2ASIC_MAPPING_PWR:
 233                 if (index >= SMU_POWER_SOURCE_COUNT ||
 234                     !smu->pwr_src_map)
 235                         return -EINVAL;
 236
 237                 mapping = smu->pwr_src_map[index];
 238                 if (!mapping.valid_mapping)
 239                         return -EINVAL;
 240
 241                 return mapping.map_to;
 242
 243         case CMN2ASIC_MAPPING_WORKLOAD:
 244                 if (index > PP_SMC_POWER_PROFILE_CUSTOM ||
 245                     !smu->workload_map)
 246                         return -EINVAL;
 247
 248                 mapping = smu->workload_map[index];
 249                 if (!mapping.valid_mapping)
 250                         return -EINVAL;
 251
 252                 return mapping.map_to;
 253
 254         default:
 255                 return -EINVAL;
 256         }
 257 }
 258
 259 int smu_cmn_feature_is_supported(struct smu_context *smu,
 260                                  enum smu_feature_mask mask)
 261 {
 262         struct smu_feature *feature = &smu->smu_feature;
 263         int feature_id;
 264         int ret = 0;
 265
 266         feature_id = smu_cmn_to_asic_specific_index(smu,
 267                                                     CMN2ASIC_MAPPING_FEATURE,
 268                                                     mask);
 269         if (feature_id < 0)
 270                 return 0;
 271
 272         WARN_ON(feature_id > feature->feature_num);
 273
 274         mutex_lock(&feature->mutex);
 275         ret = test_bit(feature_id, feature->supported);
 276         mutex_unlock(&feature->mutex);
 277
 278         return ret;
 279 }
 280
 281 int smu_cmn_feature_is_enabled(struct smu_context *smu,
 282                                enum smu_feature_mask mask)
 283 {
 284         struct smu_feature *feature = &smu->smu_feature;
 285         struct amdgpu_device *adev = smu->adev;
 286         int feature_id;
 287         int ret = 0;
 288
 289         if (smu->is_apu && adev->family < AMDGPU_FAMILY_VGH)
 290                 return 1;
 291
 292         feature_id = smu_cmn_to_asic_specific_index(smu,
 293                                                     CMN2ASIC_MAPPING_FEATURE,
 294                                                     mask);
 295         if (feature_id < 0)
 296                 return 0;
 297
 298         WARN_ON(feature_id > feature->feature_num);
 299
 300         mutex_lock(&feature->mutex);
 301         ret = test_bit(feature_id, feature->enabled);
 302         mutex_unlock(&feature->mutex);
 303
 304         return ret;
 305 }
 306
 307 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
 308                                 enum smu_clk_type clk_type)
 309 {
 310         enum smu_feature_mask feature_id = 0;
 311
 312         switch (clk_type) {
 313         case SMU_MCLK:
 314         case SMU_UCLK:
 315                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 316                 break;
 317         case SMU_GFXCLK:
 318         case SMU_SCLK:
 319                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 320                 break;
 321         case SMU_SOCCLK:
 322                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 323                 break;
 324         default:
 325                 return true;
 326         }
 327
 328         if (!smu_cmn_feature_is_enabled(smu, feature_id))
 329                 return false;
 330
 331         return true;
 332 }
 333
 334 int smu_cmn_get_enabled_mask(struct smu_context *smu,
 335                              uint32_t *feature_mask,
 336                              uint32_t num)
 337 {
 338         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 339         struct smu_feature *feature = &smu->smu_feature;
 340         int ret = 0;
 341
 342         if (!feature_mask || num < 2)
 343                 return -EINVAL;
 344
 345         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 346                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high);
 347                 if (ret)
 348                         return ret;
 349
 350                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low);
 351                 if (ret)
 352                         return ret;
 353
 354                 feature_mask[0] = feature_mask_low;
 355                 feature_mask[1] = feature_mask_high;
 356         } else {
 357                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 358                              feature->feature_num);
 359         }
 360
 361         return ret;
 362 }
 363
 364 int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
 365                                         uint32_t *feature_mask,
 366                                         uint32_t num)
 367 {
 368         uint32_t feature_mask_en_low = 0;
 369         uint32_t feature_mask_en_high = 0;
 370         struct smu_feature *feature = &smu->smu_feature;
 371         int ret = 0;
 372
 373         if (!feature_mask || num < 2)
 374                 return -EINVAL;
 375
 376         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 377                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 0,
 378                                                                                  &feature_mask_en_low);
 379
 380                 if (ret)
 381                         return ret;
 382
 383                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 1,
 384                                                                                  &feature_mask_en_high);
 385
 386                 if (ret)
 387                         return ret;
 388
 389                 feature_mask[0] = feature_mask_en_low;
 390                 feature_mask[1] = feature_mask_en_high;
 391
 392         } else {
 393                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 394                                  feature->feature_num);
 395         }
 396
 397         return ret;
 398
 399 }
 400
 401 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 402                                         uint64_t feature_mask,
 403                                         bool enabled)
 404 {
 405         struct smu_feature *feature = &smu->smu_feature;
 406         int ret = 0;
 407
 408         if (enabled) {
 409                 ret = smu_cmn_send_smc_msg_with_param(smu,
 410                                                   SMU_MSG_EnableSmuFeaturesLow,
 411                                                   lower_32_bits(feature_mask),
 412                                                   NULL);
 413                 if (ret)
 414                         return ret;
 415                 ret = smu_cmn_send_smc_msg_with_param(smu,
 416                                                   SMU_MSG_EnableSmuFeaturesHigh,
 417                                                   upper_32_bits(feature_mask),
 418                                                   NULL);
 419                 if (ret)
 420                         return ret;
 421         } else {
 422                 ret = smu_cmn_send_smc_msg_with_param(smu,
 423                                                   SMU_MSG_DisableSmuFeaturesLow,
 424                                                   lower_32_bits(feature_mask),
 425                                                   NULL);
 426                 if (ret)
 427                         return ret;
 428                 ret = smu_cmn_send_smc_msg_with_param(smu,
 429                                                   SMU_MSG_DisableSmuFeaturesHigh,
 430                                                   upper_32_bits(feature_mask),
 431                                                   NULL);
 432                 if (ret)
 433                         return ret;
 434         }
 435
 436         mutex_lock(&feature->mutex);
 437         if (enabled)
 438                 bitmap_or(feature->enabled, feature->enabled,
 439                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 440         else
 441                 bitmap_andnot(feature->enabled, feature->enabled,
 442                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 443         mutex_unlock(&feature->mutex);
 444
 445         return ret;
 446 }
 447
 448 int smu_cmn_feature_set_enabled(struct smu_context *smu,
 449                                 enum smu_feature_mask mask,
 450                                 bool enable)
 451 {
 452         struct smu_feature *feature = &smu->smu_feature;
 453         int feature_id;
 454
 455         feature_id = smu_cmn_to_asic_specific_index(smu,
 456                                                     CMN2ASIC_MAPPING_FEATURE,
 457                                                     mask);
 458         if (feature_id < 0)
 459                 return -EINVAL;
 460
 461         WARN_ON(feature_id > feature->feature_num);
 462
 463         return smu_cmn_feature_update_enable_state(smu,
 464                                                1ULL << feature_id,
 465                                                enable);
 466 }
 467
 468 #undef __SMU_DUMMY_MAP
 469 #define __SMU_DUMMY_MAP(fea)    #fea
 470 static const char* __smu_feature_names[] = {
 471         SMU_FEATURE_MASKS
 472 };
 473
 474 static const char *smu_get_feature_name(struct smu_context *smu,
 475                                         enum smu_feature_mask feature)
 476 {
 477         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
 478                 return "unknown smu feature";
 479         return __smu_feature_names[feature];
 480 }
 481
 482 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
 483                                    char *buf)
 484 {
 485         uint32_t feature_mask[2] = { 0 };
 486         int feature_index = 0;
 487         uint32_t count = 0;
 488         int8_t sort_feature[SMU_FEATURE_COUNT];
 489         size_t size = 0;
 490         int ret = 0, i;
 491
 492         if (!smu->is_apu) {
 493                 ret = smu_cmn_get_enabled_mask(smu,
 494                                                 feature_mask,
 495                                                 2);
 496                 if (ret)
 497                         return 0;
 498         } else {
 499                 ret = smu_cmn_get_enabled_32_bits_mask(smu,
 500                                         feature_mask,
 501                                         2);
 502                 if (ret)
 503                         return 0;
 504         }
 505
 506         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
 507                         feature_mask[1], feature_mask[0]);
 508
 509         memset(sort_feature, -1, sizeof(sort_feature));
 510
 511         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
 512                 feature_index = smu_cmn_to_asic_specific_index(smu,
 513                                                                CMN2ASIC_MAPPING_FEATURE,
 514                                                                i);
 515                 if (feature_index < 0)
 516                         continue;
 517
 518                 sort_feature[feature_index] = i;
 519         }
 520
 521         size += sprintf(buf + size, "%-2s. %-20s  %-3s : %-s\n",
 522                         "No", "Feature", "Bit", "State");
 523
 524         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
 525                 if (sort_feature[i] < 0)
 526                         continue;
 527
 528                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
 529                                 count++,
 530                                 smu_get_feature_name(smu, sort_feature[i]),
 531                                 i,
 532                                 !!smu_cmn_feature_is_enabled(smu, sort_feature[i]) ?
 533                                 "enabled" : "disabled");
 534         }
 535
 536         return size;
 537 }
 538
 539 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
 540                                 uint64_t new_mask)
 541 {
 542         int ret = 0;
 543         uint32_t feature_mask[2] = { 0 };
 544         uint64_t feature_2_enabled = 0;
 545         uint64_t feature_2_disabled = 0;
 546         uint64_t feature_enables = 0;
 547
 548         ret = smu_cmn_get_enabled_mask(smu,
 549                                        feature_mask,
 550                                        2);
 551         if (ret)
 552                 return ret;
 553
 554         feature_enables = ((uint64_t)feature_mask[1] << 32 |
 555                            (uint64_t)feature_mask[0]);
 556
 557         feature_2_enabled  = ~feature_enables & new_mask;
 558         feature_2_disabled = feature_enables & ~new_mask;
 559
 560         if (feature_2_enabled) {
 561                 ret = smu_cmn_feature_update_enable_state(smu,
 562                                                           feature_2_enabled,
 563                                                           true);
 564                 if (ret)
 565                         return ret;
 566         }
 567         if (feature_2_disabled) {
 568                 ret = smu_cmn_feature_update_enable_state(smu,
 569                                                           feature_2_disabled,
 570                                                           false);
 571                 if (ret)
 572                         return ret;
 573         }
 574
 575         return ret;
 576 }
 577
 578 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
 579                                                 enum smu_feature_mask mask)
 580 {
 581         uint64_t features_to_disable = U64_MAX;
 582         int skipped_feature_id;
 583
 584         skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
 585                                                             CMN2ASIC_MAPPING_FEATURE,
 586                                                             mask);
 587         if (skipped_feature_id < 0)
 588                 return -EINVAL;
 589
 590         features_to_disable &= ~(1ULL << skipped_feature_id);
 591
 592         return smu_cmn_feature_update_enable_state(smu,
 593                                                    features_to_disable,
 594                                                    0);
 595 }
 596
 597 int smu_cmn_get_smc_version(struct smu_context *smu,
 598                             uint32_t *if_version,
 599                             uint32_t *smu_version)
 600 {
 601         int ret = 0;
 602
 603         if (!if_version && !smu_version)
 604                 return -EINVAL;
 605
 606         if (smu->smc_fw_if_version && smu->smc_fw_version)
 607         {
 608                 if (if_version)
 609                         *if_version = smu->smc_fw_if_version;
 610
 611                 if (smu_version)
 612                         *smu_version = smu->smc_fw_version;
 613
 614                 return 0;
 615         }
 616
 617         if (if_version) {
 618                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
 619                 if (ret)
 620                         return ret;
 621
 622                 smu->smc_fw_if_version = *if_version;
 623         }
 624
 625         if (smu_version) {
 626                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
 627                 if (ret)
 628                         return ret;
 629
 630                 smu->smc_fw_version = *smu_version;
 631         }
 632
 633         return ret;
 634 }
 635
 636 int smu_cmn_update_table(struct smu_context *smu,
 637                          enum smu_table_id table_index,
 638                          int argument,
 639                          void *table_data,
 640                          bool drv2smu)
 641 {
 642         struct smu_table_context *smu_table = &smu->smu_table;
 643         struct amdgpu_device *adev = smu->adev;
 644         struct smu_table *table = &smu_table->driver_table;
 645         int table_id = smu_cmn_to_asic_specific_index(smu,
 646                                                       CMN2ASIC_MAPPING_TABLE,
 647                                                       table_index);
 648         uint32_t table_size;
 649         int ret = 0;
 650         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 651                 return -EINVAL;
 652
 653         table_size = smu_table->tables[table_index].size;
 654
 655         if (drv2smu) {
 656                 memcpy(table->cpu_addr, table_data, table_size);
 657                 /*
 658                  * Flush hdp cache: to guard the content seen by
 659                  * GPU is consitent with CPU.
 660                  */
 661                 amdgpu_asic_flush_hdp(adev, NULL);
 662         }
 663
 664         ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
 665                                           SMU_MSG_TransferTableDram2Smu :
 666                                           SMU_MSG_TransferTableSmu2Dram,
 667                                           table_id | ((argument & 0xFFFF) << 16),
 668                                           NULL);
 669         if (ret)
 670                 return ret;
 671
 672         if (!drv2smu) {
 673                 amdgpu_asic_invalidate_hdp(adev, NULL);
 674                 memcpy(table_data, table->cpu_addr, table_size);
 675         }
 676
 677         return 0;
 678 }
 679
 680 int smu_cmn_write_watermarks_table(struct smu_context *smu)
 681 {
 682         void *watermarks_table = smu->smu_table.watermarks_table;
 683
 684         if (!watermarks_table)
 685                 return -EINVAL;
 686
 687         return smu_cmn_update_table(smu,
 688                                     SMU_TABLE_WATERMARKS,
 689                                     0,
 690                                     watermarks_table,
 691                                     true);
 692 }
 693
 694 int smu_cmn_write_pptable(struct smu_context *smu)
 695 {
 696         void *pptable = smu->smu_table.driver_pptable;
 697
 698         return smu_cmn_update_table(smu,
 699                                     SMU_TABLE_PPTABLE,
 700                                     0,
 701                                     pptable,
 702                                     true);
 703 }
 704
 705 int smu_cmn_get_metrics_table_locked(struct smu_context *smu,
 706                                      void *metrics_table,
 707                                      bool bypass_cache)
 708 {
 709         struct smu_table_context *smu_table= &smu->smu_table;
 710         uint32_t table_size =
 711                 smu_table->tables[SMU_TABLE_SMU_METRICS].size;
 712         int ret = 0;
 713
 714         if (bypass_cache ||
 715             !smu_table->metrics_time ||
 716             time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 717                 ret = smu_cmn_update_table(smu,
 718                                        SMU_TABLE_SMU_METRICS,
 719                                        0,
 720                                        smu_table->metrics_table,
 721                                        false);
 722                 if (ret) {
 723                         dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
 724                         return ret;
 725                 }
 726                 smu_table->metrics_time = jiffies;
 727         }
 728
 729         if (metrics_table)
 730                 memcpy(metrics_table, smu_table->metrics_table, table_size);
 731
 732         return 0;
 733 }
 734
 735 int smu_cmn_get_metrics_table(struct smu_context *smu,
 736                               void *metrics_table,
 737                               bool bypass_cache)
 738 {
 739         int ret = 0;
 740
 741         mutex_lock(&smu->metrics_lock);
 742         ret = smu_cmn_get_metrics_table_locked(smu,
 743                                                metrics_table,
 744                                                bypass_cache);
 745         mutex_unlock(&smu->metrics_lock);
 746
 747         return ret;
 748 }
 749
 750 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
 751 {
 752         struct metrics_table_header *header = (struct metrics_table_header *)table;
 753         uint16_t structure_size;
 754
 755 #define METRICS_VERSION(a, b)   ((a << 16) | b )
 756
 757         switch (METRICS_VERSION(frev, crev)) {
 758         case METRICS_VERSION(1, 0):
 759                 structure_size = sizeof(struct gpu_metrics_v1_0);
 760                 break;
 761         case METRICS_VERSION(1, 1):
 762                 structure_size = sizeof(struct gpu_metrics_v1_1);
 763                 break;
 764         case METRICS_VERSION(2, 0):
 765                 structure_size = sizeof(struct gpu_metrics_v2_0);
 766                 break;
 767         case METRICS_VERSION(2, 1):
 768                 structure_size = sizeof(struct gpu_metrics_v2_1);
 769                 break;
 770         default:
 771                 return;
 772         }
 773
 774 #undef METRICS_VERSION
 775
 776         memset(header, 0xFF, structure_size);
 777
 778         header->format_revision = frev;
 779         header->content_revision = crev;
 780         header->structure_size = structure_size;
 781
 782 }
 783
 784 int smu_cmn_set_mp1_state(struct smu_context *smu,
 785                           enum pp_mp1_state mp1_state)
 786 {
 787         enum smu_message_type msg;
 788         int ret;
 789
 790         switch (mp1_state) {
 791         case PP_MP1_STATE_SHUTDOWN:
 792                 msg = SMU_MSG_PrepareMp1ForShutdown;
 793                 break;
 794         case PP_MP1_STATE_UNLOAD:
 795                 msg = SMU_MSG_PrepareMp1ForUnload;
 796                 break;
 797         case PP_MP1_STATE_RESET:
 798                 msg = SMU_MSG_PrepareMp1ForReset;
 799                 break;
 800         case PP_MP1_STATE_NONE:
 801         default:
 802                 return 0;
 803         }
 804
 805         ret = smu_cmn_send_smc_msg(smu, msg, NULL);
 806         if (ret)
 807                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
 808
 809         return ret;
 810 }