2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_v13_0_5.h"
30 #include "smu_v13_0_5_ppt.h"
31 #include "smu_v13_0_5_ppsmc.h"
32 #include "smu_v13_0_5_pmfw.h"
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
45 #define FEATURE_MASK(feature) (1ULL << feature)
46 #define SMC_DPM_FEATURE ( \
47 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
48 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
49 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
50 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
51 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
52 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
53 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
54 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
55 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
57 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
58 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
59 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
60 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
61 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
62 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
63 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
64 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1),
65 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu , 1),
70 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
71 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
72 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
73 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
74 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
75 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
76 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
77 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
78 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
79 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
80 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
81 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
84 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
85 FEA_MAP(DATA_CALCULATION),
91 FEA_MAP_REVERSE(FCLK),
94 FEA_MAP(FAN_CONTROLLER),
96 FEA_MAP_HALF_REVERSE(GFX),
103 FEA_MAP_REVERSE(SOCCLK),
104 FEA_MAP(SHUBCLK_DPM),
108 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
109 TAB_MAP_VALID(WATERMARKS),
110 TAB_MAP_VALID(SMU_METRICS),
111 TAB_MAP_VALID(CUSTOM_DPM),
112 TAB_MAP_VALID(DPMCLOCKS),
115 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
117 struct smu_table_context *smu_table = &smu->smu_table;
118 struct smu_table *tables = smu_table->tables;
120 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
121 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
122 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
123 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
124 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
125 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
127 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
128 if (!smu_table->clocks_table)
131 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
132 if (!smu_table->metrics_table)
134 smu_table->metrics_time = 0;
136 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
137 if (!smu_table->watermarks_table)
140 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
141 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
142 if (!smu_table->gpu_metrics_table)
148 kfree(smu_table->watermarks_table);
150 kfree(smu_table->metrics_table);
152 kfree(smu_table->clocks_table);
157 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
159 struct smu_table_context *smu_table = &smu->smu_table;
161 kfree(smu_table->clocks_table);
162 smu_table->clocks_table = NULL;
164 kfree(smu_table->metrics_table);
165 smu_table->metrics_table = NULL;
167 kfree(smu_table->watermarks_table);
168 smu_table->watermarks_table = NULL;
173 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
175 struct amdgpu_device *adev = smu->adev;
178 if (!en && !adev->in_s0ix)
179 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
184 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
188 /* vcn dpm on is a prerequisite for vcn power gate messages */
190 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
193 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
199 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
204 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
207 ret = smu_cmn_send_smc_msg_with_param(smu,
208 SMU_MSG_PowerDownJpeg, 0,
215 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
218 uint64_t feature_enabled;
220 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
225 return !!(feature_enabled & SMC_DPM_FEATURE);
228 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
232 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
234 dev_err(smu->adev->dev, "Failed to mode reset!\n");
239 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
241 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
244 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
245 MetricsMember_t member,
248 struct smu_table_context *smu_table = &smu->smu_table;
250 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
253 ret = smu_cmn_get_metrics_table(smu, NULL, false);
258 case METRICS_AVERAGE_GFXCLK:
259 *value = metrics->GfxclkFrequency;
261 case METRICS_AVERAGE_SOCCLK:
262 *value = metrics->SocclkFrequency;
264 case METRICS_AVERAGE_VCLK:
265 *value = metrics->VclkFrequency;
267 case METRICS_AVERAGE_DCLK:
268 *value = metrics->DclkFrequency;
270 case METRICS_AVERAGE_UCLK:
271 *value = metrics->MemclkFrequency;
273 case METRICS_AVERAGE_GFXACTIVITY:
274 *value = metrics->GfxActivity / 100;
276 case METRICS_AVERAGE_VCNACTIVITY:
277 *value = metrics->UvdActivity;
279 case METRICS_AVERAGE_SOCKETPOWER:
280 *value = (metrics->CurrentSocketPower << 8) / 1000;
282 case METRICS_TEMPERATURE_EDGE:
283 *value = metrics->GfxTemperature / 100 *
284 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
286 case METRICS_TEMPERATURE_HOTSPOT:
287 *value = metrics->SocTemperature / 100 *
288 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
290 case METRICS_THROTTLER_STATUS:
291 *value = metrics->ThrottlerStatus;
293 case METRICS_VOLTAGE_VDDGFX:
294 *value = metrics->Voltage[0];
296 case METRICS_VOLTAGE_VDDSOC:
297 *value = metrics->Voltage[1];
307 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
308 enum amd_pp_sensors sensor,
309 void *data, uint32_t *size)
317 case AMDGPU_PP_SENSOR_GPU_LOAD:
318 ret = smu_v13_0_5_get_smu_metrics_data(smu,
319 METRICS_AVERAGE_GFXACTIVITY,
323 case AMDGPU_PP_SENSOR_GPU_POWER:
324 ret = smu_v13_0_5_get_smu_metrics_data(smu,
325 METRICS_AVERAGE_SOCKETPOWER,
329 case AMDGPU_PP_SENSOR_EDGE_TEMP:
330 ret = smu_v13_0_5_get_smu_metrics_data(smu,
331 METRICS_TEMPERATURE_EDGE,
335 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
336 ret = smu_v13_0_5_get_smu_metrics_data(smu,
337 METRICS_TEMPERATURE_HOTSPOT,
341 case AMDGPU_PP_SENSOR_GFX_MCLK:
342 ret = smu_v13_0_5_get_smu_metrics_data(smu,
343 METRICS_AVERAGE_UCLK,
345 *(uint32_t *)data *= 100;
348 case AMDGPU_PP_SENSOR_GFX_SCLK:
349 ret = smu_v13_0_5_get_smu_metrics_data(smu,
350 METRICS_AVERAGE_GFXCLK,
352 *(uint32_t *)data *= 100;
355 case AMDGPU_PP_SENSOR_VDDGFX:
356 ret = smu_v13_0_5_get_smu_metrics_data(smu,
357 METRICS_VOLTAGE_VDDGFX,
361 case AMDGPU_PP_SENSOR_VDDNB:
362 ret = smu_v13_0_5_get_smu_metrics_data(smu,
363 METRICS_VOLTAGE_VDDSOC,
367 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
368 ret = smu_v13_0_5_get_smu_metrics_data(smu,
369 METRICS_SS_APU_SHARE,
373 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
374 ret = smu_v13_0_5_get_smu_metrics_data(smu,
375 METRICS_SS_DGPU_SHARE,
387 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
388 struct pp_smu_wm_range_sets *clock_ranges)
392 Watermarks_t *table = smu->smu_table.watermarks_table;
394 if (!table || !clock_ranges)
398 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
399 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
402 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
403 table->WatermarkRow[WM_DCFCLK][i].MinClock =
404 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
405 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
406 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
407 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
408 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
409 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
410 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
412 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
413 clock_ranges->reader_wm_sets[i].wm_inst;
416 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
417 table->WatermarkRow[WM_SOCCLK][i].MinClock =
418 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
419 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
420 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
421 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
422 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
423 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
424 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
426 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
427 clock_ranges->writer_wm_sets[i].wm_inst;
430 smu->watermarks_bitmap |= WATERMARKS_EXIST;
433 /* pass data to smu controller */
434 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
435 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
436 ret = smu_cmn_write_watermarks_table(smu);
438 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
441 smu->watermarks_bitmap |= WATERMARKS_LOADED;
447 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
450 struct smu_table_context *smu_table = &smu->smu_table;
451 struct gpu_metrics_v2_1 *gpu_metrics =
452 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
453 SmuMetrics_t metrics;
456 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
460 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
462 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
463 gpu_metrics->temperature_soc = metrics.SocTemperature;
465 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
466 gpu_metrics->average_mm_activity = metrics.UvdActivity;
468 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
469 gpu_metrics->average_gfx_power = metrics.Power[0];
470 gpu_metrics->average_soc_power = metrics.Power[1];
471 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
472 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
473 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
474 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
475 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
476 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
477 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
478 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
480 *table = (void *)gpu_metrics;
482 return sizeof(struct gpu_metrics_v2_1);
485 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
487 struct smu_table_context *smu_table = &smu->smu_table;
489 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
492 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
493 long input[], uint32_t size)
495 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
498 /* Only allowed in manual mode */
499 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
503 case PP_OD_EDIT_SCLK_VDDC_TABLE:
505 dev_err(smu->adev->dev, "Input parameter number not correct\n");
510 if (input[1] < smu->gfx_default_hard_min_freq) {
511 dev_warn(smu->adev->dev,
512 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
513 input[1], smu->gfx_default_hard_min_freq);
516 smu->gfx_actual_hard_min_freq = input[1];
517 } else if (input[0] == 1) {
518 if (input[1] > smu->gfx_default_soft_max_freq) {
519 dev_warn(smu->adev->dev,
520 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
521 input[1], smu->gfx_default_soft_max_freq);
524 smu->gfx_actual_soft_max_freq = input[1];
529 case PP_OD_RESTORE_DEFAULT_TABLE:
531 dev_err(smu->adev->dev, "Input parameter number not correct\n");
534 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
535 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
538 case PP_OD_COMMIT_DPM_TABLE:
540 dev_err(smu->adev->dev, "Input parameter number not correct\n");
543 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
544 dev_err(smu->adev->dev,
545 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
546 smu->gfx_actual_hard_min_freq,
547 smu->gfx_actual_soft_max_freq);
551 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
552 smu->gfx_actual_hard_min_freq, NULL);
554 dev_err(smu->adev->dev, "Set hard min sclk failed!");
558 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
559 smu->gfx_actual_soft_max_freq, NULL);
561 dev_err(smu->adev->dev, "Set soft max sclk failed!");
573 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
574 enum smu_clk_type clk_type,
577 MetricsMember_t member_type;
581 member_type = METRICS_AVERAGE_SOCCLK;
584 member_type = METRICS_AVERAGE_VCLK;
587 member_type = METRICS_AVERAGE_DCLK;
590 member_type = METRICS_AVERAGE_UCLK;
594 return smu_cmn_send_smc_msg_with_param(smu,
595 SMU_MSG_GetGfxclkFrequency, 0, value);
601 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
604 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
605 enum smu_clk_type clk_type,
608 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
612 *count = clk_table->NumSocClkLevelsEnabled;
615 *count = clk_table->VcnClkLevelsEnabled;
618 *count = clk_table->VcnClkLevelsEnabled;
621 *count = clk_table->NumDfPstatesEnabled;
624 *count = clk_table->NumDfPstatesEnabled;
633 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
634 enum smu_clk_type clk_type,
638 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
640 if (!clk_table || clk_type >= SMU_CLK_COUNT)
645 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
647 *freq = clk_table->SocClocks[dpm_level];
650 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
652 *freq = clk_table->VClocks[dpm_level];
655 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
657 *freq = clk_table->DClocks[dpm_level];
661 if (dpm_level >= clk_table->NumDfPstatesEnabled)
663 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
666 if (dpm_level >= clk_table->NumDfPstatesEnabled)
668 *freq = clk_table->DfPstateTable[dpm_level].FClk;
677 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
678 enum smu_clk_type clk_type)
680 enum smu_feature_mask feature_id = 0;
686 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
690 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
693 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
697 feature_id = SMU_FEATURE_VCN_DPM_BIT;
703 return smu_cmn_feature_is_enabled(smu, feature_id);
706 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
707 enum smu_clk_type clk_type,
711 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
712 uint32_t clock_limit;
713 uint32_t max_dpm_level, min_dpm_level;
716 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
720 clock_limit = smu->smu_table.boot_values.uclk;
723 clock_limit = smu->smu_table.boot_values.fclk;
727 clock_limit = smu->smu_table.boot_values.gfxclk;
730 clock_limit = smu->smu_table.boot_values.socclk;
733 clock_limit = smu->smu_table.boot_values.vclk;
736 clock_limit = smu->smu_table.boot_values.dclk;
743 /* clock in Mhz unit */
745 *min = clock_limit / 100;
747 *max = clock_limit / 100;
756 *max = clk_table->MaxGfxClk;
764 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
768 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
775 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
776 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
786 *min = clk_table->MinGfxClk;
791 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
805 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
806 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
816 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
817 enum smu_clk_type clk_type,
821 enum smu_message_type msg_set_min, msg_set_max;
824 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
830 msg_set_min = SMU_MSG_SetHardMinGfxClk;
831 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
835 msg_set_min = SMU_MSG_SetHardMinVcn;
836 msg_set_max = SMU_MSG_SetSoftMaxVcn;
842 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
846 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
854 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
855 enum smu_clk_type clk_type, char *buf)
857 int i, size = 0, ret = 0;
858 uint32_t cur_value = 0, value = 0, count = 0;
859 uint32_t min = 0, max = 0;
861 smu_cmn_get_sysfs_buf(&buf, &size);
865 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
866 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
867 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
868 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
869 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
872 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
873 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
874 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
880 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
884 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
888 for (i = 0; i < count; i++) {
889 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value);
893 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
894 cur_value == value ? "*" : "");
899 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
902 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
903 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
904 if (cur_value == max)
906 else if (cur_value == min)
910 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
912 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
913 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
915 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
927 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
928 enum smu_clk_type clk_type, uint32_t mask)
930 uint32_t soft_min_level = 0, soft_max_level = 0;
931 uint32_t min_freq = 0, max_freq = 0;
934 soft_min_level = mask ? (ffs(mask) - 1) : 0;
935 soft_max_level = mask ? (fls(mask) - 1) : 0;
940 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
942 goto force_level_out;
944 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
946 goto force_level_out;
948 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
950 goto force_level_out;
961 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
962 enum amd_dpm_forced_level level)
964 struct amdgpu_device *adev = smu->adev;
965 uint32_t sclk_min = 0, sclk_max = 0;
969 case AMD_DPM_FORCED_LEVEL_HIGH:
970 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
973 case AMD_DPM_FORCED_LEVEL_LOW:
974 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
977 case AMD_DPM_FORCED_LEVEL_AUTO:
978 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
980 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
981 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
982 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
983 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
984 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
986 case AMD_DPM_FORCED_LEVEL_MANUAL:
987 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
990 dev_err(adev->dev, "Invalid performance level %d\n", level);
994 if (sclk_min && sclk_max) {
995 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1002 smu->gfx_actual_hard_min_freq = sclk_min;
1003 smu->gfx_actual_soft_max_freq = sclk_max;
1009 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1011 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1013 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1014 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1015 smu->gfx_actual_hard_min_freq = 0;
1016 smu->gfx_actual_soft_max_freq = 0;
1021 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1022 .check_fw_status = smu_v13_0_check_fw_status,
1023 .check_fw_version = smu_v13_0_check_fw_version,
1024 .init_smc_tables = smu_v13_0_5_init_smc_tables,
1025 .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1026 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1027 .system_features_control = smu_v13_0_5_system_features_control,
1028 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1029 .send_smc_msg = smu_cmn_send_smc_msg,
1030 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1031 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1032 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1033 .read_sensor = smu_v13_0_5_read_sensor,
1034 .is_dpm_running = smu_v13_0_5_is_dpm_running,
1035 .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1036 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1037 .get_enabled_mask = smu_cmn_get_enabled_mask,
1038 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1039 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1040 .gfx_off_control = smu_v13_0_gfx_off_control,
1041 .mode2_reset = smu_v13_0_5_mode2_reset,
1042 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1043 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1044 .print_clk_levels = smu_v13_0_5_print_clk_levels,
1045 .force_clk_levels = smu_v13_0_5_force_clk_levels,
1046 .set_performance_level = smu_v13_0_5_set_performance_level,
1047 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1050 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1052 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1053 smu->message_map = smu_v13_0_5_message_map;
1054 smu->feature_map = smu_v13_0_5_feature_mask_map;
1055 smu->table_map = smu_v13_0_5_table_map;