2 * Copyright 2021 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
48 #include "amdgpu_ras.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
73 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
96 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
97 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
98 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
101 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
102 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
103 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
104 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
105 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
106 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
107 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
108 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
109 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
110 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
113 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
114 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
115 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
116 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
117 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
118 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
119 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
120 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
121 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
124 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
125 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
126 CLK_MAP(SCLK, PPCLK_GFXCLK),
127 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
128 CLK_MAP(FCLK, PPCLK_FCLK),
129 CLK_MAP(UCLK, PPCLK_UCLK),
130 CLK_MAP(MCLK, PPCLK_UCLK),
131 CLK_MAP(VCLK, PPCLK_VCLK_0),
132 CLK_MAP(VCLK1, PPCLK_VCLK_1),
133 CLK_MAP(DCLK, PPCLK_DCLK_0),
134 CLK_MAP(DCLK1, PPCLK_DCLK_1),
137 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
138 FEA_MAP(FW_DATA_READ),
140 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
147 FEA_MAP(VMEMP_SCALING),
148 FEA_MAP(VDDIO_MEM_SCALING),
160 FEA_MAP(SOC_MPCLK_DS),
161 FEA_MAP(BACO_MPCLK_DS),
168 FEA_MAP(FAN_CONTROL),
170 FEA_MAP(GFX_READ_MARGIN),
171 FEA_MAP(LED_DISPLAY),
172 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
173 FEA_MAP(OUT_OF_BAND_MONITOR),
174 FEA_MAP(OPTIMIZED_VMIN),
176 FEA_MAP(BOOT_TIME_CAL),
177 FEA_MAP(GFX_PCC_DFLL),
181 FEA_MAP(BOOT_POWER_OPT),
182 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
185 FEA_MAP(MEM_TEMP_READ),
186 FEA_MAP(ATHUB_MMHUB_PG),
190 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
193 TAB_MAP(AVFS_PSM_DEBUG),
194 TAB_MAP(PMSTATUSLOG),
195 TAB_MAP(SMU_METRICS),
196 TAB_MAP(DRIVER_SMU_CONFIG),
197 TAB_MAP(ACTIVITY_MONITOR_COEFF),
198 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
199 TAB_MAP(I2C_COMMANDS),
202 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
207 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
217 static const uint8_t smu_v13_0_0_throttler_map[] = {
218 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
219 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
220 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
221 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
222 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
223 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
224 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
225 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
226 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
227 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
228 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
229 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
230 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
231 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
232 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
233 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
234 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
238 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
239 uint32_t *feature_mask, uint32_t num)
241 struct amdgpu_device *adev = smu->adev;
246 memset(feature_mask, 0, sizeof(uint32_t) * num);
248 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
250 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
251 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
255 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
256 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
258 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
259 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
262 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
263 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
266 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
275 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
277 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
283 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
293 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) {
294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
300 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
304 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_UCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
317 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
319 struct smu_table_context *table_context = &smu->smu_table;
320 struct smu_13_0_0_powerplay_table *powerplay_table =
321 table_context->power_play_table;
322 struct smu_baco_context *smu_baco = &smu->smu_baco;
324 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
325 smu->dc_controlled_by_gpio = true;
327 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO ||
328 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
329 smu_baco->platform_support = true;
331 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
332 smu_baco->maco_support = true;
334 table_context->thermal_controller_type =
335 powerplay_table->thermal_controller_type;
338 * Instead of having its own buffer space and get overdrive_table copied,
339 * smu->od_settings just points to the actual overdrive_table
341 smu->od_settings = &powerplay_table->overdrive_table;
346 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
348 struct smu_table_context *table_context = &smu->smu_table;
349 struct smu_13_0_0_powerplay_table *powerplay_table =
350 table_context->power_play_table;
352 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
358 #ifndef atom_smc_dpm_info_table_13_0_0
359 struct atom_smc_dpm_info_table_13_0_0 {
360 struct atom_common_table_header table_header;
361 BoardTable_t BoardTable;
365 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
367 struct smu_table_context *table_context = &smu->smu_table;
368 PPTable_t *smc_pptable = table_context->driver_pptable;
369 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
370 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
373 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
376 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
377 (uint8_t **)&smc_dpm_table);
381 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
386 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
388 struct smu_table_context *smu_table = &smu->smu_table;
389 void *combo_pptable = smu_table->combo_pptable;
390 struct amdgpu_device *adev = smu->adev;
394 * With SCPM enabled, the pptable used will be signed. It cannot
395 * be used directly by driver. To get the raw pptable, we need to
396 * rely on the combo pptable(and its revelant SMU message).
398 if (adev->scpm_enabled) {
399 ret = smu_cmn_get_combo_pptable(smu);
403 smu->smu_table.power_play_table = combo_pptable;
404 smu->smu_table.power_play_table_size = sizeof(struct smu_13_0_0_powerplay_table);
406 ret = smu_v13_0_setup_pptable(smu);
411 ret = smu_v13_0_0_store_powerplay_table(smu);
416 * With SCPM enabled, the operation below will be handled
417 * by PSP. Driver involvment is unnecessary and useless.
419 if (!adev->scpm_enabled) {
420 ret = smu_v13_0_0_append_powerplay_table(smu);
425 ret = smu_v13_0_0_check_powerplay_table(smu);
432 static int smu_v13_0_0_tables_init(struct smu_context *smu)
434 struct smu_table_context *smu_table = &smu->smu_table;
435 struct smu_table *tables = smu_table->tables;
437 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
439 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
440 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
441 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
442 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
443 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
444 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
445 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
446 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
447 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
448 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
449 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
450 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
451 AMDGPU_GEM_DOMAIN_VRAM);
452 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
453 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
455 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
456 if (!smu_table->metrics_table)
458 smu_table->metrics_time = 0;
460 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
461 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
462 if (!smu_table->gpu_metrics_table)
465 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
466 if (!smu_table->watermarks_table)
472 kfree(smu_table->gpu_metrics_table);
474 kfree(smu_table->metrics_table);
479 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
481 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
483 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
485 if (!smu_dpm->dpm_context)
488 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
493 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
497 ret = smu_v13_0_0_tables_init(smu);
501 ret = smu_v13_0_0_allocate_dpm_context(smu);
505 return smu_v13_0_init_smc_tables(smu);
508 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
510 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
511 struct smu_table_context *table_context = &smu->smu_table;
512 PPTable_t *pptable = table_context->driver_pptable;
513 SkuTable_t *skutable = &pptable->SkuTable;
514 struct smu_13_0_dpm_table *dpm_table;
515 struct smu_13_0_pcie_table *pcie_table;
519 /* socclk dpm table setup */
520 dpm_table = &dpm_context->dpm_tables.soc_table;
521 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
522 ret = smu_v13_0_set_single_dpm_table(smu,
528 dpm_table->count = 1;
529 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
530 dpm_table->dpm_levels[0].enabled = true;
531 dpm_table->min = dpm_table->dpm_levels[0].value;
532 dpm_table->max = dpm_table->dpm_levels[0].value;
535 /* gfxclk dpm table setup */
536 dpm_table = &dpm_context->dpm_tables.gfx_table;
537 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
538 ret = smu_v13_0_set_single_dpm_table(smu,
544 dpm_table->count = 1;
545 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
546 dpm_table->dpm_levels[0].enabled = true;
547 dpm_table->min = dpm_table->dpm_levels[0].value;
548 dpm_table->max = dpm_table->dpm_levels[0].value;
551 /* uclk dpm table setup */
552 dpm_table = &dpm_context->dpm_tables.uclk_table;
553 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
554 ret = smu_v13_0_set_single_dpm_table(smu,
560 dpm_table->count = 1;
561 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
562 dpm_table->dpm_levels[0].enabled = true;
563 dpm_table->min = dpm_table->dpm_levels[0].value;
564 dpm_table->max = dpm_table->dpm_levels[0].value;
567 /* fclk dpm table setup */
568 dpm_table = &dpm_context->dpm_tables.fclk_table;
569 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
570 ret = smu_v13_0_set_single_dpm_table(smu,
576 dpm_table->count = 1;
577 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
578 dpm_table->dpm_levels[0].enabled = true;
579 dpm_table->min = dpm_table->dpm_levels[0].value;
580 dpm_table->max = dpm_table->dpm_levels[0].value;
583 /* vclk dpm table setup */
584 dpm_table = &dpm_context->dpm_tables.vclk_table;
585 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
586 ret = smu_v13_0_set_single_dpm_table(smu,
592 dpm_table->count = 1;
593 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
594 dpm_table->dpm_levels[0].enabled = true;
595 dpm_table->min = dpm_table->dpm_levels[0].value;
596 dpm_table->max = dpm_table->dpm_levels[0].value;
599 /* dclk dpm table setup */
600 dpm_table = &dpm_context->dpm_tables.dclk_table;
601 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
602 ret = smu_v13_0_set_single_dpm_table(smu,
608 dpm_table->count = 1;
609 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
610 dpm_table->dpm_levels[0].enabled = true;
611 dpm_table->min = dpm_table->dpm_levels[0].value;
612 dpm_table->max = dpm_table->dpm_levels[0].value;
615 /* lclk dpm table setup */
616 pcie_table = &dpm_context->dpm_tables.pcie_table;
617 pcie_table->num_of_link_levels = 0;
618 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
619 if (!skutable->PcieGenSpeed[link_level] &&
620 !skutable->PcieLaneCount[link_level] &&
621 !skutable->LclkFreq[link_level])
624 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
625 skutable->PcieGenSpeed[link_level];
626 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
627 skutable->PcieLaneCount[link_level];
628 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
629 skutable->LclkFreq[link_level];
630 pcie_table->num_of_link_levels++;
636 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
639 uint64_t feature_enabled;
641 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
645 return !!(feature_enabled & SMC_DPM_FEATURE);
648 static void smu_v13_0_0_dump_pptable(struct smu_context *smu)
650 struct smu_table_context *table_context = &smu->smu_table;
651 PPTable_t *pptable = table_context->driver_pptable;
652 SkuTable_t *skutable = &pptable->SkuTable;
654 dev_info(smu->adev->dev, "Dumped PPTable:\n");
656 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
657 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
658 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
661 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
664 return smu_v13_0_system_features_control(smu, en);
667 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
669 uint32_t throttler_status = 0;
672 for (i = 0; i < THROTTLER_COUNT; i++)
674 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
676 return throttler_status;
679 #define SMU_13_0_0_BUSY_THRESHOLD 15
680 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
681 MetricsMember_t member,
684 struct smu_table_context *smu_table = &smu->smu_table;
685 SmuMetrics_t *metrics =
686 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
689 ret = smu_cmn_get_metrics_table(smu,
696 case METRICS_CURR_GFXCLK:
697 *value = metrics->CurrClock[PPCLK_GFXCLK];
699 case METRICS_CURR_SOCCLK:
700 *value = metrics->CurrClock[PPCLK_SOCCLK];
702 case METRICS_CURR_UCLK:
703 *value = metrics->CurrClock[PPCLK_UCLK];
705 case METRICS_CURR_VCLK:
706 *value = metrics->CurrClock[PPCLK_VCLK_0];
708 case METRICS_CURR_VCLK1:
709 *value = metrics->CurrClock[PPCLK_VCLK_1];
711 case METRICS_CURR_DCLK:
712 *value = metrics->CurrClock[PPCLK_DCLK_0];
714 case METRICS_CURR_DCLK1:
715 *value = metrics->CurrClock[PPCLK_DCLK_1];
717 case METRICS_CURR_FCLK:
718 *value = metrics->CurrClock[PPCLK_FCLK];
720 case METRICS_AVERAGE_GFXCLK:
721 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
722 *value = metrics->AverageGfxclkFrequencyPostDs;
724 *value = metrics->AverageGfxclkFrequencyPreDs;
726 case METRICS_AVERAGE_FCLK:
727 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
728 *value = metrics->AverageFclkFrequencyPostDs;
730 *value = metrics->AverageFclkFrequencyPreDs;
732 case METRICS_AVERAGE_UCLK:
733 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
734 *value = metrics->AverageMemclkFrequencyPostDs;
736 *value = metrics->AverageMemclkFrequencyPreDs;
738 case METRICS_AVERAGE_VCLK:
739 *value = metrics->AverageVclk0Frequency;
741 case METRICS_AVERAGE_DCLK:
742 *value = metrics->AverageDclk0Frequency;
744 case METRICS_AVERAGE_VCLK1:
745 *value = metrics->AverageVclk1Frequency;
747 case METRICS_AVERAGE_DCLK1:
748 *value = metrics->AverageDclk1Frequency;
750 case METRICS_AVERAGE_GFXACTIVITY:
751 *value = metrics->AverageGfxActivity;
753 case METRICS_AVERAGE_MEMACTIVITY:
754 *value = metrics->AverageUclkActivity;
756 case METRICS_AVERAGE_SOCKETPOWER:
757 *value = metrics->AverageSocketPower << 8;
759 case METRICS_TEMPERATURE_EDGE:
760 *value = metrics->AvgTemperature[TEMP_EDGE] *
761 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
763 case METRICS_TEMPERATURE_HOTSPOT:
764 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
765 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
767 case METRICS_TEMPERATURE_MEM:
768 *value = metrics->AvgTemperature[TEMP_MEM] *
769 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
771 case METRICS_TEMPERATURE_VRGFX:
772 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
773 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
775 case METRICS_TEMPERATURE_VRSOC:
776 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
777 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
779 case METRICS_THROTTLER_STATUS:
780 *value = smu_v13_0_get_throttler_status(metrics);
782 case METRICS_CURR_FANSPEED:
783 *value = metrics->AvgFanRpm;
785 case METRICS_CURR_FANPWM:
786 *value = metrics->AvgFanPwm;
788 case METRICS_VOLTAGE_VDDGFX:
789 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
791 case METRICS_PCIE_RATE:
792 *value = metrics->PcieRate;
794 case METRICS_PCIE_WIDTH:
795 *value = metrics->PcieWidth;
805 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
806 enum amd_pp_sensors sensor,
810 struct smu_table_context *table_context = &smu->smu_table;
811 PPTable_t *smc_pptable = table_context->driver_pptable;
815 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
816 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
819 case AMDGPU_PP_SENSOR_MEM_LOAD:
820 ret = smu_v13_0_0_get_smu_metrics_data(smu,
821 METRICS_AVERAGE_MEMACTIVITY,
825 case AMDGPU_PP_SENSOR_GPU_LOAD:
826 ret = smu_v13_0_0_get_smu_metrics_data(smu,
827 METRICS_AVERAGE_GFXACTIVITY,
831 case AMDGPU_PP_SENSOR_GPU_POWER:
832 ret = smu_v13_0_0_get_smu_metrics_data(smu,
833 METRICS_AVERAGE_SOCKETPOWER,
837 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
838 ret = smu_v13_0_0_get_smu_metrics_data(smu,
839 METRICS_TEMPERATURE_HOTSPOT,
843 case AMDGPU_PP_SENSOR_EDGE_TEMP:
844 ret = smu_v13_0_0_get_smu_metrics_data(smu,
845 METRICS_TEMPERATURE_EDGE,
849 case AMDGPU_PP_SENSOR_MEM_TEMP:
850 ret = smu_v13_0_0_get_smu_metrics_data(smu,
851 METRICS_TEMPERATURE_MEM,
855 case AMDGPU_PP_SENSOR_GFX_MCLK:
856 ret = smu_v13_0_0_get_smu_metrics_data(smu,
859 *(uint32_t *)data *= 100;
862 case AMDGPU_PP_SENSOR_GFX_SCLK:
863 ret = smu_v13_0_0_get_smu_metrics_data(smu,
864 METRICS_AVERAGE_GFXCLK,
866 *(uint32_t *)data *= 100;
869 case AMDGPU_PP_SENSOR_VDDGFX:
870 ret = smu_v13_0_0_get_smu_metrics_data(smu,
871 METRICS_VOLTAGE_VDDGFX,
883 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
884 enum smu_clk_type clk_type,
887 MetricsMember_t member_type;
890 clk_id = smu_cmn_to_asic_specific_index(smu,
891 CMN2ASIC_MAPPING_CLK,
898 member_type = METRICS_AVERAGE_GFXCLK;
901 member_type = METRICS_CURR_UCLK;
904 member_type = METRICS_CURR_FCLK;
907 member_type = METRICS_CURR_SOCCLK;
910 member_type = METRICS_AVERAGE_VCLK;
913 member_type = METRICS_AVERAGE_DCLK;
916 member_type = METRICS_AVERAGE_VCLK1;
919 member_type = METRICS_AVERAGE_DCLK1;
925 return smu_v13_0_0_get_smu_metrics_data(smu,
930 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
931 enum smu_clk_type clk_type,
934 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
935 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
936 struct smu_13_0_dpm_table *single_dpm_table;
937 struct smu_13_0_pcie_table *pcie_table;
938 const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
939 uint32_t gen_speed, lane_width;
940 int i, curr_freq, size = 0;
943 smu_cmn_get_sysfs_buf(&buf, &size);
945 if (amdgpu_ras_intr_triggered()) {
946 size += sysfs_emit_at(buf, size, "unavailable\n");
952 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
955 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
958 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
961 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
965 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
969 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
984 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
986 dev_err(smu->adev->dev, "Failed to get current clock freq!");
990 if (single_dpm_table->is_fine_grained) {
992 * For fine grained dpms, there are only two dpm levels:
993 * - level 0 -> min clock freq
994 * - level 1 -> max clock freq
995 * And the current clock frequency can be any value between them.
996 * So, if the current clock frequency is not at level 0 or level 1,
997 * we will fake it as three dpm levels:
998 * - level 0 -> min clock freq
999 * - level 1 -> current actual clock freq
1000 * - level 2 -> max clock freq
1002 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1003 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1004 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1005 single_dpm_table->dpm_levels[0].value);
1006 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1008 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1009 single_dpm_table->dpm_levels[1].value);
1011 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1012 single_dpm_table->dpm_levels[0].value,
1013 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1014 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1015 single_dpm_table->dpm_levels[1].value,
1016 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1019 for (i = 0; i < single_dpm_table->count; i++)
1020 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1021 i, single_dpm_table->dpm_levels[i].value,
1022 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1026 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1032 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1038 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1039 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1040 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1041 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1042 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1043 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1044 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1045 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1046 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1047 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1048 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1049 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1050 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1051 pcie_table->clk_freq[i],
1052 ((gen_speed - 1) == pcie_table->pcie_gen[i]) &&
1053 (lane_width == link_width[pcie_table->pcie_lane[i]]) ?
1064 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1065 enum smu_clk_type clk_type,
1068 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1069 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1070 struct smu_13_0_dpm_table *single_dpm_table;
1071 uint32_t soft_min_level, soft_max_level;
1072 uint32_t min_freq, max_freq;
1075 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1076 soft_max_level = mask ? (fls(mask) - 1) : 0;
1081 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1085 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1088 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1091 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1095 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1099 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1116 if (single_dpm_table->is_fine_grained) {
1117 /* There is only 2 levels for fine grained DPM */
1118 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1119 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1121 if ((soft_max_level >= single_dpm_table->count) ||
1122 (soft_min_level >= single_dpm_table->count))
1126 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1127 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1129 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1143 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
1144 uint32_t pcie_gen_cap,
1145 uint32_t pcie_width_cap)
1147 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1148 struct smu_13_0_pcie_table *pcie_table =
1149 &dpm_context->dpm_tables.pcie_table;
1150 uint32_t smu_pcie_arg;
1153 for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1154 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1155 pcie_table->pcie_gen[i] = pcie_gen_cap;
1156 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1157 pcie_table->pcie_lane[i] = pcie_width_cap;
1159 smu_pcie_arg = i << 16;
1160 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1161 smu_pcie_arg |= pcie_table->pcie_lane[i];
1163 ret = smu_cmn_send_smc_msg_with_param(smu,
1164 SMU_MSG_OverridePcieParameters,
1174 static const struct smu_temperature_range smu13_thermal_policy[] = {
1175 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1176 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1179 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
1180 struct smu_temperature_range *range)
1182 struct smu_table_context *table_context = &smu->smu_table;
1183 struct smu_13_0_0_powerplay_table *powerplay_table =
1184 table_context->power_play_table;
1185 PPTable_t *pptable = smu->smu_table.driver_pptable;
1190 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1192 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1193 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1194 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1195 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1196 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1197 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1198 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1199 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1200 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1201 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1202 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1203 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1204 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1209 #define MAX(a, b) ((a) > (b) ? (a) : (b))
1210 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
1213 struct smu_table_context *smu_table = &smu->smu_table;
1214 struct gpu_metrics_v1_3 *gpu_metrics =
1215 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1216 SmuMetricsExternal_t metrics_ext;
1217 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1220 ret = smu_cmn_get_metrics_table(smu,
1226 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1228 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1229 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1230 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1231 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1232 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1233 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1234 metrics->AvgTemperature[TEMP_VR_MEM1]);
1236 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1237 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1238 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1239 metrics->Vcn1ActivityPercentage);
1241 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1242 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1244 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1245 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1247 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1249 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1250 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1252 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1254 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1255 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1256 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1257 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1259 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1260 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
1261 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
1262 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1263 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1264 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1265 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1267 gpu_metrics->throttle_status =
1268 smu_v13_0_get_throttler_status(metrics);
1269 gpu_metrics->indep_throttle_status =
1270 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1271 smu_v13_0_0_throttler_map);
1273 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1275 gpu_metrics->pcie_link_width = metrics->PcieWidth;
1276 gpu_metrics->pcie_link_speed = metrics->PcieRate;
1278 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1280 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1281 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1282 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1284 *table = (void *)gpu_metrics;
1286 return sizeof(struct gpu_metrics_v1_3);
1289 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
1291 struct smu_13_0_dpm_context *dpm_context =
1292 smu->smu_dpm.dpm_context;
1293 struct smu_13_0_dpm_table *gfx_table =
1294 &dpm_context->dpm_tables.gfx_table;
1295 struct smu_13_0_dpm_table *mem_table =
1296 &dpm_context->dpm_tables.uclk_table;
1297 struct smu_13_0_dpm_table *soc_table =
1298 &dpm_context->dpm_tables.soc_table;
1299 struct smu_13_0_dpm_table *vclk_table =
1300 &dpm_context->dpm_tables.vclk_table;
1301 struct smu_13_0_dpm_table *dclk_table =
1302 &dpm_context->dpm_tables.dclk_table;
1303 struct smu_13_0_dpm_table *fclk_table =
1304 &dpm_context->dpm_tables.fclk_table;
1305 struct smu_umd_pstate_table *pstate_table =
1308 pstate_table->gfxclk_pstate.min = gfx_table->min;
1309 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1311 pstate_table->uclk_pstate.min = mem_table->min;
1312 pstate_table->uclk_pstate.peak = mem_table->max;
1314 pstate_table->socclk_pstate.min = soc_table->min;
1315 pstate_table->socclk_pstate.peak = soc_table->max;
1317 pstate_table->vclk_pstate.min = vclk_table->min;
1318 pstate_table->vclk_pstate.peak = vclk_table->max;
1320 pstate_table->dclk_pstate.min = dclk_table->min;
1321 pstate_table->dclk_pstate.peak = dclk_table->max;
1323 pstate_table->fclk_pstate.min = fclk_table->min;
1324 pstate_table->fclk_pstate.peak = fclk_table->max;
1327 * For now, just use the mininum clock frequency.
1328 * TODO: update them when the real pstate settings available
1330 pstate_table->gfxclk_pstate.standard = gfx_table->min;
1331 pstate_table->uclk_pstate.standard = mem_table->min;
1332 pstate_table->socclk_pstate.standard = soc_table->min;
1333 pstate_table->vclk_pstate.standard = vclk_table->min;
1334 pstate_table->dclk_pstate.standard = dclk_table->min;
1335 pstate_table->fclk_pstate.standard = fclk_table->min;
1340 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
1342 struct smu_table_context *smu_table = &smu->smu_table;
1343 SmuMetrics_t *metrics =
1344 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1345 struct amdgpu_device *adev = smu->adev;
1346 uint32_t upper32 = 0, lower32 = 0;
1349 ret = smu_cmn_get_metrics_table(smu, NULL, false);
1353 upper32 = metrics->PublicSerialNumberUpper;
1354 lower32 = metrics->PublicSerialNumberLower;
1357 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1358 if (adev->serial[0] == '\0')
1359 sprintf(adev->serial, "%016llx", adev->unique_id);
1362 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
1368 return smu_v13_0_0_get_smu_metrics_data(smu,
1369 METRICS_CURR_FANPWM,
1373 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
1379 return smu_v13_0_0_get_smu_metrics_data(smu,
1380 METRICS_CURR_FANSPEED,
1384 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
1386 struct smu_table_context *table_context = &smu->smu_table;
1387 PPTable_t *pptable = table_context->driver_pptable;
1388 SkuTable_t *skutable = &pptable->SkuTable;
1391 * Skip the MGpuFanBoost setting for those ASICs
1392 * which do not support it
1394 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1397 return smu_cmn_send_smc_msg_with_param(smu,
1398 SMU_MSG_SetMGpuFanBoostLimitRpm,
1403 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
1404 uint32_t *current_power_limit,
1405 uint32_t *default_power_limit,
1406 uint32_t *max_power_limit)
1408 struct smu_table_context *table_context = &smu->smu_table;
1409 struct smu_13_0_0_powerplay_table *powerplay_table =
1410 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
1411 PPTable_t *pptable = table_context->driver_pptable;
1412 SkuTable_t *skutable = &pptable->SkuTable;
1413 uint32_t power_limit, od_percent;
1415 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1416 power_limit = smu->adev->pm.ac_power ?
1417 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1418 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1420 if (current_power_limit)
1421 *current_power_limit = power_limit;
1422 if (default_power_limit)
1423 *default_power_limit = power_limit;
1425 if (max_power_limit) {
1426 if (smu->od_enabled) {
1427 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
1429 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1431 power_limit *= (100 + od_percent);
1434 *max_power_limit = power_limit;
1440 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
1443 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1444 DpmActivityMonitorCoeffInt_t *activity_monitor =
1445 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1446 static const char *title[] = {
1447 "PROFILE_INDEX(NAME)",
1450 "MinActiveFreqType",
1455 "PD_Data_error_coeff",
1456 "PD_Data_error_rate_coeff"};
1457 int16_t workload_type = 0;
1458 uint32_t i, size = 0;
1464 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1465 title[0], title[1], title[2], title[3], title[4], title[5],
1466 title[6], title[7], title[8], title[9]);
1468 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1469 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1470 workload_type = smu_cmn_to_asic_specific_index(smu,
1471 CMN2ASIC_MAPPING_WORKLOAD,
1473 if (workload_type < 0)
1476 result = smu_cmn_update_table(smu,
1477 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1479 (void *)(&activity_monitor_external),
1482 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1486 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1487 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1489 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1493 activity_monitor->Gfx_FPS,
1494 activity_monitor->Gfx_MinActiveFreqType,
1495 activity_monitor->Gfx_MinActiveFreq,
1496 activity_monitor->Gfx_BoosterFreqType,
1497 activity_monitor->Gfx_BoosterFreq,
1498 activity_monitor->Gfx_PD_Data_limit_c,
1499 activity_monitor->Gfx_PD_Data_error_coeff,
1500 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1502 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1506 activity_monitor->Fclk_FPS,
1507 activity_monitor->Fclk_MinActiveFreqType,
1508 activity_monitor->Fclk_MinActiveFreq,
1509 activity_monitor->Fclk_BoosterFreqType,
1510 activity_monitor->Fclk_BoosterFreq,
1511 activity_monitor->Fclk_PD_Data_limit_c,
1512 activity_monitor->Fclk_PD_Data_error_coeff,
1513 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1519 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
1523 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1524 DpmActivityMonitorCoeffInt_t *activity_monitor =
1525 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1526 int workload_type, ret = 0;
1528 smu->power_profile_mode = input[size];
1530 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1531 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1535 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1536 ret = smu_cmn_update_table(smu,
1537 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1538 WORKLOAD_PPLIB_CUSTOM_BIT,
1539 (void *)(&activity_monitor_external),
1542 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1547 case 0: /* Gfxclk */
1548 activity_monitor->Gfx_FPS = input[1];
1549 activity_monitor->Gfx_MinActiveFreqType = input[2];
1550 activity_monitor->Gfx_MinActiveFreq = input[3];
1551 activity_monitor->Gfx_BoosterFreqType = input[4];
1552 activity_monitor->Gfx_BoosterFreq = input[5];
1553 activity_monitor->Gfx_PD_Data_limit_c = input[6];
1554 activity_monitor->Gfx_PD_Data_error_coeff = input[7];
1555 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
1558 activity_monitor->Fclk_FPS = input[1];
1559 activity_monitor->Fclk_MinActiveFreqType = input[2];
1560 activity_monitor->Fclk_MinActiveFreq = input[3];
1561 activity_monitor->Fclk_BoosterFreqType = input[4];
1562 activity_monitor->Fclk_BoosterFreq = input[5];
1563 activity_monitor->Fclk_PD_Data_limit_c = input[6];
1564 activity_monitor->Fclk_PD_Data_error_coeff = input[7];
1565 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
1569 ret = smu_cmn_update_table(smu,
1570 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1571 WORKLOAD_PPLIB_CUSTOM_BIT,
1572 (void *)(&activity_monitor_external),
1575 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1580 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1581 workload_type = smu_cmn_to_asic_specific_index(smu,
1582 CMN2ASIC_MAPPING_WORKLOAD,
1583 smu->power_profile_mode);
1584 if (workload_type < 0)
1587 return smu_cmn_send_smc_msg_with_param(smu,
1588 SMU_MSG_SetWorkloadMask,
1593 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
1595 struct amdgpu_device *adev = smu->adev;
1598 /* SRIOV does not support SMU mode1 reset */
1599 if (amdgpu_sriov_vf(adev))
1602 /* PMFW support is available since 78.41 */
1603 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1604 if (smu_version < 0x004e2900)
1610 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
1611 struct i2c_msg *msg, int num_msgs)
1613 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1614 struct amdgpu_device *adev = smu_i2c->adev;
1615 struct smu_context *smu = adev->powerplay.pp_handle;
1616 struct smu_table_context *smu_table = &smu->smu_table;
1617 struct smu_table *table = &smu_table->driver_table;
1618 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1622 if (!adev->pm.dpm_enabled)
1625 req = kzalloc(sizeof(*req), GFP_KERNEL);
1629 req->I2CcontrollerPort = smu_i2c->port;
1630 req->I2CSpeed = I2C_SPEED_FAST_400K;
1631 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1632 dir = msg[0].flags & I2C_M_RD;
1634 for (c = i = 0; i < num_msgs; i++) {
1635 for (j = 0; j < msg[i].len; j++, c++) {
1636 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1638 if (!(msg[i].flags & I2C_M_RD)) {
1640 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1641 cmd->ReadWriteData = msg[i].buf[j];
1644 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1645 /* The direction changes.
1647 dir = msg[i].flags & I2C_M_RD;
1648 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1654 * Insert STOP if we are at the last byte of either last
1655 * message for the transaction or the client explicitly
1656 * requires a STOP at this particular message.
1658 if ((j == msg[i].len - 1) &&
1659 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1660 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1661 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1665 mutex_lock(&adev->pm.mutex);
1666 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1667 mutex_unlock(&adev->pm.mutex);
1671 for (c = i = 0; i < num_msgs; i++) {
1672 if (!(msg[i].flags & I2C_M_RD)) {
1676 for (j = 0; j < msg[i].len; j++, c++) {
1677 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1679 msg[i].buf[j] = cmd->ReadWriteData;
1688 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
1690 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1693 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
1694 .master_xfer = smu_v13_0_0_i2c_xfer,
1695 .functionality = smu_v13_0_0_i2c_func,
1698 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
1699 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1700 .max_read_len = MAX_SW_I2C_COMMANDS,
1701 .max_write_len = MAX_SW_I2C_COMMANDS,
1702 .max_comb_1st_msg_len = 2,
1703 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1706 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
1708 struct amdgpu_device *adev = smu->adev;
1711 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1712 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1713 struct i2c_adapter *control = &smu_i2c->adapter;
1715 smu_i2c->adev = adev;
1717 mutex_init(&smu_i2c->mutex);
1718 control->owner = THIS_MODULE;
1719 control->class = I2C_CLASS_SPD;
1720 control->dev.parent = &adev->pdev->dev;
1721 control->algo = &smu_v13_0_0_i2c_algo;
1722 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1723 control->quirks = &smu_v13_0_0_i2c_control_quirks;
1724 i2c_set_adapdata(control, smu_i2c);
1726 res = i2c_add_adapter(control);
1728 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1733 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
1734 /* XXX ideally this would be something in a vbios data table */
1735 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1736 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1740 for ( ; i >= 0; i--) {
1741 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1742 struct i2c_adapter *control = &smu_i2c->adapter;
1744 i2c_del_adapter(control);
1749 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
1751 struct amdgpu_device *adev = smu->adev;
1754 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1755 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1756 struct i2c_adapter *control = &smu_i2c->adapter;
1758 i2c_del_adapter(control);
1760 adev->pm.ras_eeprom_i2c_bus = NULL;
1761 adev->pm.fru_eeprom_i2c_bus = NULL;
1764 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
1765 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
1766 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
1767 .i2c_init = smu_v13_0_0_i2c_control_init,
1768 .i2c_fini = smu_v13_0_0_i2c_control_fini,
1769 .is_dpm_running = smu_v13_0_0_is_dpm_running,
1770 .dump_pptable = smu_v13_0_0_dump_pptable,
1771 .init_microcode = smu_v13_0_init_microcode,
1772 .load_microcode = smu_v13_0_load_microcode,
1773 .init_smc_tables = smu_v13_0_0_init_smc_tables,
1774 .init_power = smu_v13_0_init_power,
1775 .fini_power = smu_v13_0_fini_power,
1776 .check_fw_status = smu_v13_0_check_fw_status,
1777 .setup_pptable = smu_v13_0_0_setup_pptable,
1778 .check_fw_version = smu_v13_0_check_fw_version,
1779 .write_pptable = smu_cmn_write_pptable,
1780 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1781 .system_features_control = smu_v13_0_0_system_features_control,
1782 .set_allowed_mask = smu_v13_0_set_allowed_mask,
1783 .get_enabled_mask = smu_cmn_get_enabled_mask,
1784 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1785 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1786 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1787 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1788 .read_sensor = smu_v13_0_0_read_sensor,
1789 .feature_is_enabled = smu_cmn_feature_is_enabled,
1790 .print_clk_levels = smu_v13_0_0_print_clk_levels,
1791 .force_clk_levels = smu_v13_0_0_force_clk_levels,
1792 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
1793 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
1794 .register_irq_handler = smu_v13_0_register_irq_handler,
1795 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1796 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1797 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1798 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
1799 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1800 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1801 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
1802 .set_performance_level = smu_v13_0_set_performance_level,
1803 .gfx_off_control = smu_v13_0_gfx_off_control,
1804 .get_unique_id = smu_v13_0_0_get_unique_id,
1805 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
1806 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
1807 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1808 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1809 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1810 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1811 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
1812 .get_power_limit = smu_v13_0_0_get_power_limit,
1813 .set_power_limit = smu_v13_0_set_power_limit,
1814 .set_power_source = smu_v13_0_set_power_source,
1815 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
1816 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
1817 .run_btc = smu_v13_0_run_btc,
1818 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1819 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1820 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1821 .deep_sleep_control = smu_v13_0_deep_sleep_control,
1822 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
1823 .baco_is_support = smu_v13_0_baco_is_support,
1824 .baco_get_state = smu_v13_0_baco_get_state,
1825 .baco_set_state = smu_v13_0_baco_set_state,
1826 .baco_enter = smu_v13_0_baco_enter,
1827 .baco_exit = smu_v13_0_baco_exit,
1828 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
1829 .mode1_reset = smu_v13_0_mode1_reset,
1830 .set_mp1_state = smu_cmn_set_mp1_state,
1833 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
1835 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
1836 smu->message_map = smu_v13_0_0_message_map;
1837 smu->clock_map = smu_v13_0_0_clk_map;
1838 smu->feature_map = smu_v13_0_0_feature_mask_map;
1839 smu->table_map = smu_v13_0_0_table_map;
1840 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
1841 smu->workload_map = smu_v13_0_0_workload_map;
1842 smu_v13_0_set_smu_mailbox_registers(smu);