2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
61 #define SMU13_VOLTAGE_SCALE 4
63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
65 #define LINK_WIDTH_MAX 6
66 #define LINK_SPEED_MAX 3
68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71 #define smnPCIE_LC_SPEED_CNTL 0x11140290
72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76 static const int link_speed[] = {25, 50, 80, 160};
78 int smu_v13_0_init_microcode(struct smu_context *smu)
80 struct amdgpu_device *adev = smu->adev;
81 const char *chip_name;
84 const struct smc_firmware_header_v1_0 *hdr;
85 const struct common_firmware_header *header;
86 struct amdgpu_firmware_info *ucode = NULL;
88 /* doesn't need to load smu firmware in IOV mode */
89 if (amdgpu_sriov_vf(adev))
92 switch (adev->asic_type) {
94 chip_name = "aldebaran";
97 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
101 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
103 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
106 err = amdgpu_ucode_validate(adev->pm.fw);
110 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
111 amdgpu_ucode_print_smc_hdr(&hdr->header);
112 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
115 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
116 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
117 ucode->fw = adev->pm.fw;
118 header = (const struct common_firmware_header *)ucode->fw->data;
119 adev->firmware.fw_size +=
120 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
125 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
127 release_firmware(adev->pm.fw);
133 void smu_v13_0_fini_microcode(struct smu_context *smu)
135 struct amdgpu_device *adev = smu->adev;
137 release_firmware(adev->pm.fw);
139 adev->pm.fw_version = 0;
142 int smu_v13_0_load_microcode(struct smu_context *smu)
145 struct amdgpu_device *adev = smu->adev;
147 const struct smc_firmware_header_v1_0 *hdr;
148 uint32_t addr_start = MP1_SRAM;
150 uint32_t smc_fw_size;
151 uint32_t mp1_fw_flags;
153 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
154 src = (const uint32_t *)(adev->pm.fw->data +
155 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
156 smc_fw_size = hdr->header.ucode_size_bytes;
158 for (i = 1; i < smc_fw_size/4 - 1; i++) {
159 WREG32_PCIE(addr_start, src[i]);
163 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
164 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
165 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
168 for (i = 0; i < adev->usec_timeout; i++) {
169 mp1_fw_flags = RREG32_PCIE(MP1_Public |
170 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
171 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
172 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
177 if (i == adev->usec_timeout)
183 int smu_v13_0_check_fw_status(struct smu_context *smu)
185 struct amdgpu_device *adev = smu->adev;
186 uint32_t mp1_fw_flags;
188 mp1_fw_flags = RREG32_PCIE(MP1_Public |
189 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
191 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
192 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
198 int smu_v13_0_check_fw_version(struct smu_context *smu)
200 uint32_t if_version = 0xff, smu_version = 0xff;
202 uint8_t smu_minor, smu_debug;
205 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
209 smu_major = (smu_version >> 16) & 0xffff;
210 smu_minor = (smu_version >> 8) & 0xff;
211 smu_debug = (smu_version >> 0) & 0xff;
213 switch (smu->adev->asic_type) {
215 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
217 case CHIP_YELLOW_CARP:
218 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
221 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
222 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
226 dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
227 smu_version, smu_major, smu_minor, smu_debug);
230 * 1. if_version mismatch is not critical as our fw is designed
231 * to be backward compatible.
232 * 2. New fw usually brings some optimizations. But that's visible
233 * only on the paired driver.
234 * Considering above, we just leave user a warning message instead
235 * of halt driver loading.
237 if (if_version != smu->smc_driver_if_version) {
238 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
239 "smu fw version = 0x%08x (%d.%d.%d)\n",
240 smu->smc_driver_if_version, if_version,
241 smu_version, smu_major, smu_minor, smu_debug);
242 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
248 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
249 uint32_t *size, uint32_t pptable_id)
251 struct amdgpu_device *adev = smu->adev;
252 const struct smc_firmware_header_v2_1 *v2_1;
253 struct smc_soft_pptable_entry *entries;
254 uint32_t pptable_count = 0;
257 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
258 entries = (struct smc_soft_pptable_entry *)
259 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
260 pptable_count = le32_to_cpu(v2_1->pptable_count);
261 for (i = 0; i < pptable_count; i++) {
262 if (le32_to_cpu(entries[i].id) == pptable_id) {
263 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
264 *size = le32_to_cpu(entries[i].ppt_size_bytes);
269 if (i == pptable_count)
275 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
277 struct amdgpu_device *adev = smu->adev;
278 uint16_t atom_table_size;
282 dev_info(adev->dev, "use vbios provided pptable\n");
283 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
286 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
292 *size = atom_table_size;
297 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
300 const struct smc_firmware_header_v1_0 *hdr;
301 struct amdgpu_device *adev = smu->adev;
302 uint16_t version_major, version_minor;
305 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
309 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
311 version_major = le16_to_cpu(hdr->header.header_version_major);
312 version_minor = le16_to_cpu(hdr->header.header_version_minor);
313 if (version_major != 2) {
314 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
315 version_major, version_minor);
319 switch (version_minor) {
321 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
331 int smu_v13_0_setup_pptable(struct smu_context *smu)
333 struct amdgpu_device *adev = smu->adev;
334 uint32_t size = 0, pptable_id = 0;
338 /* override pptable_id from driver parameter */
339 if (amdgpu_smu_pptable_id >= 0) {
340 pptable_id = amdgpu_smu_pptable_id;
341 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
343 pptable_id = smu->smu_table.boot_values.pp_table_id;
346 /* force using vbios pptable in sriov mode */
347 if (amdgpu_sriov_vf(adev) || !pptable_id)
348 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
350 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
355 if (!smu->smu_table.power_play_table)
356 smu->smu_table.power_play_table = table;
357 if (!smu->smu_table.power_play_table_size)
358 smu->smu_table.power_play_table_size = size;
363 int smu_v13_0_init_smc_tables(struct smu_context *smu)
365 struct smu_table_context *smu_table = &smu->smu_table;
366 struct smu_table *tables = smu_table->tables;
369 smu_table->driver_pptable =
370 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
371 if (!smu_table->driver_pptable) {
376 smu_table->max_sustainable_clocks =
377 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
378 if (!smu_table->max_sustainable_clocks) {
383 /* Aldebaran does not support OVERDRIVE */
384 if (tables[SMU_TABLE_OVERDRIVE].size) {
385 smu_table->overdrive_table =
386 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
387 if (!smu_table->overdrive_table) {
392 smu_table->boot_overdrive_table =
393 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
394 if (!smu_table->boot_overdrive_table) {
403 kfree(smu_table->overdrive_table);
405 kfree(smu_table->max_sustainable_clocks);
407 kfree(smu_table->driver_pptable);
412 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
414 struct smu_table_context *smu_table = &smu->smu_table;
415 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
417 kfree(smu_table->gpu_metrics_table);
418 kfree(smu_table->boot_overdrive_table);
419 kfree(smu_table->overdrive_table);
420 kfree(smu_table->max_sustainable_clocks);
421 kfree(smu_table->driver_pptable);
422 smu_table->gpu_metrics_table = NULL;
423 smu_table->boot_overdrive_table = NULL;
424 smu_table->overdrive_table = NULL;
425 smu_table->max_sustainable_clocks = NULL;
426 smu_table->driver_pptable = NULL;
427 kfree(smu_table->hardcode_pptable);
428 smu_table->hardcode_pptable = NULL;
430 kfree(smu_table->metrics_table);
431 kfree(smu_table->watermarks_table);
432 smu_table->metrics_table = NULL;
433 smu_table->watermarks_table = NULL;
434 smu_table->metrics_time = 0;
436 kfree(smu_dpm->dpm_context);
437 kfree(smu_dpm->golden_dpm_context);
438 kfree(smu_dpm->dpm_current_power_state);
439 kfree(smu_dpm->dpm_request_power_state);
440 smu_dpm->dpm_context = NULL;
441 smu_dpm->golden_dpm_context = NULL;
442 smu_dpm->dpm_context_size = 0;
443 smu_dpm->dpm_current_power_state = NULL;
444 smu_dpm->dpm_request_power_state = NULL;
449 int smu_v13_0_init_power(struct smu_context *smu)
451 struct smu_power_context *smu_power = &smu->smu_power;
453 if (smu_power->power_context || smu_power->power_context_size != 0)
456 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
458 if (!smu_power->power_context)
460 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
465 int smu_v13_0_fini_power(struct smu_context *smu)
467 struct smu_power_context *smu_power = &smu->smu_power;
469 if (!smu_power->power_context || smu_power->power_context_size == 0)
472 kfree(smu_power->power_context);
473 smu_power->power_context = NULL;
474 smu_power->power_context_size = 0;
479 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
484 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
485 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
488 input.clk_id = clk_id;
489 input.syspll_id = syspll_id;
490 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
491 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
494 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
499 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
500 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
505 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
510 struct atom_common_table_header *header;
511 struct atom_firmware_info_v3_4 *v_3_4;
512 struct atom_firmware_info_v3_3 *v_3_3;
513 struct atom_firmware_info_v3_1 *v_3_1;
515 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
518 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
519 (uint8_t **)&header);
523 if (header->format_revision != 3) {
524 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
528 switch (header->content_revision) {
532 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
533 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
534 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
535 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
536 smu->smu_table.boot_values.socclk = 0;
537 smu->smu_table.boot_values.dcefclk = 0;
538 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
539 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
540 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
541 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
542 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
543 smu->smu_table.boot_values.pp_table_id = 0;
546 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
547 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
548 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
549 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
550 smu->smu_table.boot_values.socclk = 0;
551 smu->smu_table.boot_values.dcefclk = 0;
552 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
553 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
554 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
555 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
556 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
557 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
561 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
562 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
563 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
564 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
565 smu->smu_table.boot_values.socclk = 0;
566 smu->smu_table.boot_values.dcefclk = 0;
567 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
568 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
569 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
570 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
571 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
572 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
576 smu->smu_table.boot_values.format_revision = header->format_revision;
577 smu->smu_table.boot_values.content_revision = header->content_revision;
579 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
580 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
582 &smu->smu_table.boot_values.socclk);
584 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
585 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
587 &smu->smu_table.boot_values.dcefclk);
589 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
590 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
592 &smu->smu_table.boot_values.eclk);
594 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
595 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
597 &smu->smu_table.boot_values.vclk);
599 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
600 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
602 &smu->smu_table.boot_values.dclk);
604 if ((smu->smu_table.boot_values.format_revision == 3) &&
605 (smu->smu_table.boot_values.content_revision >= 2))
606 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
607 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
608 (uint8_t)SMU11_SYSPLL1_2_ID,
609 &smu->smu_table.boot_values.fclk);
615 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
617 struct smu_table_context *smu_table = &smu->smu_table;
618 struct smu_table *memory_pool = &smu_table->memory_pool;
621 uint32_t address_low, address_high;
623 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
626 address = memory_pool->mc_address;
627 address_high = (uint32_t)upper_32_bits(address);
628 address_low = (uint32_t)lower_32_bits(address);
630 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
634 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
638 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
639 (uint32_t)memory_pool->size, NULL);
646 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
650 ret = smu_cmn_send_smc_msg_with_param(smu,
651 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
653 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
658 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
660 struct smu_table *driver_table = &smu->smu_table.driver_table;
663 if (driver_table->mc_address) {
664 ret = smu_cmn_send_smc_msg_with_param(smu,
665 SMU_MSG_SetDriverDramAddrHigh,
666 upper_32_bits(driver_table->mc_address),
669 ret = smu_cmn_send_smc_msg_with_param(smu,
670 SMU_MSG_SetDriverDramAddrLow,
671 lower_32_bits(driver_table->mc_address),
678 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
681 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
683 if (tool_table->mc_address) {
684 ret = smu_cmn_send_smc_msg_with_param(smu,
685 SMU_MSG_SetToolsDramAddrHigh,
686 upper_32_bits(tool_table->mc_address),
689 ret = smu_cmn_send_smc_msg_with_param(smu,
690 SMU_MSG_SetToolsDramAddrLow,
691 lower_32_bits(tool_table->mc_address),
698 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
702 if (!smu->pm_enabled)
705 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
711 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
713 struct smu_feature *feature = &smu->smu_feature;
715 uint32_t feature_mask[2];
717 mutex_lock(&feature->mutex);
718 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
721 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
723 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
724 feature_mask[1], NULL);
728 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
729 feature_mask[0], NULL);
734 mutex_unlock(&feature->mutex);
738 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
741 struct amdgpu_device *adev = smu->adev;
743 switch (adev->asic_type) {
744 case CHIP_YELLOW_CARP:
745 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
748 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
750 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
759 int smu_v13_0_system_features_control(struct smu_context *smu,
762 struct smu_feature *feature = &smu->smu_feature;
763 uint32_t feature_mask[2];
766 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
767 SMU_MSG_DisableAllSmuFeatures), NULL);
771 bitmap_zero(feature->enabled, feature->feature_num);
772 bitmap_zero(feature->supported, feature->feature_num);
775 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
779 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
780 feature->feature_num);
781 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
782 feature->feature_num);
788 int smu_v13_0_notify_display_change(struct smu_context *smu)
792 if (!smu->pm_enabled)
795 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
796 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
797 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
803 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
804 enum smu_clk_type clock_select)
809 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
810 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
813 clk_id = smu_cmn_to_asic_specific_index(smu,
814 CMN2ASIC_MAPPING_CLK,
819 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
820 clk_id << 16, clock);
822 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
829 /* if DC limit is zero, return AC limit */
830 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
831 clk_id << 16, clock);
833 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
840 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
842 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
843 smu->smu_table.max_sustainable_clocks;
846 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
847 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
848 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
849 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
850 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
851 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
853 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
854 ret = smu_v13_0_get_max_sustainable_clock(smu,
855 &(max_sustainable_clocks->uclock),
858 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
864 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
865 ret = smu_v13_0_get_max_sustainable_clock(smu,
866 &(max_sustainable_clocks->soc_clock),
869 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
875 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
876 ret = smu_v13_0_get_max_sustainable_clock(smu,
877 &(max_sustainable_clocks->dcef_clock),
880 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
885 ret = smu_v13_0_get_max_sustainable_clock(smu,
886 &(max_sustainable_clocks->display_clock),
889 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
893 ret = smu_v13_0_get_max_sustainable_clock(smu,
894 &(max_sustainable_clocks->phy_clock),
897 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
901 ret = smu_v13_0_get_max_sustainable_clock(smu,
902 &(max_sustainable_clocks->pixel_clock),
905 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
911 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
912 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
917 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
918 uint32_t *power_limit)
923 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
926 power_src = smu_cmn_to_asic_specific_index(smu,
927 CMN2ASIC_MAPPING_PWR,
928 smu->adev->pm.ac_power ?
929 SMU_POWER_SOURCE_AC :
930 SMU_POWER_SOURCE_DC);
934 ret = smu_cmn_send_smc_msg_with_param(smu,
939 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
944 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
948 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
949 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
953 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
955 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
959 smu->current_power_limit = n;
964 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
966 if (smu->smu_table.thermal_controller_type)
967 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
972 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
974 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
977 static uint16_t convert_to_vddc(uint8_t vid)
979 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
982 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
984 struct amdgpu_device *adev = smu->adev;
985 uint32_t vdd = 0, val_vid = 0;
989 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
990 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
991 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
993 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1002 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1003 struct pp_display_clock_request
1006 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1008 enum smu_clk_type clk_select = 0;
1009 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1012 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1014 case amd_pp_dcef_clock:
1015 clk_select = SMU_DCEFCLK;
1017 case amd_pp_disp_clock:
1018 clk_select = SMU_DISPCLK;
1020 case amd_pp_pixel_clock:
1021 clk_select = SMU_PIXCLK;
1023 case amd_pp_phy_clock:
1024 clk_select = SMU_PHYCLK;
1026 case amd_pp_mem_clock:
1027 clk_select = SMU_UCLK;
1030 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1038 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1041 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1043 if(clk_select == SMU_UCLK)
1044 smu->hard_min_uclk_req_from_dal = clk_freq;
1051 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1053 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1054 return AMD_FAN_CTRL_MANUAL;
1056 return AMD_FAN_CTRL_AUTO;
1060 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1064 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1067 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1069 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1070 __func__, (auto_fan_control ? "Start" : "Stop"));
1076 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1078 struct amdgpu_device *adev = smu->adev;
1080 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1081 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1082 CG_FDO_CTRL2, TMIN, 0));
1083 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1084 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1085 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1091 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1093 struct amdgpu_device *adev = smu->adev;
1094 uint32_t duty100, duty;
1100 if (smu_v13_0_auto_fan_control(smu, 0))
1103 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1104 CG_FDO_CTRL1, FMAX_DUTY100);
1108 tmp64 = (uint64_t)speed * duty100;
1110 duty = (uint32_t)tmp64;
1112 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1113 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1114 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1116 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1120 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1126 case AMD_FAN_CTRL_NONE:
1127 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1129 case AMD_FAN_CTRL_MANUAL:
1130 ret = smu_v13_0_auto_fan_control(smu, 0);
1132 case AMD_FAN_CTRL_AUTO:
1133 ret = smu_v13_0_auto_fan_control(smu, 1);
1140 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1147 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1150 struct amdgpu_device *adev = smu->adev;
1152 uint32_t tach_period, crystal_clock_freq;
1157 ret = smu_v13_0_auto_fan_control(smu, 0);
1161 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1162 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1163 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1164 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1165 CG_TACH_CTRL, TARGET_PERIOD,
1168 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1173 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1177 ret = smu_cmn_send_smc_msg_with_param(smu,
1178 SMU_MSG_SetXgmiMode,
1179 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1184 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1185 struct amdgpu_irq_src *source,
1187 enum amdgpu_interrupt_state state)
1189 struct smu_context *smu = &adev->smu;
1194 case AMDGPU_IRQ_STATE_DISABLE:
1196 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1197 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1198 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1199 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1201 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1203 /* For MP1 SW irqs */
1204 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1205 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1206 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1209 case AMDGPU_IRQ_STATE_ENABLE:
1211 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1212 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1213 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1214 smu->thermal_range.software_shutdown_temp);
1216 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1217 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1218 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1219 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1220 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1221 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1222 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1223 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1224 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1226 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1227 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1228 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1229 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1231 /* For MP1 SW irqs */
1232 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1233 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1234 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1235 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1237 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1238 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1239 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1249 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1251 return smu_cmn_send_smc_msg(smu,
1252 SMU_MSG_ReenableAcDcInterrupt,
1256 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1257 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1258 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1260 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1261 struct amdgpu_irq_src *source,
1262 struct amdgpu_iv_entry *entry)
1264 struct smu_context *smu = &adev->smu;
1265 uint32_t client_id = entry->client_id;
1266 uint32_t src_id = entry->src_id;
1268 * ctxid is used to distinguish different
1269 * events for SMCToHost interrupt.
1271 uint32_t ctxid = entry->src_data[0];
1274 if (client_id == SOC15_IH_CLIENTID_THM) {
1276 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1277 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1279 * SW CTF just occurred.
1280 * Try to do a graceful shutdown to prevent further damage.
1282 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1283 orderly_poweroff(true);
1285 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1286 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1289 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1293 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1294 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1296 * HW CTF just occurred. Shutdown to prevent further damage.
1298 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1299 orderly_poweroff(true);
1300 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1301 if (src_id == 0xfe) {
1302 /* ACK SMUToHost interrupt */
1303 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1304 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1305 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1309 dev_dbg(adev->dev, "Switched to AC mode!\n");
1310 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1313 dev_dbg(adev->dev, "Switched to DC mode!\n");
1314 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1318 * Increment the throttle interrupt counter
1320 atomic64_inc(&smu->throttle_int_counter);
1322 if (!atomic_read(&adev->throttling_logging_enabled))
1325 if (__ratelimit(&adev->throttling_logging_rs))
1326 schedule_work(&smu->throttling_logging_work);
1336 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1338 .set = smu_v13_0_set_irq_state,
1339 .process = smu_v13_0_irq_process,
1342 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1344 struct amdgpu_device *adev = smu->adev;
1345 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1348 irq_src->num_types = 1;
1349 irq_src->funcs = &smu_v13_0_irq_funcs;
1351 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1352 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1357 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1358 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1363 /* Register CTF(GPIO_19) interrupt */
1364 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1365 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1370 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1379 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1380 struct pp_smu_nv_clock_table *max_clocks)
1382 struct smu_table_context *table_context = &smu->smu_table;
1383 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1385 if (!max_clocks || !table_context->max_sustainable_clocks)
1388 sustainable_clocks = table_context->max_sustainable_clocks;
1390 max_clocks->dcfClockInKhz =
1391 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1392 max_clocks->displayClockInKhz =
1393 (unsigned int) sustainable_clocks->display_clock * 1000;
1394 max_clocks->phyClockInKhz =
1395 (unsigned int) sustainable_clocks->phy_clock * 1000;
1396 max_clocks->pixelClockInKhz =
1397 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1398 max_clocks->uClockInKhz =
1399 (unsigned int) sustainable_clocks->uclock * 1000;
1400 max_clocks->socClockInKhz =
1401 (unsigned int) sustainable_clocks->soc_clock * 1000;
1402 max_clocks->dscClockInKhz = 0;
1403 max_clocks->dppClockInKhz = 0;
1404 max_clocks->fabricClockInKhz = 0;
1409 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1413 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1418 int smu_v13_0_mode1_reset(struct smu_context *smu)
1423 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1425 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1426 if (smu_version < 0x00440700)
1427 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1429 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1432 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1437 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1442 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1443 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1448 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1454 case SMU_EVENT_RESET_COMPLETE:
1455 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1464 int smu_v13_0_mode2_reset(struct smu_context *smu)
1468 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1469 SMU_RESET_MODE_2, NULL);
1470 /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1472 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1477 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1478 uint32_t *min, uint32_t *max)
1480 int ret = 0, clk_id = 0;
1482 uint32_t clock_limit;
1484 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1488 clock_limit = smu->smu_table.boot_values.uclk;
1492 clock_limit = smu->smu_table.boot_values.gfxclk;
1495 clock_limit = smu->smu_table.boot_values.socclk;
1502 /* clock in Mhz unit */
1504 *min = clock_limit / 100;
1506 *max = clock_limit / 100;
1511 clk_id = smu_cmn_to_asic_specific_index(smu,
1512 CMN2ASIC_MAPPING_CLK,
1518 param = (clk_id & 0xffff) << 16;
1521 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1527 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1536 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1537 enum smu_clk_type clk_type,
1541 struct amdgpu_device *adev = smu->adev;
1542 int ret = 0, clk_id = 0;
1545 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1548 clk_id = smu_cmn_to_asic_specific_index(smu,
1549 CMN2ASIC_MAPPING_CLK,
1554 if (clk_type == SMU_GFXCLK)
1555 amdgpu_gfx_off_ctrl(adev, false);
1558 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1559 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1566 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1574 if (clk_type == SMU_GFXCLK)
1575 amdgpu_gfx_off_ctrl(adev, true);
1580 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1581 enum smu_clk_type clk_type,
1585 int ret = 0, clk_id = 0;
1588 if (min <= 0 && max <= 0)
1591 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1594 clk_id = smu_cmn_to_asic_specific_index(smu,
1595 CMN2ASIC_MAPPING_CLK,
1601 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1602 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1609 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1610 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1619 int smu_v13_0_set_performance_level(struct smu_context *smu,
1620 enum amd_dpm_forced_level level)
1622 struct smu_13_0_dpm_context *dpm_context =
1623 smu->smu_dpm.dpm_context;
1624 struct smu_13_0_dpm_table *gfx_table =
1625 &dpm_context->dpm_tables.gfx_table;
1626 struct smu_13_0_dpm_table *mem_table =
1627 &dpm_context->dpm_tables.uclk_table;
1628 struct smu_13_0_dpm_table *soc_table =
1629 &dpm_context->dpm_tables.soc_table;
1630 struct smu_umd_pstate_table *pstate_table =
1632 struct amdgpu_device *adev = smu->adev;
1633 uint32_t sclk_min = 0, sclk_max = 0;
1634 uint32_t mclk_min = 0, mclk_max = 0;
1635 uint32_t socclk_min = 0, socclk_max = 0;
1639 case AMD_DPM_FORCED_LEVEL_HIGH:
1640 sclk_min = sclk_max = gfx_table->max;
1641 mclk_min = mclk_max = mem_table->max;
1642 socclk_min = socclk_max = soc_table->max;
1644 case AMD_DPM_FORCED_LEVEL_LOW:
1645 sclk_min = sclk_max = gfx_table->min;
1646 mclk_min = mclk_max = mem_table->min;
1647 socclk_min = socclk_max = soc_table->min;
1649 case AMD_DPM_FORCED_LEVEL_AUTO:
1650 sclk_min = gfx_table->min;
1651 sclk_max = gfx_table->max;
1652 mclk_min = mem_table->min;
1653 mclk_max = mem_table->max;
1654 socclk_min = soc_table->min;
1655 socclk_max = soc_table->max;
1657 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1658 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1659 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1660 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1662 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1663 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1665 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1666 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1668 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1669 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1670 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1671 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1673 case AMD_DPM_FORCED_LEVEL_MANUAL:
1674 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1677 dev_err(adev->dev, "Invalid performance level %d\n", level);
1681 mclk_min = mclk_max = 0;
1682 socclk_min = socclk_max = 0;
1684 if (sclk_min && sclk_max) {
1685 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1692 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1693 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1696 if (mclk_min && mclk_max) {
1697 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1704 pstate_table->uclk_pstate.curr.min = mclk_min;
1705 pstate_table->uclk_pstate.curr.max = mclk_max;
1708 if (socclk_min && socclk_max) {
1709 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1716 pstate_table->socclk_pstate.curr.min = socclk_min;
1717 pstate_table->socclk_pstate.curr.max = socclk_max;
1723 int smu_v13_0_set_power_source(struct smu_context *smu,
1724 enum smu_power_src_type power_src)
1728 pwr_source = smu_cmn_to_asic_specific_index(smu,
1729 CMN2ASIC_MAPPING_PWR,
1730 (uint32_t)power_src);
1734 return smu_cmn_send_smc_msg_with_param(smu,
1735 SMU_MSG_NotifyPowerSource,
1740 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1741 enum smu_clk_type clk_type,
1745 int ret = 0, clk_id = 0;
1751 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1754 clk_id = smu_cmn_to_asic_specific_index(smu,
1755 CMN2ASIC_MAPPING_CLK,
1760 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1762 ret = smu_cmn_send_smc_msg_with_param(smu,
1763 SMU_MSG_GetDpmFreqByIndex,
1770 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1771 * now, we un-support it
1773 *value = *value & 0x7fffffff;
1778 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1779 enum smu_clk_type clk_type,
1784 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1785 /* FW returns 0 based max level, increment by one */
1792 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1793 enum smu_clk_type clk_type,
1794 struct smu_13_0_dpm_table *single_dpm_table)
1800 ret = smu_v13_0_get_dpm_level_count(smu,
1802 &single_dpm_table->count);
1804 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1808 for (i = 0; i < single_dpm_table->count; i++) {
1809 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1814 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1818 single_dpm_table->dpm_levels[i].value = clk;
1819 single_dpm_table->dpm_levels[i].enabled = true;
1822 single_dpm_table->min = clk;
1823 else if (i == single_dpm_table->count - 1)
1824 single_dpm_table->max = clk;
1830 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1831 enum smu_clk_type clk_type,
1832 uint32_t *min_value,
1833 uint32_t *max_value)
1835 uint32_t level_count = 0;
1838 if (!min_value && !max_value)
1842 /* by default, level 0 clock value as min value */
1843 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1852 ret = smu_v13_0_get_dpm_level_count(smu,
1858 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1869 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1871 struct amdgpu_device *adev = smu->adev;
1873 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1874 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1875 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1878 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1880 uint32_t width_level;
1882 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1883 if (width_level > LINK_WIDTH_MAX)
1886 return link_width[width_level];
1889 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1891 struct amdgpu_device *adev = smu->adev;
1893 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1894 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1895 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1898 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1900 uint32_t speed_level;
1902 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1903 if (speed_level > LINK_SPEED_MAX)
1906 return link_speed[speed_level];