drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60
  61 #define SMU13_VOLTAGE_SCALE 4
  62
  63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  64
  65 #define LINK_WIDTH_MAX                          6
  66 #define LINK_SPEED_MAX                          3
  67
  68 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  71 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  74
  75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  76 static const int link_speed[] = {25, 50, 80, 160};
  77
  78 int smu_v13_0_init_microcode(struct smu_context *smu)
  79 {
  80         struct amdgpu_device *adev = smu->adev;
  81         const char *chip_name;
  82         char fw_name[30];
  83         int err = 0;
  84         const struct smc_firmware_header_v1_0 *hdr;
  85         const struct common_firmware_header *header;
  86         struct amdgpu_firmware_info *ucode = NULL;
  87
  88         switch (adev->asic_type) {
  89         case CHIP_ALDEBARAN:
  90                 chip_name = "aldebaran";
  91                 break;
  92         default:
  93                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
  94                 return -EINVAL;
  95         }
  96
  97         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
  98
  99         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 100         if (err)
 101                 goto out;
 102         err = amdgpu_ucode_validate(adev->pm.fw);
 103         if (err)
 104                 goto out;
 105
 106         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 107         amdgpu_ucode_print_smc_hdr(&hdr->header);
 108         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 109
 110         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 111                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 112                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 113                 ucode->fw = adev->pm.fw;
 114                 header = (const struct common_firmware_header *)ucode->fw->data;
 115                 adev->firmware.fw_size +=
 116                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 117         }
 118
 119 out:
 120         if (err) {
 121                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 122                           fw_name);
 123                 release_firmware(adev->pm.fw);
 124                 adev->pm.fw = NULL;
 125         }
 126         return err;
 127 }
 128
 129 void smu_v13_0_fini_microcode(struct smu_context *smu)
 130 {
 131         struct amdgpu_device *adev = smu->adev;
 132
 133         release_firmware(adev->pm.fw);
 134         adev->pm.fw = NULL;
 135         adev->pm.fw_version = 0;
 136 }
 137
 138 int smu_v13_0_load_microcode(struct smu_context *smu)
 139 {
 140 #if 0
 141         struct amdgpu_device *adev = smu->adev;
 142         const uint32_t *src;
 143         const struct smc_firmware_header_v1_0 *hdr;
 144         uint32_t addr_start = MP1_SRAM;
 145         uint32_t i;
 146         uint32_t smc_fw_size;
 147         uint32_t mp1_fw_flags;
 148
 149         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 150         src = (const uint32_t *)(adev->pm.fw->data +
 151                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 152         smc_fw_size = hdr->header.ucode_size_bytes;
 153
 154         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 155                 WREG32_PCIE(addr_start, src[i]);
 156                 addr_start += 4;
 157         }
 158
 159         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 160                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 161         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 162                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 163
 164         for (i = 0; i < adev->usec_timeout; i++) {
 165                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 166                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 167                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 168                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 169                         break;
 170                 udelay(1);
 171         }
 172
 173         if (i == adev->usec_timeout)
 174                 return -ETIME;
 175 #endif
 176         return 0;
 177 }
 178
 179 int smu_v13_0_check_fw_status(struct smu_context *smu)
 180 {
 181         struct amdgpu_device *adev = smu->adev;
 182         uint32_t mp1_fw_flags;
 183
 184         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 185                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 186
 187         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 188             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 189                 return 0;
 190
 191         return -EIO;
 192 }
 193
 194 int smu_v13_0_check_fw_version(struct smu_context *smu)
 195 {
 196         uint32_t if_version = 0xff, smu_version = 0xff;
 197         uint16_t smu_major;
 198         uint8_t smu_minor, smu_debug;
 199         int ret = 0;
 200
 201         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 202         if (ret)
 203                 return ret;
 204
 205         smu_major = (smu_version >> 16) & 0xffff;
 206         smu_minor = (smu_version >> 8) & 0xff;
 207         smu_debug = (smu_version >> 0) & 0xff;
 208
 209         switch (smu->adev->asic_type) {
 210         case CHIP_ALDEBARAN:
 211                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 212                 break;
 213         case CHIP_YELLOW_CARP:
 214                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 215                 break;
 216         default:
 217                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 218                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 219                 break;
 220         }
 221
 222         dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
 223                          smu_version, smu_major, smu_minor, smu_debug);
 224
 225         /*
 226          * 1. if_version mismatch is not critical as our fw is designed
 227          * to be backward compatible.
 228          * 2. New fw usually brings some optimizations. But that's visible
 229          * only on the paired driver.
 230          * Considering above, we just leave user a warning message instead
 231          * of halt driver loading.
 232          */
 233         if (if_version != smu->smc_driver_if_version) {
 234                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 235                          "smu fw version = 0x%08x (%d.%d.%d)\n",
 236                          smu->smc_driver_if_version, if_version,
 237                          smu_version, smu_major, smu_minor, smu_debug);
 238                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 239         }
 240
 241         return ret;
 242 }
 243
 244 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 245                                       uint32_t *size, uint32_t pptable_id)
 246 {
 247         struct amdgpu_device *adev = smu->adev;
 248         const struct smc_firmware_header_v2_1 *v2_1;
 249         struct smc_soft_pptable_entry *entries;
 250         uint32_t pptable_count = 0;
 251         int i = 0;
 252
 253         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 254         entries = (struct smc_soft_pptable_entry *)
 255                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 256         pptable_count = le32_to_cpu(v2_1->pptable_count);
 257         for (i = 0; i < pptable_count; i++) {
 258                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 259                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 260                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 261                         break;
 262                 }
 263         }
 264
 265         if (i == pptable_count)
 266                 return -EINVAL;
 267
 268         return 0;
 269 }
 270
 271 int smu_v13_0_setup_pptable(struct smu_context *smu)
 272 {
 273         struct amdgpu_device *adev = smu->adev;
 274         const struct smc_firmware_header_v1_0 *hdr;
 275         int ret, index;
 276         uint32_t size = 0;
 277         uint16_t atom_table_size;
 278         uint8_t frev, crev;
 279         void *table;
 280         uint16_t version_major, version_minor;
 281
 282
 283         if (amdgpu_smu_pptable_id >= 0) {
 284                 smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
 285                 dev_info(adev->dev, "override pptable id %d\n", amdgpu_smu_pptable_id);
 286         }
 287
 288         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 289         version_major = le16_to_cpu(hdr->header.header_version_major);
 290         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 291         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 292                 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 293                 switch (version_minor) {
 294                 case 1:
 295                         ret = smu_v13_0_set_pptable_v2_1(smu, &table, &size,
 296                                                          smu->smu_table.boot_values.pp_table_id);
 297                         break;
 298                 default:
 299                         ret = -EINVAL;
 300                         break;
 301                 }
 302                 if (ret)
 303                         return ret;
 304
 305         } else {
 306                 dev_info(adev->dev, "use vbios provided pptable\n");
 307                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 308                                                     powerplayinfo);
 309
 310                 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 311                                                      (uint8_t **)&table);
 312                 if (ret)
 313                         return ret;
 314                 size = atom_table_size;
 315         }
 316
 317         if (!smu->smu_table.power_play_table)
 318                 smu->smu_table.power_play_table = table;
 319         if (!smu->smu_table.power_play_table_size)
 320                 smu->smu_table.power_play_table_size = size;
 321
 322         return 0;
 323 }
 324
 325 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 326 {
 327         struct smu_table_context *smu_table = &smu->smu_table;
 328         struct smu_table *tables = smu_table->tables;
 329         int ret = 0;
 330
 331         smu_table->driver_pptable =
 332                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 333         if (!smu_table->driver_pptable) {
 334                 ret = -ENOMEM;
 335                 goto err0_out;
 336         }
 337
 338         smu_table->max_sustainable_clocks =
 339                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 340         if (!smu_table->max_sustainable_clocks) {
 341                 ret = -ENOMEM;
 342                 goto err1_out;
 343         }
 344
 345         /* Aldebaran does not support OVERDRIVE */
 346         if (tables[SMU_TABLE_OVERDRIVE].size) {
 347                 smu_table->overdrive_table =
 348                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 349                 if (!smu_table->overdrive_table) {
 350                         ret = -ENOMEM;
 351                         goto err2_out;
 352                 }
 353
 354                 smu_table->boot_overdrive_table =
 355                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 356                 if (!smu_table->boot_overdrive_table) {
 357                         ret = -ENOMEM;
 358                         goto err3_out;
 359                 }
 360         }
 361
 362         return 0;
 363
 364 err3_out:
 365         kfree(smu_table->overdrive_table);
 366 err2_out:
 367         kfree(smu_table->max_sustainable_clocks);
 368 err1_out:
 369         kfree(smu_table->driver_pptable);
 370 err0_out:
 371         return ret;
 372 }
 373
 374 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 375 {
 376         struct smu_table_context *smu_table = &smu->smu_table;
 377         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 378
 379         kfree(smu_table->gpu_metrics_table);
 380         kfree(smu_table->boot_overdrive_table);
 381         kfree(smu_table->overdrive_table);
 382         kfree(smu_table->max_sustainable_clocks);
 383         kfree(smu_table->driver_pptable);
 384         smu_table->gpu_metrics_table = NULL;
 385         smu_table->boot_overdrive_table = NULL;
 386         smu_table->overdrive_table = NULL;
 387         smu_table->max_sustainable_clocks = NULL;
 388         smu_table->driver_pptable = NULL;
 389         kfree(smu_table->hardcode_pptable);
 390         smu_table->hardcode_pptable = NULL;
 391
 392         kfree(smu_table->metrics_table);
 393         kfree(smu_table->watermarks_table);
 394         smu_table->metrics_table = NULL;
 395         smu_table->watermarks_table = NULL;
 396         smu_table->metrics_time = 0;
 397
 398         kfree(smu_dpm->dpm_context);
 399         kfree(smu_dpm->golden_dpm_context);
 400         kfree(smu_dpm->dpm_current_power_state);
 401         kfree(smu_dpm->dpm_request_power_state);
 402         smu_dpm->dpm_context = NULL;
 403         smu_dpm->golden_dpm_context = NULL;
 404         smu_dpm->dpm_context_size = 0;
 405         smu_dpm->dpm_current_power_state = NULL;
 406         smu_dpm->dpm_request_power_state = NULL;
 407
 408         return 0;
 409 }
 410
 411 int smu_v13_0_init_power(struct smu_context *smu)
 412 {
 413         struct smu_power_context *smu_power = &smu->smu_power;
 414
 415         if (smu_power->power_context || smu_power->power_context_size != 0)
 416                 return -EINVAL;
 417
 418         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 419                                            GFP_KERNEL);
 420         if (!smu_power->power_context)
 421                 return -ENOMEM;
 422         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 423
 424         return 0;
 425 }
 426
 427 int smu_v13_0_fini_power(struct smu_context *smu)
 428 {
 429         struct smu_power_context *smu_power = &smu->smu_power;
 430
 431         if (!smu_power->power_context || smu_power->power_context_size == 0)
 432                 return -EINVAL;
 433
 434         kfree(smu_power->power_context);
 435         smu_power->power_context = NULL;
 436         smu_power->power_context_size = 0;
 437
 438         return 0;
 439 }
 440
 441 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 442                                             uint8_t clk_id,
 443                                             uint8_t syspll_id,
 444                                             uint32_t *clk_freq)
 445 {
 446         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 447         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 448         int ret, index;
 449
 450         input.clk_id = clk_id;
 451         input.syspll_id = syspll_id;
 452         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 453         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 454                                             getsmuclockinfo);
 455
 456         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 457                                         (uint32_t *)&input);
 458         if (ret)
 459                 return -EINVAL;
 460
 461         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 462         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 463
 464         return 0;
 465 }
 466
 467 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 468 {
 469         int ret, index;
 470         uint16_t size;
 471         uint8_t frev, crev;
 472         struct atom_common_table_header *header;
 473         struct atom_firmware_info_v3_4 *v_3_4;
 474         struct atom_firmware_info_v3_3 *v_3_3;
 475         struct atom_firmware_info_v3_1 *v_3_1;
 476
 477         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 478                                             firmwareinfo);
 479
 480         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 481                                              (uint8_t **)&header);
 482         if (ret)
 483                 return ret;
 484
 485         if (header->format_revision != 3) {
 486                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 487                 return -EINVAL;
 488         }
 489
 490         switch (header->content_revision) {
 491         case 0:
 492         case 1:
 493         case 2:
 494                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 495                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 496                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 497                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 498                 smu->smu_table.boot_values.socclk = 0;
 499                 smu->smu_table.boot_values.dcefclk = 0;
 500                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 501                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 502                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 503                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 504                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 505                 smu->smu_table.boot_values.pp_table_id = 0;
 506                 break;
 507         case 3:
 508                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 509                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 510                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 511                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 512                 smu->smu_table.boot_values.socclk = 0;
 513                 smu->smu_table.boot_values.dcefclk = 0;
 514                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 515                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 516                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 517                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 518                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 519                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 520                 break;
 521         case 4:
 522         default:
 523                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 524                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 525                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 526                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 527                 smu->smu_table.boot_values.socclk = 0;
 528                 smu->smu_table.boot_values.dcefclk = 0;
 529                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 530                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 531                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 532                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 533                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 534                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 535                 break;
 536         }
 537
 538         smu->smu_table.boot_values.format_revision = header->format_revision;
 539         smu->smu_table.boot_values.content_revision = header->content_revision;
 540
 541         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 542                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 543                                          (uint8_t)0,
 544                                          &smu->smu_table.boot_values.socclk);
 545
 546         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 547                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 548                                          (uint8_t)0,
 549                                          &smu->smu_table.boot_values.dcefclk);
 550
 551         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 552                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 553                                          (uint8_t)0,
 554                                          &smu->smu_table.boot_values.eclk);
 555
 556         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 557                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 558                                          (uint8_t)0,
 559                                          &smu->smu_table.boot_values.vclk);
 560
 561         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 562                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 563                                          (uint8_t)0,
 564                                          &smu->smu_table.boot_values.dclk);
 565
 566         if ((smu->smu_table.boot_values.format_revision == 3) &&
 567             (smu->smu_table.boot_values.content_revision >= 2))
 568                 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 569                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 570                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 571                                                  &smu->smu_table.boot_values.fclk);
 572
 573         return 0;
 574 }
 575
 576
 577 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 578 {
 579         struct smu_table_context *smu_table = &smu->smu_table;
 580         struct smu_table *memory_pool = &smu_table->memory_pool;
 581         int ret = 0;
 582         uint64_t address;
 583         uint32_t address_low, address_high;
 584
 585         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 586                 return ret;
 587
 588         address = memory_pool->mc_address;
 589         address_high = (uint32_t)upper_32_bits(address);
 590         address_low  = (uint32_t)lower_32_bits(address);
 591
 592         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 593                                               address_high, NULL);
 594         if (ret)
 595                 return ret;
 596         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 597                                               address_low, NULL);
 598         if (ret)
 599                 return ret;
 600         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 601                                               (uint32_t)memory_pool->size, NULL);
 602         if (ret)
 603                 return ret;
 604
 605         return ret;
 606 }
 607
 608 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 609 {
 610         int ret;
 611
 612         ret = smu_cmn_send_smc_msg_with_param(smu,
 613                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 614         if (ret)
 615                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 616
 617         return ret;
 618 }
 619
 620 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 621 {
 622         struct smu_table *driver_table = &smu->smu_table.driver_table;
 623         int ret = 0;
 624
 625         if (driver_table->mc_address) {
 626                 ret = smu_cmn_send_smc_msg_with_param(smu,
 627                                                       SMU_MSG_SetDriverDramAddrHigh,
 628                                                       upper_32_bits(driver_table->mc_address),
 629                                                       NULL);
 630                 if (!ret)
 631                         ret = smu_cmn_send_smc_msg_with_param(smu,
 632                                                               SMU_MSG_SetDriverDramAddrLow,
 633                                                               lower_32_bits(driver_table->mc_address),
 634                                                               NULL);
 635         }
 636
 637         return ret;
 638 }
 639
 640 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 641 {
 642         int ret = 0;
 643         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 644
 645         if (tool_table->mc_address) {
 646                 ret = smu_cmn_send_smc_msg_with_param(smu,
 647                                                       SMU_MSG_SetToolsDramAddrHigh,
 648                                                       upper_32_bits(tool_table->mc_address),
 649                                                       NULL);
 650                 if (!ret)
 651                         ret = smu_cmn_send_smc_msg_with_param(smu,
 652                                                               SMU_MSG_SetToolsDramAddrLow,
 653                                                               lower_32_bits(tool_table->mc_address),
 654                                                               NULL);
 655         }
 656
 657         return ret;
 658 }
 659
 660 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 661 {
 662         int ret = 0;
 663
 664         if (!smu->pm_enabled)
 665                 return ret;
 666
 667         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 668
 669         return ret;
 670 }
 671
 672
 673 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 674 {
 675         struct smu_feature *feature = &smu->smu_feature;
 676         int ret = 0;
 677         uint32_t feature_mask[2];
 678
 679         mutex_lock(&feature->mutex);
 680         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 681                 goto failed;
 682
 683         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 684
 685         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 686                                               feature_mask[1], NULL);
 687         if (ret)
 688                 goto failed;
 689
 690         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 691                                               feature_mask[0], NULL);
 692         if (ret)
 693                 goto failed;
 694
 695 failed:
 696         mutex_unlock(&feature->mutex);
 697         return ret;
 698 }
 699
 700 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 701 {
 702         int ret = 0;
 703         struct amdgpu_device *adev = smu->adev;
 704
 705         switch (adev->asic_type) {
 706         case CHIP_YELLOW_CARP:
 707                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 708                         return 0;
 709                 if (enable)
 710                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 711                 else
 712                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 713                 break;
 714         default:
 715                 break;
 716         }
 717
 718         return ret;
 719 }
 720
 721 int smu_v13_0_system_features_control(struct smu_context *smu,
 722                                       bool en)
 723 {
 724         struct smu_feature *feature = &smu->smu_feature;
 725         uint32_t feature_mask[2];
 726         int ret = 0;
 727
 728         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 729                                          SMU_MSG_DisableAllSmuFeatures), NULL);
 730         if (ret)
 731                 return ret;
 732
 733         bitmap_zero(feature->enabled, feature->feature_num);
 734         bitmap_zero(feature->supported, feature->feature_num);
 735
 736         if (en) {
 737                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 738                 if (ret)
 739                         return ret;
 740
 741                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 742                             feature->feature_num);
 743                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 744                             feature->feature_num);
 745         }
 746
 747         return ret;
 748 }
 749
 750 int smu_v13_0_notify_display_change(struct smu_context *smu)
 751 {
 752         int ret = 0;
 753
 754         if (!smu->pm_enabled)
 755                 return ret;
 756
 757         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 758             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 759                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 760
 761         return ret;
 762 }
 763
 764         static int
 765 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 766                                     enum smu_clk_type clock_select)
 767 {
 768         int ret = 0;
 769         int clk_id;
 770
 771         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 772             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 773                 return 0;
 774
 775         clk_id = smu_cmn_to_asic_specific_index(smu,
 776                                                 CMN2ASIC_MAPPING_CLK,
 777                                                 clock_select);
 778         if (clk_id < 0)
 779                 return -EINVAL;
 780
 781         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 782                                               clk_id << 16, clock);
 783         if (ret) {
 784                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 785                 return ret;
 786         }
 787
 788         if (*clock != 0)
 789                 return 0;
 790
 791         /* if DC limit is zero, return AC limit */
 792         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 793                                               clk_id << 16, clock);
 794         if (ret) {
 795                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 796                 return ret;
 797         }
 798
 799         return 0;
 800 }
 801
 802 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 803 {
 804         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 805                 smu->smu_table.max_sustainable_clocks;
 806         int ret = 0;
 807
 808         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 809         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 810         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 811         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 812         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 813         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 814
 815         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 816                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 817                                                           &(max_sustainable_clocks->uclock),
 818                                                           SMU_UCLK);
 819                 if (ret) {
 820                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 821                                 __func__);
 822                         return ret;
 823                 }
 824         }
 825
 826         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 827                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 828                                                           &(max_sustainable_clocks->soc_clock),
 829                                                           SMU_SOCCLK);
 830                 if (ret) {
 831                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 832                                 __func__);
 833                         return ret;
 834                 }
 835         }
 836
 837         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 838                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 839                                                           &(max_sustainable_clocks->dcef_clock),
 840                                                           SMU_DCEFCLK);
 841                 if (ret) {
 842                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 843                                 __func__);
 844                         return ret;
 845                 }
 846
 847                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 848                                                           &(max_sustainable_clocks->display_clock),
 849                                                           SMU_DISPCLK);
 850                 if (ret) {
 851                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 852                                 __func__);
 853                         return ret;
 854                 }
 855                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 856                                                           &(max_sustainable_clocks->phy_clock),
 857                                                           SMU_PHYCLK);
 858                 if (ret) {
 859                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 860                                 __func__);
 861                         return ret;
 862                 }
 863                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 864                                                           &(max_sustainable_clocks->pixel_clock),
 865                                                           SMU_PIXCLK);
 866                 if (ret) {
 867                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 868                                 __func__);
 869                         return ret;
 870                 }
 871         }
 872
 873         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 874                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 875
 876         return 0;
 877 }
 878
 879 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 880                                       uint32_t *power_limit)
 881 {
 882         int power_src;
 883         int ret = 0;
 884
 885         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 886                 return -EINVAL;
 887
 888         power_src = smu_cmn_to_asic_specific_index(smu,
 889                                                    CMN2ASIC_MAPPING_PWR,
 890                                                    smu->adev->pm.ac_power ?
 891                                                    SMU_POWER_SOURCE_AC :
 892                                                    SMU_POWER_SOURCE_DC);
 893         if (power_src < 0)
 894                 return -EINVAL;
 895
 896         ret = smu_cmn_send_smc_msg_with_param(smu,
 897                                               SMU_MSG_GetPptLimit,
 898                                               power_src << 16,
 899                                               power_limit);
 900         if (ret)
 901                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 902
 903         return ret;
 904 }
 905
 906 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
 907 {
 908         int ret = 0;
 909
 910         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 911                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 912                 return -EOPNOTSUPP;
 913         }
 914
 915         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 916         if (ret) {
 917                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 918                 return ret;
 919         }
 920
 921         smu->current_power_limit = n;
 922
 923         return 0;
 924 }
 925
 926 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 927 {
 928         if (smu->smu_table.thermal_controller_type)
 929                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 930
 931         return 0;
 932 }
 933
 934 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
 935 {
 936         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 937 }
 938
 939 static uint16_t convert_to_vddc(uint8_t vid)
 940 {
 941         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
 942 }
 943
 944 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 945 {
 946         struct amdgpu_device *adev = smu->adev;
 947         uint32_t vdd = 0, val_vid = 0;
 948
 949         if (!value)
 950                 return -EINVAL;
 951         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
 952                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 953                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 954
 955         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 956
 957         *value = vdd;
 958
 959         return 0;
 960
 961 }
 962
 963 int
 964 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
 965                                         struct pp_display_clock_request
 966                                         *clock_req)
 967 {
 968         enum amd_pp_clock_type clk_type = clock_req->clock_type;
 969         int ret = 0;
 970         enum smu_clk_type clk_select = 0;
 971         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
 972
 973         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
 974             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 975                 switch (clk_type) {
 976                 case amd_pp_dcef_clock:
 977                         clk_select = SMU_DCEFCLK;
 978                         break;
 979                 case amd_pp_disp_clock:
 980                         clk_select = SMU_DISPCLK;
 981                         break;
 982                 case amd_pp_pixel_clock:
 983                         clk_select = SMU_PIXCLK;
 984                         break;
 985                 case amd_pp_phy_clock:
 986                         clk_select = SMU_PHYCLK;
 987                         break;
 988                 case amd_pp_mem_clock:
 989                         clk_select = SMU_UCLK;
 990                         break;
 991                 default:
 992                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
 993                         ret = -EINVAL;
 994                         break;
 995                 }
 996
 997                 if (ret)
 998                         goto failed;
 999
1000                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1001                         return 0;
1002
1003                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1004
1005                 if(clk_select == SMU_UCLK)
1006                         smu->hard_min_uclk_req_from_dal = clk_freq;
1007         }
1008
1009 failed:
1010         return ret;
1011 }
1012
1013 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1014 {
1015         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1016                 return AMD_FAN_CTRL_MANUAL;
1017         else
1018                 return AMD_FAN_CTRL_AUTO;
1019 }
1020
1021         static int
1022 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1023 {
1024         int ret = 0;
1025
1026         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1027                 return 0;
1028
1029         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1030         if (ret)
1031                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1032                         __func__, (auto_fan_control ? "Start" : "Stop"));
1033
1034         return ret;
1035 }
1036
1037         static int
1038 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1039 {
1040         struct amdgpu_device *adev = smu->adev;
1041
1042         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1043                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1044                                    CG_FDO_CTRL2, TMIN, 0));
1045         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1046                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1047                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1048
1049         return 0;
1050 }
1051
1052         int
1053 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1054 {
1055         struct amdgpu_device *adev = smu->adev;
1056         uint32_t duty100, duty;
1057         uint64_t tmp64;
1058
1059         if (speed > 100)
1060                 speed = 100;
1061
1062         if (smu_v13_0_auto_fan_control(smu, 0))
1063                 return -EINVAL;
1064
1065         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1066                                 CG_FDO_CTRL1, FMAX_DUTY100);
1067         if (!duty100)
1068                 return -EINVAL;
1069
1070         tmp64 = (uint64_t)speed * duty100;
1071         do_div(tmp64, 100);
1072         duty = (uint32_t)tmp64;
1073
1074         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1075                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1076                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1077
1078         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1079 }
1080
1081         int
1082 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1083                                uint32_t mode)
1084 {
1085         int ret = 0;
1086
1087         switch (mode) {
1088         case AMD_FAN_CTRL_NONE:
1089                 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1090                 break;
1091         case AMD_FAN_CTRL_MANUAL:
1092                 ret = smu_v13_0_auto_fan_control(smu, 0);
1093                 break;
1094         case AMD_FAN_CTRL_AUTO:
1095                 ret = smu_v13_0_auto_fan_control(smu, 1);
1096                 break;
1097         default:
1098                 break;
1099         }
1100
1101         if (ret) {
1102                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1103                 return -EINVAL;
1104         }
1105
1106         return ret;
1107 }
1108
1109 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1110                                 uint32_t speed)
1111 {
1112         struct amdgpu_device *adev = smu->adev;
1113         int ret;
1114         uint32_t tach_period, crystal_clock_freq;
1115
1116         if (!speed)
1117                 return -EINVAL;
1118
1119         ret = smu_v13_0_auto_fan_control(smu, 0);
1120         if (ret)
1121                 return ret;
1122
1123         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1124         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1125         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1126                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1127                                    CG_TACH_CTRL, TARGET_PERIOD,
1128                                    tach_period));
1129
1130         ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1131
1132         return ret;
1133 }
1134
1135 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1136                               uint32_t pstate)
1137 {
1138         int ret = 0;
1139         ret = smu_cmn_send_smc_msg_with_param(smu,
1140                                               SMU_MSG_SetXgmiMode,
1141                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1142                                               NULL);
1143         return ret;
1144 }
1145
1146 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1147                                    struct amdgpu_irq_src *source,
1148                                    unsigned tyep,
1149                                    enum amdgpu_interrupt_state state)
1150 {
1151         struct smu_context *smu = &adev->smu;
1152         uint32_t low, high;
1153         uint32_t val = 0;
1154
1155         switch (state) {
1156         case AMDGPU_IRQ_STATE_DISABLE:
1157                 /* For THM irqs */
1158                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1159                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1160                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1161                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1162
1163                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1164
1165                 /* For MP1 SW irqs */
1166                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1167                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1168                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1169
1170                 break;
1171         case AMDGPU_IRQ_STATE_ENABLE:
1172                 /* For THM irqs */
1173                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1174                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1175                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1176                            smu->thermal_range.software_shutdown_temp);
1177
1178                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1179                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1180                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1181                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1182                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1183                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1184                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1185                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1186                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1187
1188                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1189                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1190                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1191                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1192
1193                 /* For MP1 SW irqs */
1194                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1195                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1196                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1197                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1198
1199                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1200                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1201                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1202
1203                 break;
1204         default:
1205                 break;
1206         }
1207
1208         return 0;
1209 }
1210
1211 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1212 {
1213         return smu_cmn_send_smc_msg(smu,
1214                                     SMU_MSG_ReenableAcDcInterrupt,
1215                                     NULL);
1216 }
1217
1218 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1219 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1220 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1221
1222 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1223                                  struct amdgpu_irq_src *source,
1224                                  struct amdgpu_iv_entry *entry)
1225 {
1226         struct smu_context *smu = &adev->smu;
1227         uint32_t client_id = entry->client_id;
1228         uint32_t src_id = entry->src_id;
1229         /*
1230          * ctxid is used to distinguish different
1231          * events for SMCToHost interrupt.
1232          */
1233         uint32_t ctxid = entry->src_data[0];
1234         uint32_t data;
1235
1236         if (client_id == SOC15_IH_CLIENTID_THM) {
1237                 switch (src_id) {
1238                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1239                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1240                         /*
1241                          * SW CTF just occurred.
1242                          * Try to do a graceful shutdown to prevent further damage.
1243                          */
1244                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1245                         orderly_poweroff(true);
1246                         break;
1247                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1248                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1249                         break;
1250                 default:
1251                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1252                                   src_id);
1253                         break;
1254                 }
1255         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1256                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1257                 /*
1258                  * HW CTF just occurred. Shutdown to prevent further damage.
1259                  */
1260                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1261                 orderly_poweroff(true);
1262         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1263                 if (src_id == 0xfe) {
1264                         /* ACK SMUToHost interrupt */
1265                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1266                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1267                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1268
1269                         switch (ctxid) {
1270                         case 0x3:
1271                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1272                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1273                                 break;
1274                         case 0x4:
1275                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1276                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1277                                 break;
1278                         case 0x7:
1279                                 /*
1280                                  * Increment the throttle interrupt counter
1281                                  */
1282                                 atomic64_inc(&smu->throttle_int_counter);
1283
1284                                 if (!atomic_read(&adev->throttling_logging_enabled))
1285                                         return 0;
1286
1287                                 if (__ratelimit(&adev->throttling_logging_rs))
1288                                         schedule_work(&smu->throttling_logging_work);
1289
1290                                 break;
1291                         }
1292                 }
1293         }
1294
1295         return 0;
1296 }
1297
1298 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1299 {
1300         .set = smu_v13_0_set_irq_state,
1301         .process = smu_v13_0_irq_process,
1302 };
1303
1304 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1305 {
1306         struct amdgpu_device *adev = smu->adev;
1307         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1308         int ret = 0;
1309
1310         irq_src->num_types = 1;
1311         irq_src->funcs = &smu_v13_0_irq_funcs;
1312
1313         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1314                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1315                                 irq_src);
1316         if (ret)
1317                 return ret;
1318
1319         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1320                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1321                                 irq_src);
1322         if (ret)
1323                 return ret;
1324
1325         /* Register CTF(GPIO_19) interrupt */
1326         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1327                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1328                                 irq_src);
1329         if (ret)
1330                 return ret;
1331
1332         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1333                                 0xfe,
1334                                 irq_src);
1335         if (ret)
1336                 return ret;
1337
1338         return ret;
1339 }
1340
1341 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1342                                                struct pp_smu_nv_clock_table *max_clocks)
1343 {
1344         struct smu_table_context *table_context = &smu->smu_table;
1345         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1346
1347         if (!max_clocks || !table_context->max_sustainable_clocks)
1348                 return -EINVAL;
1349
1350         sustainable_clocks = table_context->max_sustainable_clocks;
1351
1352         max_clocks->dcfClockInKhz =
1353                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1354         max_clocks->displayClockInKhz =
1355                 (unsigned int) sustainable_clocks->display_clock * 1000;
1356         max_clocks->phyClockInKhz =
1357                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1358         max_clocks->pixelClockInKhz =
1359                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1360         max_clocks->uClockInKhz =
1361                 (unsigned int) sustainable_clocks->uclock * 1000;
1362         max_clocks->socClockInKhz =
1363                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1364         max_clocks->dscClockInKhz = 0;
1365         max_clocks->dppClockInKhz = 0;
1366         max_clocks->fabricClockInKhz = 0;
1367
1368         return 0;
1369 }
1370
1371 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1372 {
1373         int ret = 0;
1374
1375         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1376
1377         return ret;
1378 }
1379
1380 int smu_v13_0_mode1_reset(struct smu_context *smu)
1381 {
1382         u32 smu_version;
1383         int ret = 0;
1384         /*
1385         * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1386         */
1387         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1388         if (smu_version < 0x00440700)
1389                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1390         else
1391                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1392
1393         if (!ret)
1394                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1395
1396         return ret;
1397 }
1398
1399 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1400                                              uint64_t event_arg)
1401 {
1402         int ret = 0;
1403
1404         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1405         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1406
1407         return ret;
1408 }
1409
1410 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1411                              uint64_t event_arg)
1412 {
1413         int ret = -EINVAL;
1414
1415         switch (event) {
1416         case SMU_EVENT_RESET_COMPLETE:
1417                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1418                 break;
1419         default:
1420                 break;
1421         }
1422
1423         return ret;
1424 }
1425
1426 int smu_v13_0_mode2_reset(struct smu_context *smu)
1427 {
1428         int ret;
1429
1430         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1431                         SMU_RESET_MODE_2, NULL);
1432         /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1433         if (!ret)
1434                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1435
1436         return ret;
1437 }
1438
1439 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1440                                     uint32_t *min, uint32_t *max)
1441 {
1442         int ret = 0, clk_id = 0;
1443         uint32_t param = 0;
1444         uint32_t clock_limit;
1445
1446         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1447                 switch (clk_type) {
1448                 case SMU_MCLK:
1449                 case SMU_UCLK:
1450                         clock_limit = smu->smu_table.boot_values.uclk;
1451                         break;
1452                 case SMU_GFXCLK:
1453                 case SMU_SCLK:
1454                         clock_limit = smu->smu_table.boot_values.gfxclk;
1455                         break;
1456                 case SMU_SOCCLK:
1457                         clock_limit = smu->smu_table.boot_values.socclk;
1458                         break;
1459                 default:
1460                         clock_limit = 0;
1461                         break;
1462                 }
1463
1464                 /* clock in Mhz unit */
1465                 if (min)
1466                         *min = clock_limit / 100;
1467                 if (max)
1468                         *max = clock_limit / 100;
1469
1470                 return 0;
1471         }
1472
1473         clk_id = smu_cmn_to_asic_specific_index(smu,
1474                                                 CMN2ASIC_MAPPING_CLK,
1475                                                 clk_type);
1476         if (clk_id < 0) {
1477                 ret = -EINVAL;
1478                 goto failed;
1479         }
1480         param = (clk_id & 0xffff) << 16;
1481
1482         if (max) {
1483                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1484                 if (ret)
1485                         goto failed;
1486         }
1487
1488         if (min) {
1489                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1490                 if (ret)
1491                         goto failed;
1492         }
1493
1494 failed:
1495         return ret;
1496 }
1497
1498 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1499                                           enum smu_clk_type clk_type,
1500                                           uint32_t min,
1501                                           uint32_t max)
1502 {
1503         struct amdgpu_device *adev = smu->adev;
1504         int ret = 0, clk_id = 0;
1505         uint32_t param;
1506
1507         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1508                 return 0;
1509
1510         clk_id = smu_cmn_to_asic_specific_index(smu,
1511                                                 CMN2ASIC_MAPPING_CLK,
1512                                                 clk_type);
1513         if (clk_id < 0)
1514                 return clk_id;
1515
1516         if (clk_type == SMU_GFXCLK)
1517                 amdgpu_gfx_off_ctrl(adev, false);
1518
1519         if (max > 0) {
1520                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1521                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1522                                                       param, NULL);
1523                 if (ret)
1524                         goto out;
1525         }
1526
1527         if (min > 0) {
1528                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1529                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1530                                                       param, NULL);
1531                 if (ret)
1532                         goto out;
1533         }
1534
1535 out:
1536         if (clk_type == SMU_GFXCLK)
1537                 amdgpu_gfx_off_ctrl(adev, true);
1538
1539         return ret;
1540 }
1541
1542 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1543                                           enum smu_clk_type clk_type,
1544                                           uint32_t min,
1545                                           uint32_t max)
1546 {
1547         int ret = 0, clk_id = 0;
1548         uint32_t param;
1549
1550         if (min <= 0 && max <= 0)
1551                 return -EINVAL;
1552
1553         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1554                 return 0;
1555
1556         clk_id = smu_cmn_to_asic_specific_index(smu,
1557                                                 CMN2ASIC_MAPPING_CLK,
1558                                                 clk_type);
1559         if (clk_id < 0)
1560                 return clk_id;
1561
1562         if (max > 0) {
1563                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1564                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1565                                                       param, NULL);
1566                 if (ret)
1567                         return ret;
1568         }
1569
1570         if (min > 0) {
1571                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1572                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1573                                                       param, NULL);
1574                 if (ret)
1575                         return ret;
1576         }
1577
1578         return ret;
1579 }
1580
1581 int smu_v13_0_set_performance_level(struct smu_context *smu,
1582                                     enum amd_dpm_forced_level level)
1583 {
1584         struct smu_13_0_dpm_context *dpm_context =
1585                 smu->smu_dpm.dpm_context;
1586         struct smu_13_0_dpm_table *gfx_table =
1587                 &dpm_context->dpm_tables.gfx_table;
1588         struct smu_13_0_dpm_table *mem_table =
1589                 &dpm_context->dpm_tables.uclk_table;
1590         struct smu_13_0_dpm_table *soc_table =
1591                 &dpm_context->dpm_tables.soc_table;
1592         struct smu_umd_pstate_table *pstate_table =
1593                 &smu->pstate_table;
1594         struct amdgpu_device *adev = smu->adev;
1595         uint32_t sclk_min = 0, sclk_max = 0;
1596         uint32_t mclk_min = 0, mclk_max = 0;
1597         uint32_t socclk_min = 0, socclk_max = 0;
1598         int ret = 0;
1599
1600         switch (level) {
1601         case AMD_DPM_FORCED_LEVEL_HIGH:
1602                 sclk_min = sclk_max = gfx_table->max;
1603                 mclk_min = mclk_max = mem_table->max;
1604                 socclk_min = socclk_max = soc_table->max;
1605                 break;
1606         case AMD_DPM_FORCED_LEVEL_LOW:
1607                 sclk_min = sclk_max = gfx_table->min;
1608                 mclk_min = mclk_max = mem_table->min;
1609                 socclk_min = socclk_max = soc_table->min;
1610                 break;
1611         case AMD_DPM_FORCED_LEVEL_AUTO:
1612                 sclk_min = gfx_table->min;
1613                 sclk_max = gfx_table->max;
1614                 mclk_min = mem_table->min;
1615                 mclk_max = mem_table->max;
1616                 socclk_min = soc_table->min;
1617                 socclk_max = soc_table->max;
1618                 break;
1619         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1620                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1621                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1622                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1623                 break;
1624         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1625                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1626                 break;
1627         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1628                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1629                 break;
1630         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1631                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1632                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1633                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1634                 break;
1635         case AMD_DPM_FORCED_LEVEL_MANUAL:
1636         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1637                 return 0;
1638         default:
1639                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1640                 return -EINVAL;
1641         }
1642
1643         mclk_min = mclk_max = 0;
1644         socclk_min = socclk_max = 0;
1645
1646         if (sclk_min && sclk_max) {
1647                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1648                                                             SMU_GFXCLK,
1649                                                             sclk_min,
1650                                                             sclk_max);
1651                 if (ret)
1652                         return ret;
1653
1654                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1655                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1656         }
1657
1658         if (mclk_min && mclk_max) {
1659                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1660                                                             SMU_MCLK,
1661                                                             mclk_min,
1662                                                             mclk_max);
1663                 if (ret)
1664                         return ret;
1665
1666                 pstate_table->uclk_pstate.curr.min = mclk_min;
1667                 pstate_table->uclk_pstate.curr.max = mclk_max;
1668         }
1669
1670         if (socclk_min && socclk_max) {
1671                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1672                                                             SMU_SOCCLK,
1673                                                             socclk_min,
1674                                                             socclk_max);
1675                 if (ret)
1676                         return ret;
1677
1678                 pstate_table->socclk_pstate.curr.min = socclk_min;
1679                 pstate_table->socclk_pstate.curr.max = socclk_max;
1680         }
1681
1682         return ret;
1683 }
1684
1685 int smu_v13_0_set_power_source(struct smu_context *smu,
1686                                enum smu_power_src_type power_src)
1687 {
1688         int pwr_source;
1689
1690         pwr_source = smu_cmn_to_asic_specific_index(smu,
1691                                                     CMN2ASIC_MAPPING_PWR,
1692                                                     (uint32_t)power_src);
1693         if (pwr_source < 0)
1694                 return -EINVAL;
1695
1696         return smu_cmn_send_smc_msg_with_param(smu,
1697                                                SMU_MSG_NotifyPowerSource,
1698                                                pwr_source,
1699                                                NULL);
1700 }
1701
1702 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1703                                     enum smu_clk_type clk_type,
1704                                     uint16_t level,
1705                                     uint32_t *value)
1706 {
1707         int ret = 0, clk_id = 0;
1708         uint32_t param;
1709
1710         if (!value)
1711                 return -EINVAL;
1712
1713         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1714                 return 0;
1715
1716         clk_id = smu_cmn_to_asic_specific_index(smu,
1717                                                 CMN2ASIC_MAPPING_CLK,
1718                                                 clk_type);
1719         if (clk_id < 0)
1720                 return clk_id;
1721
1722         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1723
1724         ret = smu_cmn_send_smc_msg_with_param(smu,
1725                                               SMU_MSG_GetDpmFreqByIndex,
1726                                               param,
1727                                               value);
1728         if (ret)
1729                 return ret;
1730
1731         /*
1732          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1733          * now, we un-support it
1734          */
1735         *value = *value & 0x7fffffff;
1736
1737         return ret;
1738 }
1739
1740 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1741                                   enum smu_clk_type clk_type,
1742                                   uint32_t *value)
1743 {
1744         int ret;
1745
1746         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1747         /* FW returns 0 based max level, increment by one */
1748         if (!ret && value)
1749                 ++(*value);
1750
1751         return ret;
1752 }
1753
1754 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1755                                    enum smu_clk_type clk_type,
1756                                    struct smu_13_0_dpm_table *single_dpm_table)
1757 {
1758         int ret = 0;
1759         uint32_t clk;
1760         int i;
1761
1762         ret = smu_v13_0_get_dpm_level_count(smu,
1763                                             clk_type,
1764                                             &single_dpm_table->count);
1765         if (ret) {
1766                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1767                 return ret;
1768         }
1769
1770         for (i = 0; i < single_dpm_table->count; i++) {
1771                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1772                                                       clk_type,
1773                                                       i,
1774                                                       &clk);
1775                 if (ret) {
1776                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1777                         return ret;
1778                 }
1779
1780                 single_dpm_table->dpm_levels[i].value = clk;
1781                 single_dpm_table->dpm_levels[i].enabled = true;
1782
1783                 if (i == 0)
1784                         single_dpm_table->min = clk;
1785                 else if (i == single_dpm_table->count - 1)
1786                         single_dpm_table->max = clk;
1787         }
1788
1789         return 0;
1790 }
1791
1792 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1793                                   enum smu_clk_type clk_type,
1794                                   uint32_t *min_value,
1795                                   uint32_t *max_value)
1796 {
1797         uint32_t level_count = 0;
1798         int ret = 0;
1799
1800         if (!min_value && !max_value)
1801                 return -EINVAL;
1802
1803         if (min_value) {
1804                 /* by default, level 0 clock value as min value */
1805                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1806                                                       clk_type,
1807                                                       0,
1808                                                       min_value);
1809                 if (ret)
1810                         return ret;
1811         }
1812
1813         if (max_value) {
1814                 ret = smu_v13_0_get_dpm_level_count(smu,
1815                                                     clk_type,
1816                                                     &level_count);
1817                 if (ret)
1818                         return ret;
1819
1820                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1821                                                       clk_type,
1822                                                       level_count - 1,
1823                                                       max_value);
1824                 if (ret)
1825                         return ret;
1826         }
1827
1828         return ret;
1829 }
1830
1831 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1832 {
1833         struct amdgpu_device *adev = smu->adev;
1834
1835         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1836                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1837                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1838 }
1839
1840 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1841 {
1842         uint32_t width_level;
1843
1844         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1845         if (width_level > LINK_WIDTH_MAX)
1846                 width_level = 0;
1847
1848         return link_width[width_level];
1849 }
1850
1851 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1852 {
1853         struct amdgpu_device *adev = smu->adev;
1854
1855         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1856                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1857                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1858 }
1859
1860 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1861 {
1862         uint32_t speed_level;
1863
1864         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1865         if (speed_level > LINK_SPEED_MAX)
1866                 speed_level = 0;
1867
1868         return link_speed[speed_level];
1869 }
1870