2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
61 #define SMU13_VOLTAGE_SCALE 4
63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
65 #define LINK_WIDTH_MAX 6
66 #define LINK_SPEED_MAX 3
68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71 #define smnPCIE_LC_SPEED_CNTL 0x11140290
72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76 static const int link_speed[] = {25, 50, 80, 160};
78 int smu_v13_0_init_microcode(struct smu_context *smu)
80 struct amdgpu_device *adev = smu->adev;
81 const char *chip_name;
84 const struct smc_firmware_header_v1_0 *hdr;
85 const struct common_firmware_header *header;
86 struct amdgpu_firmware_info *ucode = NULL;
88 switch (adev->asic_type) {
90 chip_name = "aldebaran";
93 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
97 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
99 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
102 err = amdgpu_ucode_validate(adev->pm.fw);
106 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
107 amdgpu_ucode_print_smc_hdr(&hdr->header);
108 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
110 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
111 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
112 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
113 ucode->fw = adev->pm.fw;
114 header = (const struct common_firmware_header *)ucode->fw->data;
115 adev->firmware.fw_size +=
116 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
121 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
123 release_firmware(adev->pm.fw);
129 void smu_v13_0_fini_microcode(struct smu_context *smu)
131 struct amdgpu_device *adev = smu->adev;
133 release_firmware(adev->pm.fw);
135 adev->pm.fw_version = 0;
138 int smu_v13_0_load_microcode(struct smu_context *smu)
141 struct amdgpu_device *adev = smu->adev;
143 const struct smc_firmware_header_v1_0 *hdr;
144 uint32_t addr_start = MP1_SRAM;
146 uint32_t smc_fw_size;
147 uint32_t mp1_fw_flags;
149 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
150 src = (const uint32_t *)(adev->pm.fw->data +
151 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
152 smc_fw_size = hdr->header.ucode_size_bytes;
154 for (i = 1; i < smc_fw_size/4 - 1; i++) {
155 WREG32_PCIE(addr_start, src[i]);
159 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
160 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
162 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
164 for (i = 0; i < adev->usec_timeout; i++) {
165 mp1_fw_flags = RREG32_PCIE(MP1_Public |
166 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
167 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
168 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
173 if (i == adev->usec_timeout)
179 int smu_v13_0_check_fw_status(struct smu_context *smu)
181 struct amdgpu_device *adev = smu->adev;
182 uint32_t mp1_fw_flags;
184 mp1_fw_flags = RREG32_PCIE(MP1_Public |
185 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
187 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
188 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
194 int smu_v13_0_check_fw_version(struct smu_context *smu)
196 uint32_t if_version = 0xff, smu_version = 0xff;
198 uint8_t smu_minor, smu_debug;
201 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
205 smu_major = (smu_version >> 16) & 0xffff;
206 smu_minor = (smu_version >> 8) & 0xff;
207 smu_debug = (smu_version >> 0) & 0xff;
209 switch (smu->adev->asic_type) {
211 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
213 case CHIP_YELLOW_CARP:
214 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
217 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
218 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
222 dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
223 smu_version, smu_major, smu_minor, smu_debug);
226 * 1. if_version mismatch is not critical as our fw is designed
227 * to be backward compatible.
228 * 2. New fw usually brings some optimizations. But that's visible
229 * only on the paired driver.
230 * Considering above, we just leave user a warning message instead
231 * of halt driver loading.
233 if (if_version != smu->smc_driver_if_version) {
234 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
235 "smu fw version = 0x%08x (%d.%d.%d)\n",
236 smu->smc_driver_if_version, if_version,
237 smu_version, smu_major, smu_minor, smu_debug);
238 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
244 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
245 uint32_t *size, uint32_t pptable_id)
247 struct amdgpu_device *adev = smu->adev;
248 const struct smc_firmware_header_v2_1 *v2_1;
249 struct smc_soft_pptable_entry *entries;
250 uint32_t pptable_count = 0;
253 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
254 entries = (struct smc_soft_pptable_entry *)
255 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
256 pptable_count = le32_to_cpu(v2_1->pptable_count);
257 for (i = 0; i < pptable_count; i++) {
258 if (le32_to_cpu(entries[i].id) == pptable_id) {
259 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
260 *size = le32_to_cpu(entries[i].ppt_size_bytes);
265 if (i == pptable_count)
271 int smu_v13_0_setup_pptable(struct smu_context *smu)
273 struct amdgpu_device *adev = smu->adev;
274 const struct smc_firmware_header_v1_0 *hdr;
277 uint16_t atom_table_size;
280 uint16_t version_major, version_minor;
283 if (amdgpu_smu_pptable_id >= 0) {
284 smu->smu_table.boot_values.pp_table_id = amdgpu_smu_pptable_id;
285 dev_info(adev->dev, "override pptable id %d\n", amdgpu_smu_pptable_id);
288 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
289 version_major = le16_to_cpu(hdr->header.header_version_major);
290 version_minor = le16_to_cpu(hdr->header.header_version_minor);
291 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
292 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
293 switch (version_minor) {
295 ret = smu_v13_0_set_pptable_v2_1(smu, &table, &size,
296 smu->smu_table.boot_values.pp_table_id);
306 dev_info(adev->dev, "use vbios provided pptable\n");
307 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
310 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
314 size = atom_table_size;
317 if (!smu->smu_table.power_play_table)
318 smu->smu_table.power_play_table = table;
319 if (!smu->smu_table.power_play_table_size)
320 smu->smu_table.power_play_table_size = size;
325 int smu_v13_0_init_smc_tables(struct smu_context *smu)
327 struct smu_table_context *smu_table = &smu->smu_table;
328 struct smu_table *tables = smu_table->tables;
331 smu_table->driver_pptable =
332 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
333 if (!smu_table->driver_pptable) {
338 smu_table->max_sustainable_clocks =
339 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
340 if (!smu_table->max_sustainable_clocks) {
345 /* Aldebaran does not support OVERDRIVE */
346 if (tables[SMU_TABLE_OVERDRIVE].size) {
347 smu_table->overdrive_table =
348 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
349 if (!smu_table->overdrive_table) {
354 smu_table->boot_overdrive_table =
355 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
356 if (!smu_table->boot_overdrive_table) {
365 kfree(smu_table->overdrive_table);
367 kfree(smu_table->max_sustainable_clocks);
369 kfree(smu_table->driver_pptable);
374 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
376 struct smu_table_context *smu_table = &smu->smu_table;
377 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
379 kfree(smu_table->gpu_metrics_table);
380 kfree(smu_table->boot_overdrive_table);
381 kfree(smu_table->overdrive_table);
382 kfree(smu_table->max_sustainable_clocks);
383 kfree(smu_table->driver_pptable);
384 smu_table->gpu_metrics_table = NULL;
385 smu_table->boot_overdrive_table = NULL;
386 smu_table->overdrive_table = NULL;
387 smu_table->max_sustainable_clocks = NULL;
388 smu_table->driver_pptable = NULL;
389 kfree(smu_table->hardcode_pptable);
390 smu_table->hardcode_pptable = NULL;
392 kfree(smu_table->metrics_table);
393 kfree(smu_table->watermarks_table);
394 smu_table->metrics_table = NULL;
395 smu_table->watermarks_table = NULL;
396 smu_table->metrics_time = 0;
398 kfree(smu_dpm->dpm_context);
399 kfree(smu_dpm->golden_dpm_context);
400 kfree(smu_dpm->dpm_current_power_state);
401 kfree(smu_dpm->dpm_request_power_state);
402 smu_dpm->dpm_context = NULL;
403 smu_dpm->golden_dpm_context = NULL;
404 smu_dpm->dpm_context_size = 0;
405 smu_dpm->dpm_current_power_state = NULL;
406 smu_dpm->dpm_request_power_state = NULL;
411 int smu_v13_0_init_power(struct smu_context *smu)
413 struct smu_power_context *smu_power = &smu->smu_power;
415 if (smu_power->power_context || smu_power->power_context_size != 0)
418 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
420 if (!smu_power->power_context)
422 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
427 int smu_v13_0_fini_power(struct smu_context *smu)
429 struct smu_power_context *smu_power = &smu->smu_power;
431 if (!smu_power->power_context || smu_power->power_context_size == 0)
434 kfree(smu_power->power_context);
435 smu_power->power_context = NULL;
436 smu_power->power_context_size = 0;
441 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
446 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
447 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
450 input.clk_id = clk_id;
451 input.syspll_id = syspll_id;
452 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
453 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
456 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
461 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
462 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
467 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
472 struct atom_common_table_header *header;
473 struct atom_firmware_info_v3_4 *v_3_4;
474 struct atom_firmware_info_v3_3 *v_3_3;
475 struct atom_firmware_info_v3_1 *v_3_1;
477 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
480 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
481 (uint8_t **)&header);
485 if (header->format_revision != 3) {
486 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
490 switch (header->content_revision) {
494 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
495 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
496 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
497 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
498 smu->smu_table.boot_values.socclk = 0;
499 smu->smu_table.boot_values.dcefclk = 0;
500 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
501 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
502 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
503 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
504 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
505 smu->smu_table.boot_values.pp_table_id = 0;
508 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
509 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
510 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
511 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
512 smu->smu_table.boot_values.socclk = 0;
513 smu->smu_table.boot_values.dcefclk = 0;
514 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
515 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
516 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
517 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
518 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
519 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
523 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
524 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
525 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
526 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
527 smu->smu_table.boot_values.socclk = 0;
528 smu->smu_table.boot_values.dcefclk = 0;
529 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
530 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
531 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
532 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
533 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
534 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
538 smu->smu_table.boot_values.format_revision = header->format_revision;
539 smu->smu_table.boot_values.content_revision = header->content_revision;
541 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
542 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
544 &smu->smu_table.boot_values.socclk);
546 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
547 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
549 &smu->smu_table.boot_values.dcefclk);
551 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
552 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
554 &smu->smu_table.boot_values.eclk);
556 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
557 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
559 &smu->smu_table.boot_values.vclk);
561 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
562 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
564 &smu->smu_table.boot_values.dclk);
566 if ((smu->smu_table.boot_values.format_revision == 3) &&
567 (smu->smu_table.boot_values.content_revision >= 2))
568 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
569 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
570 (uint8_t)SMU11_SYSPLL1_2_ID,
571 &smu->smu_table.boot_values.fclk);
577 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
579 struct smu_table_context *smu_table = &smu->smu_table;
580 struct smu_table *memory_pool = &smu_table->memory_pool;
583 uint32_t address_low, address_high;
585 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
588 address = memory_pool->mc_address;
589 address_high = (uint32_t)upper_32_bits(address);
590 address_low = (uint32_t)lower_32_bits(address);
592 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
596 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
600 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
601 (uint32_t)memory_pool->size, NULL);
608 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
612 ret = smu_cmn_send_smc_msg_with_param(smu,
613 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
615 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
620 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
622 struct smu_table *driver_table = &smu->smu_table.driver_table;
625 if (driver_table->mc_address) {
626 ret = smu_cmn_send_smc_msg_with_param(smu,
627 SMU_MSG_SetDriverDramAddrHigh,
628 upper_32_bits(driver_table->mc_address),
631 ret = smu_cmn_send_smc_msg_with_param(smu,
632 SMU_MSG_SetDriverDramAddrLow,
633 lower_32_bits(driver_table->mc_address),
640 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
643 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
645 if (tool_table->mc_address) {
646 ret = smu_cmn_send_smc_msg_with_param(smu,
647 SMU_MSG_SetToolsDramAddrHigh,
648 upper_32_bits(tool_table->mc_address),
651 ret = smu_cmn_send_smc_msg_with_param(smu,
652 SMU_MSG_SetToolsDramAddrLow,
653 lower_32_bits(tool_table->mc_address),
660 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
664 if (!smu->pm_enabled)
667 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
673 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
675 struct smu_feature *feature = &smu->smu_feature;
677 uint32_t feature_mask[2];
679 mutex_lock(&feature->mutex);
680 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
683 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
685 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
686 feature_mask[1], NULL);
690 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
691 feature_mask[0], NULL);
696 mutex_unlock(&feature->mutex);
700 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
703 struct amdgpu_device *adev = smu->adev;
705 switch (adev->asic_type) {
706 case CHIP_YELLOW_CARP:
707 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
710 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
712 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
721 int smu_v13_0_system_features_control(struct smu_context *smu,
724 struct smu_feature *feature = &smu->smu_feature;
725 uint32_t feature_mask[2];
728 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
729 SMU_MSG_DisableAllSmuFeatures), NULL);
733 bitmap_zero(feature->enabled, feature->feature_num);
734 bitmap_zero(feature->supported, feature->feature_num);
737 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
741 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
742 feature->feature_num);
743 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
744 feature->feature_num);
750 int smu_v13_0_notify_display_change(struct smu_context *smu)
754 if (!smu->pm_enabled)
757 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
758 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
759 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
765 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
766 enum smu_clk_type clock_select)
771 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
772 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
775 clk_id = smu_cmn_to_asic_specific_index(smu,
776 CMN2ASIC_MAPPING_CLK,
781 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
782 clk_id << 16, clock);
784 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
791 /* if DC limit is zero, return AC limit */
792 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
793 clk_id << 16, clock);
795 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
802 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
804 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
805 smu->smu_table.max_sustainable_clocks;
808 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
809 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
810 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
811 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
812 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
813 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
815 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
816 ret = smu_v13_0_get_max_sustainable_clock(smu,
817 &(max_sustainable_clocks->uclock),
820 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
826 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
827 ret = smu_v13_0_get_max_sustainable_clock(smu,
828 &(max_sustainable_clocks->soc_clock),
831 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
837 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
838 ret = smu_v13_0_get_max_sustainable_clock(smu,
839 &(max_sustainable_clocks->dcef_clock),
842 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
847 ret = smu_v13_0_get_max_sustainable_clock(smu,
848 &(max_sustainable_clocks->display_clock),
851 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
855 ret = smu_v13_0_get_max_sustainable_clock(smu,
856 &(max_sustainable_clocks->phy_clock),
859 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
863 ret = smu_v13_0_get_max_sustainable_clock(smu,
864 &(max_sustainable_clocks->pixel_clock),
867 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
873 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
874 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
879 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
880 uint32_t *power_limit)
885 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
888 power_src = smu_cmn_to_asic_specific_index(smu,
889 CMN2ASIC_MAPPING_PWR,
890 smu->adev->pm.ac_power ?
891 SMU_POWER_SOURCE_AC :
892 SMU_POWER_SOURCE_DC);
896 ret = smu_cmn_send_smc_msg_with_param(smu,
901 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
906 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
910 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
911 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
915 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
917 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
921 smu->current_power_limit = n;
926 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
928 if (smu->smu_table.thermal_controller_type)
929 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
934 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
936 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
939 static uint16_t convert_to_vddc(uint8_t vid)
941 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
944 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
946 struct amdgpu_device *adev = smu->adev;
947 uint32_t vdd = 0, val_vid = 0;
951 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
952 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
953 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
955 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
964 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
965 struct pp_display_clock_request
968 enum amd_pp_clock_type clk_type = clock_req->clock_type;
970 enum smu_clk_type clk_select = 0;
971 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
973 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
974 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
976 case amd_pp_dcef_clock:
977 clk_select = SMU_DCEFCLK;
979 case amd_pp_disp_clock:
980 clk_select = SMU_DISPCLK;
982 case amd_pp_pixel_clock:
983 clk_select = SMU_PIXCLK;
985 case amd_pp_phy_clock:
986 clk_select = SMU_PHYCLK;
988 case amd_pp_mem_clock:
989 clk_select = SMU_UCLK;
992 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1000 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1003 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1005 if(clk_select == SMU_UCLK)
1006 smu->hard_min_uclk_req_from_dal = clk_freq;
1013 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1015 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1016 return AMD_FAN_CTRL_MANUAL;
1018 return AMD_FAN_CTRL_AUTO;
1022 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1026 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1029 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1031 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1032 __func__, (auto_fan_control ? "Start" : "Stop"));
1038 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1040 struct amdgpu_device *adev = smu->adev;
1042 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1043 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1044 CG_FDO_CTRL2, TMIN, 0));
1045 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1046 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1047 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1053 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1055 struct amdgpu_device *adev = smu->adev;
1056 uint32_t duty100, duty;
1062 if (smu_v13_0_auto_fan_control(smu, 0))
1065 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1066 CG_FDO_CTRL1, FMAX_DUTY100);
1070 tmp64 = (uint64_t)speed * duty100;
1072 duty = (uint32_t)tmp64;
1074 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1075 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1076 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1078 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1082 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1088 case AMD_FAN_CTRL_NONE:
1089 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1091 case AMD_FAN_CTRL_MANUAL:
1092 ret = smu_v13_0_auto_fan_control(smu, 0);
1094 case AMD_FAN_CTRL_AUTO:
1095 ret = smu_v13_0_auto_fan_control(smu, 1);
1102 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1109 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1112 struct amdgpu_device *adev = smu->adev;
1114 uint32_t tach_period, crystal_clock_freq;
1119 ret = smu_v13_0_auto_fan_control(smu, 0);
1123 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1124 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1125 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1126 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1127 CG_TACH_CTRL, TARGET_PERIOD,
1130 ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1135 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1139 ret = smu_cmn_send_smc_msg_with_param(smu,
1140 SMU_MSG_SetXgmiMode,
1141 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1146 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1147 struct amdgpu_irq_src *source,
1149 enum amdgpu_interrupt_state state)
1151 struct smu_context *smu = &adev->smu;
1156 case AMDGPU_IRQ_STATE_DISABLE:
1158 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1159 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1160 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1161 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1163 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1165 /* For MP1 SW irqs */
1166 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1167 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1168 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1171 case AMDGPU_IRQ_STATE_ENABLE:
1173 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1174 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1175 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1176 smu->thermal_range.software_shutdown_temp);
1178 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1179 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1180 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1181 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1182 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1183 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1184 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1185 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1186 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1188 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1189 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1190 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1191 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1193 /* For MP1 SW irqs */
1194 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1195 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1196 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1197 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1199 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1200 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1201 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1211 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1213 return smu_cmn_send_smc_msg(smu,
1214 SMU_MSG_ReenableAcDcInterrupt,
1218 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1219 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1220 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1222 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1223 struct amdgpu_irq_src *source,
1224 struct amdgpu_iv_entry *entry)
1226 struct smu_context *smu = &adev->smu;
1227 uint32_t client_id = entry->client_id;
1228 uint32_t src_id = entry->src_id;
1230 * ctxid is used to distinguish different
1231 * events for SMCToHost interrupt.
1233 uint32_t ctxid = entry->src_data[0];
1236 if (client_id == SOC15_IH_CLIENTID_THM) {
1238 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1239 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1241 * SW CTF just occurred.
1242 * Try to do a graceful shutdown to prevent further damage.
1244 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1245 orderly_poweroff(true);
1247 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1248 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1251 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1255 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1256 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1258 * HW CTF just occurred. Shutdown to prevent further damage.
1260 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1261 orderly_poweroff(true);
1262 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1263 if (src_id == 0xfe) {
1264 /* ACK SMUToHost interrupt */
1265 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1266 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1267 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1271 dev_dbg(adev->dev, "Switched to AC mode!\n");
1272 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1275 dev_dbg(adev->dev, "Switched to DC mode!\n");
1276 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1280 * Increment the throttle interrupt counter
1282 atomic64_inc(&smu->throttle_int_counter);
1284 if (!atomic_read(&adev->throttling_logging_enabled))
1287 if (__ratelimit(&adev->throttling_logging_rs))
1288 schedule_work(&smu->throttling_logging_work);
1298 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1300 .set = smu_v13_0_set_irq_state,
1301 .process = smu_v13_0_irq_process,
1304 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1306 struct amdgpu_device *adev = smu->adev;
1307 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1310 irq_src->num_types = 1;
1311 irq_src->funcs = &smu_v13_0_irq_funcs;
1313 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1314 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1319 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1320 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1325 /* Register CTF(GPIO_19) interrupt */
1326 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1327 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1332 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1341 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1342 struct pp_smu_nv_clock_table *max_clocks)
1344 struct smu_table_context *table_context = &smu->smu_table;
1345 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1347 if (!max_clocks || !table_context->max_sustainable_clocks)
1350 sustainable_clocks = table_context->max_sustainable_clocks;
1352 max_clocks->dcfClockInKhz =
1353 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1354 max_clocks->displayClockInKhz =
1355 (unsigned int) sustainable_clocks->display_clock * 1000;
1356 max_clocks->phyClockInKhz =
1357 (unsigned int) sustainable_clocks->phy_clock * 1000;
1358 max_clocks->pixelClockInKhz =
1359 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1360 max_clocks->uClockInKhz =
1361 (unsigned int) sustainable_clocks->uclock * 1000;
1362 max_clocks->socClockInKhz =
1363 (unsigned int) sustainable_clocks->soc_clock * 1000;
1364 max_clocks->dscClockInKhz = 0;
1365 max_clocks->dppClockInKhz = 0;
1366 max_clocks->fabricClockInKhz = 0;
1371 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1375 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1380 int smu_v13_0_mode1_reset(struct smu_context *smu)
1385 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1387 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1388 if (smu_version < 0x00440700)
1389 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1391 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1394 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1399 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1404 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1405 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1410 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1416 case SMU_EVENT_RESET_COMPLETE:
1417 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1426 int smu_v13_0_mode2_reset(struct smu_context *smu)
1430 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1431 SMU_RESET_MODE_2, NULL);
1432 /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1434 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1439 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1440 uint32_t *min, uint32_t *max)
1442 int ret = 0, clk_id = 0;
1444 uint32_t clock_limit;
1446 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1450 clock_limit = smu->smu_table.boot_values.uclk;
1454 clock_limit = smu->smu_table.boot_values.gfxclk;
1457 clock_limit = smu->smu_table.boot_values.socclk;
1464 /* clock in Mhz unit */
1466 *min = clock_limit / 100;
1468 *max = clock_limit / 100;
1473 clk_id = smu_cmn_to_asic_specific_index(smu,
1474 CMN2ASIC_MAPPING_CLK,
1480 param = (clk_id & 0xffff) << 16;
1483 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1498 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1499 enum smu_clk_type clk_type,
1503 struct amdgpu_device *adev = smu->adev;
1504 int ret = 0, clk_id = 0;
1507 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1510 clk_id = smu_cmn_to_asic_specific_index(smu,
1511 CMN2ASIC_MAPPING_CLK,
1516 if (clk_type == SMU_GFXCLK)
1517 amdgpu_gfx_off_ctrl(adev, false);
1520 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1521 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1528 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1529 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1536 if (clk_type == SMU_GFXCLK)
1537 amdgpu_gfx_off_ctrl(adev, true);
1542 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1543 enum smu_clk_type clk_type,
1547 int ret = 0, clk_id = 0;
1550 if (min <= 0 && max <= 0)
1553 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1556 clk_id = smu_cmn_to_asic_specific_index(smu,
1557 CMN2ASIC_MAPPING_CLK,
1563 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1564 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1571 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1572 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1581 int smu_v13_0_set_performance_level(struct smu_context *smu,
1582 enum amd_dpm_forced_level level)
1584 struct smu_13_0_dpm_context *dpm_context =
1585 smu->smu_dpm.dpm_context;
1586 struct smu_13_0_dpm_table *gfx_table =
1587 &dpm_context->dpm_tables.gfx_table;
1588 struct smu_13_0_dpm_table *mem_table =
1589 &dpm_context->dpm_tables.uclk_table;
1590 struct smu_13_0_dpm_table *soc_table =
1591 &dpm_context->dpm_tables.soc_table;
1592 struct smu_umd_pstate_table *pstate_table =
1594 struct amdgpu_device *adev = smu->adev;
1595 uint32_t sclk_min = 0, sclk_max = 0;
1596 uint32_t mclk_min = 0, mclk_max = 0;
1597 uint32_t socclk_min = 0, socclk_max = 0;
1601 case AMD_DPM_FORCED_LEVEL_HIGH:
1602 sclk_min = sclk_max = gfx_table->max;
1603 mclk_min = mclk_max = mem_table->max;
1604 socclk_min = socclk_max = soc_table->max;
1606 case AMD_DPM_FORCED_LEVEL_LOW:
1607 sclk_min = sclk_max = gfx_table->min;
1608 mclk_min = mclk_max = mem_table->min;
1609 socclk_min = socclk_max = soc_table->min;
1611 case AMD_DPM_FORCED_LEVEL_AUTO:
1612 sclk_min = gfx_table->min;
1613 sclk_max = gfx_table->max;
1614 mclk_min = mem_table->min;
1615 mclk_max = mem_table->max;
1616 socclk_min = soc_table->min;
1617 socclk_max = soc_table->max;
1619 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1620 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1621 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1622 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1624 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1625 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1627 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1628 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1630 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1631 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1632 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1633 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1635 case AMD_DPM_FORCED_LEVEL_MANUAL:
1636 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1639 dev_err(adev->dev, "Invalid performance level %d\n", level);
1643 mclk_min = mclk_max = 0;
1644 socclk_min = socclk_max = 0;
1646 if (sclk_min && sclk_max) {
1647 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1654 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1655 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1658 if (mclk_min && mclk_max) {
1659 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1666 pstate_table->uclk_pstate.curr.min = mclk_min;
1667 pstate_table->uclk_pstate.curr.max = mclk_max;
1670 if (socclk_min && socclk_max) {
1671 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1678 pstate_table->socclk_pstate.curr.min = socclk_min;
1679 pstate_table->socclk_pstate.curr.max = socclk_max;
1685 int smu_v13_0_set_power_source(struct smu_context *smu,
1686 enum smu_power_src_type power_src)
1690 pwr_source = smu_cmn_to_asic_specific_index(smu,
1691 CMN2ASIC_MAPPING_PWR,
1692 (uint32_t)power_src);
1696 return smu_cmn_send_smc_msg_with_param(smu,
1697 SMU_MSG_NotifyPowerSource,
1702 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1703 enum smu_clk_type clk_type,
1707 int ret = 0, clk_id = 0;
1713 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1716 clk_id = smu_cmn_to_asic_specific_index(smu,
1717 CMN2ASIC_MAPPING_CLK,
1722 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1724 ret = smu_cmn_send_smc_msg_with_param(smu,
1725 SMU_MSG_GetDpmFreqByIndex,
1732 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1733 * now, we un-support it
1735 *value = *value & 0x7fffffff;
1740 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1741 enum smu_clk_type clk_type,
1746 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1747 /* FW returns 0 based max level, increment by one */
1754 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1755 enum smu_clk_type clk_type,
1756 struct smu_13_0_dpm_table *single_dpm_table)
1762 ret = smu_v13_0_get_dpm_level_count(smu,
1764 &single_dpm_table->count);
1766 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1770 for (i = 0; i < single_dpm_table->count; i++) {
1771 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1776 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1780 single_dpm_table->dpm_levels[i].value = clk;
1781 single_dpm_table->dpm_levels[i].enabled = true;
1784 single_dpm_table->min = clk;
1785 else if (i == single_dpm_table->count - 1)
1786 single_dpm_table->max = clk;
1792 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1793 enum smu_clk_type clk_type,
1794 uint32_t *min_value,
1795 uint32_t *max_value)
1797 uint32_t level_count = 0;
1800 if (!min_value && !max_value)
1804 /* by default, level 0 clock value as min value */
1805 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1814 ret = smu_v13_0_get_dpm_level_count(smu,
1820 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1831 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1833 struct amdgpu_device *adev = smu->adev;
1835 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1836 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1837 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1840 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1842 uint32_t width_level;
1844 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1845 if (width_level > LINK_WIDTH_MAX)
1848 return link_width[width_level];
1851 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1853 struct amdgpu_device *adev = smu->adev;
1855 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1856 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1857 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1860 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1862 uint32_t speed_level;
1864 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1865 if (speed_level > LINK_SPEED_MAX)
1868 return link_speed[speed_level];