drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60
  61 #define SMU13_VOLTAGE_SCALE 4
  62
  63 #define LINK_WIDTH_MAX                          6
  64 #define LINK_SPEED_MAX                          3
  65
  66 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  67 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  68 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  69 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  70 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  71 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  72
  73 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  74 static const int link_speed[] = {25, 50, 80, 160};
  75
  76 int smu_v13_0_init_microcode(struct smu_context *smu)
  77 {
  78         struct amdgpu_device *adev = smu->adev;
  79         const char *chip_name;
  80         char fw_name[30];
  81         int err = 0;
  82         const struct smc_firmware_header_v1_0 *hdr;
  83         const struct common_firmware_header *header;
  84         struct amdgpu_firmware_info *ucode = NULL;
  85
  86         /* doesn't need to load smu firmware in IOV mode */
  87         if (amdgpu_sriov_vf(adev))
  88                 return 0;
  89
  90         switch (adev->ip_versions[MP1_HWIP][0]) {
  91         case IP_VERSION(13, 0, 2):
  92                 chip_name = "aldebaran";
  93                 break;
  94         default:
  95                 dev_err(adev->dev, "Unsupported IP version 0x%x\n",
  96                         adev->ip_versions[MP1_HWIP][0]);
  97                 return -EINVAL;
  98         }
  99
 100         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 101
 102         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 103         if (err)
 104                 goto out;
 105         err = amdgpu_ucode_validate(adev->pm.fw);
 106         if (err)
 107                 goto out;
 108
 109         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 110         amdgpu_ucode_print_smc_hdr(&hdr->header);
 111         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 112
 113         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 114                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 115                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 116                 ucode->fw = adev->pm.fw;
 117                 header = (const struct common_firmware_header *)ucode->fw->data;
 118                 adev->firmware.fw_size +=
 119                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 120         }
 121
 122 out:
 123         if (err) {
 124                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 125                           fw_name);
 126                 release_firmware(adev->pm.fw);
 127                 adev->pm.fw = NULL;
 128         }
 129         return err;
 130 }
 131
 132 void smu_v13_0_fini_microcode(struct smu_context *smu)
 133 {
 134         struct amdgpu_device *adev = smu->adev;
 135
 136         release_firmware(adev->pm.fw);
 137         adev->pm.fw = NULL;
 138         adev->pm.fw_version = 0;
 139 }
 140
 141 int smu_v13_0_load_microcode(struct smu_context *smu)
 142 {
 143 #if 0
 144         struct amdgpu_device *adev = smu->adev;
 145         const uint32_t *src;
 146         const struct smc_firmware_header_v1_0 *hdr;
 147         uint32_t addr_start = MP1_SRAM;
 148         uint32_t i;
 149         uint32_t smc_fw_size;
 150         uint32_t mp1_fw_flags;
 151
 152         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 153         src = (const uint32_t *)(adev->pm.fw->data +
 154                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 155         smc_fw_size = hdr->header.ucode_size_bytes;
 156
 157         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 158                 WREG32_PCIE(addr_start, src[i]);
 159                 addr_start += 4;
 160         }
 161
 162         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 163                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 164         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 165                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 166
 167         for (i = 0; i < adev->usec_timeout; i++) {
 168                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 169                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 170                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 171                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 172                         break;
 173                 udelay(1);
 174         }
 175
 176         if (i == adev->usec_timeout)
 177                 return -ETIME;
 178 #endif
 179         return 0;
 180 }
 181
 182 int smu_v13_0_check_fw_status(struct smu_context *smu)
 183 {
 184         struct amdgpu_device *adev = smu->adev;
 185         uint32_t mp1_fw_flags;
 186
 187         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 188                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 189
 190         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 191             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 192                 return 0;
 193
 194         return -EIO;
 195 }
 196
 197 int smu_v13_0_check_fw_version(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         uint32_t if_version = 0xff, smu_version = 0xff;
 201         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 202         int ret = 0;
 203
 204         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 205         if (ret)
 206                 return ret;
 207
 208         smu_program = (smu_version >> 24) & 0xff;
 209         smu_major = (smu_version >> 16) & 0xff;
 210         smu_minor = (smu_version >> 8) & 0xff;
 211         smu_debug = (smu_version >> 0) & 0xff;
 212         if (smu->is_apu)
 213                 adev->pm.fw_version = smu_version;
 214
 215         switch (adev->ip_versions[MP1_HWIP][0]) {
 216         case IP_VERSION(13, 0, 2):
 217                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 218                 break;
 219         case IP_VERSION(13, 0, 1):
 220         case IP_VERSION(13, 0, 3):
 221         case IP_VERSION(13, 0, 8):
 222                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 223                 break;
 224         case IP_VERSION(13, 0, 5):
 225                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
 226                 break;
 227         default:
 228                 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
 229                         adev->ip_versions[MP1_HWIP][0]);
 230                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 231                 break;
 232         }
 233
 234         /* only for dGPU w/ SMU13*/
 235         if (adev->pm.fw)
 236                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 237                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 238
 239         /*
 240          * 1. if_version mismatch is not critical as our fw is designed
 241          * to be backward compatible.
 242          * 2. New fw usually brings some optimizations. But that's visible
 243          * only on the paired driver.
 244          * Considering above, we just leave user a warning message instead
 245          * of halt driver loading.
 246          */
 247         if (if_version != smu->smc_driver_if_version) {
 248                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 249                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 250                          smu->smc_driver_if_version, if_version,
 251                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 252                 dev_warn(adev->dev, "SMU driver if version not matched\n");
 253         }
 254
 255         return ret;
 256 }
 257
 258 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 259                                       uint32_t *size, uint32_t pptable_id)
 260 {
 261         struct amdgpu_device *adev = smu->adev;
 262         const struct smc_firmware_header_v2_1 *v2_1;
 263         struct smc_soft_pptable_entry *entries;
 264         uint32_t pptable_count = 0;
 265         int i = 0;
 266
 267         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 268         entries = (struct smc_soft_pptable_entry *)
 269                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 270         pptable_count = le32_to_cpu(v2_1->pptable_count);
 271         for (i = 0; i < pptable_count; i++) {
 272                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 273                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 274                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 275                         break;
 276                 }
 277         }
 278
 279         if (i == pptable_count)
 280                 return -EINVAL;
 281
 282         return 0;
 283 }
 284
 285 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 286 {
 287         struct amdgpu_device *adev = smu->adev;
 288         uint16_t atom_table_size;
 289         uint8_t frev, crev;
 290         int ret, index;
 291
 292         dev_info(adev->dev, "use vbios provided pptable\n");
 293         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 294                                             powerplayinfo);
 295
 296         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 297                                              (uint8_t **)table);
 298         if (ret)
 299                 return ret;
 300
 301         if (size)
 302                 *size = atom_table_size;
 303
 304         return 0;
 305 }
 306
 307 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
 308                                                uint32_t pptable_id)
 309 {
 310         const struct smc_firmware_header_v1_0 *hdr;
 311         struct amdgpu_device *adev = smu->adev;
 312         uint16_t version_major, version_minor;
 313         int ret;
 314
 315         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 316         if (!hdr)
 317                 return -EINVAL;
 318
 319         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 320
 321         version_major = le16_to_cpu(hdr->header.header_version_major);
 322         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 323         if (version_major != 2) {
 324                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 325                         version_major, version_minor);
 326                 return -EINVAL;
 327         }
 328
 329         switch (version_minor) {
 330         case 1:
 331                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 332                 break;
 333         default:
 334                 ret = -EINVAL;
 335                 break;
 336         }
 337
 338         return ret;
 339 }
 340
 341 int smu_v13_0_setup_pptable(struct smu_context *smu)
 342 {
 343         struct amdgpu_device *adev = smu->adev;
 344         uint32_t size = 0, pptable_id = 0;
 345         void *table;
 346         int ret = 0;
 347
 348         /* override pptable_id from driver parameter */
 349         if (amdgpu_smu_pptable_id >= 0) {
 350                 pptable_id = amdgpu_smu_pptable_id;
 351                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 352         } else {
 353                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 354         }
 355
 356         /* force using vbios pptable in sriov mode */
 357         if (amdgpu_sriov_vf(adev) || !pptable_id)
 358                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 359         else
 360                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 361
 362         if (ret)
 363                 return ret;
 364
 365         if (!smu->smu_table.power_play_table)
 366                 smu->smu_table.power_play_table = table;
 367         if (!smu->smu_table.power_play_table_size)
 368                 smu->smu_table.power_play_table_size = size;
 369
 370         return 0;
 371 }
 372
 373 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 374 {
 375         struct smu_table_context *smu_table = &smu->smu_table;
 376         struct smu_table *tables = smu_table->tables;
 377         int ret = 0;
 378
 379         smu_table->driver_pptable =
 380                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 381         if (!smu_table->driver_pptable) {
 382                 ret = -ENOMEM;
 383                 goto err0_out;
 384         }
 385
 386         smu_table->max_sustainable_clocks =
 387                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 388         if (!smu_table->max_sustainable_clocks) {
 389                 ret = -ENOMEM;
 390                 goto err1_out;
 391         }
 392
 393         /* Aldebaran does not support OVERDRIVE */
 394         if (tables[SMU_TABLE_OVERDRIVE].size) {
 395                 smu_table->overdrive_table =
 396                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 397                 if (!smu_table->overdrive_table) {
 398                         ret = -ENOMEM;
 399                         goto err2_out;
 400                 }
 401
 402                 smu_table->boot_overdrive_table =
 403                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 404                 if (!smu_table->boot_overdrive_table) {
 405                         ret = -ENOMEM;
 406                         goto err3_out;
 407                 }
 408         }
 409
 410         return 0;
 411
 412 err3_out:
 413         kfree(smu_table->overdrive_table);
 414 err2_out:
 415         kfree(smu_table->max_sustainable_clocks);
 416 err1_out:
 417         kfree(smu_table->driver_pptable);
 418 err0_out:
 419         return ret;
 420 }
 421
 422 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 423 {
 424         struct smu_table_context *smu_table = &smu->smu_table;
 425         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 426
 427         kfree(smu_table->gpu_metrics_table);
 428         kfree(smu_table->boot_overdrive_table);
 429         kfree(smu_table->overdrive_table);
 430         kfree(smu_table->max_sustainable_clocks);
 431         kfree(smu_table->driver_pptable);
 432         smu_table->gpu_metrics_table = NULL;
 433         smu_table->boot_overdrive_table = NULL;
 434         smu_table->overdrive_table = NULL;
 435         smu_table->max_sustainable_clocks = NULL;
 436         smu_table->driver_pptable = NULL;
 437         kfree(smu_table->hardcode_pptable);
 438         smu_table->hardcode_pptable = NULL;
 439
 440         kfree(smu_table->ecc_table);
 441         kfree(smu_table->metrics_table);
 442         kfree(smu_table->watermarks_table);
 443         smu_table->ecc_table = NULL;
 444         smu_table->metrics_table = NULL;
 445         smu_table->watermarks_table = NULL;
 446         smu_table->metrics_time = 0;
 447
 448         kfree(smu_dpm->dpm_context);
 449         kfree(smu_dpm->golden_dpm_context);
 450         kfree(smu_dpm->dpm_current_power_state);
 451         kfree(smu_dpm->dpm_request_power_state);
 452         smu_dpm->dpm_context = NULL;
 453         smu_dpm->golden_dpm_context = NULL;
 454         smu_dpm->dpm_context_size = 0;
 455         smu_dpm->dpm_current_power_state = NULL;
 456         smu_dpm->dpm_request_power_state = NULL;
 457
 458         return 0;
 459 }
 460
 461 int smu_v13_0_init_power(struct smu_context *smu)
 462 {
 463         struct smu_power_context *smu_power = &smu->smu_power;
 464
 465         if (smu_power->power_context || smu_power->power_context_size != 0)
 466                 return -EINVAL;
 467
 468         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 469                                            GFP_KERNEL);
 470         if (!smu_power->power_context)
 471                 return -ENOMEM;
 472         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 473
 474         return 0;
 475 }
 476
 477 int smu_v13_0_fini_power(struct smu_context *smu)
 478 {
 479         struct smu_power_context *smu_power = &smu->smu_power;
 480
 481         if (!smu_power->power_context || smu_power->power_context_size == 0)
 482                 return -EINVAL;
 483
 484         kfree(smu_power->power_context);
 485         smu_power->power_context = NULL;
 486         smu_power->power_context_size = 0;
 487
 488         return 0;
 489 }
 490
 491 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 492                                             uint8_t clk_id,
 493                                             uint8_t syspll_id,
 494                                             uint32_t *clk_freq)
 495 {
 496         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 497         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 498         int ret, index;
 499
 500         input.clk_id = clk_id;
 501         input.syspll_id = syspll_id;
 502         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 503         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 504                                             getsmuclockinfo);
 505
 506         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 507                                         (uint32_t *)&input);
 508         if (ret)
 509                 return -EINVAL;
 510
 511         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 512         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 513
 514         return 0;
 515 }
 516
 517 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 518 {
 519         int ret, index;
 520         uint16_t size;
 521         uint8_t frev, crev;
 522         struct atom_common_table_header *header;
 523         struct atom_firmware_info_v3_4 *v_3_4;
 524         struct atom_firmware_info_v3_3 *v_3_3;
 525         struct atom_firmware_info_v3_1 *v_3_1;
 526
 527         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 528                                             firmwareinfo);
 529
 530         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 531                                              (uint8_t **)&header);
 532         if (ret)
 533                 return ret;
 534
 535         if (header->format_revision != 3) {
 536                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 537                 return -EINVAL;
 538         }
 539
 540         switch (header->content_revision) {
 541         case 0:
 542         case 1:
 543         case 2:
 544                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 545                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 546                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 547                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 548                 smu->smu_table.boot_values.socclk = 0;
 549                 smu->smu_table.boot_values.dcefclk = 0;
 550                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 551                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 552                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 553                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 554                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 555                 smu->smu_table.boot_values.pp_table_id = 0;
 556                 break;
 557         case 3:
 558                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 559                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 560                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 561                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 562                 smu->smu_table.boot_values.socclk = 0;
 563                 smu->smu_table.boot_values.dcefclk = 0;
 564                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 565                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 566                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 567                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 568                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 569                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 570                 break;
 571         case 4:
 572         default:
 573                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 574                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 575                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 576                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 577                 smu->smu_table.boot_values.socclk = 0;
 578                 smu->smu_table.boot_values.dcefclk = 0;
 579                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 580                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 581                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 582                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 583                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 584                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 585                 break;
 586         }
 587
 588         smu->smu_table.boot_values.format_revision = header->format_revision;
 589         smu->smu_table.boot_values.content_revision = header->content_revision;
 590
 591         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 592                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 593                                          (uint8_t)0,
 594                                          &smu->smu_table.boot_values.socclk);
 595
 596         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 597                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 598                                          (uint8_t)0,
 599                                          &smu->smu_table.boot_values.dcefclk);
 600
 601         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 602                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 603                                          (uint8_t)0,
 604                                          &smu->smu_table.boot_values.eclk);
 605
 606         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 607                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 608                                          (uint8_t)0,
 609                                          &smu->smu_table.boot_values.vclk);
 610
 611         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 612                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 613                                          (uint8_t)0,
 614                                          &smu->smu_table.boot_values.dclk);
 615
 616         if ((smu->smu_table.boot_values.format_revision == 3) &&
 617             (smu->smu_table.boot_values.content_revision >= 2))
 618                 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 619                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 620                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 621                                                  &smu->smu_table.boot_values.fclk);
 622
 623         return 0;
 624 }
 625
 626
 627 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 628 {
 629         struct smu_table_context *smu_table = &smu->smu_table;
 630         struct smu_table *memory_pool = &smu_table->memory_pool;
 631         int ret = 0;
 632         uint64_t address;
 633         uint32_t address_low, address_high;
 634
 635         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 636                 return ret;
 637
 638         address = memory_pool->mc_address;
 639         address_high = (uint32_t)upper_32_bits(address);
 640         address_low  = (uint32_t)lower_32_bits(address);
 641
 642         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 643                                               address_high, NULL);
 644         if (ret)
 645                 return ret;
 646         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 647                                               address_low, NULL);
 648         if (ret)
 649                 return ret;
 650         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 651                                               (uint32_t)memory_pool->size, NULL);
 652         if (ret)
 653                 return ret;
 654
 655         return ret;
 656 }
 657
 658 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 659 {
 660         int ret;
 661
 662         ret = smu_cmn_send_smc_msg_with_param(smu,
 663                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 664         if (ret)
 665                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 666
 667         return ret;
 668 }
 669
 670 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 671 {
 672         struct smu_table *driver_table = &smu->smu_table.driver_table;
 673         int ret = 0;
 674
 675         if (driver_table->mc_address) {
 676                 ret = smu_cmn_send_smc_msg_with_param(smu,
 677                                                       SMU_MSG_SetDriverDramAddrHigh,
 678                                                       upper_32_bits(driver_table->mc_address),
 679                                                       NULL);
 680                 if (!ret)
 681                         ret = smu_cmn_send_smc_msg_with_param(smu,
 682                                                               SMU_MSG_SetDriverDramAddrLow,
 683                                                               lower_32_bits(driver_table->mc_address),
 684                                                               NULL);
 685         }
 686
 687         return ret;
 688 }
 689
 690 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 691 {
 692         int ret = 0;
 693         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 694
 695         if (tool_table->mc_address) {
 696                 ret = smu_cmn_send_smc_msg_with_param(smu,
 697                                                       SMU_MSG_SetToolsDramAddrHigh,
 698                                                       upper_32_bits(tool_table->mc_address),
 699                                                       NULL);
 700                 if (!ret)
 701                         ret = smu_cmn_send_smc_msg_with_param(smu,
 702                                                               SMU_MSG_SetToolsDramAddrLow,
 703                                                               lower_32_bits(tool_table->mc_address),
 704                                                               NULL);
 705         }
 706
 707         return ret;
 708 }
 709
 710 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 711 {
 712         int ret = 0;
 713
 714         if (!smu->pm_enabled)
 715                 return ret;
 716
 717         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 718
 719         return ret;
 720 }
 721
 722
 723 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 724 {
 725         struct smu_feature *feature = &smu->smu_feature;
 726         int ret = 0;
 727         uint32_t feature_mask[2];
 728
 729         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 730             feature->feature_num < 64)
 731                 return -EINVAL;
 732
 733         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 734
 735         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 736                                               feature_mask[1], NULL);
 737         if (ret)
 738                 return ret;
 739
 740         return smu_cmn_send_smc_msg_with_param(smu,
 741                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 742                                                feature_mask[0],
 743                                                NULL);
 744 }
 745
 746 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 747 {
 748         int ret = 0;
 749         struct amdgpu_device *adev = smu->adev;
 750
 751         switch (adev->ip_versions[MP1_HWIP][0]) {
 752         case IP_VERSION(13, 0, 1):
 753         case IP_VERSION(13, 0, 3):
 754         case IP_VERSION(13, 0, 5):
 755         case IP_VERSION(13, 0, 8):
 756                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 757                         return 0;
 758                 if (enable)
 759                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 760                 else
 761                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 762                 break;
 763         default:
 764                 break;
 765         }
 766
 767         return ret;
 768 }
 769
 770 int smu_v13_0_system_features_control(struct smu_context *smu,
 771                                       bool en)
 772 {
 773         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 774                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 775 }
 776
 777 int smu_v13_0_notify_display_change(struct smu_context *smu)
 778 {
 779         int ret = 0;
 780
 781         if (!smu->pm_enabled)
 782                 return ret;
 783
 784         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 785             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 786                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 787
 788         return ret;
 789 }
 790
 791         static int
 792 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 793                                     enum smu_clk_type clock_select)
 794 {
 795         int ret = 0;
 796         int clk_id;
 797
 798         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 799             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 800                 return 0;
 801
 802         clk_id = smu_cmn_to_asic_specific_index(smu,
 803                                                 CMN2ASIC_MAPPING_CLK,
 804                                                 clock_select);
 805         if (clk_id < 0)
 806                 return -EINVAL;
 807
 808         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 809                                               clk_id << 16, clock);
 810         if (ret) {
 811                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 812                 return ret;
 813         }
 814
 815         if (*clock != 0)
 816                 return 0;
 817
 818         /* if DC limit is zero, return AC limit */
 819         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 820                                               clk_id << 16, clock);
 821         if (ret) {
 822                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 823                 return ret;
 824         }
 825
 826         return 0;
 827 }
 828
 829 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 830 {
 831         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 832                 smu->smu_table.max_sustainable_clocks;
 833         int ret = 0;
 834
 835         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 836         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 837         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 838         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 839         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 840         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 841
 842         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 843                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 844                                                           &(max_sustainable_clocks->uclock),
 845                                                           SMU_UCLK);
 846                 if (ret) {
 847                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 848                                 __func__);
 849                         return ret;
 850                 }
 851         }
 852
 853         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 854                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 855                                                           &(max_sustainable_clocks->soc_clock),
 856                                                           SMU_SOCCLK);
 857                 if (ret) {
 858                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 859                                 __func__);
 860                         return ret;
 861                 }
 862         }
 863
 864         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 865                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 866                                                           &(max_sustainable_clocks->dcef_clock),
 867                                                           SMU_DCEFCLK);
 868                 if (ret) {
 869                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 870                                 __func__);
 871                         return ret;
 872                 }
 873
 874                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 875                                                           &(max_sustainable_clocks->display_clock),
 876                                                           SMU_DISPCLK);
 877                 if (ret) {
 878                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 879                                 __func__);
 880                         return ret;
 881                 }
 882                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 883                                                           &(max_sustainable_clocks->phy_clock),
 884                                                           SMU_PHYCLK);
 885                 if (ret) {
 886                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 887                                 __func__);
 888                         return ret;
 889                 }
 890                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 891                                                           &(max_sustainable_clocks->pixel_clock),
 892                                                           SMU_PIXCLK);
 893                 if (ret) {
 894                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 895                                 __func__);
 896                         return ret;
 897                 }
 898         }
 899
 900         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 901                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 902
 903         return 0;
 904 }
 905
 906 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 907                                       uint32_t *power_limit)
 908 {
 909         int power_src;
 910         int ret = 0;
 911
 912         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 913                 return -EINVAL;
 914
 915         power_src = smu_cmn_to_asic_specific_index(smu,
 916                                                    CMN2ASIC_MAPPING_PWR,
 917                                                    smu->adev->pm.ac_power ?
 918                                                    SMU_POWER_SOURCE_AC :
 919                                                    SMU_POWER_SOURCE_DC);
 920         if (power_src < 0)
 921                 return -EINVAL;
 922
 923         ret = smu_cmn_send_smc_msg_with_param(smu,
 924                                               SMU_MSG_GetPptLimit,
 925                                               power_src << 16,
 926                                               power_limit);
 927         if (ret)
 928                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 929
 930         return ret;
 931 }
 932
 933 int smu_v13_0_set_power_limit(struct smu_context *smu,
 934                               enum smu_ppt_limit_type limit_type,
 935                               uint32_t limit)
 936 {
 937         int ret = 0;
 938
 939         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
 940                 return -EINVAL;
 941
 942         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 943                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 944                 return -EOPNOTSUPP;
 945         }
 946
 947         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
 948         if (ret) {
 949                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 950                 return ret;
 951         }
 952
 953         smu->current_power_limit = limit;
 954
 955         return 0;
 956 }
 957
 958 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 959 {
 960         if (smu->smu_table.thermal_controller_type)
 961                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 962
 963         return 0;
 964 }
 965
 966 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
 967 {
 968         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 969 }
 970
 971 static uint16_t convert_to_vddc(uint8_t vid)
 972 {
 973         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
 974 }
 975
 976 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 977 {
 978         struct amdgpu_device *adev = smu->adev;
 979         uint32_t vdd = 0, val_vid = 0;
 980
 981         if (!value)
 982                 return -EINVAL;
 983         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
 984                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 985                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 986
 987         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 988
 989         *value = vdd;
 990
 991         return 0;
 992
 993 }
 994
 995 int
 996 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
 997                                         struct pp_display_clock_request
 998                                         *clock_req)
 999 {
1000         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1001         int ret = 0;
1002         enum smu_clk_type clk_select = 0;
1003         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1004
1005         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1006             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1007                 switch (clk_type) {
1008                 case amd_pp_dcef_clock:
1009                         clk_select = SMU_DCEFCLK;
1010                         break;
1011                 case amd_pp_disp_clock:
1012                         clk_select = SMU_DISPCLK;
1013                         break;
1014                 case amd_pp_pixel_clock:
1015                         clk_select = SMU_PIXCLK;
1016                         break;
1017                 case amd_pp_phy_clock:
1018                         clk_select = SMU_PHYCLK;
1019                         break;
1020                 case amd_pp_mem_clock:
1021                         clk_select = SMU_UCLK;
1022                         break;
1023                 default:
1024                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1025                         ret = -EINVAL;
1026                         break;
1027                 }
1028
1029                 if (ret)
1030                         goto failed;
1031
1032                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1033                         return 0;
1034
1035                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1036
1037                 if(clk_select == SMU_UCLK)
1038                         smu->hard_min_uclk_req_from_dal = clk_freq;
1039         }
1040
1041 failed:
1042         return ret;
1043 }
1044
1045 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1046 {
1047         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1048                 return AMD_FAN_CTRL_MANUAL;
1049         else
1050                 return AMD_FAN_CTRL_AUTO;
1051 }
1052
1053         static int
1054 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1055 {
1056         int ret = 0;
1057
1058         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1059                 return 0;
1060
1061         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1062         if (ret)
1063                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1064                         __func__, (auto_fan_control ? "Start" : "Stop"));
1065
1066         return ret;
1067 }
1068
1069         static int
1070 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1071 {
1072         struct amdgpu_device *adev = smu->adev;
1073
1074         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1075                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1076                                    CG_FDO_CTRL2, TMIN, 0));
1077         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1078                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1079                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1080
1081         return 0;
1082 }
1083
1084         int
1085 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1086 {
1087         struct amdgpu_device *adev = smu->adev;
1088         uint32_t duty100, duty;
1089         uint64_t tmp64;
1090
1091         if (speed > 100)
1092                 speed = 100;
1093
1094         if (smu_v13_0_auto_fan_control(smu, 0))
1095                 return -EINVAL;
1096
1097         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1098                                 CG_FDO_CTRL1, FMAX_DUTY100);
1099         if (!duty100)
1100                 return -EINVAL;
1101
1102         tmp64 = (uint64_t)speed * duty100;
1103         do_div(tmp64, 100);
1104         duty = (uint32_t)tmp64;
1105
1106         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1107                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1108                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1109
1110         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1111 }
1112
1113         int
1114 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1115                                uint32_t mode)
1116 {
1117         int ret = 0;
1118
1119         switch (mode) {
1120         case AMD_FAN_CTRL_NONE:
1121                 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1122                 break;
1123         case AMD_FAN_CTRL_MANUAL:
1124                 ret = smu_v13_0_auto_fan_control(smu, 0);
1125                 break;
1126         case AMD_FAN_CTRL_AUTO:
1127                 ret = smu_v13_0_auto_fan_control(smu, 1);
1128                 break;
1129         default:
1130                 break;
1131         }
1132
1133         if (ret) {
1134                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1135                 return -EINVAL;
1136         }
1137
1138         return ret;
1139 }
1140
1141 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1142                                 uint32_t speed)
1143 {
1144         struct amdgpu_device *adev = smu->adev;
1145         int ret;
1146         uint32_t tach_period, crystal_clock_freq;
1147
1148         if (!speed)
1149                 return -EINVAL;
1150
1151         ret = smu_v13_0_auto_fan_control(smu, 0);
1152         if (ret)
1153                 return ret;
1154
1155         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1156         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1157         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1158                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1159                                    CG_TACH_CTRL, TARGET_PERIOD,
1160                                    tach_period));
1161
1162         ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1163
1164         return ret;
1165 }
1166
1167 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1168                               uint32_t pstate)
1169 {
1170         int ret = 0;
1171         ret = smu_cmn_send_smc_msg_with_param(smu,
1172                                               SMU_MSG_SetXgmiMode,
1173                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1174                                               NULL);
1175         return ret;
1176 }
1177
1178 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1179                                    struct amdgpu_irq_src *source,
1180                                    unsigned tyep,
1181                                    enum amdgpu_interrupt_state state)
1182 {
1183         struct smu_context *smu = adev->powerplay.pp_handle;
1184         uint32_t low, high;
1185         uint32_t val = 0;
1186
1187         switch (state) {
1188         case AMDGPU_IRQ_STATE_DISABLE:
1189                 /* For THM irqs */
1190                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1191                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1192                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1193                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1194
1195                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1196
1197                 /* For MP1 SW irqs */
1198                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1199                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1200                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1201
1202                 break;
1203         case AMDGPU_IRQ_STATE_ENABLE:
1204                 /* For THM irqs */
1205                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1206                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1207                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1208                            smu->thermal_range.software_shutdown_temp);
1209
1210                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1211                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1212                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1213                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1214                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1215                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1216                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1217                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1218                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1219
1220                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1221                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1222                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1223                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1224
1225                 /* For MP1 SW irqs */
1226                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1227                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1228                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1229                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1230
1231                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1232                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1233                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1234
1235                 break;
1236         default:
1237                 break;
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1244 {
1245         return smu_cmn_send_smc_msg(smu,
1246                                     SMU_MSG_ReenableAcDcInterrupt,
1247                                     NULL);
1248 }
1249
1250 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1251 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1252 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1253
1254 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1255                                  struct amdgpu_irq_src *source,
1256                                  struct amdgpu_iv_entry *entry)
1257 {
1258         struct smu_context *smu = adev->powerplay.pp_handle;
1259         uint32_t client_id = entry->client_id;
1260         uint32_t src_id = entry->src_id;
1261         /*
1262          * ctxid is used to distinguish different
1263          * events for SMCToHost interrupt.
1264          */
1265         uint32_t ctxid = entry->src_data[0];
1266         uint32_t data;
1267
1268         if (client_id == SOC15_IH_CLIENTID_THM) {
1269                 switch (src_id) {
1270                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1271                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1272                         /*
1273                          * SW CTF just occurred.
1274                          * Try to do a graceful shutdown to prevent further damage.
1275                          */
1276                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1277                         orderly_poweroff(true);
1278                         break;
1279                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1280                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1281                         break;
1282                 default:
1283                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1284                                   src_id);
1285                         break;
1286                 }
1287         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1288                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1289                 /*
1290                  * HW CTF just occurred. Shutdown to prevent further damage.
1291                  */
1292                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1293                 orderly_poweroff(true);
1294         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1295                 if (src_id == 0xfe) {
1296                         /* ACK SMUToHost interrupt */
1297                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1298                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1299                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1300
1301                         switch (ctxid) {
1302                         case 0x3:
1303                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1304                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1305                                 break;
1306                         case 0x4:
1307                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1308                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1309                                 break;
1310                         case 0x7:
1311                                 /*
1312                                  * Increment the throttle interrupt counter
1313                                  */
1314                                 atomic64_inc(&smu->throttle_int_counter);
1315
1316                                 if (!atomic_read(&adev->throttling_logging_enabled))
1317                                         return 0;
1318
1319                                 if (__ratelimit(&adev->throttling_logging_rs))
1320                                         schedule_work(&smu->throttling_logging_work);
1321
1322                                 break;
1323                         }
1324                 }
1325         }
1326
1327         return 0;
1328 }
1329
1330 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1331 {
1332         .set = smu_v13_0_set_irq_state,
1333         .process = smu_v13_0_irq_process,
1334 };
1335
1336 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1337 {
1338         struct amdgpu_device *adev = smu->adev;
1339         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1340         int ret = 0;
1341
1342         irq_src->num_types = 1;
1343         irq_src->funcs = &smu_v13_0_irq_funcs;
1344
1345         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1346                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1347                                 irq_src);
1348         if (ret)
1349                 return ret;
1350
1351         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1352                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1353                                 irq_src);
1354         if (ret)
1355                 return ret;
1356
1357         /* Register CTF(GPIO_19) interrupt */
1358         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1359                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1360                                 irq_src);
1361         if (ret)
1362                 return ret;
1363
1364         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1365                                 0xfe,
1366                                 irq_src);
1367         if (ret)
1368                 return ret;
1369
1370         return ret;
1371 }
1372
1373 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1374                                                struct pp_smu_nv_clock_table *max_clocks)
1375 {
1376         struct smu_table_context *table_context = &smu->smu_table;
1377         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1378
1379         if (!max_clocks || !table_context->max_sustainable_clocks)
1380                 return -EINVAL;
1381
1382         sustainable_clocks = table_context->max_sustainable_clocks;
1383
1384         max_clocks->dcfClockInKhz =
1385                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1386         max_clocks->displayClockInKhz =
1387                 (unsigned int) sustainable_clocks->display_clock * 1000;
1388         max_clocks->phyClockInKhz =
1389                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1390         max_clocks->pixelClockInKhz =
1391                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1392         max_clocks->uClockInKhz =
1393                 (unsigned int) sustainable_clocks->uclock * 1000;
1394         max_clocks->socClockInKhz =
1395                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1396         max_clocks->dscClockInKhz = 0;
1397         max_clocks->dppClockInKhz = 0;
1398         max_clocks->fabricClockInKhz = 0;
1399
1400         return 0;
1401 }
1402
1403 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1404 {
1405         int ret = 0;
1406
1407         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1408
1409         return ret;
1410 }
1411
1412 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1413                                              uint64_t event_arg)
1414 {
1415         int ret = 0;
1416
1417         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1418         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1419
1420         return ret;
1421 }
1422
1423 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1424                              uint64_t event_arg)
1425 {
1426         int ret = -EINVAL;
1427
1428         switch (event) {
1429         case SMU_EVENT_RESET_COMPLETE:
1430                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1431                 break;
1432         default:
1433                 break;
1434         }
1435
1436         return ret;
1437 }
1438
1439 int smu_v13_0_mode2_reset(struct smu_context *smu)
1440 {
1441         int ret;
1442
1443         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1444                         SMU_RESET_MODE_2, NULL);
1445         /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1446         if (!ret)
1447                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1448
1449         return ret;
1450 }
1451
1452 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1453                                     uint32_t *min, uint32_t *max)
1454 {
1455         int ret = 0, clk_id = 0;
1456         uint32_t param = 0;
1457         uint32_t clock_limit;
1458
1459         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1460                 switch (clk_type) {
1461                 case SMU_MCLK:
1462                 case SMU_UCLK:
1463                         clock_limit = smu->smu_table.boot_values.uclk;
1464                         break;
1465                 case SMU_GFXCLK:
1466                 case SMU_SCLK:
1467                         clock_limit = smu->smu_table.boot_values.gfxclk;
1468                         break;
1469                 case SMU_SOCCLK:
1470                         clock_limit = smu->smu_table.boot_values.socclk;
1471                         break;
1472                 default:
1473                         clock_limit = 0;
1474                         break;
1475                 }
1476
1477                 /* clock in Mhz unit */
1478                 if (min)
1479                         *min = clock_limit / 100;
1480                 if (max)
1481                         *max = clock_limit / 100;
1482
1483                 return 0;
1484         }
1485
1486         clk_id = smu_cmn_to_asic_specific_index(smu,
1487                                                 CMN2ASIC_MAPPING_CLK,
1488                                                 clk_type);
1489         if (clk_id < 0) {
1490                 ret = -EINVAL;
1491                 goto failed;
1492         }
1493         param = (clk_id & 0xffff) << 16;
1494
1495         if (max) {
1496                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1497                 if (ret)
1498                         goto failed;
1499         }
1500
1501         if (min) {
1502                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1503                 if (ret)
1504                         goto failed;
1505         }
1506
1507 failed:
1508         return ret;
1509 }
1510
1511 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1512                                           enum smu_clk_type clk_type,
1513                                           uint32_t min,
1514                                           uint32_t max)
1515 {
1516         int ret = 0, clk_id = 0;
1517         uint32_t param;
1518
1519         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1520                 return 0;
1521
1522         clk_id = smu_cmn_to_asic_specific_index(smu,
1523                                                 CMN2ASIC_MAPPING_CLK,
1524                                                 clk_type);
1525         if (clk_id < 0)
1526                 return clk_id;
1527
1528         if (max > 0) {
1529                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1530                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1531                                                       param, NULL);
1532                 if (ret)
1533                         goto out;
1534         }
1535
1536         if (min > 0) {
1537                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1538                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1539                                                       param, NULL);
1540                 if (ret)
1541                         goto out;
1542         }
1543
1544 out:
1545         return ret;
1546 }
1547
1548 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1549                                           enum smu_clk_type clk_type,
1550                                           uint32_t min,
1551                                           uint32_t max)
1552 {
1553         int ret = 0, clk_id = 0;
1554         uint32_t param;
1555
1556         if (min <= 0 && max <= 0)
1557                 return -EINVAL;
1558
1559         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1560                 return 0;
1561
1562         clk_id = smu_cmn_to_asic_specific_index(smu,
1563                                                 CMN2ASIC_MAPPING_CLK,
1564                                                 clk_type);
1565         if (clk_id < 0)
1566                 return clk_id;
1567
1568         if (max > 0) {
1569                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1570                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1571                                                       param, NULL);
1572                 if (ret)
1573                         return ret;
1574         }
1575
1576         if (min > 0) {
1577                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1578                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1579                                                       param, NULL);
1580                 if (ret)
1581                         return ret;
1582         }
1583
1584         return ret;
1585 }
1586
1587 int smu_v13_0_set_performance_level(struct smu_context *smu,
1588                                     enum amd_dpm_forced_level level)
1589 {
1590         struct smu_13_0_dpm_context *dpm_context =
1591                 smu->smu_dpm.dpm_context;
1592         struct smu_13_0_dpm_table *gfx_table =
1593                 &dpm_context->dpm_tables.gfx_table;
1594         struct smu_13_0_dpm_table *mem_table =
1595                 &dpm_context->dpm_tables.uclk_table;
1596         struct smu_13_0_dpm_table *soc_table =
1597                 &dpm_context->dpm_tables.soc_table;
1598         struct smu_umd_pstate_table *pstate_table =
1599                 &smu->pstate_table;
1600         struct amdgpu_device *adev = smu->adev;
1601         uint32_t sclk_min = 0, sclk_max = 0;
1602         uint32_t mclk_min = 0, mclk_max = 0;
1603         uint32_t socclk_min = 0, socclk_max = 0;
1604         int ret = 0;
1605
1606         switch (level) {
1607         case AMD_DPM_FORCED_LEVEL_HIGH:
1608                 sclk_min = sclk_max = gfx_table->max;
1609                 mclk_min = mclk_max = mem_table->max;
1610                 socclk_min = socclk_max = soc_table->max;
1611                 break;
1612         case AMD_DPM_FORCED_LEVEL_LOW:
1613                 sclk_min = sclk_max = gfx_table->min;
1614                 mclk_min = mclk_max = mem_table->min;
1615                 socclk_min = socclk_max = soc_table->min;
1616                 break;
1617         case AMD_DPM_FORCED_LEVEL_AUTO:
1618                 sclk_min = gfx_table->min;
1619                 sclk_max = gfx_table->max;
1620                 mclk_min = mem_table->min;
1621                 mclk_max = mem_table->max;
1622                 socclk_min = soc_table->min;
1623                 socclk_max = soc_table->max;
1624                 break;
1625         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1626                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1627                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1628                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1629                 break;
1630         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1631                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1632                 break;
1633         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1634                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1635                 break;
1636         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1637                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1638                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1639                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1640                 break;
1641         case AMD_DPM_FORCED_LEVEL_MANUAL:
1642         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1643                 return 0;
1644         default:
1645                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1646                 return -EINVAL;
1647         }
1648
1649         mclk_min = mclk_max = 0;
1650         socclk_min = socclk_max = 0;
1651
1652         if (sclk_min && sclk_max) {
1653                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1654                                                             SMU_GFXCLK,
1655                                                             sclk_min,
1656                                                             sclk_max);
1657                 if (ret)
1658                         return ret;
1659
1660                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1661                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1662         }
1663
1664         if (mclk_min && mclk_max) {
1665                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1666                                                             SMU_MCLK,
1667                                                             mclk_min,
1668                                                             mclk_max);
1669                 if (ret)
1670                         return ret;
1671
1672                 pstate_table->uclk_pstate.curr.min = mclk_min;
1673                 pstate_table->uclk_pstate.curr.max = mclk_max;
1674         }
1675
1676         if (socclk_min && socclk_max) {
1677                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1678                                                             SMU_SOCCLK,
1679                                                             socclk_min,
1680                                                             socclk_max);
1681                 if (ret)
1682                         return ret;
1683
1684                 pstate_table->socclk_pstate.curr.min = socclk_min;
1685                 pstate_table->socclk_pstate.curr.max = socclk_max;
1686         }
1687
1688         return ret;
1689 }
1690
1691 int smu_v13_0_set_power_source(struct smu_context *smu,
1692                                enum smu_power_src_type power_src)
1693 {
1694         int pwr_source;
1695
1696         pwr_source = smu_cmn_to_asic_specific_index(smu,
1697                                                     CMN2ASIC_MAPPING_PWR,
1698                                                     (uint32_t)power_src);
1699         if (pwr_source < 0)
1700                 return -EINVAL;
1701
1702         return smu_cmn_send_smc_msg_with_param(smu,
1703                                                SMU_MSG_NotifyPowerSource,
1704                                                pwr_source,
1705                                                NULL);
1706 }
1707
1708 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1709                                     enum smu_clk_type clk_type,
1710                                     uint16_t level,
1711                                     uint32_t *value)
1712 {
1713         int ret = 0, clk_id = 0;
1714         uint32_t param;
1715
1716         if (!value)
1717                 return -EINVAL;
1718
1719         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1720                 return 0;
1721
1722         clk_id = smu_cmn_to_asic_specific_index(smu,
1723                                                 CMN2ASIC_MAPPING_CLK,
1724                                                 clk_type);
1725         if (clk_id < 0)
1726                 return clk_id;
1727
1728         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1729
1730         ret = smu_cmn_send_smc_msg_with_param(smu,
1731                                               SMU_MSG_GetDpmFreqByIndex,
1732                                               param,
1733                                               value);
1734         if (ret)
1735                 return ret;
1736
1737         /*
1738          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1739          * now, we un-support it
1740          */
1741         *value = *value & 0x7fffffff;
1742
1743         return ret;
1744 }
1745
1746 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1747                                   enum smu_clk_type clk_type,
1748                                   uint32_t *value)
1749 {
1750         int ret;
1751
1752         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1753         /* FW returns 0 based max level, increment by one */
1754         if (!ret && value)
1755                 ++(*value);
1756
1757         return ret;
1758 }
1759
1760 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1761                                    enum smu_clk_type clk_type,
1762                                    struct smu_13_0_dpm_table *single_dpm_table)
1763 {
1764         int ret = 0;
1765         uint32_t clk;
1766         int i;
1767
1768         ret = smu_v13_0_get_dpm_level_count(smu,
1769                                             clk_type,
1770                                             &single_dpm_table->count);
1771         if (ret) {
1772                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1773                 return ret;
1774         }
1775
1776         for (i = 0; i < single_dpm_table->count; i++) {
1777                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1778                                                       clk_type,
1779                                                       i,
1780                                                       &clk);
1781                 if (ret) {
1782                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1783                         return ret;
1784                 }
1785
1786                 single_dpm_table->dpm_levels[i].value = clk;
1787                 single_dpm_table->dpm_levels[i].enabled = true;
1788
1789                 if (i == 0)
1790                         single_dpm_table->min = clk;
1791                 else if (i == single_dpm_table->count - 1)
1792                         single_dpm_table->max = clk;
1793         }
1794
1795         return 0;
1796 }
1797
1798 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1799                                   enum smu_clk_type clk_type,
1800                                   uint32_t *min_value,
1801                                   uint32_t *max_value)
1802 {
1803         uint32_t level_count = 0;
1804         int ret = 0;
1805
1806         if (!min_value && !max_value)
1807                 return -EINVAL;
1808
1809         if (min_value) {
1810                 /* by default, level 0 clock value as min value */
1811                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1812                                                       clk_type,
1813                                                       0,
1814                                                       min_value);
1815                 if (ret)
1816                         return ret;
1817         }
1818
1819         if (max_value) {
1820                 ret = smu_v13_0_get_dpm_level_count(smu,
1821                                                     clk_type,
1822                                                     &level_count);
1823                 if (ret)
1824                         return ret;
1825
1826                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1827                                                       clk_type,
1828                                                       level_count - 1,
1829                                                       max_value);
1830                 if (ret)
1831                         return ret;
1832         }
1833
1834         return ret;
1835 }
1836
1837 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1838 {
1839         struct amdgpu_device *adev = smu->adev;
1840
1841         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1842                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1843                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1844 }
1845
1846 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1847 {
1848         uint32_t width_level;
1849
1850         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1851         if (width_level > LINK_WIDTH_MAX)
1852                 width_level = 0;
1853
1854         return link_width[width_level];
1855 }
1856
1857 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1858 {
1859         struct amdgpu_device *adev = smu->adev;
1860
1861         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1862                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1863                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1864 }
1865
1866 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1867 {
1868         uint32_t speed_level;
1869
1870         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1871         if (speed_level > LINK_SPEED_MAX)
1872                 speed_level = 0;
1873
1874         return link_speed[speed_level];
1875 }
1876