2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
63 #define SMU13_VOLTAGE_SCALE 4
65 #define LINK_WIDTH_MAX 6
66 #define LINK_SPEED_MAX 3
68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71 #define smnPCIE_LC_SPEED_CNTL 0x11140290
72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76 static const int link_speed[] = {25, 50, 80, 160};
78 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
81 int smu_v13_0_init_microcode(struct smu_context *smu)
83 struct amdgpu_device *adev = smu->adev;
84 const char *chip_name;
86 char ucode_prefix[30];
88 const struct smc_firmware_header_v1_0 *hdr;
89 const struct common_firmware_header *header;
90 struct amdgpu_firmware_info *ucode = NULL;
92 /* doesn't need to load smu firmware in IOV mode */
93 if (amdgpu_sriov_vf(adev))
96 switch (adev->ip_versions[MP1_HWIP][0]) {
97 case IP_VERSION(13, 0, 2):
98 chip_name = "aldebaran_smc";
101 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
102 chip_name = ucode_prefix;
105 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
107 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
110 err = amdgpu_ucode_validate(adev->pm.fw);
114 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
115 amdgpu_ucode_print_smc_hdr(&hdr->header);
116 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
119 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
120 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
121 ucode->fw = adev->pm.fw;
122 header = (const struct common_firmware_header *)ucode->fw->data;
123 adev->firmware.fw_size +=
124 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
129 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
131 release_firmware(adev->pm.fw);
137 void smu_v13_0_fini_microcode(struct smu_context *smu)
139 struct amdgpu_device *adev = smu->adev;
141 release_firmware(adev->pm.fw);
143 adev->pm.fw_version = 0;
146 int smu_v13_0_load_microcode(struct smu_context *smu)
149 struct amdgpu_device *adev = smu->adev;
151 const struct smc_firmware_header_v1_0 *hdr;
152 uint32_t addr_start = MP1_SRAM;
154 uint32_t smc_fw_size;
155 uint32_t mp1_fw_flags;
157 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
158 src = (const uint32_t *)(adev->pm.fw->data +
159 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
160 smc_fw_size = hdr->header.ucode_size_bytes;
162 for (i = 1; i < smc_fw_size/4 - 1; i++) {
163 WREG32_PCIE(addr_start, src[i]);
167 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
168 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
169 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
170 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
172 for (i = 0; i < adev->usec_timeout; i++) {
173 mp1_fw_flags = RREG32_PCIE(MP1_Public |
174 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
175 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
176 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
181 if (i == adev->usec_timeout)
188 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
190 struct amdgpu_device *adev = smu->adev;
191 struct amdgpu_firmware_info *ucode = NULL;
192 uint32_t size = 0, pptable_id = 0;
196 /* doesn't need to load smu firmware in IOV mode */
197 if (amdgpu_sriov_vf(adev))
200 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
203 if (!adev->scpm_enabled)
206 /* override pptable_id from driver parameter */
207 if (amdgpu_smu_pptable_id >= 0) {
208 pptable_id = amdgpu_smu_pptable_id;
209 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
211 pptable_id = smu->smu_table.boot_values.pp_table_id;
213 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
217 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
221 * Temporary solution for SMU V13.0.0 with SCPM enabled:
222 * - use 36831 signed pptable when pp_table_id is 3683
223 * - use 36641 signed pptable when pp_table_id is 3664 or 0
224 * TODO: drop these when the pptable carried in vbios is ready.
226 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
227 switch (pptable_id) {
236 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
242 /* "pptable_id == 0" means vbios carries the pptable. */
246 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
250 smu->pptable_firmware.data = table;
251 smu->pptable_firmware.size = size;
253 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
254 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
255 ucode->fw = &smu->pptable_firmware;
256 adev->firmware.fw_size +=
257 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
262 int smu_v13_0_check_fw_status(struct smu_context *smu)
264 struct amdgpu_device *adev = smu->adev;
265 uint32_t mp1_fw_flags;
267 mp1_fw_flags = RREG32_PCIE(MP1_Public |
268 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
270 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
271 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
277 int smu_v13_0_check_fw_version(struct smu_context *smu)
279 struct amdgpu_device *adev = smu->adev;
280 uint32_t if_version = 0xff, smu_version = 0xff;
281 uint8_t smu_program, smu_major, smu_minor, smu_debug;
284 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
288 smu_program = (smu_version >> 24) & 0xff;
289 smu_major = (smu_version >> 16) & 0xff;
290 smu_minor = (smu_version >> 8) & 0xff;
291 smu_debug = (smu_version >> 0) & 0xff;
293 adev->pm.fw_version = smu_version;
295 switch (adev->ip_versions[MP1_HWIP][0]) {
296 case IP_VERSION(13, 0, 2):
297 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
299 case IP_VERSION(13, 0, 0):
300 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
302 case IP_VERSION(13, 0, 7):
303 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
305 case IP_VERSION(13, 0, 1):
306 case IP_VERSION(13, 0, 3):
307 case IP_VERSION(13, 0, 8):
308 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
310 case IP_VERSION(13, 0, 4):
311 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
313 case IP_VERSION(13, 0, 5):
314 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
317 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
318 adev->ip_versions[MP1_HWIP][0]);
319 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
323 /* only for dGPU w/ SMU13*/
325 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
326 smu_program, smu_version, smu_major, smu_minor, smu_debug);
329 * 1. if_version mismatch is not critical as our fw is designed
330 * to be backward compatible.
331 * 2. New fw usually brings some optimizations. But that's visible
332 * only on the paired driver.
333 * Considering above, we just leave user a warning message instead
334 * of halt driver loading.
336 if (if_version != smu->smc_driver_if_version) {
337 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
338 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
339 smu->smc_driver_if_version, if_version,
340 smu_program, smu_version, smu_major, smu_minor, smu_debug);
341 dev_warn(adev->dev, "SMU driver if version not matched\n");
347 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
349 struct amdgpu_device *adev = smu->adev;
350 uint32_t ppt_offset_bytes;
351 const struct smc_firmware_header_v2_0 *v2;
353 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
355 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
356 *size = le32_to_cpu(v2->ppt_size_bytes);
357 *table = (uint8_t *)v2 + ppt_offset_bytes;
362 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
363 uint32_t *size, uint32_t pptable_id)
365 struct amdgpu_device *adev = smu->adev;
366 const struct smc_firmware_header_v2_1 *v2_1;
367 struct smc_soft_pptable_entry *entries;
368 uint32_t pptable_count = 0;
371 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
372 entries = (struct smc_soft_pptable_entry *)
373 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
374 pptable_count = le32_to_cpu(v2_1->pptable_count);
375 for (i = 0; i < pptable_count; i++) {
376 if (le32_to_cpu(entries[i].id) == pptable_id) {
377 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
378 *size = le32_to_cpu(entries[i].ppt_size_bytes);
383 if (i == pptable_count)
389 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
391 struct amdgpu_device *adev = smu->adev;
392 uint16_t atom_table_size;
396 dev_info(adev->dev, "use vbios provided pptable\n");
397 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
400 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
406 *size = atom_table_size;
411 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
414 const struct smc_firmware_header_v1_0 *hdr;
415 struct amdgpu_device *adev = smu->adev;
416 uint16_t version_major, version_minor;
419 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
423 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
425 version_major = le16_to_cpu(hdr->header.header_version_major);
426 version_minor = le16_to_cpu(hdr->header.header_version_minor);
427 if (version_major != 2) {
428 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
429 version_major, version_minor);
433 switch (version_minor) {
435 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
438 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
448 int smu_v13_0_setup_pptable(struct smu_context *smu)
450 struct amdgpu_device *adev = smu->adev;
451 uint32_t size = 0, pptable_id = 0;
455 /* override pptable_id from driver parameter */
456 if (amdgpu_smu_pptable_id >= 0) {
457 pptable_id = amdgpu_smu_pptable_id;
458 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
460 pptable_id = smu->smu_table.boot_values.pp_table_id;
463 * Temporary solution for SMU V13.0.0 with SCPM disabled:
464 * - use 3664 or 3683 on request
465 * - use 3664 when pptable_id is 0
466 * TODO: drop these when the pptable carried in vbios is ready.
468 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
469 switch (pptable_id) {
477 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
483 /* force using vbios pptable in sriov mode */
484 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
485 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
487 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
492 if (!smu->smu_table.power_play_table)
493 smu->smu_table.power_play_table = table;
494 if (!smu->smu_table.power_play_table_size)
495 smu->smu_table.power_play_table_size = size;
500 int smu_v13_0_init_smc_tables(struct smu_context *smu)
502 struct smu_table_context *smu_table = &smu->smu_table;
503 struct smu_table *tables = smu_table->tables;
506 smu_table->driver_pptable =
507 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
508 if (!smu_table->driver_pptable) {
513 smu_table->max_sustainable_clocks =
514 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
515 if (!smu_table->max_sustainable_clocks) {
520 /* Aldebaran does not support OVERDRIVE */
521 if (tables[SMU_TABLE_OVERDRIVE].size) {
522 smu_table->overdrive_table =
523 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
524 if (!smu_table->overdrive_table) {
529 smu_table->boot_overdrive_table =
530 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
531 if (!smu_table->boot_overdrive_table) {
537 smu_table->combo_pptable =
538 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
539 if (!smu_table->combo_pptable) {
547 kfree(smu_table->boot_overdrive_table);
549 kfree(smu_table->overdrive_table);
551 kfree(smu_table->max_sustainable_clocks);
553 kfree(smu_table->driver_pptable);
558 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
560 struct smu_table_context *smu_table = &smu->smu_table;
561 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
563 kfree(smu_table->gpu_metrics_table);
564 kfree(smu_table->combo_pptable);
565 kfree(smu_table->boot_overdrive_table);
566 kfree(smu_table->overdrive_table);
567 kfree(smu_table->max_sustainable_clocks);
568 kfree(smu_table->driver_pptable);
569 smu_table->gpu_metrics_table = NULL;
570 smu_table->combo_pptable = NULL;
571 smu_table->boot_overdrive_table = NULL;
572 smu_table->overdrive_table = NULL;
573 smu_table->max_sustainable_clocks = NULL;
574 smu_table->driver_pptable = NULL;
575 kfree(smu_table->hardcode_pptable);
576 smu_table->hardcode_pptable = NULL;
578 kfree(smu_table->ecc_table);
579 kfree(smu_table->metrics_table);
580 kfree(smu_table->watermarks_table);
581 smu_table->ecc_table = NULL;
582 smu_table->metrics_table = NULL;
583 smu_table->watermarks_table = NULL;
584 smu_table->metrics_time = 0;
586 kfree(smu_dpm->dpm_context);
587 kfree(smu_dpm->golden_dpm_context);
588 kfree(smu_dpm->dpm_current_power_state);
589 kfree(smu_dpm->dpm_request_power_state);
590 smu_dpm->dpm_context = NULL;
591 smu_dpm->golden_dpm_context = NULL;
592 smu_dpm->dpm_context_size = 0;
593 smu_dpm->dpm_current_power_state = NULL;
594 smu_dpm->dpm_request_power_state = NULL;
599 int smu_v13_0_init_power(struct smu_context *smu)
601 struct smu_power_context *smu_power = &smu->smu_power;
603 if (smu_power->power_context || smu_power->power_context_size != 0)
606 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
608 if (!smu_power->power_context)
610 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
615 int smu_v13_0_fini_power(struct smu_context *smu)
617 struct smu_power_context *smu_power = &smu->smu_power;
619 if (!smu_power->power_context || smu_power->power_context_size == 0)
622 kfree(smu_power->power_context);
623 smu_power->power_context = NULL;
624 smu_power->power_context_size = 0;
629 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
634 struct atom_common_table_header *header;
635 struct atom_firmware_info_v3_4 *v_3_4;
636 struct atom_firmware_info_v3_3 *v_3_3;
637 struct atom_firmware_info_v3_1 *v_3_1;
638 struct atom_smu_info_v3_6 *smu_info_v3_6;
639 struct atom_smu_info_v4_0 *smu_info_v4_0;
641 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
644 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
645 (uint8_t **)&header);
649 if (header->format_revision != 3) {
650 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
654 switch (header->content_revision) {
658 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
659 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
660 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
661 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
662 smu->smu_table.boot_values.socclk = 0;
663 smu->smu_table.boot_values.dcefclk = 0;
664 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
665 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
666 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
667 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
668 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
669 smu->smu_table.boot_values.pp_table_id = 0;
672 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
673 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
674 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
675 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
676 smu->smu_table.boot_values.socclk = 0;
677 smu->smu_table.boot_values.dcefclk = 0;
678 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
679 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
680 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
681 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
682 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
683 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
687 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
688 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
689 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
690 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
691 smu->smu_table.boot_values.socclk = 0;
692 smu->smu_table.boot_values.dcefclk = 0;
693 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
694 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
695 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
696 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
697 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
698 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
702 smu->smu_table.boot_values.format_revision = header->format_revision;
703 smu->smu_table.boot_values.content_revision = header->content_revision;
705 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
707 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
708 (uint8_t **)&header)) {
710 if ((frev == 3) && (crev == 6)) {
711 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
713 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
714 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
715 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
716 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
717 } else if ((frev == 4) && (crev == 0)) {
718 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
720 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
721 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
722 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
723 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
724 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
726 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
727 (uint32_t)frev, (uint32_t)crev);
735 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
737 struct smu_table_context *smu_table = &smu->smu_table;
738 struct smu_table *memory_pool = &smu_table->memory_pool;
741 uint32_t address_low, address_high;
743 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
746 address = memory_pool->mc_address;
747 address_high = (uint32_t)upper_32_bits(address);
748 address_low = (uint32_t)lower_32_bits(address);
750 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
754 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
758 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
759 (uint32_t)memory_pool->size, NULL);
766 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
770 ret = smu_cmn_send_smc_msg_with_param(smu,
771 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
773 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
778 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
780 struct smu_table *driver_table = &smu->smu_table.driver_table;
783 if (driver_table->mc_address) {
784 ret = smu_cmn_send_smc_msg_with_param(smu,
785 SMU_MSG_SetDriverDramAddrHigh,
786 upper_32_bits(driver_table->mc_address),
789 ret = smu_cmn_send_smc_msg_with_param(smu,
790 SMU_MSG_SetDriverDramAddrLow,
791 lower_32_bits(driver_table->mc_address),
798 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
801 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
803 if (tool_table->mc_address) {
804 ret = smu_cmn_send_smc_msg_with_param(smu,
805 SMU_MSG_SetToolsDramAddrHigh,
806 upper_32_bits(tool_table->mc_address),
809 ret = smu_cmn_send_smc_msg_with_param(smu,
810 SMU_MSG_SetToolsDramAddrLow,
811 lower_32_bits(tool_table->mc_address),
818 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
822 if (!smu->pm_enabled)
825 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
830 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
832 struct smu_feature *feature = &smu->smu_feature;
834 uint32_t feature_mask[2];
836 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
837 feature->feature_num < 64)
840 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
842 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
843 feature_mask[1], NULL);
847 return smu_cmn_send_smc_msg_with_param(smu,
848 SMU_MSG_SetAllowedFeaturesMaskLow,
853 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
856 struct amdgpu_device *adev = smu->adev;
858 switch (adev->ip_versions[MP1_HWIP][0]) {
859 case IP_VERSION(13, 0, 0):
860 case IP_VERSION(13, 0, 1):
861 case IP_VERSION(13, 0, 3):
862 case IP_VERSION(13, 0, 4):
863 case IP_VERSION(13, 0, 5):
864 case IP_VERSION(13, 0, 7):
865 case IP_VERSION(13, 0, 8):
866 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
869 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
871 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
880 int smu_v13_0_system_features_control(struct smu_context *smu,
883 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
884 SMU_MSG_DisableAllSmuFeatures), NULL);
887 int smu_v13_0_notify_display_change(struct smu_context *smu)
891 if (!smu->pm_enabled)
894 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
895 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
896 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
902 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
903 enum smu_clk_type clock_select)
908 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
909 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
912 clk_id = smu_cmn_to_asic_specific_index(smu,
913 CMN2ASIC_MAPPING_CLK,
918 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
919 clk_id << 16, clock);
921 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
928 /* if DC limit is zero, return AC limit */
929 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
930 clk_id << 16, clock);
932 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
939 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
941 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
942 smu->smu_table.max_sustainable_clocks;
945 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
946 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
947 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
948 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
949 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
950 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
952 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
953 ret = smu_v13_0_get_max_sustainable_clock(smu,
954 &(max_sustainable_clocks->uclock),
957 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
963 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
964 ret = smu_v13_0_get_max_sustainable_clock(smu,
965 &(max_sustainable_clocks->soc_clock),
968 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
974 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
975 ret = smu_v13_0_get_max_sustainable_clock(smu,
976 &(max_sustainable_clocks->dcef_clock),
979 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
984 ret = smu_v13_0_get_max_sustainable_clock(smu,
985 &(max_sustainable_clocks->display_clock),
988 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
992 ret = smu_v13_0_get_max_sustainable_clock(smu,
993 &(max_sustainable_clocks->phy_clock),
996 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1000 ret = smu_v13_0_get_max_sustainable_clock(smu,
1001 &(max_sustainable_clocks->pixel_clock),
1004 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1010 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1011 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1016 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1017 uint32_t *power_limit)
1022 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1025 power_src = smu_cmn_to_asic_specific_index(smu,
1026 CMN2ASIC_MAPPING_PWR,
1027 smu->adev->pm.ac_power ?
1028 SMU_POWER_SOURCE_AC :
1029 SMU_POWER_SOURCE_DC);
1033 ret = smu_cmn_send_smc_msg_with_param(smu,
1034 SMU_MSG_GetPptLimit,
1038 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1043 int smu_v13_0_set_power_limit(struct smu_context *smu,
1044 enum smu_ppt_limit_type limit_type,
1049 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1052 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1053 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1057 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1059 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1063 smu->current_power_limit = limit;
1068 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1070 if (smu->smu_table.thermal_controller_type)
1071 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1076 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1078 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1081 static uint16_t convert_to_vddc(uint8_t vid)
1083 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1086 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1088 struct amdgpu_device *adev = smu->adev;
1089 uint32_t vdd = 0, val_vid = 0;
1093 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1094 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1095 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1097 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1106 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1107 struct pp_display_clock_request
1110 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1112 enum smu_clk_type clk_select = 0;
1113 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1115 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1116 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1118 case amd_pp_dcef_clock:
1119 clk_select = SMU_DCEFCLK;
1121 case amd_pp_disp_clock:
1122 clk_select = SMU_DISPCLK;
1124 case amd_pp_pixel_clock:
1125 clk_select = SMU_PIXCLK;
1127 case amd_pp_phy_clock:
1128 clk_select = SMU_PHYCLK;
1130 case amd_pp_mem_clock:
1131 clk_select = SMU_UCLK;
1134 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1142 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1145 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1147 if(clk_select == SMU_UCLK)
1148 smu->hard_min_uclk_req_from_dal = clk_freq;
1155 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1157 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1158 return AMD_FAN_CTRL_MANUAL;
1160 return AMD_FAN_CTRL_AUTO;
1164 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1168 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1171 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1173 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1174 __func__, (auto_fan_control ? "Start" : "Stop"));
1180 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1182 struct amdgpu_device *adev = smu->adev;
1184 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1185 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1186 CG_FDO_CTRL2, TMIN, 0));
1187 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1188 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1189 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1194 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1197 struct amdgpu_device *adev = smu->adev;
1198 uint32_t duty100, duty;
1201 speed = MIN(speed, 255);
1203 if (smu_v13_0_auto_fan_control(smu, 0))
1206 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1207 CG_FDO_CTRL1, FMAX_DUTY100);
1211 tmp64 = (uint64_t)speed * duty100;
1213 duty = (uint32_t)tmp64;
1215 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1216 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1217 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1219 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1223 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1229 case AMD_FAN_CTRL_NONE:
1230 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1232 case AMD_FAN_CTRL_MANUAL:
1233 ret = smu_v13_0_auto_fan_control(smu, 0);
1235 case AMD_FAN_CTRL_AUTO:
1236 ret = smu_v13_0_auto_fan_control(smu, 1);
1243 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1250 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1253 struct amdgpu_device *adev = smu->adev;
1254 uint32_t tach_period, crystal_clock_freq;
1260 ret = smu_v13_0_auto_fan_control(smu, 0);
1264 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1265 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1266 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1267 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1268 CG_TACH_CTRL, TARGET_PERIOD,
1271 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1274 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1278 ret = smu_cmn_send_smc_msg_with_param(smu,
1279 SMU_MSG_SetXgmiMode,
1280 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1285 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1286 struct amdgpu_irq_src *source,
1288 enum amdgpu_interrupt_state state)
1290 struct smu_context *smu = adev->powerplay.pp_handle;
1295 case AMDGPU_IRQ_STATE_DISABLE:
1297 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1298 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1299 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1300 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1302 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1304 /* For MP1 SW irqs */
1305 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1306 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1307 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1310 case AMDGPU_IRQ_STATE_ENABLE:
1312 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1313 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1314 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1315 smu->thermal_range.software_shutdown_temp);
1317 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1318 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1319 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1320 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1321 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1322 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1323 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1324 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1325 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1327 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1328 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1329 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1330 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1332 /* For MP1 SW irqs */
1333 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1334 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1335 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1336 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1338 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1339 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1340 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1350 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1352 return smu_cmn_send_smc_msg(smu,
1353 SMU_MSG_ReenableAcDcInterrupt,
1357 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1358 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1359 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1361 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1362 struct amdgpu_irq_src *source,
1363 struct amdgpu_iv_entry *entry)
1365 struct smu_context *smu = adev->powerplay.pp_handle;
1366 uint32_t client_id = entry->client_id;
1367 uint32_t src_id = entry->src_id;
1369 * ctxid is used to distinguish different
1370 * events for SMCToHost interrupt.
1372 uint32_t ctxid = entry->src_data[0];
1375 if (client_id == SOC15_IH_CLIENTID_THM) {
1377 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1378 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1380 * SW CTF just occurred.
1381 * Try to do a graceful shutdown to prevent further damage.
1383 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1384 orderly_poweroff(true);
1386 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1387 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1390 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1394 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1395 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1397 * HW CTF just occurred. Shutdown to prevent further damage.
1399 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1400 orderly_poweroff(true);
1401 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1402 if (src_id == 0xfe) {
1403 /* ACK SMUToHost interrupt */
1404 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1405 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1406 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1410 dev_dbg(adev->dev, "Switched to AC mode!\n");
1411 smu_v13_0_ack_ac_dc_interrupt(smu);
1414 dev_dbg(adev->dev, "Switched to DC mode!\n");
1415 smu_v13_0_ack_ac_dc_interrupt(smu);
1419 * Increment the throttle interrupt counter
1421 atomic64_inc(&smu->throttle_int_counter);
1423 if (!atomic_read(&adev->throttling_logging_enabled))
1426 if (__ratelimit(&adev->throttling_logging_rs))
1427 schedule_work(&smu->throttling_logging_work);
1437 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1439 .set = smu_v13_0_set_irq_state,
1440 .process = smu_v13_0_irq_process,
1443 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1445 struct amdgpu_device *adev = smu->adev;
1446 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1449 irq_src->num_types = 1;
1450 irq_src->funcs = &smu_v13_0_irq_funcs;
1452 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1453 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1458 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1459 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1464 /* Register CTF(GPIO_19) interrupt */
1465 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1466 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1471 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1480 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1481 struct pp_smu_nv_clock_table *max_clocks)
1483 struct smu_table_context *table_context = &smu->smu_table;
1484 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1486 if (!max_clocks || !table_context->max_sustainable_clocks)
1489 sustainable_clocks = table_context->max_sustainable_clocks;
1491 max_clocks->dcfClockInKhz =
1492 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1493 max_clocks->displayClockInKhz =
1494 (unsigned int) sustainable_clocks->display_clock * 1000;
1495 max_clocks->phyClockInKhz =
1496 (unsigned int) sustainable_clocks->phy_clock * 1000;
1497 max_clocks->pixelClockInKhz =
1498 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1499 max_clocks->uClockInKhz =
1500 (unsigned int) sustainable_clocks->uclock * 1000;
1501 max_clocks->socClockInKhz =
1502 (unsigned int) sustainable_clocks->soc_clock * 1000;
1503 max_clocks->dscClockInKhz = 0;
1504 max_clocks->dppClockInKhz = 0;
1505 max_clocks->fabricClockInKhz = 0;
1510 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1514 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1519 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1524 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1525 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1530 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1536 case SMU_EVENT_RESET_COMPLETE:
1537 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1546 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1547 uint32_t *min, uint32_t *max)
1549 int ret = 0, clk_id = 0;
1551 uint32_t clock_limit;
1553 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1557 clock_limit = smu->smu_table.boot_values.uclk;
1561 clock_limit = smu->smu_table.boot_values.gfxclk;
1564 clock_limit = smu->smu_table.boot_values.socclk;
1571 /* clock in Mhz unit */
1573 *min = clock_limit / 100;
1575 *max = clock_limit / 100;
1580 clk_id = smu_cmn_to_asic_specific_index(smu,
1581 CMN2ASIC_MAPPING_CLK,
1587 param = (clk_id & 0xffff) << 16;
1590 if (smu->adev->pm.ac_power)
1591 ret = smu_cmn_send_smc_msg_with_param(smu,
1592 SMU_MSG_GetMaxDpmFreq,
1596 ret = smu_cmn_send_smc_msg_with_param(smu,
1597 SMU_MSG_GetDcModeMaxDpmFreq,
1605 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1614 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1615 enum smu_clk_type clk_type,
1619 int ret = 0, clk_id = 0;
1622 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1625 clk_id = smu_cmn_to_asic_specific_index(smu,
1626 CMN2ASIC_MAPPING_CLK,
1632 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1640 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1641 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1651 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1652 enum smu_clk_type clk_type,
1656 int ret = 0, clk_id = 0;
1659 if (min <= 0 && max <= 0)
1662 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1665 clk_id = smu_cmn_to_asic_specific_index(smu,
1666 CMN2ASIC_MAPPING_CLK,
1672 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1673 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1680 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1681 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1690 int smu_v13_0_set_performance_level(struct smu_context *smu,
1691 enum amd_dpm_forced_level level)
1693 struct smu_13_0_dpm_context *dpm_context =
1694 smu->smu_dpm.dpm_context;
1695 struct smu_13_0_dpm_table *gfx_table =
1696 &dpm_context->dpm_tables.gfx_table;
1697 struct smu_13_0_dpm_table *mem_table =
1698 &dpm_context->dpm_tables.uclk_table;
1699 struct smu_13_0_dpm_table *soc_table =
1700 &dpm_context->dpm_tables.soc_table;
1701 struct smu_13_0_dpm_table *vclk_table =
1702 &dpm_context->dpm_tables.vclk_table;
1703 struct smu_13_0_dpm_table *dclk_table =
1704 &dpm_context->dpm_tables.dclk_table;
1705 struct smu_13_0_dpm_table *fclk_table =
1706 &dpm_context->dpm_tables.fclk_table;
1707 struct smu_umd_pstate_table *pstate_table =
1709 struct amdgpu_device *adev = smu->adev;
1710 uint32_t sclk_min = 0, sclk_max = 0;
1711 uint32_t mclk_min = 0, mclk_max = 0;
1712 uint32_t socclk_min = 0, socclk_max = 0;
1713 uint32_t vclk_min = 0, vclk_max = 0;
1714 uint32_t dclk_min = 0, dclk_max = 0;
1715 uint32_t fclk_min = 0, fclk_max = 0;
1719 case AMD_DPM_FORCED_LEVEL_HIGH:
1720 sclk_min = sclk_max = gfx_table->max;
1721 mclk_min = mclk_max = mem_table->max;
1722 socclk_min = socclk_max = soc_table->max;
1723 vclk_min = vclk_max = vclk_table->max;
1724 dclk_min = dclk_max = dclk_table->max;
1725 fclk_min = fclk_max = fclk_table->max;
1727 case AMD_DPM_FORCED_LEVEL_LOW:
1728 sclk_min = sclk_max = gfx_table->min;
1729 mclk_min = mclk_max = mem_table->min;
1730 socclk_min = socclk_max = soc_table->min;
1731 vclk_min = vclk_max = vclk_table->min;
1732 dclk_min = dclk_max = dclk_table->min;
1733 fclk_min = fclk_max = fclk_table->min;
1735 case AMD_DPM_FORCED_LEVEL_AUTO:
1736 sclk_min = gfx_table->min;
1737 sclk_max = gfx_table->max;
1738 mclk_min = mem_table->min;
1739 mclk_max = mem_table->max;
1740 socclk_min = soc_table->min;
1741 socclk_max = soc_table->max;
1742 vclk_min = vclk_table->min;
1743 vclk_max = vclk_table->max;
1744 dclk_min = dclk_table->min;
1745 dclk_max = dclk_table->max;
1746 fclk_min = fclk_table->min;
1747 fclk_max = fclk_table->max;
1749 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1750 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1751 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1752 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1753 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1754 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1755 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1757 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1758 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1760 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1761 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1763 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1764 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1765 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1766 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1767 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1768 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1769 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1771 case AMD_DPM_FORCED_LEVEL_MANUAL:
1772 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1775 dev_err(adev->dev, "Invalid performance level %d\n", level);
1780 * Unset those settings for SMU 13.0.2. As soft limits settings
1781 * for those clock domains are not supported.
1783 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1784 mclk_min = mclk_max = 0;
1785 socclk_min = socclk_max = 0;
1786 vclk_min = vclk_max = 0;
1787 dclk_min = dclk_max = 0;
1788 fclk_min = fclk_max = 0;
1791 if (sclk_min && sclk_max) {
1792 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1799 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1800 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1803 if (mclk_min && mclk_max) {
1804 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1811 pstate_table->uclk_pstate.curr.min = mclk_min;
1812 pstate_table->uclk_pstate.curr.max = mclk_max;
1815 if (socclk_min && socclk_max) {
1816 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1823 pstate_table->socclk_pstate.curr.min = socclk_min;
1824 pstate_table->socclk_pstate.curr.max = socclk_max;
1827 if (vclk_min && vclk_max) {
1828 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1829 if (adev->vcn.harvest_config & (1 << i))
1831 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1832 i ? SMU_VCLK1 : SMU_VCLK,
1838 pstate_table->vclk_pstate.curr.min = vclk_min;
1839 pstate_table->vclk_pstate.curr.max = vclk_max;
1842 if (dclk_min && dclk_max) {
1843 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1844 if (adev->vcn.harvest_config & (1 << i))
1846 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1847 i ? SMU_DCLK1 : SMU_DCLK,
1853 pstate_table->dclk_pstate.curr.min = dclk_min;
1854 pstate_table->dclk_pstate.curr.max = dclk_max;
1857 if (fclk_min && fclk_max) {
1858 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1865 pstate_table->fclk_pstate.curr.min = fclk_min;
1866 pstate_table->fclk_pstate.curr.max = fclk_max;
1872 int smu_v13_0_set_power_source(struct smu_context *smu,
1873 enum smu_power_src_type power_src)
1877 pwr_source = smu_cmn_to_asic_specific_index(smu,
1878 CMN2ASIC_MAPPING_PWR,
1879 (uint32_t)power_src);
1883 return smu_cmn_send_smc_msg_with_param(smu,
1884 SMU_MSG_NotifyPowerSource,
1889 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1890 enum smu_clk_type clk_type,
1894 int ret = 0, clk_id = 0;
1900 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1903 clk_id = smu_cmn_to_asic_specific_index(smu,
1904 CMN2ASIC_MAPPING_CLK,
1909 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1911 ret = smu_cmn_send_smc_msg_with_param(smu,
1912 SMU_MSG_GetDpmFreqByIndex,
1918 *value = *value & 0x7fffffff;
1923 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1924 enum smu_clk_type clk_type,
1929 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1930 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1931 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1937 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1938 enum smu_clk_type clk_type,
1939 bool *is_fine_grained_dpm)
1941 int ret = 0, clk_id = 0;
1945 if (!is_fine_grained_dpm)
1948 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1951 clk_id = smu_cmn_to_asic_specific_index(smu,
1952 CMN2ASIC_MAPPING_CLK,
1957 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1959 ret = smu_cmn_send_smc_msg_with_param(smu,
1960 SMU_MSG_GetDpmFreqByIndex,
1967 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1968 * now, we un-support it
1970 *is_fine_grained_dpm = value & 0x80000000;
1975 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1976 enum smu_clk_type clk_type,
1977 struct smu_13_0_dpm_table *single_dpm_table)
1983 ret = smu_v13_0_get_dpm_level_count(smu,
1985 &single_dpm_table->count);
1987 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1991 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1992 ret = smu_v13_0_get_fine_grained_status(smu,
1994 &single_dpm_table->is_fine_grained);
1996 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2001 for (i = 0; i < single_dpm_table->count; i++) {
2002 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2007 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2011 single_dpm_table->dpm_levels[i].value = clk;
2012 single_dpm_table->dpm_levels[i].enabled = true;
2015 single_dpm_table->min = clk;
2016 else if (i == single_dpm_table->count - 1)
2017 single_dpm_table->max = clk;
2023 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2024 enum smu_clk_type clk_type,
2025 uint32_t *min_value,
2026 uint32_t *max_value)
2028 uint32_t level_count = 0;
2031 if (!min_value && !max_value)
2035 /* by default, level 0 clock value as min value */
2036 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2045 ret = smu_v13_0_get_dpm_level_count(smu,
2051 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2062 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2064 struct amdgpu_device *adev = smu->adev;
2066 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2067 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2068 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2071 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2073 uint32_t width_level;
2075 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2076 if (width_level > LINK_WIDTH_MAX)
2079 return link_width[width_level];
2082 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2084 struct amdgpu_device *adev = smu->adev;
2086 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2087 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2088 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2091 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2093 uint32_t speed_level;
2095 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2096 if (speed_level > LINK_SPEED_MAX)
2099 return link_speed[speed_level];
2102 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2105 struct amdgpu_device *adev = smu->adev;
2108 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2109 if (adev->vcn.harvest_config & (1 << i))
2112 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2113 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2122 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2125 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2126 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2130 int smu_v13_0_run_btc(struct smu_context *smu)
2134 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2136 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2141 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2144 struct amdgpu_device *adev = smu->adev;
2147 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2148 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2150 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2155 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2156 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2158 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2163 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2164 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2166 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2171 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2172 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2174 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2179 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2180 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2182 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2187 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2188 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2190 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2195 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2196 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2198 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2203 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2204 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2206 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2214 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2219 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2220 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2225 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2227 struct smu_baco_context *smu_baco = &smu->smu_baco;
2229 if (amdgpu_sriov_vf(smu->adev) ||
2230 !smu_baco->platform_support)
2233 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2234 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2240 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2242 struct smu_baco_context *smu_baco = &smu->smu_baco;
2244 return smu_baco->state;
2247 int smu_v13_0_baco_set_state(struct smu_context *smu,
2248 enum smu_baco_state state)
2250 struct smu_baco_context *smu_baco = &smu->smu_baco;
2251 struct amdgpu_device *adev = smu->adev;
2254 if (smu_v13_0_baco_get_state(smu) == state)
2257 if (state == SMU_BACO_STATE_ENTER) {
2258 ret = smu_cmn_send_smc_msg_with_param(smu,
2263 ret = smu_cmn_send_smc_msg(smu,
2269 /* clear vbios scratch 6 and 7 for coming asic reinit */
2270 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2271 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2275 smu_baco->state = state;
2280 int smu_v13_0_baco_enter(struct smu_context *smu)
2284 ret = smu_v13_0_baco_set_state(smu,
2285 SMU_BACO_STATE_ENTER);
2294 int smu_v13_0_baco_exit(struct smu_context *smu)
2296 return smu_v13_0_baco_set_state(smu,
2297 SMU_BACO_STATE_EXIT);
2300 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2301 enum PP_OD_DPM_TABLE_COMMAND type,
2302 long input[], uint32_t size)
2304 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2307 /* Only allowed in manual mode */
2308 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2312 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2314 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2318 if (input[0] == 0) {
2319 if (input[1] < smu->gfx_default_hard_min_freq) {
2320 dev_warn(smu->adev->dev,
2321 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2322 input[1], smu->gfx_default_hard_min_freq);
2325 smu->gfx_actual_hard_min_freq = input[1];
2326 } else if (input[0] == 1) {
2327 if (input[1] > smu->gfx_default_soft_max_freq) {
2328 dev_warn(smu->adev->dev,
2329 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2330 input[1], smu->gfx_default_soft_max_freq);
2333 smu->gfx_actual_soft_max_freq = input[1];
2338 case PP_OD_RESTORE_DEFAULT_TABLE:
2340 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2343 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2344 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2346 case PP_OD_COMMIT_DPM_TABLE:
2348 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2351 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2352 dev_err(smu->adev->dev,
2353 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2354 smu->gfx_actual_hard_min_freq,
2355 smu->gfx_actual_soft_max_freq);
2359 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2360 smu->gfx_actual_hard_min_freq,
2363 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2367 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2368 smu->gfx_actual_soft_max_freq,
2371 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2382 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2384 struct smu_table_context *smu_table = &smu->smu_table;
2386 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2387 smu_table->clocks_table, false);