drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_dpm.h"
  29 #include "amdgpu_smu.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_atombios.h"
  33 #include "smu_v13_0.h"
  34 #include "smu13_driver_if_aldebaran.h"
  35 #include "soc15_common.h"
  36 #include "atom.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  61         [smu_feature] = {1, (aldebaran_feature)}
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  66                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  67                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  68                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  71                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  73
  74 /* possible frequency drift (1Mhz) */
  75 #define EPSILON                         1
  76
  77 #define smnPCIE_ESM_CTRL                        0x111003D0
  78
  79 /*
  80  * SMU support ECCTABLE since version 68.42.0,
  81  * use this to check ECCTALE feature whether support
  82  */
  83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
  84
  85 /*
  86  * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
  87  * use this to check mca_ceumc_addr record whether support
  88  */
  89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
  90
  91 /*
  92  * SMU support BAD CHENNEL info MSG since version 68.51.00,
  93  * use this to check ECCTALE feature whether support
  94  */
  95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
  96
  97 static const struct smu_temperature_range smu13_thermal_policy[] = {
  98         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  99         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
 100 };
 101
 102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
 103         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 104         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 105         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 106         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 107         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 108         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        1),
 109         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       1),
 110         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 111         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 112         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 113         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 114         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 115         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 116         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 117         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 118         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 119         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 120         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 121         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 122         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 123         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 124         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 125         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 126         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 127         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 128         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 129         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 130         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 131         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 132         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 133         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 134         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 135         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 136         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 137         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 138         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 139         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 140         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 141         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 142         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 143         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 144         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 145         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 146         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 147         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 148         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 149         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 150         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 151         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 152         MSG_MAP(BoardPowerCalibration,               PPSMC_MSG_BoardPowerCalibration,           0),
 153         MSG_MAP(HeavySBR,                            PPSMC_MSG_HeavySBR,                        0),
 154         MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel,   PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0),
 155 };
 156
 157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 158         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 159         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 160         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 161         CLK_MAP(FCLK, PPCLK_FCLK),
 162         CLK_MAP(UCLK, PPCLK_UCLK),
 163         CLK_MAP(MCLK, PPCLK_UCLK),
 164         CLK_MAP(DCLK, PPCLK_DCLK),
 165         CLK_MAP(VCLK, PPCLK_VCLK),
 166         CLK_MAP(LCLK,   PPCLK_LCLK),
 167 };
 168
 169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT,            FEATURE_DATA_CALCULATIONS),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT,                             FEATURE_DPM_XGMI_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 182         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 183         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT,                              FEATURE_DPM_VCN_BIT),
 184         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 185         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 186         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 187         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 188         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 189         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 190         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 191         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 192         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 193         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 194         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 195         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 196         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 197         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 198         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN),
 199         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 200 };
 201
 202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 203         TAB_MAP(PPTABLE),
 204         TAB_MAP(AVFS_PSM_DEBUG),
 205         TAB_MAP(AVFS_FUSE_OVERRIDE),
 206         TAB_MAP(PMSTATUSLOG),
 207         TAB_MAP(SMU_METRICS),
 208         TAB_MAP(DRIVER_SMU_CONFIG),
 209         TAB_MAP(I2C_COMMANDS),
 210         TAB_MAP(ECCINFO),
 211 };
 212
 213 static const uint8_t aldebaran_throttler_map[] = {
 214         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 215         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 216         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 217         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 218         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 219         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 220         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 221         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 222         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 223         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 224         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 225 };
 226
 227 static int aldebaran_tables_init(struct smu_context *smu)
 228 {
 229         struct smu_table_context *smu_table = &smu->smu_table;
 230         struct smu_table *tables = smu_table->tables;
 231
 232         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 233                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 234
 235         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 236                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 237
 238         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 239                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 240
 241         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 242                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 243
 244         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 245                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 246
 247         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 248         if (!smu_table->metrics_table)
 249                 return -ENOMEM;
 250         smu_table->metrics_time = 0;
 251
 252         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 253         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 254         if (!smu_table->gpu_metrics_table) {
 255                 kfree(smu_table->metrics_table);
 256                 return -ENOMEM;
 257         }
 258
 259         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 260         if (!smu_table->ecc_table) {
 261                 kfree(smu_table->metrics_table);
 262                 kfree(smu_table->gpu_metrics_table);
 263                 return -ENOMEM;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 270 {
 271         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 272
 273         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 274                                        GFP_KERNEL);
 275         if (!smu_dpm->dpm_context)
 276                 return -ENOMEM;
 277         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 278
 279         return 0;
 280 }
 281
 282 static int aldebaran_init_smc_tables(struct smu_context *smu)
 283 {
 284         int ret = 0;
 285
 286         ret = aldebaran_tables_init(smu);
 287         if (ret)
 288                 return ret;
 289
 290         ret = aldebaran_allocate_dpm_context(smu);
 291         if (ret)
 292                 return ret;
 293
 294         return smu_v13_0_init_smc_tables(smu);
 295 }
 296
 297 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 298                                               uint32_t *feature_mask, uint32_t num)
 299 {
 300         if (num > 2)
 301                 return -EINVAL;
 302
 303         /* pptable will handle the features to enable */
 304         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 305
 306         return 0;
 307 }
 308
 309 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 310 {
 311         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 312         struct smu_13_0_dpm_table *dpm_table = NULL;
 313         PPTable_t *pptable = smu->smu_table.driver_pptable;
 314         int ret = 0;
 315
 316         /* socclk dpm table setup */
 317         dpm_table = &dpm_context->dpm_tables.soc_table;
 318         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 319                 ret = smu_v13_0_set_single_dpm_table(smu,
 320                                                      SMU_SOCCLK,
 321                                                      dpm_table);
 322                 if (ret)
 323                         return ret;
 324         } else {
 325                 dpm_table->count = 1;
 326                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 327                 dpm_table->dpm_levels[0].enabled = true;
 328                 dpm_table->min = dpm_table->dpm_levels[0].value;
 329                 dpm_table->max = dpm_table->dpm_levels[0].value;
 330         }
 331
 332         /* gfxclk dpm table setup */
 333         dpm_table = &dpm_context->dpm_tables.gfx_table;
 334         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 335                 /* in the case of gfxclk, only fine-grained dpm is honored */
 336                 dpm_table->count = 2;
 337                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 338                 dpm_table->dpm_levels[0].enabled = true;
 339                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 340                 dpm_table->dpm_levels[1].enabled = true;
 341                 dpm_table->min = dpm_table->dpm_levels[0].value;
 342                 dpm_table->max = dpm_table->dpm_levels[1].value;
 343         } else {
 344                 dpm_table->count = 1;
 345                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 346                 dpm_table->dpm_levels[0].enabled = true;
 347                 dpm_table->min = dpm_table->dpm_levels[0].value;
 348                 dpm_table->max = dpm_table->dpm_levels[0].value;
 349         }
 350
 351         /* memclk dpm table setup */
 352         dpm_table = &dpm_context->dpm_tables.uclk_table;
 353         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 354                 ret = smu_v13_0_set_single_dpm_table(smu,
 355                                                      SMU_UCLK,
 356                                                      dpm_table);
 357                 if (ret)
 358                         return ret;
 359         } else {
 360                 dpm_table->count = 1;
 361                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 362                 dpm_table->dpm_levels[0].enabled = true;
 363                 dpm_table->min = dpm_table->dpm_levels[0].value;
 364                 dpm_table->max = dpm_table->dpm_levels[0].value;
 365         }
 366
 367         /* fclk dpm table setup */
 368         dpm_table = &dpm_context->dpm_tables.fclk_table;
 369         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 370                 ret = smu_v13_0_set_single_dpm_table(smu,
 371                                                      SMU_FCLK,
 372                                                      dpm_table);
 373                 if (ret)
 374                         return ret;
 375         } else {
 376                 dpm_table->count = 1;
 377                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 378                 dpm_table->dpm_levels[0].enabled = true;
 379                 dpm_table->min = dpm_table->dpm_levels[0].value;
 380                 dpm_table->max = dpm_table->dpm_levels[0].value;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 387 {
 388         struct smu_table_context *table_context = &smu->smu_table;
 389         struct smu_13_0_powerplay_table *powerplay_table =
 390                 table_context->power_play_table;
 391
 392         table_context->thermal_controller_type =
 393                 powerplay_table->thermal_controller_type;
 394
 395         return 0;
 396 }
 397
 398 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 399 {
 400         struct smu_table_context *table_context = &smu->smu_table;
 401         struct smu_13_0_powerplay_table *powerplay_table =
 402                 table_context->power_play_table;
 403         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 404                sizeof(PPTable_t));
 405
 406         return 0;
 407 }
 408
 409 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 410 {
 411         struct smu_table_context *table_context = &smu->smu_table;
 412         PPTable_t *smc_pptable = table_context->driver_pptable;
 413         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 414         int index, ret;
 415
 416         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 417                                            smc_dpm_info);
 418
 419         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 420                                       (uint8_t **)&smc_dpm_table);
 421         if (ret)
 422                 return ret;
 423
 424         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 425                         smc_dpm_table->table_header.format_revision,
 426                         smc_dpm_table->table_header.content_revision);
 427
 428         if ((smc_dpm_table->table_header.format_revision == 4) &&
 429             (smc_dpm_table->table_header.content_revision == 10))
 430                 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
 431                                     smc_dpm_table, GfxMaxCurrent);
 432         return 0;
 433 }
 434
 435 static int aldebaran_setup_pptable(struct smu_context *smu)
 436 {
 437         int ret = 0;
 438
 439         /* VBIOS pptable is the first choice */
 440         smu->smu_table.boot_values.pp_table_id = 0;
 441
 442         ret = smu_v13_0_setup_pptable(smu);
 443         if (ret)
 444                 return ret;
 445
 446         ret = aldebaran_store_powerplay_table(smu);
 447         if (ret)
 448                 return ret;
 449
 450         ret = aldebaran_append_powerplay_table(smu);
 451         if (ret)
 452                 return ret;
 453
 454         ret = aldebaran_check_powerplay_table(smu);
 455         if (ret)
 456                 return ret;
 457
 458         return ret;
 459 }
 460
 461 static bool aldebaran_is_primary(struct smu_context *smu)
 462 {
 463         struct amdgpu_device *adev = smu->adev;
 464
 465         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 466                 return adev->smuio.funcs->get_die_id(adev) == 0;
 467
 468         return true;
 469 }
 470
 471 static int aldebaran_run_board_btc(struct smu_context *smu)
 472 {
 473         int ret;
 474
 475         if (!aldebaran_is_primary(smu))
 476                 return 0;
 477
 478         if (smu->smc_fw_version <= 0x00441d00)
 479                 return 0;
 480
 481         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
 482         if (ret)
 483                 dev_err(smu->adev->dev, "Board power calibration failed!\n");
 484
 485         return ret;
 486 }
 487
 488 static int aldebaran_run_btc(struct smu_context *smu)
 489 {
 490         int ret;
 491
 492         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 493         if (ret)
 494                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 495         else
 496                 ret = aldebaran_run_board_btc(smu);
 497
 498         return ret;
 499 }
 500
 501 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 502 {
 503         struct smu_13_0_dpm_context *dpm_context =
 504                 smu->smu_dpm.dpm_context;
 505         struct smu_13_0_dpm_table *gfx_table =
 506                 &dpm_context->dpm_tables.gfx_table;
 507         struct smu_13_0_dpm_table *mem_table =
 508                 &dpm_context->dpm_tables.uclk_table;
 509         struct smu_13_0_dpm_table *soc_table =
 510                 &dpm_context->dpm_tables.soc_table;
 511         struct smu_umd_pstate_table *pstate_table =
 512                 &smu->pstate_table;
 513
 514         pstate_table->gfxclk_pstate.min = gfx_table->min;
 515         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 516         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 517         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 518
 519         pstate_table->uclk_pstate.min = mem_table->min;
 520         pstate_table->uclk_pstate.peak = mem_table->max;
 521         pstate_table->uclk_pstate.curr.min = mem_table->min;
 522         pstate_table->uclk_pstate.curr.max = mem_table->max;
 523
 524         pstate_table->socclk_pstate.min = soc_table->min;
 525         pstate_table->socclk_pstate.peak = soc_table->max;
 526         pstate_table->socclk_pstate.curr.min = soc_table->min;
 527         pstate_table->socclk_pstate.curr.max = soc_table->max;
 528
 529         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 530             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 531             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 532                 pstate_table->gfxclk_pstate.standard =
 533                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 534                 pstate_table->uclk_pstate.standard =
 535                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 536                 pstate_table->socclk_pstate.standard =
 537                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 538         } else {
 539                 pstate_table->gfxclk_pstate.standard =
 540                         pstate_table->gfxclk_pstate.min;
 541                 pstate_table->uclk_pstate.standard =
 542                         pstate_table->uclk_pstate.min;
 543                 pstate_table->socclk_pstate.standard =
 544                         pstate_table->socclk_pstate.min;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static void aldebaran_get_clk_table(struct smu_context *smu,
 551                                     struct pp_clock_levels_with_latency *clocks,
 552                                     struct smu_13_0_dpm_table *dpm_table)
 553 {
 554         uint32_t i;
 555
 556         clocks->num_levels = min_t(uint32_t,
 557                                    dpm_table->count,
 558                                    (uint32_t)PP_MAX_CLOCK_LEVELS);
 559
 560         for (i = 0; i < clocks->num_levels; i++) {
 561                 clocks->data[i].clocks_in_khz =
 562                         dpm_table->dpm_levels[i].value * 1000;
 563                 clocks->data[i].latency_in_us = 0;
 564         }
 565
 566 }
 567
 568 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 569                                          int32_t frequency2)
 570 {
 571         return (abs(frequency1 - frequency2) <= EPSILON);
 572 }
 573
 574 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 575                                           MetricsMember_t member,
 576                                           uint32_t *value)
 577 {
 578         struct smu_table_context *smu_table = &smu->smu_table;
 579         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 580         int ret = 0;
 581
 582         ret = smu_cmn_get_metrics_table(smu,
 583                                         NULL,
 584                                         false);
 585         if (ret)
 586                 return ret;
 587
 588         switch (member) {
 589         case METRICS_CURR_GFXCLK:
 590                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 591                 break;
 592         case METRICS_CURR_SOCCLK:
 593                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 594                 break;
 595         case METRICS_CURR_UCLK:
 596                 *value = metrics->CurrClock[PPCLK_UCLK];
 597                 break;
 598         case METRICS_CURR_VCLK:
 599                 *value = metrics->CurrClock[PPCLK_VCLK];
 600                 break;
 601         case METRICS_CURR_DCLK:
 602                 *value = metrics->CurrClock[PPCLK_DCLK];
 603                 break;
 604         case METRICS_CURR_FCLK:
 605                 *value = metrics->CurrClock[PPCLK_FCLK];
 606                 break;
 607         case METRICS_AVERAGE_GFXCLK:
 608                 *value = metrics->AverageGfxclkFrequency;
 609                 break;
 610         case METRICS_AVERAGE_SOCCLK:
 611                 *value = metrics->AverageSocclkFrequency;
 612                 break;
 613         case METRICS_AVERAGE_UCLK:
 614                 *value = metrics->AverageUclkFrequency;
 615                 break;
 616         case METRICS_AVERAGE_GFXACTIVITY:
 617                 *value = metrics->AverageGfxActivity;
 618                 break;
 619         case METRICS_AVERAGE_MEMACTIVITY:
 620                 *value = metrics->AverageUclkActivity;
 621                 break;
 622         case METRICS_AVERAGE_SOCKETPOWER:
 623                 /* Valid power data is available only from primary die */
 624                 if (aldebaran_is_primary(smu))
 625                         *value = metrics->AverageSocketPower << 8;
 626                 else
 627                         ret = -EOPNOTSUPP;
 628                 break;
 629         case METRICS_TEMPERATURE_EDGE:
 630                 *value = metrics->TemperatureEdge *
 631                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 632                 break;
 633         case METRICS_TEMPERATURE_HOTSPOT:
 634                 *value = metrics->TemperatureHotspot *
 635                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 636                 break;
 637         case METRICS_TEMPERATURE_MEM:
 638                 *value = metrics->TemperatureHBM *
 639                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 640                 break;
 641         case METRICS_TEMPERATURE_VRGFX:
 642                 *value = metrics->TemperatureVrGfx *
 643                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 644                 break;
 645         case METRICS_TEMPERATURE_VRSOC:
 646                 *value = metrics->TemperatureVrSoc *
 647                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 648                 break;
 649         case METRICS_TEMPERATURE_VRMEM:
 650                 *value = metrics->TemperatureVrMem *
 651                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 652                 break;
 653         case METRICS_THROTTLER_STATUS:
 654                 *value = metrics->ThrottlerStatus;
 655                 break;
 656         case METRICS_UNIQUE_ID_UPPER32:
 657                 *value = metrics->PublicSerialNumUpper32;
 658                 break;
 659         case METRICS_UNIQUE_ID_LOWER32:
 660                 *value = metrics->PublicSerialNumLower32;
 661                 break;
 662         default:
 663                 *value = UINT_MAX;
 664                 break;
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 671                                                    enum smu_clk_type clk_type,
 672                                                    uint32_t *value)
 673 {
 674         MetricsMember_t member_type;
 675         int clk_id = 0;
 676
 677         if (!value)
 678                 return -EINVAL;
 679
 680         clk_id = smu_cmn_to_asic_specific_index(smu,
 681                                                 CMN2ASIC_MAPPING_CLK,
 682                                                 clk_type);
 683         if (clk_id < 0)
 684                 return -EINVAL;
 685
 686         switch (clk_id) {
 687         case PPCLK_GFXCLK:
 688                 /*
 689                  * CurrClock[clk_id] can provide accurate
 690                  *   output only when the dpm feature is enabled.
 691                  * We can use Average_* for dpm disabled case.
 692                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 693                  */
 694                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 695                         member_type = METRICS_CURR_GFXCLK;
 696                 else
 697                         member_type = METRICS_AVERAGE_GFXCLK;
 698                 break;
 699         case PPCLK_UCLK:
 700                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 701                         member_type = METRICS_CURR_UCLK;
 702                 else
 703                         member_type = METRICS_AVERAGE_UCLK;
 704                 break;
 705         case PPCLK_SOCCLK:
 706                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 707                         member_type = METRICS_CURR_SOCCLK;
 708                 else
 709                         member_type = METRICS_AVERAGE_SOCCLK;
 710                 break;
 711         case PPCLK_VCLK:
 712                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 713                         member_type = METRICS_CURR_VCLK;
 714                 else
 715                         member_type = METRICS_AVERAGE_VCLK;
 716                 break;
 717         case PPCLK_DCLK:
 718                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 719                         member_type = METRICS_CURR_DCLK;
 720                 else
 721                         member_type = METRICS_AVERAGE_DCLK;
 722                 break;
 723         case PPCLK_FCLK:
 724                 member_type = METRICS_CURR_FCLK;
 725                 break;
 726         default:
 727                 return -EINVAL;
 728         }
 729
 730         return aldebaran_get_smu_metrics_data(smu,
 731                                               member_type,
 732                                               value);
 733 }
 734
 735 static int aldebaran_emit_clk_levels(struct smu_context *smu,
 736                                      enum smu_clk_type type, char *buf, int *offset)
 737 {
 738         int ret = 0;
 739         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 740         struct pp_clock_levels_with_latency clocks;
 741         struct smu_13_0_dpm_table *single_dpm_table;
 742         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 743         struct smu_13_0_dpm_context *dpm_context = NULL;
 744         uint32_t i;
 745         int display_levels;
 746         uint32_t freq_values[3] = {0};
 747         uint32_t min_clk, max_clk, cur_value = 0;
 748         bool freq_match;
 749         unsigned int clock_mhz;
 750         static const char attempt_string[] = "Attempt to get current";
 751
 752         if (amdgpu_ras_intr_triggered()) {
 753                 *offset += sysfs_emit_at(buf, *offset, "unavailable\n");
 754                 return -EBUSY;
 755         }
 756
 757         dpm_context = smu_dpm->dpm_context;
 758
 759         switch (type) {
 760
 761         case SMU_OD_SCLK:
 762                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "GFXCLK");
 763                 fallthrough;
 764         case SMU_SCLK:
 765                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
 766                 if (ret) {
 767                         dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
 768                         return ret;
 769                 }
 770
 771                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 772                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 773
 774                 display_levels = (clocks.num_levels == 1) ? 1 : 2;
 775
 776                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 777                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 778
 779                 freq_values[0] = min_clk;
 780                 freq_values[1] = max_clk;
 781
 782                 /* fine-grained dpm has only 2 levels */
 783                 if (cur_value > min_clk && cur_value < max_clk) {
 784                         display_levels++;
 785                         freq_values[2] = max_clk;
 786                         freq_values[1] = cur_value;
 787                 }
 788                 break;
 789
 790         case SMU_OD_MCLK:
 791                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "MCLK");
 792                 fallthrough;
 793         case SMU_MCLK:
 794                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
 795                 if (ret) {
 796                         dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
 797                         return ret;
 798                 }
 799
 800                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 801                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 802                 break;
 803
 804         case SMU_SOCCLK:
 805                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
 806                 if (ret) {
 807                         dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
 808                         return ret;
 809                 }
 810
 811                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 812                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 813                 break;
 814
 815         case SMU_FCLK:
 816                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
 817                 if (ret) {
 818                         dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
 819                         return ret;
 820                 }
 821
 822                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 823                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 824                 break;
 825
 826         case SMU_VCLK:
 827                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
 828                 if (ret) {
 829                         dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
 830                         return ret;
 831                 }
 832
 833                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 834                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 835                 break;
 836
 837         case SMU_DCLK:
 838                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
 839                 if (ret) {
 840                         dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
 841                         return ret;
 842                 }
 843
 844                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 845                 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 846                 break;
 847
 848         default:
 849                 return -EINVAL;
 850         }
 851
 852         switch (type) {
 853         case SMU_OD_SCLK:
 854         case SMU_SCLK:
 855                 for (i = 0; i < display_levels; i++) {
 856                         clock_mhz = freq_values[i];
 857                         freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value);
 858                         freq_match |= (display_levels == 1);
 859
 860                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", i,
 861                                 clock_mhz,
 862                                 (freq_match) ? "*" : "");
 863                 }
 864                 break;
 865
 866         case SMU_OD_MCLK:
 867         case SMU_MCLK:
 868         case SMU_SOCCLK:
 869         case SMU_FCLK:
 870         case SMU_VCLK:
 871         case SMU_DCLK:
 872                 for (i = 0; i < clocks.num_levels; i++) {
 873                         clock_mhz = clocks.data[i].clocks_in_khz / 1000;
 874                         freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value);
 875                         freq_match |= (clocks.num_levels == 1);
 876
 877                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
 878                                 i, clock_mhz,
 879                                 (freq_match) ? "*" : "");
 880                 }
 881                 break;
 882         default:
 883                 return -EINVAL;
 884         }
 885
 886         return 0;
 887 }
 888
 889 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 890                                       bool max,
 891                                       uint32_t feature_mask,
 892                                       uint32_t level)
 893 {
 894         struct smu_13_0_dpm_context *dpm_context =
 895                 smu->smu_dpm.dpm_context;
 896         uint32_t freq;
 897         int ret = 0;
 898
 899         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 900             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 901                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 902                 ret = smu_cmn_send_smc_msg_with_param(smu,
 903                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 904                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 905                                                       NULL);
 906                 if (ret) {
 907                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 908                                 max ? "max" : "min");
 909                         return ret;
 910                 }
 911         }
 912
 913         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 914             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 915                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 916                 ret = smu_cmn_send_smc_msg_with_param(smu,
 917                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 918                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 919                                                       NULL);
 920                 if (ret) {
 921                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 922                                 max ? "max" : "min");
 923                         return ret;
 924                 }
 925         }
 926
 927         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 928             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 929                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 930                 ret = smu_cmn_send_smc_msg_with_param(smu,
 931                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 932                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 933                                                       NULL);
 934                 if (ret) {
 935                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 936                                 max ? "max" : "min");
 937                         return ret;
 938                 }
 939         }
 940
 941         return ret;
 942 }
 943
 944 static int aldebaran_force_clk_levels(struct smu_context *smu,
 945                                       enum smu_clk_type type, uint32_t mask)
 946 {
 947         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 948         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 949         uint32_t soft_min_level, soft_max_level;
 950         int ret = 0;
 951
 952         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 953         soft_max_level = mask ? (fls(mask) - 1) : 0;
 954
 955         switch (type) {
 956         case SMU_SCLK:
 957                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 958                 if (soft_max_level >= single_dpm_table->count) {
 959                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 960                                 soft_max_level, single_dpm_table->count - 1);
 961                         ret = -EINVAL;
 962                         break;
 963                 }
 964
 965                 ret = aldebaran_upload_dpm_level(smu,
 966                                                  false,
 967                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 968                                                  soft_min_level);
 969                 if (ret) {
 970                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 971                         break;
 972                 }
 973
 974                 ret = aldebaran_upload_dpm_level(smu,
 975                                                  true,
 976                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 977                                                  soft_max_level);
 978                 if (ret)
 979                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 980
 981                 break;
 982
 983         case SMU_MCLK:
 984         case SMU_SOCCLK:
 985         case SMU_FCLK:
 986                 /*
 987                  * Should not arrive here since aldebaran does not
 988                  * support mclk/socclk/fclk softmin/softmax settings
 989                  */
 990                 ret = -EINVAL;
 991                 break;
 992
 993         default:
 994                 break;
 995         }
 996
 997         return ret;
 998 }
 999
1000 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1001                                                    struct smu_temperature_range *range)
1002 {
1003         struct smu_table_context *table_context = &smu->smu_table;
1004         struct smu_13_0_powerplay_table *powerplay_table =
1005                 table_context->power_play_table;
1006         PPTable_t *pptable = smu->smu_table.driver_pptable;
1007
1008         if (!range)
1009                 return -EINVAL;
1010
1011         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1012
1013         range->hotspot_crit_max = pptable->ThotspotLimit *
1014                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1015         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1016                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1017         range->mem_crit_max = pptable->TmemLimit *
1018                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1019         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1020                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1021         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1022
1023         return 0;
1024 }
1025
1026 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1027                                                   enum amd_pp_sensors sensor,
1028                                                   uint32_t *value)
1029 {
1030         int ret = 0;
1031
1032         if (!value)
1033                 return -EINVAL;
1034
1035         switch (sensor) {
1036         case AMDGPU_PP_SENSOR_GPU_LOAD:
1037                 ret = aldebaran_get_smu_metrics_data(smu,
1038                                                      METRICS_AVERAGE_GFXACTIVITY,
1039                                                      value);
1040                 break;
1041         case AMDGPU_PP_SENSOR_MEM_LOAD:
1042                 ret = aldebaran_get_smu_metrics_data(smu,
1043                                                      METRICS_AVERAGE_MEMACTIVITY,
1044                                                      value);
1045                 break;
1046         default:
1047                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1048                 return -EINVAL;
1049         }
1050
1051         return ret;
1052 }
1053
1054 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1055                                              enum amd_pp_sensors sensor,
1056                                              uint32_t *value)
1057 {
1058         int ret = 0;
1059
1060         if (!value)
1061                 return -EINVAL;
1062
1063         switch (sensor) {
1064         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1065                 ret = aldebaran_get_smu_metrics_data(smu,
1066                                                      METRICS_TEMPERATURE_HOTSPOT,
1067                                                      value);
1068                 break;
1069         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1070                 ret = aldebaran_get_smu_metrics_data(smu,
1071                                                      METRICS_TEMPERATURE_EDGE,
1072                                                      value);
1073                 break;
1074         case AMDGPU_PP_SENSOR_MEM_TEMP:
1075                 ret = aldebaran_get_smu_metrics_data(smu,
1076                                                      METRICS_TEMPERATURE_MEM,
1077                                                      value);
1078                 break;
1079         default:
1080                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1081                 return -EINVAL;
1082         }
1083
1084         return ret;
1085 }
1086
1087 static int aldebaran_read_sensor(struct smu_context *smu,
1088                                  enum amd_pp_sensors sensor,
1089                                  void *data, uint32_t *size)
1090 {
1091         int ret = 0;
1092
1093         if (amdgpu_ras_intr_triggered())
1094                 return 0;
1095
1096         if (!data || !size)
1097                 return -EINVAL;
1098
1099         switch (sensor) {
1100         case AMDGPU_PP_SENSOR_MEM_LOAD:
1101         case AMDGPU_PP_SENSOR_GPU_LOAD:
1102                 ret = aldebaran_get_current_activity_percent(smu,
1103                                                              sensor,
1104                                                              (uint32_t *)data);
1105                 *size = 4;
1106                 break;
1107         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1108                 ret = aldebaran_get_smu_metrics_data(smu,
1109                                                      METRICS_AVERAGE_SOCKETPOWER,
1110                                                      (uint32_t *)data);
1111                 *size = 4;
1112                 break;
1113         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1114         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1115         case AMDGPU_PP_SENSOR_MEM_TEMP:
1116                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1117                                                         (uint32_t *)data);
1118                 *size = 4;
1119                 break;
1120         case AMDGPU_PP_SENSOR_GFX_MCLK:
1121                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1122                 /* the output clock frequency in 10K unit */
1123                 *(uint32_t *)data *= 100;
1124                 *size = 4;
1125                 break;
1126         case AMDGPU_PP_SENSOR_GFX_SCLK:
1127                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1128                 *(uint32_t *)data *= 100;
1129                 *size = 4;
1130                 break;
1131         case AMDGPU_PP_SENSOR_VDDGFX:
1132                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1133                 *size = 4;
1134                 break;
1135         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1136         default:
1137                 ret = -EOPNOTSUPP;
1138                 break;
1139         }
1140
1141         return ret;
1142 }
1143
1144 static int aldebaran_get_power_limit(struct smu_context *smu,
1145                                                 uint32_t *current_power_limit,
1146                                                 uint32_t *default_power_limit,
1147                                                 uint32_t *max_power_limit,
1148                                                 uint32_t *min_power_limit)
1149 {
1150         PPTable_t *pptable = smu->smu_table.driver_pptable;
1151         uint32_t power_limit = 0;
1152         int ret;
1153
1154         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1155                 if (current_power_limit)
1156                         *current_power_limit = 0;
1157                 if (default_power_limit)
1158                         *default_power_limit = 0;
1159                 if (max_power_limit)
1160                         *max_power_limit = 0;
1161                 if (min_power_limit)
1162                         *min_power_limit = 0;
1163                 dev_warn(smu->adev->dev,
1164                         "PPT feature is not enabled, power values can't be fetched.");
1165
1166                 return 0;
1167         }
1168
1169         /* Valid power data is available only from primary die.
1170          * For secondary die show the value as 0.
1171          */
1172         if (aldebaran_is_primary(smu)) {
1173                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1174                                            &power_limit);
1175
1176                 if (ret) {
1177                         /* the last hope to figure out the ppt limit */
1178                         if (!pptable) {
1179                                 dev_err(smu->adev->dev,
1180                                         "Cannot get PPT limit due to pptable missing!");
1181                                 return -EINVAL;
1182                         }
1183                         power_limit = pptable->PptLimit;
1184                 }
1185         }
1186
1187         if (current_power_limit)
1188                 *current_power_limit = power_limit;
1189         if (default_power_limit)
1190                 *default_power_limit = power_limit;
1191
1192         if (max_power_limit) {
1193                 if (pptable)
1194                         *max_power_limit = pptable->PptLimit;
1195         }
1196
1197         if (min_power_limit)
1198                 *min_power_limit = 0;
1199
1200         return 0;
1201 }
1202
1203 static int aldebaran_set_power_limit(struct smu_context *smu,
1204                                      enum smu_ppt_limit_type limit_type,
1205                                      uint32_t limit)
1206 {
1207         /* Power limit can be set only through primary die */
1208         if (aldebaran_is_primary(smu))
1209                 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1210
1211         return -EINVAL;
1212 }
1213
1214 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1215 {
1216         int ret;
1217
1218         ret = smu_v13_0_system_features_control(smu, enable);
1219         if (!ret && enable)
1220                 ret = aldebaran_run_btc(smu);
1221
1222         return ret;
1223 }
1224
1225 static int aldebaran_set_performance_level(struct smu_context *smu,
1226                                            enum amd_dpm_forced_level level)
1227 {
1228         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1229         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1230         struct smu_13_0_dpm_table *gfx_table =
1231                 &dpm_context->dpm_tables.gfx_table;
1232         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1233
1234         /* Disable determinism if switching to another mode */
1235         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1236             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1237                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1238                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1239         }
1240
1241         switch (level) {
1242
1243         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1244                 return 0;
1245
1246         case AMD_DPM_FORCED_LEVEL_HIGH:
1247         case AMD_DPM_FORCED_LEVEL_LOW:
1248         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1249         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1250         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1251         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1252         default:
1253                 break;
1254         }
1255
1256         return smu_v13_0_set_performance_level(smu, level);
1257 }
1258
1259 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1260                                           enum smu_clk_type clk_type,
1261                                           uint32_t min,
1262                                           uint32_t max)
1263 {
1264         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1265         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1266         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1267         struct amdgpu_device *adev = smu->adev;
1268         uint32_t min_clk;
1269         uint32_t max_clk;
1270         int ret = 0;
1271
1272         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1273                 return -EINVAL;
1274
1275         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1276                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1277                 return -EINVAL;
1278
1279         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1280                 if (min >= max) {
1281                         dev_err(smu->adev->dev,
1282                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1283                         return -EINVAL;
1284                 }
1285
1286                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1287                     (max == pstate_table->gfxclk_pstate.curr.max))
1288                         return 0;
1289
1290                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1291                                                             min, max);
1292                 if (!ret) {
1293                         pstate_table->gfxclk_pstate.curr.min = min;
1294                         pstate_table->gfxclk_pstate.curr.max = max;
1295                 }
1296
1297                 return ret;
1298         }
1299
1300         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1301                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1302                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1303                         dev_warn(adev->dev,
1304                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1305                         return -EINVAL;
1306                 }
1307
1308                 /* Restore default min/max clocks and enable determinism */
1309                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1310                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1311                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1312                 if (!ret) {
1313                         usleep_range(500, 1000);
1314                         ret = smu_cmn_send_smc_msg_with_param(smu,
1315                                         SMU_MSG_EnableDeterminism,
1316                                         max, NULL);
1317                         if (ret) {
1318                                 dev_err(adev->dev,
1319                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1320                         } else {
1321                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1322                                 pstate_table->gfxclk_pstate.curr.max = max;
1323                         }
1324                 }
1325         }
1326
1327         return ret;
1328 }
1329
1330 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1331                                                         long input[], uint32_t size)
1332 {
1333         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1334         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1335         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1336         uint32_t min_clk;
1337         uint32_t max_clk;
1338         int ret = 0;
1339
1340         /* Only allowed in manual or determinism mode */
1341         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1342                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1343                 return -EINVAL;
1344
1345         switch (type) {
1346         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1347                 if (size != 2) {
1348                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1349                         return -EINVAL;
1350                 }
1351
1352                 if (input[0] == 0) {
1353                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1354                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1355                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1356                                 pstate_table->gfxclk_pstate.custom.min =
1357                                         pstate_table->gfxclk_pstate.curr.min;
1358                                 return -EINVAL;
1359                         }
1360
1361                         pstate_table->gfxclk_pstate.custom.min = input[1];
1362                 } else if (input[0] == 1) {
1363                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1364                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1365                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1366                                 pstate_table->gfxclk_pstate.custom.max =
1367                                         pstate_table->gfxclk_pstate.curr.max;
1368                                 return -EINVAL;
1369                         }
1370
1371                         pstate_table->gfxclk_pstate.custom.max = input[1];
1372                 } else {
1373                         return -EINVAL;
1374                 }
1375                 break;
1376         case PP_OD_RESTORE_DEFAULT_TABLE:
1377                 if (size != 0) {
1378                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1379                         return -EINVAL;
1380                 } else {
1381                         /* Use the default frequencies for manual and determinism mode */
1382                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1383                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1384
1385                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1386                 }
1387                 break;
1388         case PP_OD_COMMIT_DPM_TABLE:
1389                 if (size != 0) {
1390                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1391                         return -EINVAL;
1392                 } else {
1393                         if (!pstate_table->gfxclk_pstate.custom.min)
1394                                 pstate_table->gfxclk_pstate.custom.min =
1395                                         pstate_table->gfxclk_pstate.curr.min;
1396
1397                         if (!pstate_table->gfxclk_pstate.custom.max)
1398                                 pstate_table->gfxclk_pstate.custom.max =
1399                                         pstate_table->gfxclk_pstate.curr.max;
1400
1401                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1402                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1403
1404                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1405                 }
1406                 break;
1407         default:
1408                 return -ENOSYS;
1409         }
1410
1411         return ret;
1412 }
1413
1414 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1415 {
1416         int ret;
1417         uint64_t feature_enabled;
1418
1419         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1420         if (ret)
1421                 return false;
1422         return !!(feature_enabled & SMC_DPM_FEATURE);
1423 }
1424
1425 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1426                               struct i2c_msg *msg, int num_msgs)
1427 {
1428         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1429         struct amdgpu_device *adev = smu_i2c->adev;
1430         struct smu_context *smu = adev->powerplay.pp_handle;
1431         struct smu_table_context *smu_table = &smu->smu_table;
1432         struct smu_table *table = &smu_table->driver_table;
1433         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1434         int i, j, r, c;
1435         u16 dir;
1436
1437         if (!adev->pm.dpm_enabled)
1438                 return -EBUSY;
1439
1440         req = kzalloc(sizeof(*req), GFP_KERNEL);
1441         if (!req)
1442                 return -ENOMEM;
1443
1444         req->I2CcontrollerPort = smu_i2c->port;
1445         req->I2CSpeed = I2C_SPEED_FAST_400K;
1446         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1447         dir = msg[0].flags & I2C_M_RD;
1448
1449         for (c = i = 0; i < num_msgs; i++) {
1450                 for (j = 0; j < msg[i].len; j++, c++) {
1451                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1452
1453                         if (!(msg[i].flags & I2C_M_RD)) {
1454                                 /* write */
1455                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1456                                 cmd->ReadWriteData = msg[i].buf[j];
1457                         }
1458
1459                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
1460                                 /* The direction changes.
1461                                  */
1462                                 dir = msg[i].flags & I2C_M_RD;
1463                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1464                         }
1465
1466                         req->NumCmds++;
1467
1468                         /*
1469                          * Insert STOP if we are at the last byte of either last
1470                          * message for the transaction or the client explicitly
1471                          * requires a STOP at this particular message.
1472                          */
1473                         if ((j == msg[i].len - 1) &&
1474                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1475                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1476                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1477                         }
1478                 }
1479         }
1480         mutex_lock(&adev->pm.mutex);
1481         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1482         if (r)
1483                 goto fail;
1484
1485         for (c = i = 0; i < num_msgs; i++) {
1486                 if (!(msg[i].flags & I2C_M_RD)) {
1487                         c += msg[i].len;
1488                         continue;
1489                 }
1490                 for (j = 0; j < msg[i].len; j++, c++) {
1491                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1492
1493                         msg[i].buf[j] = cmd->ReadWriteData;
1494                 }
1495         }
1496         r = num_msgs;
1497 fail:
1498         mutex_unlock(&adev->pm.mutex);
1499         kfree(req);
1500         return r;
1501 }
1502
1503 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1504 {
1505         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1506 }
1507
1508
1509 static const struct i2c_algorithm aldebaran_i2c_algo = {
1510         .master_xfer = aldebaran_i2c_xfer,
1511         .functionality = aldebaran_i2c_func,
1512 };
1513
1514 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1515         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1516         .max_read_len  = MAX_SW_I2C_COMMANDS,
1517         .max_write_len = MAX_SW_I2C_COMMANDS,
1518         .max_comb_1st_msg_len = 2,
1519         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1520 };
1521
1522 static int aldebaran_i2c_control_init(struct smu_context *smu)
1523 {
1524         struct amdgpu_device *adev = smu->adev;
1525         struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1526         struct i2c_adapter *control = &smu_i2c->adapter;
1527         int res;
1528
1529         smu_i2c->adev = adev;
1530         smu_i2c->port = 0;
1531         mutex_init(&smu_i2c->mutex);
1532         control->owner = THIS_MODULE;
1533         control->dev.parent = &adev->pdev->dev;
1534         control->algo = &aldebaran_i2c_algo;
1535         snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1536         control->quirks = &aldebaran_i2c_control_quirks;
1537         i2c_set_adapdata(control, smu_i2c);
1538
1539         res = i2c_add_adapter(control);
1540         if (res) {
1541                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1542                 goto Out_err;
1543         }
1544
1545         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1546         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1547
1548         return 0;
1549 Out_err:
1550         i2c_del_adapter(control);
1551
1552         return res;
1553 }
1554
1555 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1556 {
1557         struct amdgpu_device *adev = smu->adev;
1558         int i;
1559
1560         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1561                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1562                 struct i2c_adapter *control = &smu_i2c->adapter;
1563
1564                 i2c_del_adapter(control);
1565         }
1566         adev->pm.ras_eeprom_i2c_bus = NULL;
1567         adev->pm.fru_eeprom_i2c_bus = NULL;
1568 }
1569
1570 static void aldebaran_get_unique_id(struct smu_context *smu)
1571 {
1572         struct amdgpu_device *adev = smu->adev;
1573         uint32_t upper32 = 0, lower32 = 0;
1574
1575         if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1576                 goto out;
1577         if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1578                 goto out;
1579
1580 out:
1581         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1582 }
1583
1584 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1585 {
1586         /* aldebaran is not support baco */
1587
1588         return false;
1589 }
1590
1591 static int aldebaran_set_df_cstate(struct smu_context *smu,
1592                                    enum pp_df_cstate state)
1593 {
1594         struct amdgpu_device *adev = smu->adev;
1595
1596         /*
1597          * Aldebaran does not need the cstate disablement
1598          * prerequisite for gpu reset.
1599          */
1600         if (amdgpu_in_reset(adev) || adev->in_suspend)
1601                 return 0;
1602
1603         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1604 }
1605
1606 static int aldebaran_select_xgmi_plpd_policy(struct smu_context *smu,
1607                                              enum pp_xgmi_plpd_mode mode)
1608 {
1609         struct amdgpu_device *adev = smu->adev;
1610
1611         /* The message only works on master die and NACK will be sent
1612            back for other dies, only send it on master die */
1613         if (adev->smuio.funcs->get_socket_id(adev) ||
1614             adev->smuio.funcs->get_die_id(adev))
1615                 return 0;
1616
1617         if (mode == XGMI_PLPD_DEFAULT)
1618                 return smu_cmn_send_smc_msg_with_param(smu,
1619                                                        SMU_MSG_GmiPwrDnControl,
1620                                                        0, NULL);
1621         else if (mode == XGMI_PLPD_DISALLOW)
1622                 return smu_cmn_send_smc_msg_with_param(smu,
1623                                                        SMU_MSG_GmiPwrDnControl,
1624                                                        1, NULL);
1625         else
1626                 return -EINVAL;
1627 }
1628
1629 static const struct throttling_logging_label {
1630         uint32_t feature_mask;
1631         const char *label;
1632 } logging_label[] = {
1633         {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1634         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1635         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1636         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1637         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1638 };
1639 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1640 {
1641         int ret;
1642         int throttler_idx, throttling_events = 0, buf_idx = 0;
1643         struct amdgpu_device *adev = smu->adev;
1644         uint32_t throttler_status;
1645         char log_buf[256];
1646
1647         ret = aldebaran_get_smu_metrics_data(smu,
1648                                              METRICS_THROTTLER_STATUS,
1649                                              &throttler_status);
1650         if (ret)
1651                 return;
1652
1653         memset(log_buf, 0, sizeof(log_buf));
1654         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1655              throttler_idx++) {
1656                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1657                         throttling_events++;
1658                         buf_idx += snprintf(log_buf + buf_idx,
1659                                             sizeof(log_buf) - buf_idx,
1660                                             "%s%s",
1661                                             throttling_events > 1 ? " and " : "",
1662                                             logging_label[throttler_idx].label);
1663                         if (buf_idx >= sizeof(log_buf)) {
1664                                 dev_err(adev->dev, "buffer overflow!\n");
1665                                 log_buf[sizeof(log_buf) - 1] = '\0';
1666                                 break;
1667                         }
1668                 }
1669         }
1670
1671         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1672                  log_buf);
1673         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1674                 smu_cmn_get_indep_throttler_status(throttler_status,
1675                                                    aldebaran_throttler_map));
1676 }
1677
1678 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1679 {
1680         struct amdgpu_device *adev = smu->adev;
1681         uint32_t esm_ctrl;
1682
1683         /* TODO: confirm this on real target */
1684         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1685         if ((esm_ctrl >> 15) & 0x1)
1686                 return (((esm_ctrl >> 8) & 0x7F) + 128);
1687
1688         return smu_v13_0_get_current_pcie_link_speed(smu);
1689 }
1690
1691 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1692                                          void **table)
1693 {
1694         struct smu_table_context *smu_table = &smu->smu_table;
1695         struct gpu_metrics_v1_3 *gpu_metrics =
1696                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1697         SmuMetrics_t metrics;
1698         int i, ret = 0;
1699
1700         ret = smu_cmn_get_metrics_table(smu,
1701                                         &metrics,
1702                                         true);
1703         if (ret)
1704                 return ret;
1705
1706         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1707
1708         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1709         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1710         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1711         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1712         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1713         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1714
1715         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1716         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1717         gpu_metrics->average_mm_activity = 0;
1718
1719         /* Valid power data is available only from primary die */
1720         if (aldebaran_is_primary(smu)) {
1721                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1722                 gpu_metrics->energy_accumulator =
1723                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1724                         metrics.EnergyAcc64bitLow;
1725         } else {
1726                 gpu_metrics->average_socket_power = 0;
1727                 gpu_metrics->energy_accumulator = 0;
1728         }
1729
1730         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1731         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1732         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1733         gpu_metrics->average_vclk0_frequency = 0;
1734         gpu_metrics->average_dclk0_frequency = 0;
1735
1736         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1737         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1738         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1739         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1740         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1741
1742         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1743         gpu_metrics->indep_throttle_status =
1744                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1745                                                            aldebaran_throttler_map);
1746
1747         gpu_metrics->current_fan_speed = 0;
1748
1749         if (!amdgpu_sriov_vf(smu->adev)) {
1750                 gpu_metrics->pcie_link_width =
1751                         smu_v13_0_get_current_pcie_link_width(smu);
1752                 gpu_metrics->pcie_link_speed =
1753                         aldebaran_get_current_pcie_link_speed(smu);
1754         }
1755
1756         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1757
1758         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1759         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1760
1761         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1762                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1763
1764         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1765                                         metrics.TimeStampLow;
1766
1767         *table = (void *)gpu_metrics;
1768
1769         return sizeof(struct gpu_metrics_v1_3);
1770 }
1771
1772 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1773                 int *ecctable_version)
1774 {
1775         if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
1776                 return -EOPNOTSUPP;
1777         else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1778                         smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1779                 *ecctable_version = 1;
1780         else
1781                 *ecctable_version = 2;
1782
1783         return 0;
1784 }
1785
1786 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1787                                          void *table)
1788 {
1789         struct smu_table_context *smu_table = &smu->smu_table;
1790         EccInfoTable_t *ecc_table = NULL;
1791         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1792         int i, ret = 0;
1793         int table_version = 0;
1794         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1795
1796         ret = aldebaran_check_ecc_table_support(smu, &table_version);
1797         if (ret)
1798                 return ret;
1799
1800         ret = smu_cmn_update_table(smu,
1801                                SMU_TABLE_ECCINFO,
1802                                0,
1803                                smu_table->ecc_table,
1804                                false);
1805         if (ret) {
1806                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1807                 return ret;
1808         }
1809
1810         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1811
1812         if (table_version == 1) {
1813                 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1814                         ecc_info_per_channel = &(eccinfo->ecc[i]);
1815                         ecc_info_per_channel->ce_count_lo_chip =
1816                                 ecc_table->EccInfo[i].ce_count_lo_chip;
1817                         ecc_info_per_channel->ce_count_hi_chip =
1818                                 ecc_table->EccInfo[i].ce_count_hi_chip;
1819                         ecc_info_per_channel->mca_umc_status =
1820                                 ecc_table->EccInfo[i].mca_umc_status;
1821                         ecc_info_per_channel->mca_umc_addr =
1822                                 ecc_table->EccInfo[i].mca_umc_addr;
1823                 }
1824         } else if (table_version == 2) {
1825                 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1826                         ecc_info_per_channel = &(eccinfo->ecc[i]);
1827                         ecc_info_per_channel->ce_count_lo_chip =
1828                                 ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1829                         ecc_info_per_channel->ce_count_hi_chip =
1830                                 ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1831                         ecc_info_per_channel->mca_umc_status =
1832                                 ecc_table->EccInfo_V2[i].mca_umc_status;
1833                         ecc_info_per_channel->mca_umc_addr =
1834                                 ecc_table->EccInfo_V2[i].mca_umc_addr;
1835                         ecc_info_per_channel->mca_ceumc_addr =
1836                                 ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1837                 }
1838                 eccinfo->record_ce_addr_supported = 1;
1839         }
1840
1841         return ret;
1842 }
1843
1844 static int aldebaran_mode1_reset(struct smu_context *smu)
1845 {
1846         u32 fatal_err, param;
1847         int ret = 0;
1848         struct amdgpu_device *adev = smu->adev;
1849         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1850
1851         fatal_err = 0;
1852         param = SMU_RESET_MODE_1;
1853
1854         /*
1855         * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1856         */
1857         if (smu->smc_fw_version < 0x00440700) {
1858                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1859         } else {
1860                 /* fatal error triggered by ras, PMFW supports the flag
1861                    from 68.44.0 */
1862                 if ((smu->smc_fw_version >= 0x00442c00) && ras &&
1863                     atomic_read(&ras->in_recovery))
1864                         fatal_err = 1;
1865
1866                 param |= (fatal_err << 16);
1867                 ret = smu_cmn_send_smc_msg_with_param(smu,
1868                                         SMU_MSG_GfxDeviceDriverReset, param, NULL);
1869         }
1870
1871         if (!ret)
1872                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1873
1874         return ret;
1875 }
1876
1877 static int aldebaran_mode2_reset(struct smu_context *smu)
1878 {
1879         int ret = 0, index;
1880         struct amdgpu_device *adev = smu->adev;
1881         int timeout = 10;
1882
1883         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1884                                                 SMU_MSG_GfxDeviceDriverReset);
1885
1886         mutex_lock(&smu->message_lock);
1887         if (smu->smc_fw_version >= 0x00441400) {
1888                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1889                 /* This is similar to FLR, wait till max FLR timeout */
1890                 msleep(100);
1891                 dev_dbg(smu->adev->dev, "restore config space...\n");
1892                 /* Restore the config space saved during init */
1893                 amdgpu_device_load_pci_state(adev->pdev);
1894
1895                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1896                 while (ret == -ETIME && timeout)  {
1897                         ret = smu_cmn_wait_for_response(smu);
1898                         /* Wait a bit more time for getting ACK */
1899                         if (ret == -ETIME) {
1900                                 --timeout;
1901                                 usleep_range(500, 1000);
1902                                 continue;
1903                         }
1904
1905                         if (ret != 1) {
1906                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1907                                                 SMU_RESET_MODE_2, ret);
1908                                 goto out;
1909                         }
1910                 }
1911
1912         } else {
1913                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1914                                 smu->smc_fw_version);
1915         }
1916
1917         if (ret == 1)
1918                 ret = 0;
1919 out:
1920         mutex_unlock(&smu->message_lock);
1921
1922         return ret;
1923 }
1924
1925 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1926 {
1927         int ret = 0;
1928         ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1929
1930         return ret;
1931 }
1932
1933 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1934 {
1935 #if 0
1936         struct amdgpu_device *adev = smu->adev;
1937         uint32_t val;
1938         uint32_t smu_version;
1939         int ret;
1940
1941         /**
1942          * PM FW version support mode1 reset from 68.07
1943          */
1944         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1945         if (ret)
1946                 return false;
1947
1948         if ((smu_version < 0x00440700))
1949                 return false;
1950
1951         /**
1952          * mode1 reset relies on PSP, so we should check if
1953          * PSP is alive.
1954          */
1955         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1956
1957         return val != 0x0;
1958 #endif
1959         return true;
1960 }
1961
1962 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1963 {
1964         return true;
1965 }
1966
1967 static int aldebaran_set_mp1_state(struct smu_context *smu,
1968                                    enum pp_mp1_state mp1_state)
1969 {
1970         switch (mp1_state) {
1971         case PP_MP1_STATE_UNLOAD:
1972                 return smu_cmn_set_mp1_state(smu, mp1_state);
1973         default:
1974                 return 0;
1975         }
1976 }
1977
1978 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1979                 uint32_t size)
1980 {
1981         int ret = 0;
1982
1983         /* message SMU to update the bad page number on SMUBUS */
1984         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1985         if (ret)
1986                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1987                                 __func__);
1988
1989         return ret;
1990 }
1991
1992 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
1993 {
1994         if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
1995                 return -EOPNOTSUPP;
1996
1997         return 0;
1998 }
1999
2000 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
2001                 uint32_t size)
2002 {
2003         int ret = 0;
2004
2005         ret = aldebaran_check_bad_channel_info_support(smu);
2006         if (ret)
2007                 return ret;
2008
2009         /* message SMU to update the bad channel info on SMUBUS */
2010         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
2011         if (ret)
2012                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
2013                                 __func__);
2014
2015         return ret;
2016 }
2017
2018 static const struct pptable_funcs aldebaran_ppt_funcs = {
2019         /* init dpm */
2020         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
2021         /* dpm/clk tables */
2022         .set_default_dpm_table = aldebaran_set_default_dpm_table,
2023         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
2024         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
2025         .emit_clk_levels = aldebaran_emit_clk_levels,
2026         .force_clk_levels = aldebaran_force_clk_levels,
2027         .read_sensor = aldebaran_read_sensor,
2028         .set_performance_level = aldebaran_set_performance_level,
2029         .get_power_limit = aldebaran_get_power_limit,
2030         .is_dpm_running = aldebaran_is_dpm_running,
2031         .get_unique_id = aldebaran_get_unique_id,
2032         .init_microcode = smu_v13_0_init_microcode,
2033         .load_microcode = smu_v13_0_load_microcode,
2034         .fini_microcode = smu_v13_0_fini_microcode,
2035         .init_smc_tables = aldebaran_init_smc_tables,
2036         .fini_smc_tables = smu_v13_0_fini_smc_tables,
2037         .init_power = smu_v13_0_init_power,
2038         .fini_power = smu_v13_0_fini_power,
2039         .check_fw_status = smu_v13_0_check_fw_status,
2040         /* pptable related */
2041         .setup_pptable = aldebaran_setup_pptable,
2042         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2043         .check_fw_version = smu_v13_0_check_fw_version,
2044         .write_pptable = smu_cmn_write_pptable,
2045         .set_driver_table_location = smu_v13_0_set_driver_table_location,
2046         .set_tool_table_location = smu_v13_0_set_tool_table_location,
2047         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2048         .system_features_control = aldebaran_system_features_control,
2049         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2050         .send_smc_msg = smu_cmn_send_smc_msg,
2051         .get_enabled_mask = smu_cmn_get_enabled_mask,
2052         .feature_is_enabled = smu_cmn_feature_is_enabled,
2053         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2054         .set_power_limit = aldebaran_set_power_limit,
2055         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2056         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2057         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2058         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2059         .register_irq_handler = smu_v13_0_register_irq_handler,
2060         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2061         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2062         .baco_is_support = aldebaran_is_baco_supported,
2063         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2064         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2065         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2066         .set_df_cstate = aldebaran_set_df_cstate,
2067         .select_xgmi_plpd_policy = aldebaran_select_xgmi_plpd_policy,
2068         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2069         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2070         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2071         .get_gpu_metrics = aldebaran_get_gpu_metrics,
2072         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2073         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2074         .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2075         .mode1_reset = aldebaran_mode1_reset,
2076         .set_mp1_state = aldebaran_set_mp1_state,
2077         .mode2_reset = aldebaran_mode2_reset,
2078         .wait_for_event = smu_v13_0_wait_for_event,
2079         .i2c_init = aldebaran_i2c_control_init,
2080         .i2c_fini = aldebaran_i2c_control_fini,
2081         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2082         .get_ecc_info = aldebaran_get_ecc_info,
2083         .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2084 };
2085
2086 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2087 {
2088         smu->ppt_funcs = &aldebaran_ppt_funcs;
2089         smu->message_map = aldebaran_message_map;
2090         smu->clock_map = aldebaran_clk_map;
2091         smu->feature_map = aldebaran_feature_mask_map;
2092         smu->table_map = aldebaran_table_map;
2093         smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
2094         smu_v13_0_set_smu_mailbox_registers(smu);
2095 }