2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0.h"
33 #include "smu13_driver_if_aldebaran.h"
34 #include "soc15_common.h"
36 #include "power_state.h"
37 #include "aldebaran_ppt.h"
38 #include "smu_v13_0_pptable.h"
39 #include "aldebaran_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
48 #include "mp/mp_13_0_2_offset.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
63 [smu_feature] = {1, (aldebaran_feature)}
65 #define FEATURE_MASK(feature) (1ULL << feature)
66 #define SMC_DPM_FEATURE ( \
67 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \
73 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \
74 FEATURE_MASK(FEATURE_DPM_VCN_BIT))
76 /* possible frequency drift (1Mhz) */
79 #define smnPCIE_ESM_CTRL 0x111003D0
81 static const struct smu_temperature_range smu13_thermal_policy[] =
83 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
84 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
87 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
88 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
89 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
90 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
92 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
93 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
94 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
95 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
96 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
97 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
98 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
99 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
100 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
101 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
102 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
103 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
104 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
105 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
106 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
107 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
108 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
109 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
110 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
111 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
112 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
113 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
114 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
115 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
117 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0),
118 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
119 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
120 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
121 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
122 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
123 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
124 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
125 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
126 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
127 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
128 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
129 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
130 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
131 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
132 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0),
133 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
134 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
135 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
136 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
137 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
140 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
141 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
142 CLK_MAP(SCLK, PPCLK_GFXCLK),
143 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
144 CLK_MAP(FCLK, PPCLK_FCLK),
145 CLK_MAP(UCLK, PPCLK_UCLK),
146 CLK_MAP(MCLK, PPCLK_UCLK),
147 CLK_MAP(DCLK, PPCLK_DCLK),
148 CLK_MAP(VCLK, PPCLK_VCLK),
149 CLK_MAP(LCLK, PPCLK_LCLK),
152 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
153 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS),
154 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT),
155 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT),
156 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT),
157 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT),
158 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT),
159 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
160 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT),
161 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT),
162 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT),
163 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT),
164 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT),
165 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT),
166 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
167 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT),
168 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT),
169 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT),
170 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT),
171 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT),
172 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT),
173 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT),
174 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT),
175 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT),
176 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT),
177 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT),
178 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT),
179 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT),
180 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT),
181 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
182 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
185 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
187 TAB_MAP(AVFS_PSM_DEBUG),
188 TAB_MAP(AVFS_FUSE_OVERRIDE),
189 TAB_MAP(PMSTATUSLOG),
190 TAB_MAP(SMU_METRICS),
191 TAB_MAP(DRIVER_SMU_CONFIG),
192 TAB_MAP(I2C_COMMANDS),
195 static const uint8_t aldebaran_throttler_map[] = {
196 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
197 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
198 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
199 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
200 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
201 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
202 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
203 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
204 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
205 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
206 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
209 static int aldebaran_tables_init(struct smu_context *smu)
211 struct smu_table_context *smu_table = &smu->smu_table;
212 struct smu_table *tables = smu_table->tables;
214 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
215 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
217 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
218 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
220 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
221 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
224 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
226 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
227 if (!smu_table->metrics_table)
229 smu_table->metrics_time = 0;
231 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
232 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
233 if (!smu_table->gpu_metrics_table) {
234 kfree(smu_table->metrics_table);
241 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
243 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
245 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
247 if (!smu_dpm->dpm_context)
249 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
251 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
253 if (!smu_dpm->dpm_current_power_state)
256 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
258 if (!smu_dpm->dpm_request_power_state)
264 static int aldebaran_init_smc_tables(struct smu_context *smu)
268 ret = aldebaran_tables_init(smu);
272 ret = aldebaran_allocate_dpm_context(smu);
276 return smu_v13_0_init_smc_tables(smu);
279 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
285 /* pptable will handle the features to enable */
286 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
291 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
293 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
294 struct smu_13_0_dpm_table *dpm_table = NULL;
295 PPTable_t *pptable = smu->smu_table.driver_pptable;
298 /* socclk dpm table setup */
299 dpm_table = &dpm_context->dpm_tables.soc_table;
300 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
301 ret = smu_v13_0_set_single_dpm_table(smu,
307 dpm_table->count = 1;
308 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
309 dpm_table->dpm_levels[0].enabled = true;
310 dpm_table->min = dpm_table->dpm_levels[0].value;
311 dpm_table->max = dpm_table->dpm_levels[0].value;
314 /* gfxclk dpm table setup */
315 dpm_table = &dpm_context->dpm_tables.gfx_table;
316 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
317 /* in the case of gfxclk, only fine-grained dpm is honored */
318 dpm_table->count = 2;
319 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
320 dpm_table->dpm_levels[0].enabled = true;
321 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
322 dpm_table->dpm_levels[1].enabled = true;
323 dpm_table->min = dpm_table->dpm_levels[0].value;
324 dpm_table->max = dpm_table->dpm_levels[1].value;
326 dpm_table->count = 1;
327 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
328 dpm_table->dpm_levels[0].enabled = true;
329 dpm_table->min = dpm_table->dpm_levels[0].value;
330 dpm_table->max = dpm_table->dpm_levels[0].value;
333 /* memclk dpm table setup */
334 dpm_table = &dpm_context->dpm_tables.uclk_table;
335 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
336 ret = smu_v13_0_set_single_dpm_table(smu,
342 dpm_table->count = 1;
343 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
344 dpm_table->dpm_levels[0].enabled = true;
345 dpm_table->min = dpm_table->dpm_levels[0].value;
346 dpm_table->max = dpm_table->dpm_levels[0].value;
349 /* fclk dpm table setup */
350 dpm_table = &dpm_context->dpm_tables.fclk_table;
351 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
352 ret = smu_v13_0_set_single_dpm_table(smu,
358 dpm_table->count = 1;
359 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
360 dpm_table->dpm_levels[0].enabled = true;
361 dpm_table->min = dpm_table->dpm_levels[0].value;
362 dpm_table->max = dpm_table->dpm_levels[0].value;
368 static int aldebaran_check_powerplay_table(struct smu_context *smu)
370 struct smu_table_context *table_context = &smu->smu_table;
371 struct smu_13_0_powerplay_table *powerplay_table =
372 table_context->power_play_table;
374 table_context->thermal_controller_type =
375 powerplay_table->thermal_controller_type;
380 static int aldebaran_store_powerplay_table(struct smu_context *smu)
382 struct smu_table_context *table_context = &smu->smu_table;
383 struct smu_13_0_powerplay_table *powerplay_table =
384 table_context->power_play_table;
385 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
391 static int aldebaran_append_powerplay_table(struct smu_context *smu)
393 struct smu_table_context *table_context = &smu->smu_table;
394 PPTable_t *smc_pptable = table_context->driver_pptable;
395 struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
398 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
401 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
402 (uint8_t **)&smc_dpm_table);
406 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
407 smc_dpm_table->table_header.format_revision,
408 smc_dpm_table->table_header.content_revision);
410 if ((smc_dpm_table->table_header.format_revision == 4) &&
411 (smc_dpm_table->table_header.content_revision == 10))
412 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
413 smc_dpm_table, GfxMaxCurrent);
417 static int aldebaran_setup_pptable(struct smu_context *smu)
421 /* VBIOS pptable is the first choice */
422 smu->smu_table.boot_values.pp_table_id = 0;
424 ret = smu_v13_0_setup_pptable(smu);
428 ret = aldebaran_store_powerplay_table(smu);
432 ret = aldebaran_append_powerplay_table(smu);
436 ret = aldebaran_check_powerplay_table(smu);
443 static bool aldebaran_is_primary(struct smu_context *smu)
445 struct amdgpu_device *adev = smu->adev;
447 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
448 return adev->smuio.funcs->get_die_id(adev) == 0;
453 static int aldebaran_run_board_btc(struct smu_context *smu)
458 if (!aldebaran_is_primary(smu))
461 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
463 dev_err(smu->adev->dev, "Failed to get smu version!\n");
466 if (smu_version <= 0x00441d00)
469 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
471 dev_err(smu->adev->dev, "Board power calibration failed!\n");
476 static int aldebaran_run_btc(struct smu_context *smu)
480 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
482 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
484 ret = aldebaran_run_board_btc(smu);
489 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
491 struct smu_13_0_dpm_context *dpm_context =
492 smu->smu_dpm.dpm_context;
493 struct smu_13_0_dpm_table *gfx_table =
494 &dpm_context->dpm_tables.gfx_table;
495 struct smu_13_0_dpm_table *mem_table =
496 &dpm_context->dpm_tables.uclk_table;
497 struct smu_13_0_dpm_table *soc_table =
498 &dpm_context->dpm_tables.soc_table;
499 struct smu_umd_pstate_table *pstate_table =
502 pstate_table->gfxclk_pstate.min = gfx_table->min;
503 pstate_table->gfxclk_pstate.peak = gfx_table->max;
504 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
505 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
507 pstate_table->uclk_pstate.min = mem_table->min;
508 pstate_table->uclk_pstate.peak = mem_table->max;
509 pstate_table->uclk_pstate.curr.min = mem_table->min;
510 pstate_table->uclk_pstate.curr.max = mem_table->max;
512 pstate_table->socclk_pstate.min = soc_table->min;
513 pstate_table->socclk_pstate.peak = soc_table->max;
514 pstate_table->socclk_pstate.curr.min = soc_table->min;
515 pstate_table->socclk_pstate.curr.max = soc_table->max;
517 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
518 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
519 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
520 pstate_table->gfxclk_pstate.standard =
521 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
522 pstate_table->uclk_pstate.standard =
523 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
524 pstate_table->socclk_pstate.standard =
525 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
527 pstate_table->gfxclk_pstate.standard =
528 pstate_table->gfxclk_pstate.min;
529 pstate_table->uclk_pstate.standard =
530 pstate_table->uclk_pstate.min;
531 pstate_table->socclk_pstate.standard =
532 pstate_table->socclk_pstate.min;
538 static int aldebaran_get_clk_table(struct smu_context *smu,
539 struct pp_clock_levels_with_latency *clocks,
540 struct smu_13_0_dpm_table *dpm_table)
544 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
545 clocks->num_levels = count;
547 for (i = 0; i < count; i++) {
548 clocks->data[i].clocks_in_khz =
549 dpm_table->dpm_levels[i].value * 1000;
550 clocks->data[i].latency_in_us = 0;
556 static int aldebaran_freqs_in_same_level(int32_t frequency1,
559 return (abs(frequency1 - frequency2) <= EPSILON);
562 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
563 MetricsMember_t member,
566 struct smu_table_context *smu_table= &smu->smu_table;
567 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
570 mutex_lock(&smu->metrics_lock);
572 ret = smu_cmn_get_metrics_table_locked(smu,
576 mutex_unlock(&smu->metrics_lock);
581 case METRICS_CURR_GFXCLK:
582 *value = metrics->CurrClock[PPCLK_GFXCLK];
584 case METRICS_CURR_SOCCLK:
585 *value = metrics->CurrClock[PPCLK_SOCCLK];
587 case METRICS_CURR_UCLK:
588 *value = metrics->CurrClock[PPCLK_UCLK];
590 case METRICS_CURR_VCLK:
591 *value = metrics->CurrClock[PPCLK_VCLK];
593 case METRICS_CURR_DCLK:
594 *value = metrics->CurrClock[PPCLK_DCLK];
596 case METRICS_CURR_FCLK:
597 *value = metrics->CurrClock[PPCLK_FCLK];
599 case METRICS_AVERAGE_GFXCLK:
600 *value = metrics->AverageGfxclkFrequency;
602 case METRICS_AVERAGE_SOCCLK:
603 *value = metrics->AverageSocclkFrequency;
605 case METRICS_AVERAGE_UCLK:
606 *value = metrics->AverageUclkFrequency;
608 case METRICS_AVERAGE_GFXACTIVITY:
609 *value = metrics->AverageGfxActivity;
611 case METRICS_AVERAGE_MEMACTIVITY:
612 *value = metrics->AverageUclkActivity;
614 case METRICS_AVERAGE_SOCKETPOWER:
615 /* Valid power data is available only from primary die */
616 *value = aldebaran_is_primary(smu) ?
617 metrics->AverageSocketPower << 8 :
620 case METRICS_TEMPERATURE_EDGE:
621 *value = metrics->TemperatureEdge *
622 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
624 case METRICS_TEMPERATURE_HOTSPOT:
625 *value = metrics->TemperatureHotspot *
626 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
628 case METRICS_TEMPERATURE_MEM:
629 *value = metrics->TemperatureHBM *
630 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
632 case METRICS_TEMPERATURE_VRGFX:
633 *value = metrics->TemperatureVrGfx *
634 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
636 case METRICS_TEMPERATURE_VRSOC:
637 *value = metrics->TemperatureVrSoc *
638 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
640 case METRICS_TEMPERATURE_VRMEM:
641 *value = metrics->TemperatureVrMem *
642 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
644 case METRICS_THROTTLER_STATUS:
645 *value = metrics->ThrottlerStatus;
652 mutex_unlock(&smu->metrics_lock);
657 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
658 enum smu_clk_type clk_type,
661 MetricsMember_t member_type;
667 clk_id = smu_cmn_to_asic_specific_index(smu,
668 CMN2ASIC_MAPPING_CLK,
676 * CurrClock[clk_id] can provide accurate
677 * output only when the dpm feature is enabled.
678 * We can use Average_* for dpm disabled case.
679 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
681 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
682 member_type = METRICS_CURR_GFXCLK;
684 member_type = METRICS_AVERAGE_GFXCLK;
687 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
688 member_type = METRICS_CURR_UCLK;
690 member_type = METRICS_AVERAGE_UCLK;
693 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
694 member_type = METRICS_CURR_SOCCLK;
696 member_type = METRICS_AVERAGE_SOCCLK;
699 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
700 member_type = METRICS_CURR_VCLK;
702 member_type = METRICS_AVERAGE_VCLK;
705 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
706 member_type = METRICS_CURR_DCLK;
708 member_type = METRICS_AVERAGE_DCLK;
711 member_type = METRICS_CURR_FCLK;
717 return aldebaran_get_smu_metrics_data(smu,
722 static int aldebaran_print_clk_levels(struct smu_context *smu,
723 enum smu_clk_type type, char *buf)
725 int i, now, size = 0;
727 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
728 struct pp_clock_levels_with_latency clocks;
729 struct smu_13_0_dpm_table *single_dpm_table;
730 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
731 struct smu_13_0_dpm_context *dpm_context = NULL;
732 uint32_t display_levels;
733 uint32_t freq_values[3] = {0};
734 uint32_t min_clk, max_clk;
736 if (amdgpu_ras_intr_triggered())
737 return sysfs_emit(buf, "unavailable\n");
739 dpm_context = smu_dpm->dpm_context;
744 size = sysfs_emit(buf, "%s:\n", "GFXCLK");
747 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
749 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
753 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
754 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
756 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
760 display_levels = clocks.num_levels;
762 min_clk = pstate_table->gfxclk_pstate.curr.min;
763 max_clk = pstate_table->gfxclk_pstate.curr.max;
765 freq_values[0] = min_clk;
766 freq_values[1] = max_clk;
768 /* fine-grained dpm has only 2 levels */
769 if (now > min_clk && now < max_clk) {
770 display_levels = clocks.num_levels + 1;
771 freq_values[2] = max_clk;
772 freq_values[1] = now;
776 * For DPM disabled case, there will be only one clock level.
777 * And it's safe to assume that is always the current clock.
779 if (display_levels == clocks.num_levels) {
780 for (i = 0; i < clocks.num_levels; i++)
781 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
783 (clocks.num_levels == 1) ?
785 (aldebaran_freqs_in_same_level(
786 freq_values[i], now) ?
790 for (i = 0; i < display_levels; i++)
791 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
792 freq_values[i], i == 1 ? "*" : "");
798 size = sysfs_emit(buf, "%s:\n", "MCLK");
801 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
803 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
807 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
808 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
810 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
814 for (i = 0; i < clocks.num_levels; i++)
815 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
816 i, clocks.data[i].clocks_in_khz / 1000,
817 (clocks.num_levels == 1) ? "*" :
818 (aldebaran_freqs_in_same_level(
819 clocks.data[i].clocks_in_khz / 1000,
824 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
826 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
830 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
831 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
833 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
837 for (i = 0; i < clocks.num_levels; i++)
838 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
839 i, clocks.data[i].clocks_in_khz / 1000,
840 (clocks.num_levels == 1) ? "*" :
841 (aldebaran_freqs_in_same_level(
842 clocks.data[i].clocks_in_khz / 1000,
847 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
849 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
853 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
854 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
856 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
860 for (i = 0; i < single_dpm_table->count; i++)
861 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
862 i, single_dpm_table->dpm_levels[i].value,
863 (clocks.num_levels == 1) ? "*" :
864 (aldebaran_freqs_in_same_level(
865 clocks.data[i].clocks_in_khz / 1000,
870 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
872 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
876 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
877 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
879 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
883 for (i = 0; i < single_dpm_table->count; i++)
884 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
885 i, single_dpm_table->dpm_levels[i].value,
886 (clocks.num_levels == 1) ? "*" :
887 (aldebaran_freqs_in_same_level(
888 clocks.data[i].clocks_in_khz / 1000,
893 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
895 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
899 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
900 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
902 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
906 for (i = 0; i < single_dpm_table->count; i++)
907 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
908 i, single_dpm_table->dpm_levels[i].value,
909 (clocks.num_levels == 1) ? "*" :
910 (aldebaran_freqs_in_same_level(
911 clocks.data[i].clocks_in_khz / 1000,
922 static int aldebaran_upload_dpm_level(struct smu_context *smu,
924 uint32_t feature_mask,
927 struct smu_13_0_dpm_context *dpm_context =
928 smu->smu_dpm.dpm_context;
932 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
933 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
934 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
935 ret = smu_cmn_send_smc_msg_with_param(smu,
936 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
937 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
940 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
941 max ? "max" : "min");
946 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
947 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
948 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
949 ret = smu_cmn_send_smc_msg_with_param(smu,
950 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
951 (PPCLK_UCLK << 16) | (freq & 0xffff),
954 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
955 max ? "max" : "min");
960 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
961 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
962 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
963 ret = smu_cmn_send_smc_msg_with_param(smu,
964 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
965 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
968 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
969 max ? "max" : "min");
977 static int aldebaran_force_clk_levels(struct smu_context *smu,
978 enum smu_clk_type type, uint32_t mask)
980 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
981 struct smu_13_0_dpm_table *single_dpm_table = NULL;
982 uint32_t soft_min_level, soft_max_level;
985 soft_min_level = mask ? (ffs(mask) - 1) : 0;
986 soft_max_level = mask ? (fls(mask) - 1) : 0;
990 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
991 if (soft_max_level >= single_dpm_table->count) {
992 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
993 soft_max_level, single_dpm_table->count - 1);
998 ret = aldebaran_upload_dpm_level(smu,
1000 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1003 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1007 ret = aldebaran_upload_dpm_level(smu,
1009 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1012 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1020 * Should not arrive here since aldebaran does not
1021 * support mclk/socclk/fclk softmin/softmax settings
1033 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1034 struct smu_temperature_range *range)
1036 struct smu_table_context *table_context = &smu->smu_table;
1037 struct smu_13_0_powerplay_table *powerplay_table =
1038 table_context->power_play_table;
1039 PPTable_t *pptable = smu->smu_table.driver_pptable;
1044 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1046 range->hotspot_crit_max = pptable->ThotspotLimit *
1047 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1048 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1049 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1050 range->mem_crit_max = pptable->TmemLimit *
1051 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1052 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1054 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1059 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1060 enum amd_pp_sensors sensor,
1069 case AMDGPU_PP_SENSOR_GPU_LOAD:
1070 ret = aldebaran_get_smu_metrics_data(smu,
1071 METRICS_AVERAGE_GFXACTIVITY,
1074 case AMDGPU_PP_SENSOR_MEM_LOAD:
1075 ret = aldebaran_get_smu_metrics_data(smu,
1076 METRICS_AVERAGE_MEMACTIVITY,
1080 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1087 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1092 return aldebaran_get_smu_metrics_data(smu,
1093 METRICS_AVERAGE_SOCKETPOWER,
1097 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1098 enum amd_pp_sensors sensor,
1107 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1108 ret = aldebaran_get_smu_metrics_data(smu,
1109 METRICS_TEMPERATURE_HOTSPOT,
1112 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1113 ret = aldebaran_get_smu_metrics_data(smu,
1114 METRICS_TEMPERATURE_EDGE,
1117 case AMDGPU_PP_SENSOR_MEM_TEMP:
1118 ret = aldebaran_get_smu_metrics_data(smu,
1119 METRICS_TEMPERATURE_MEM,
1123 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1130 static int aldebaran_read_sensor(struct smu_context *smu,
1131 enum amd_pp_sensors sensor,
1132 void *data, uint32_t *size)
1136 if (amdgpu_ras_intr_triggered())
1142 mutex_lock(&smu->sensor_lock);
1144 case AMDGPU_PP_SENSOR_MEM_LOAD:
1145 case AMDGPU_PP_SENSOR_GPU_LOAD:
1146 ret = aldebaran_get_current_activity_percent(smu,
1151 case AMDGPU_PP_SENSOR_GPU_POWER:
1152 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1155 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1156 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1157 case AMDGPU_PP_SENSOR_MEM_TEMP:
1158 ret = aldebaran_thermal_get_temperature(smu, sensor,
1162 case AMDGPU_PP_SENSOR_GFX_MCLK:
1163 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1164 /* the output clock frequency in 10K unit */
1165 *(uint32_t *)data *= 100;
1168 case AMDGPU_PP_SENSOR_GFX_SCLK:
1169 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1170 *(uint32_t *)data *= 100;
1173 case AMDGPU_PP_SENSOR_VDDGFX:
1174 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1181 mutex_unlock(&smu->sensor_lock);
1186 static int aldebaran_get_power_limit(struct smu_context *smu,
1187 uint32_t *current_power_limit,
1188 uint32_t *default_power_limit,
1189 uint32_t *max_power_limit)
1191 PPTable_t *pptable = smu->smu_table.driver_pptable;
1192 uint32_t power_limit = 0;
1195 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1196 if (current_power_limit)
1197 *current_power_limit = 0;
1198 if (default_power_limit)
1199 *default_power_limit = 0;
1200 if (max_power_limit)
1201 *max_power_limit = 0;
1203 dev_warn(smu->adev->dev,
1204 "PPT feature is not enabled, power values can't be fetched.");
1209 /* Valid power data is available only from primary die.
1210 * For secondary die show the value as 0.
1212 if (aldebaran_is_primary(smu)) {
1213 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1217 /* the last hope to figure out the ppt limit */
1219 dev_err(smu->adev->dev,
1220 "Cannot get PPT limit due to pptable missing!");
1223 power_limit = pptable->PptLimit;
1227 if (current_power_limit)
1228 *current_power_limit = power_limit;
1229 if (default_power_limit)
1230 *default_power_limit = power_limit;
1232 if (max_power_limit) {
1234 *max_power_limit = pptable->PptLimit;
1240 static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
1242 /* Power limit can be set only through primary die */
1243 if (aldebaran_is_primary(smu))
1244 return smu_v13_0_set_power_limit(smu, n);
1249 static int aldebaran_system_features_control(struct smu_context *smu, bool enable)
1253 ret = smu_v13_0_system_features_control(smu, enable);
1255 ret = aldebaran_run_btc(smu);
1260 static int aldebaran_set_performance_level(struct smu_context *smu,
1261 enum amd_dpm_forced_level level)
1263 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1264 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1265 struct smu_13_0_dpm_table *gfx_table =
1266 &dpm_context->dpm_tables.gfx_table;
1267 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1269 /* Disable determinism if switching to another mode */
1270 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1271 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1272 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1273 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1278 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1281 case AMD_DPM_FORCED_LEVEL_HIGH:
1282 case AMD_DPM_FORCED_LEVEL_LOW:
1283 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1284 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1285 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1286 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1291 return smu_v13_0_set_performance_level(smu, level);
1294 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1295 enum smu_clk_type clk_type,
1299 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1300 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1301 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1302 struct amdgpu_device *adev = smu->adev;
1307 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1310 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1311 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1314 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1316 dev_err(smu->adev->dev,
1317 "Minimum GFX clk should be less than the maximum allowed clock\n");
1321 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1322 (max == pstate_table->gfxclk_pstate.curr.max))
1325 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1328 pstate_table->gfxclk_pstate.curr.min = min;
1329 pstate_table->gfxclk_pstate.curr.max = max;
1335 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1336 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1337 (max > dpm_context->dpm_tables.gfx_table.max)) {
1339 "Invalid max frequency %d MHz specified for determinism\n", max);
1343 /* Restore default min/max clocks and enable determinism */
1344 min_clk = dpm_context->dpm_tables.gfx_table.min;
1345 max_clk = dpm_context->dpm_tables.gfx_table.max;
1346 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1348 usleep_range(500, 1000);
1349 ret = smu_cmn_send_smc_msg_with_param(smu,
1350 SMU_MSG_EnableDeterminism,
1354 "Failed to enable determinism at GFX clock %d MHz\n", max);
1356 pstate_table->gfxclk_pstate.curr.min = min_clk;
1357 pstate_table->gfxclk_pstate.curr.max = max;
1365 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1366 long input[], uint32_t size)
1368 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1369 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1370 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1375 /* Only allowed in manual or determinism mode */
1376 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1377 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1381 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1383 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1387 if (input[0] == 0) {
1388 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1389 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1390 input[1], dpm_context->dpm_tables.gfx_table.min);
1391 pstate_table->gfxclk_pstate.custom.min =
1392 pstate_table->gfxclk_pstate.curr.min;
1396 pstate_table->gfxclk_pstate.custom.min = input[1];
1397 } else if (input[0] == 1) {
1398 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1399 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1400 input[1], dpm_context->dpm_tables.gfx_table.max);
1401 pstate_table->gfxclk_pstate.custom.max =
1402 pstate_table->gfxclk_pstate.curr.max;
1406 pstate_table->gfxclk_pstate.custom.max = input[1];
1411 case PP_OD_RESTORE_DEFAULT_TABLE:
1413 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1416 /* Use the default frequencies for manual and determinism mode */
1417 min_clk = dpm_context->dpm_tables.gfx_table.min;
1418 max_clk = dpm_context->dpm_tables.gfx_table.max;
1420 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1423 case PP_OD_COMMIT_DPM_TABLE:
1425 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1428 if (!pstate_table->gfxclk_pstate.custom.min)
1429 pstate_table->gfxclk_pstate.custom.min =
1430 pstate_table->gfxclk_pstate.curr.min;
1432 if (!pstate_table->gfxclk_pstate.custom.max)
1433 pstate_table->gfxclk_pstate.custom.max =
1434 pstate_table->gfxclk_pstate.curr.max;
1436 min_clk = pstate_table->gfxclk_pstate.custom.min;
1437 max_clk = pstate_table->gfxclk_pstate.custom.max;
1439 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1449 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1452 uint32_t feature_mask[2];
1453 unsigned long feature_enabled;
1455 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1458 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1459 ((uint64_t)feature_mask[1] << 32));
1460 return !!(feature_enabled & SMC_DPM_FEATURE);
1463 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1464 struct i2c_msg *msg, int num_msgs)
1466 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
1467 struct smu_table_context *smu_table = &adev->smu.smu_table;
1468 struct smu_table *table = &smu_table->driver_table;
1469 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1473 req = kzalloc(sizeof(*req), GFP_KERNEL);
1477 req->I2CcontrollerPort = 0;
1478 req->I2CSpeed = I2C_SPEED_FAST_400K;
1479 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1480 dir = msg[0].flags & I2C_M_RD;
1482 for (c = i = 0; i < num_msgs; i++) {
1483 for (j = 0; j < msg[i].len; j++, c++) {
1484 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1486 if (!(msg[i].flags & I2C_M_RD)) {
1488 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1489 cmd->ReadWriteData = msg[i].buf[j];
1492 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1493 /* The direction changes.
1495 dir = msg[i].flags & I2C_M_RD;
1496 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1502 * Insert STOP if we are at the last byte of either last
1503 * message for the transaction or the client explicitly
1504 * requires a STOP at this particular message.
1506 if ((j == msg[i].len - 1) &&
1507 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1508 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1509 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1513 mutex_lock(&adev->smu.mutex);
1514 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1515 mutex_unlock(&adev->smu.mutex);
1519 for (c = i = 0; i < num_msgs; i++) {
1520 if (!(msg[i].flags & I2C_M_RD)) {
1524 for (j = 0; j < msg[i].len; j++, c++) {
1525 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1527 msg[i].buf[j] = cmd->ReadWriteData;
1536 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1538 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1542 static const struct i2c_algorithm aldebaran_i2c_algo = {
1543 .master_xfer = aldebaran_i2c_xfer,
1544 .functionality = aldebaran_i2c_func,
1547 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1548 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1549 .max_read_len = MAX_SW_I2C_COMMANDS,
1550 .max_write_len = MAX_SW_I2C_COMMANDS,
1551 .max_comb_1st_msg_len = 2,
1552 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1555 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1557 struct amdgpu_device *adev = to_amdgpu_device(control);
1560 control->owner = THIS_MODULE;
1561 control->class = I2C_CLASS_SPD;
1562 control->dev.parent = &adev->pdev->dev;
1563 control->algo = &aldebaran_i2c_algo;
1564 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1565 control->quirks = &aldebaran_i2c_control_quirks;
1567 res = i2c_add_adapter(control);
1569 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1574 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1576 i2c_del_adapter(control);
1579 static void aldebaran_get_unique_id(struct smu_context *smu)
1581 struct amdgpu_device *adev = smu->adev;
1582 SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1583 uint32_t upper32 = 0, lower32 = 0;
1586 mutex_lock(&smu->metrics_lock);
1587 ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1591 upper32 = metrics->PublicSerialNumUpper32;
1592 lower32 = metrics->PublicSerialNumLower32;
1595 mutex_unlock(&smu->metrics_lock);
1597 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1598 sprintf(adev->serial, "%016llx", adev->unique_id);
1601 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1603 /* aldebaran is not support baco */
1608 static int aldebaran_set_df_cstate(struct smu_context *smu,
1609 enum pp_df_cstate state)
1611 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1614 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1616 return smu_cmn_send_smc_msg_with_param(smu,
1617 SMU_MSG_GmiPwrDnControl,
1622 static const struct throttling_logging_label {
1623 uint32_t feature_mask;
1625 } logging_label[] = {
1626 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1627 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1628 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1629 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1631 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1634 int throttler_idx, throtting_events = 0, buf_idx = 0;
1635 struct amdgpu_device *adev = smu->adev;
1636 uint32_t throttler_status;
1639 ret = aldebaran_get_smu_metrics_data(smu,
1640 METRICS_THROTTLER_STATUS,
1645 memset(log_buf, 0, sizeof(log_buf));
1646 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1648 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1650 buf_idx += snprintf(log_buf + buf_idx,
1651 sizeof(log_buf) - buf_idx,
1653 throtting_events > 1 ? " and " : "",
1654 logging_label[throttler_idx].label);
1655 if (buf_idx >= sizeof(log_buf)) {
1656 dev_err(adev->dev, "buffer overflow!\n");
1657 log_buf[sizeof(log_buf) - 1] = '\0';
1663 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1665 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1666 smu_cmn_get_indep_throttler_status(throttler_status,
1667 aldebaran_throttler_map));
1670 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1672 struct amdgpu_device *adev = smu->adev;
1675 /* TODO: confirm this on real target */
1676 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1677 if ((esm_ctrl >> 15) & 0x1FFFF)
1678 return (((esm_ctrl >> 8) & 0x3F) + 128);
1680 return smu_v13_0_get_current_pcie_link_speed(smu);
1683 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1686 struct smu_table_context *smu_table = &smu->smu_table;
1687 struct gpu_metrics_v1_3 *gpu_metrics =
1688 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1689 SmuMetrics_t metrics;
1692 ret = smu_cmn_get_metrics_table(smu,
1698 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1700 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1701 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1702 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1703 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1704 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1705 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1707 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1708 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1709 gpu_metrics->average_mm_activity = 0;
1711 /* Valid power data is available only from primary die */
1712 if (aldebaran_is_primary(smu)) {
1713 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1714 gpu_metrics->energy_accumulator =
1715 (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1716 metrics.EnergyAcc64bitLow;
1718 gpu_metrics->average_socket_power = 0;
1719 gpu_metrics->energy_accumulator = 0;
1722 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1723 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1724 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1725 gpu_metrics->average_vclk0_frequency = 0;
1726 gpu_metrics->average_dclk0_frequency = 0;
1728 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1729 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1730 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1731 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1732 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1734 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1735 gpu_metrics->indep_throttle_status =
1736 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1737 aldebaran_throttler_map);
1739 gpu_metrics->current_fan_speed = 0;
1741 gpu_metrics->pcie_link_width =
1742 smu_v13_0_get_current_pcie_link_width(smu);
1743 gpu_metrics->pcie_link_speed =
1744 aldebaran_get_current_pcie_link_speed(smu);
1746 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1748 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1749 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1751 for (i = 0; i < NUM_HBM_INSTANCES; i++)
1752 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1754 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1755 metrics.TimeStampLow;
1757 *table = (void *)gpu_metrics;
1759 return sizeof(struct gpu_metrics_v1_3);
1762 static int aldebaran_mode2_reset(struct smu_context *smu)
1766 struct amdgpu_device *adev = smu->adev;
1769 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1771 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1772 SMU_MSG_GfxDeviceDriverReset);
1774 mutex_lock(&smu->message_lock);
1775 if (smu_version >= 0x00441400) {
1776 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1777 /* This is similar to FLR, wait till max FLR timeout */
1779 dev_dbg(smu->adev->dev, "restore config space...\n");
1780 /* Restore the config space saved during init */
1781 amdgpu_device_load_pci_state(adev->pdev);
1783 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1784 while (ret == -ETIME && timeout) {
1785 ret = smu_cmn_wait_for_response(smu);
1786 /* Wait a bit more time for getting ACK */
1787 if (ret == -ETIME) {
1789 usleep_range(500, 1000);
1794 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1795 SMU_RESET_MODE_2, ret);
1801 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1808 mutex_unlock(&smu->message_lock);
1813 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1816 struct amdgpu_device *adev = smu->adev;
1820 * PM FW version support mode1 reset from 68.07
1822 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1823 if ((smu_version < 0x00440700))
1826 * mode1 reset relies on PSP, so we should check if
1829 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1836 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1841 static int aldebaran_set_mp1_state(struct smu_context *smu,
1842 enum pp_mp1_state mp1_state)
1844 switch (mp1_state) {
1845 case PP_MP1_STATE_UNLOAD:
1846 return smu_cmn_set_mp1_state(smu, mp1_state);
1852 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1857 /* message SMU to update the bad page number on SMUBUS */
1858 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1860 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1866 static const struct pptable_funcs aldebaran_ppt_funcs = {
1868 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1869 /* dpm/clk tables */
1870 .set_default_dpm_table = aldebaran_set_default_dpm_table,
1871 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1872 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1873 .print_clk_levels = aldebaran_print_clk_levels,
1874 .force_clk_levels = aldebaran_force_clk_levels,
1875 .read_sensor = aldebaran_read_sensor,
1876 .set_performance_level = aldebaran_set_performance_level,
1877 .get_power_limit = aldebaran_get_power_limit,
1878 .is_dpm_running = aldebaran_is_dpm_running,
1879 .get_unique_id = aldebaran_get_unique_id,
1880 .init_microcode = smu_v13_0_init_microcode,
1881 .load_microcode = smu_v13_0_load_microcode,
1882 .fini_microcode = smu_v13_0_fini_microcode,
1883 .init_smc_tables = aldebaran_init_smc_tables,
1884 .fini_smc_tables = smu_v13_0_fini_smc_tables,
1885 .init_power = smu_v13_0_init_power,
1886 .fini_power = smu_v13_0_fini_power,
1887 .check_fw_status = smu_v13_0_check_fw_status,
1888 /* pptable related */
1889 .setup_pptable = aldebaran_setup_pptable,
1890 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1891 .check_fw_version = smu_v13_0_check_fw_version,
1892 .write_pptable = smu_cmn_write_pptable,
1893 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1894 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1895 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1896 .system_features_control = aldebaran_system_features_control,
1897 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1898 .send_smc_msg = smu_cmn_send_smc_msg,
1899 .get_enabled_mask = smu_cmn_get_enabled_mask,
1900 .feature_is_enabled = smu_cmn_feature_is_enabled,
1901 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1902 .set_power_limit = aldebaran_set_power_limit,
1903 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
1904 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1905 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1906 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
1907 .register_irq_handler = smu_v13_0_register_irq_handler,
1908 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
1909 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
1910 .baco_is_support= aldebaran_is_baco_supported,
1911 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1912 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
1913 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
1914 .set_df_cstate = aldebaran_set_df_cstate,
1915 .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
1916 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
1917 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1918 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1919 .get_gpu_metrics = aldebaran_get_gpu_metrics,
1920 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1921 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1922 .mode1_reset = smu_v13_0_mode1_reset,
1923 .set_mp1_state = aldebaran_set_mp1_state,
1924 .mode2_reset = aldebaran_mode2_reset,
1925 .wait_for_event = smu_v13_0_wait_for_event,
1926 .i2c_init = aldebaran_i2c_control_init,
1927 .i2c_fini = aldebaran_i2c_control_fini,
1928 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
1931 void aldebaran_set_ppt_funcs(struct smu_context *smu)
1933 smu->ppt_funcs = &aldebaran_ppt_funcs;
1934 smu->message_map = aldebaran_message_map;
1935 smu->clock_map = aldebaran_clk_map;
1936 smu->feature_map = aldebaran_feature_mask_map;
1937 smu->table_map = aldebaran_table_map;