2 * Copyright 2019 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L3
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v12_0.h"
31 #include "soc15_common.h"
35 #include "asic_reg/mp/mp_12_0_0_offset.h"
36 #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
37 #include "asic_reg/smuio/smuio_12_0_0_offset.h"
38 #include "asic_reg/smuio/smuio_12_0_0_sh_mask.h"
41 * DO NOT use these for err/warn/info/debug messages.
42 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
43 * They are more MGPU friendly.
50 // because some SMU12 based ASICs use older ip offset tables
51 // we should undefine this register from the smuio12 header
52 // to prevent confusion down the road
53 #undef mmPWR_MISC_CNTL_STATUS
55 #define smnMP1_FIRMWARE_FLAGS 0x3010024
57 int smu_v12_0_check_fw_status(struct smu_context *smu)
59 struct amdgpu_device *adev = smu->adev;
60 uint32_t mp1_fw_flags;
62 mp1_fw_flags = RREG32_PCIE(MP1_Public |
63 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
65 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
66 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
72 int smu_v12_0_check_fw_version(struct smu_context *smu)
74 uint32_t if_version = 0xff, smu_version = 0xff;
76 uint8_t smu_minor, smu_debug;
79 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
83 smu_major = (smu_version >> 16) & 0xffff;
84 smu_minor = (smu_version >> 8) & 0xff;
85 smu_debug = (smu_version >> 0) & 0xff;
88 * 1. if_version mismatch is not critical as our fw is designed
89 * to be backward compatible.
90 * 2. New fw usually brings some optimizations. But that's visible
91 * only on the paired driver.
92 * Considering above, we just leave user a warning message instead
93 * of halt driver loading.
95 if (if_version != smu->smc_driver_if_version) {
96 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
97 "smu fw version = 0x%08x (%d.%d.%d)\n",
98 smu->smc_driver_if_version, if_version,
99 smu_version, smu_major, smu_minor, smu_debug);
100 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
106 int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
112 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownSdma, NULL);
114 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpSdma, NULL);
117 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
119 if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
122 return smu_cmn_send_smc_msg_with_param(smu,
129 * smu_v12_0_get_gfxoff_status - get gfxoff status
131 * @smu: amdgpu_device pointer
133 * This function will be used to get gfxoff status
135 * Returns 0=GFXOFF(default).
136 * Returns 1=Transition out of GFX State.
137 * Returns 2=Not in GFXOFF.
138 * Returns 3=Transition into GFXOFF.
140 uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
143 uint32_t gfxOff_Status = 0;
144 struct amdgpu_device *adev = smu->adev;
146 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
147 gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
148 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
150 return gfxOff_Status;
153 int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
155 int ret = 0, timeout = 500;
158 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
161 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
163 /* confirm gfx is back to "on" state, timeout is 0.5 second */
164 while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
168 DRM_ERROR("disable gfxoff timeout and failed!\n");
177 int smu_v12_0_fini_smc_tables(struct smu_context *smu)
179 struct smu_table_context *smu_table = &smu->smu_table;
181 kfree(smu_table->clocks_table);
182 smu_table->clocks_table = NULL;
184 kfree(smu_table->metrics_table);
185 smu_table->metrics_table = NULL;
187 kfree(smu_table->watermarks_table);
188 smu_table->watermarks_table = NULL;
193 int smu_v12_0_set_default_dpm_tables(struct smu_context *smu)
195 struct smu_table_context *smu_table = &smu->smu_table;
197 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
200 int smu_v12_0_mode2_reset(struct smu_context *smu){
201 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
204 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
205 uint32_t min, uint32_t max)
209 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
215 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min, NULL);
219 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max, NULL);
225 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
229 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max, NULL);
234 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min, NULL);
238 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max, NULL);
243 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min, NULL);
247 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max, NULL);
258 int smu_v12_0_set_driver_table_location(struct smu_context *smu)
260 struct smu_table *driver_table = &smu->smu_table.driver_table;
263 if (driver_table->mc_address) {
264 ret = smu_cmn_send_smc_msg_with_param(smu,
265 SMU_MSG_SetDriverDramAddrHigh,
266 upper_32_bits(driver_table->mc_address),
269 ret = smu_cmn_send_smc_msg_with_param(smu,
270 SMU_MSG_SetDriverDramAddrLow,
271 lower_32_bits(driver_table->mc_address),
278 void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
280 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
282 gpu_metrics->common_header.structure_size =
283 sizeof(struct gpu_metrics_v2_0);
284 gpu_metrics->common_header.format_revision = 2;
285 gpu_metrics->common_header.content_revision = 0;
287 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();