drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v12_0_ppsmc.h"
  29 #include "smu12_driver_if.h"
  30 #include "smu_v12_0.h"
  31 #include "renoir_ppt.h"
  32 #include "smu_cmn.h"
  33
  34 /*
  35  * DO NOT use these for err/warn/info/debug messages.
  36  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  37  * They are more MGPU friendly.
  38  */
  39 #undef pr_err
  40 #undef pr_warn
  41 #undef pr_info
  42 #undef pr_debug
  43
  44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
  45         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  46         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  47         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  48         MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx,                   1),
  49         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff,                 1),
  50         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff,                1),
  51         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,           1),
  52         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,             1),
  53         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 1),
  54         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   1),
  55         MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma,                1),
  56         MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma,                  1),
  57         MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq,       1),
  58         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                1),
  59         MSG_MAP(Spare1,                         PPSMC_MSG_spare1,                       1),
  60         MSG_MAP(Spare2,                         PPSMC_MSG_spare2,                       1),
  61         MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch,           1),
  62         MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq,        1),
  63         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          1),
  64         MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy,              1),
  65         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  1),
  66         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount,              1),
  67         MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit,              1),
  68         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  69         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  70         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  71         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
  72         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         1),
  73         MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid,  1),
  74         MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq,       1),
  75         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
  76         MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS,               1),
  77         MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq,          1),
  78         MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk,        1),
  79         MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx,            1),
  80         MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq,       1),
  81         MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq,       1),
  82         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                1),
  83         MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,               1),
  84         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,           1),
  85         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             1),
  86         MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency,        1),
  87         MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency,        1),
  88         MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset,                    1),
  89         MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG,                   1),
  90         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             1),
  91         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
  92         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
  93         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
  94         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                1),
  95         MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub,               1),
  96         MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore,             1),
  97         MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState,               1),
  98         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      1),
  99         MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave,          1),
 100         MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
 101         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                1),
 102         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  1),
 103         MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub,               1),
 104         MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg,               1),
 105         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
 106 };
 107
 108 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
 109         CLK_MAP(GFXCLK, CLOCK_GFXCLK),
 110         CLK_MAP(SCLK,   CLOCK_GFXCLK),
 111         CLK_MAP(SOCCLK, CLOCK_SOCCLK),
 112         CLK_MAP(UCLK, CLOCK_FCLK),
 113         CLK_MAP(MCLK, CLOCK_FCLK),
 114 };
 115
 116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
 117         TAB_MAP_VALID(WATERMARKS),
 118         TAB_MAP_INVALID(CUSTOM_DPM),
 119         TAB_MAP_VALID(DPMCLOCKS),
 120         TAB_MAP_VALID(SMU_METRICS),
 121 };
 122
 123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 124         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 125         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 126         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 127         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 128         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 129 };
 130
 131 static int renoir_init_smc_tables(struct smu_context *smu)
 132 {
 133         struct smu_table_context *smu_table = &smu->smu_table;
 134         struct smu_table *tables = smu_table->tables;
 135
 136         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 137                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 138         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 139                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 140         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 141                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 142
 143         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 144         if (!smu_table->clocks_table)
 145                 goto err0_out;
 146
 147         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 148         if (!smu_table->metrics_table)
 149                 goto err1_out;
 150         smu_table->metrics_time = 0;
 151
 152         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 153         if (!smu_table->watermarks_table)
 154                 goto err2_out;
 155
 156         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
 157         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 158         if (!smu_table->gpu_metrics_table)
 159                 goto err3_out;
 160
 161         return 0;
 162
 163 err3_out:
 164         kfree(smu_table->watermarks_table);
 165 err2_out:
 166         kfree(smu_table->metrics_table);
 167 err1_out:
 168         kfree(smu_table->clocks_table);
 169 err0_out:
 170         return -ENOMEM;
 171 }
 172
 173 /*
 174  * This interface just for getting uclk ultimate freq and should't introduce
 175  * other likewise function result in overmuch callback.
 176  */
 177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
 178                                                 uint32_t dpm_level, uint32_t *freq)
 179 {
 180         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 181
 182         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 183                 return -EINVAL;
 184
 185         switch (clk_type) {
 186         case SMU_SOCCLK:
 187                 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
 188                         return -EINVAL;
 189                 *freq = clk_table->SocClocks[dpm_level].Freq;
 190                 break;
 191         case SMU_UCLK:
 192         case SMU_MCLK:
 193                 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
 194                         return -EINVAL;
 195                 *freq = clk_table->FClocks[dpm_level].Freq;
 196                 break;
 197         case SMU_DCEFCLK:
 198                 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
 199                         return -EINVAL;
 200                 *freq = clk_table->DcfClocks[dpm_level].Freq;
 201                 break;
 202         case SMU_FCLK:
 203                 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
 204                         return -EINVAL;
 205                 *freq = clk_table->FClocks[dpm_level].Freq;
 206                 break;
 207         default:
 208                 return -EINVAL;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
 215                                          enum amd_dpm_forced_level level,
 216                                          uint32_t *sclk_mask,
 217                                          uint32_t *mclk_mask,
 218                                          uint32_t *soc_mask)
 219 {
 220
 221         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
 222                 if (sclk_mask)
 223                         *sclk_mask = 0;
 224         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
 225                 if (mclk_mask)
 226                         /* mclk levels are in reverse order */
 227                         *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
 228         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
 229                 if(sclk_mask)
 230                         /* The sclk as gfxclk and has three level about max/min/current */
 231                         *sclk_mask = 3 - 1;
 232
 233                 if(mclk_mask)
 234                         /* mclk levels are in reverse order */
 235                         *mclk_mask = 0;
 236
 237                 if(soc_mask)
 238                         *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
 245                                         enum smu_clk_type clk_type,
 246                                         uint32_t *min,
 247                                         uint32_t *max)
 248 {
 249         int ret = 0;
 250         uint32_t mclk_mask, soc_mask;
 251         uint32_t clock_limit;
 252
 253         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
 254                 switch (clk_type) {
 255                 case SMU_MCLK:
 256                 case SMU_UCLK:
 257                         clock_limit = smu->smu_table.boot_values.uclk;
 258                         break;
 259                 case SMU_GFXCLK:
 260                 case SMU_SCLK:
 261                         clock_limit = smu->smu_table.boot_values.gfxclk;
 262                         break;
 263                 case SMU_SOCCLK:
 264                         clock_limit = smu->smu_table.boot_values.socclk;
 265                         break;
 266                 default:
 267                         clock_limit = 0;
 268                         break;
 269                 }
 270
 271                 /* clock in Mhz unit */
 272                 if (min)
 273                         *min = clock_limit / 100;
 274                 if (max)
 275                         *max = clock_limit / 100;
 276
 277                 return 0;
 278         }
 279
 280         if (max) {
 281                 ret = renoir_get_profiling_clk_mask(smu,
 282                                                     AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
 283                                                     NULL,
 284                                                     &mclk_mask,
 285                                                     &soc_mask);
 286                 if (ret)
 287                         goto failed;
 288
 289                 switch (clk_type) {
 290                 case SMU_GFXCLK:
 291                 case SMU_SCLK:
 292                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
 293                         if (ret) {
 294                                 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
 295                                 goto failed;
 296                         }
 297                         break;
 298                 case SMU_UCLK:
 299                 case SMU_FCLK:
 300                 case SMU_MCLK:
 301                         ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
 302                         if (ret)
 303                                 goto failed;
 304                         break;
 305                 case SMU_SOCCLK:
 306                         ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
 307                         if (ret)
 308                                 goto failed;
 309                         break;
 310                 default:
 311                         ret = -EINVAL;
 312                         goto failed;
 313                 }
 314         }
 315
 316         if (min) {
 317                 switch (clk_type) {
 318                 case SMU_GFXCLK:
 319                 case SMU_SCLK:
 320                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
 321                         if (ret) {
 322                                 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
 323                                 goto failed;
 324                         }
 325                         break;
 326                 case SMU_UCLK:
 327                 case SMU_FCLK:
 328                 case SMU_MCLK:
 329                         ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
 330                         if (ret)
 331                                 goto failed;
 332                         break;
 333                 case SMU_SOCCLK:
 334                         ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
 335                         if (ret)
 336                                 goto failed;
 337                         break;
 338                 default:
 339                         ret = -EINVAL;
 340                         goto failed;
 341                 }
 342         }
 343 failed:
 344         return ret;
 345 }
 346
 347 static int renoir_od_edit_dpm_table(struct smu_context *smu,
 348                                                         enum PP_OD_DPM_TABLE_COMMAND type,
 349                                                         long input[], uint32_t size)
 350 {
 351         int ret = 0;
 352         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 353
 354         if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
 355                 dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
 356                 return -EINVAL;
 357         }
 358
 359         switch (type) {
 360         case PP_OD_EDIT_SCLK_VDDC_TABLE:
 361                 if (size != 2) {
 362                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 363                         return -EINVAL;
 364                 }
 365
 366                 if (input[0] == 0) {
 367                         if (input[1] < smu->gfx_default_hard_min_freq) {
 368                                 dev_warn(smu->adev->dev,
 369                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
 370                                         input[1], smu->gfx_default_hard_min_freq);
 371                                 return -EINVAL;
 372                         }
 373                         smu->gfx_actual_hard_min_freq = input[1];
 374                 } else if (input[0] == 1) {
 375                         if (input[1] > smu->gfx_default_soft_max_freq) {
 376                                 dev_warn(smu->adev->dev,
 377                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
 378                                         input[1], smu->gfx_default_soft_max_freq);
 379                                 return -EINVAL;
 380                         }
 381                         smu->gfx_actual_soft_max_freq = input[1];
 382                 } else {
 383                         return -EINVAL;
 384                 }
 385                 break;
 386         case PP_OD_RESTORE_DEFAULT_TABLE:
 387                 if (size != 0) {
 388                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 389                         return -EINVAL;
 390                 }
 391                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 392                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 393
 394                 ret = smu_cmn_send_smc_msg_with_param(smu,
 395                                                                 SMU_MSG_SetHardMinGfxClk,
 396                                                                 smu->gfx_actual_hard_min_freq,
 397                                                                 NULL);
 398                 if (ret) {
 399                         dev_err(smu->adev->dev, "Restore the default hard min sclk failed!");
 400                         return ret;
 401                 }
 402
 403                 ret = smu_cmn_send_smc_msg_with_param(smu,
 404                                                                 SMU_MSG_SetSoftMaxGfxClk,
 405                                                                 smu->gfx_actual_soft_max_freq,
 406                                                                 NULL);
 407                 if (ret) {
 408                         dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
 409                         return ret;
 410                 }
 411                 break;
 412         case PP_OD_COMMIT_DPM_TABLE:
 413                 if (size != 0) {
 414                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 415                         return -EINVAL;
 416                 } else {
 417                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
 418                                 dev_err(smu->adev->dev,
 419                                         "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
 420                                         smu->gfx_actual_hard_min_freq,
 421                                         smu->gfx_actual_soft_max_freq);
 422                                 return -EINVAL;
 423                         }
 424
 425                         ret = smu_cmn_send_smc_msg_with_param(smu,
 426                                                                 SMU_MSG_SetHardMinGfxClk,
 427                                                                 smu->gfx_actual_hard_min_freq,
 428                                                                 NULL);
 429                         if (ret) {
 430                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
 431                                 return ret;
 432                         }
 433
 434                         ret = smu_cmn_send_smc_msg_with_param(smu,
 435                                                                 SMU_MSG_SetSoftMaxGfxClk,
 436                                                                 smu->gfx_actual_soft_max_freq,
 437                                                                 NULL);
 438                         if (ret) {
 439                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
 440                                 return ret;
 441                         }
 442                 }
 443                 break;
 444         default:
 445                 return -ENOSYS;
 446         }
 447
 448         return ret;
 449 }
 450
 451 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
 452 {
 453         uint32_t min = 0, max = 0;
 454         uint32_t ret = 0;
 455
 456         ret = smu_cmn_send_smc_msg_with_param(smu,
 457                                                                 SMU_MSG_GetMinGfxclkFrequency,
 458                                                                 0, &min);
 459         if (ret)
 460                 return ret;
 461         ret = smu_cmn_send_smc_msg_with_param(smu,
 462                                                                 SMU_MSG_GetMaxGfxclkFrequency,
 463                                                                 0, &max);
 464         if (ret)
 465                 return ret;
 466
 467         smu->gfx_default_hard_min_freq = min;
 468         smu->gfx_default_soft_max_freq = max;
 469         smu->gfx_actual_hard_min_freq = 0;
 470         smu->gfx_actual_soft_max_freq = 0;
 471
 472         return 0;
 473 }
 474
 475 static int renoir_print_clk_levels(struct smu_context *smu,
 476                         enum smu_clk_type clk_type, char *buf)
 477 {
 478         int i, size = 0, ret = 0;
 479         uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
 480         SmuMetrics_t metrics;
 481         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 482         bool cur_value_match_level = false;
 483
 484         memset(&metrics, 0, sizeof(metrics));
 485
 486         ret = smu_cmn_get_metrics_table(smu, &metrics, false);
 487         if (ret)
 488                 return ret;
 489
 490         switch (clk_type) {
 491         case SMU_OD_RANGE:
 492                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 493                         ret = smu_cmn_send_smc_msg_with_param(smu,
 494                                                 SMU_MSG_GetMinGfxclkFrequency,
 495                                                 0, &min);
 496                         if (ret)
 497                                 return ret;
 498                         ret = smu_cmn_send_smc_msg_with_param(smu,
 499                                                 SMU_MSG_GetMaxGfxclkFrequency,
 500                                                 0, &max);
 501                         if (ret)
 502                                 return ret;
 503                         size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
 504                 }
 505                 break;
 506         case SMU_OD_SCLK:
 507                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 508                         min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
 509                         max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
 510                         size += sprintf(buf + size, "OD_SCLK\n");
 511                         size += sprintf(buf + size, "0:%10uMhz\n", min);
 512                         size += sprintf(buf + size, "1:%10uMhz\n", max);
 513                 }
 514                 break;
 515         case SMU_GFXCLK:
 516         case SMU_SCLK:
 517                 /* retirve table returned paramters unit is MHz */
 518                 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
 519                 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
 520                 if (!ret) {
 521                         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 522                         if (cur_value  == max)
 523                                 i = 2;
 524                         else if (cur_value == min)
 525                                 i = 0;
 526                         else
 527                                 i = 1;
 528
 529                         size += sprintf(buf + size, "0: %uMhz %s\n", min,
 530                                         i == 0 ? "*" : "");
 531                         size += sprintf(buf + size, "1: %uMhz %s\n",
 532                                         i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
 533                                         i == 1 ? "*" : "");
 534                         size += sprintf(buf + size, "2: %uMhz %s\n", max,
 535                                         i == 2 ? "*" : "");
 536                 }
 537                 return size;
 538         case SMU_SOCCLK:
 539                 count = NUM_SOCCLK_DPM_LEVELS;
 540                 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
 541                 break;
 542         case SMU_MCLK:
 543                 count = NUM_MEMCLK_DPM_LEVELS;
 544                 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 545                 break;
 546         case SMU_DCEFCLK:
 547                 count = NUM_DCFCLK_DPM_LEVELS;
 548                 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
 549                 break;
 550         case SMU_FCLK:
 551                 count = NUM_FCLK_DPM_LEVELS;
 552                 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 553                 break;
 554         default:
 555                 break;
 556         }
 557
 558         switch (clk_type) {
 559         case SMU_GFXCLK:
 560         case SMU_SCLK:
 561         case SMU_SOCCLK:
 562         case SMU_MCLK:
 563         case SMU_DCEFCLK:
 564         case SMU_FCLK:
 565                 for (i = 0; i < count; i++) {
 566                         ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
 567                         if (ret)
 568                                 return ret;
 569                         if (!value)
 570                                 continue;
 571                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 572                                         cur_value == value ? "*" : "");
 573                         if (cur_value == value)
 574                                 cur_value_match_level = true;
 575                 }
 576
 577                 if (!cur_value_match_level)
 578                         size += sprintf(buf + size, "   %uMhz *\n", cur_value);
 579
 580                 break;
 581         default:
 582                 break;
 583         }
 584
 585         return size;
 586 }
 587
 588 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
 589 {
 590         enum amd_pm_state_type pm_type;
 591         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 592
 593         if (!smu_dpm_ctx->dpm_context ||
 594             !smu_dpm_ctx->dpm_current_power_state)
 595                 return -EINVAL;
 596
 597         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 598         case SMU_STATE_UI_LABEL_BATTERY:
 599                 pm_type = POWER_STATE_TYPE_BATTERY;
 600                 break;
 601         case SMU_STATE_UI_LABEL_BALLANCED:
 602                 pm_type = POWER_STATE_TYPE_BALANCED;
 603                 break;
 604         case SMU_STATE_UI_LABEL_PERFORMANCE:
 605                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 606                 break;
 607         default:
 608                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 609                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 610                 else
 611                         pm_type = POWER_STATE_TYPE_DEFAULT;
 612                 break;
 613         }
 614
 615         return pm_type;
 616 }
 617
 618 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 619 {
 620         int ret = 0;
 621
 622         if (enable) {
 623                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 624                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 625                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 626                         if (ret)
 627                                 return ret;
 628                 }
 629         } else {
 630                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 631                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 632                         if (ret)
 633                                 return ret;
 634                 }
 635         }
 636
 637         return ret;
 638 }
 639
 640 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 641 {
 642         int ret = 0;
 643
 644         if (enable) {
 645                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 646                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 647                         if (ret)
 648                                 return ret;
 649                 }
 650         } else {
 651                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 652                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 653                         if (ret)
 654                                 return ret;
 655                 }
 656         }
 657
 658         return ret;
 659 }
 660
 661 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
 662 {
 663         int ret = 0, i = 0;
 664         uint32_t min_freq, max_freq, force_freq;
 665         enum smu_clk_type clk_type;
 666
 667         enum smu_clk_type clks[] = {
 668                 SMU_GFXCLK,
 669                 SMU_MCLK,
 670                 SMU_SOCCLK,
 671         };
 672
 673         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 674                 clk_type = clks[i];
 675                 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
 676                 if (ret)
 677                         return ret;
 678
 679                 force_freq = highest ? max_freq : min_freq;
 680                 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
 681                 if (ret)
 682                         return ret;
 683         }
 684
 685         return ret;
 686 }
 687
 688 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
 689
 690         int ret = 0, i = 0;
 691         uint32_t min_freq, max_freq;
 692         enum smu_clk_type clk_type;
 693
 694         struct clk_feature_map {
 695                 enum smu_clk_type clk_type;
 696                 uint32_t        feature;
 697         } clk_feature_map[] = {
 698                 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
 699                 {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
 700                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
 701         };
 702
 703         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
 704                 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
 705                     continue;
 706
 707                 clk_type = clk_feature_map[i].clk_type;
 708
 709                 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
 710                 if (ret)
 711                         return ret;
 712
 713                 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
 714                 if (ret)
 715                         return ret;
 716         }
 717
 718         return ret;
 719 }
 720
 721 /*
 722  * This interface get dpm clock table for dc
 723  */
 724 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
 725 {
 726         DpmClocks_t *table = smu->smu_table.clocks_table;
 727         int i;
 728
 729         if (!clock_table || !table)
 730                 return -EINVAL;
 731
 732         for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
 733                 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
 734                 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
 735         }
 736
 737         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
 738                 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
 739                 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
 740         }
 741
 742         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
 743                 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
 744                 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
 745         }
 746
 747         for (i = 0; i<  NUM_MEMCLK_DPM_LEVELS; i++) {
 748                 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
 749                 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int renoir_force_clk_levels(struct smu_context *smu,
 756                                    enum smu_clk_type clk_type, uint32_t mask)
 757 {
 758
 759         int ret = 0 ;
 760         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 761
 762         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 763         soft_max_level = mask ? (fls(mask) - 1) : 0;
 764
 765         switch (clk_type) {
 766         case SMU_GFXCLK:
 767         case SMU_SCLK:
 768                 if (soft_min_level > 2 || soft_max_level > 2) {
 769                         dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
 770                         return -EINVAL;
 771                 }
 772
 773                 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
 774                 if (ret)
 775                         return ret;
 776                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 777                                         soft_max_level == 0 ? min_freq :
 778                                         soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
 779                                         NULL);
 780                 if (ret)
 781                         return ret;
 782                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 783                                         soft_min_level == 2 ? max_freq :
 784                                         soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
 785                                         NULL);
 786                 if (ret)
 787                         return ret;
 788                 break;
 789         case SMU_SOCCLK:
 790                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
 791                 if (ret)
 792                         return ret;
 793                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
 794                 if (ret)
 795                         return ret;
 796                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
 797                 if (ret)
 798                         return ret;
 799                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
 800                 if (ret)
 801                         return ret;
 802                 break;
 803         case SMU_MCLK:
 804         case SMU_FCLK:
 805                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
 806                 if (ret)
 807                         return ret;
 808                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
 809                 if (ret)
 810                         return ret;
 811                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
 812                 if (ret)
 813                         return ret;
 814                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
 815                 if (ret)
 816                         return ret;
 817                 break;
 818         default:
 819                 break;
 820         }
 821
 822         return ret;
 823 }
 824
 825 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
 826 {
 827         int workload_type, ret;
 828         uint32_t profile_mode = input[size];
 829
 830         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
 831                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
 832                 return -EINVAL;
 833         }
 834
 835         if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
 836                         profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
 837                 return 0;
 838
 839         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 840         workload_type = smu_cmn_to_asic_specific_index(smu,
 841                                                        CMN2ASIC_MAPPING_WORKLOAD,
 842                                                        profile_mode);
 843         if (workload_type < 0) {
 844                 /*
 845                  * TODO: If some case need switch to powersave/default power mode
 846                  * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
 847                  */
 848                 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
 849                 return -EINVAL;
 850         }
 851
 852         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
 853                                     1 << workload_type,
 854                                     NULL);
 855         if (ret) {
 856                 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
 857                 return ret;
 858         }
 859
 860         smu->power_profile_mode = profile_mode;
 861
 862         return 0;
 863 }
 864
 865 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
 866 {
 867         int ret = 0;
 868         uint32_t sclk_freq = 0, uclk_freq = 0;
 869
 870         ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
 871         if (ret)
 872                 return ret;
 873
 874         ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
 875         if (ret)
 876                 return ret;
 877
 878         ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
 879         if (ret)
 880                 return ret;
 881
 882         ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
 883         if (ret)
 884                 return ret;
 885
 886         return ret;
 887 }
 888
 889 static int renoir_set_performance_level(struct smu_context *smu,
 890                                         enum amd_dpm_forced_level level)
 891 {
 892         int ret = 0;
 893         uint32_t sclk_mask, mclk_mask, soc_mask;
 894
 895         switch (level) {
 896         case AMD_DPM_FORCED_LEVEL_HIGH:
 897                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 898                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 899
 900                 ret = renoir_force_dpm_limit_value(smu, true);
 901                 break;
 902         case AMD_DPM_FORCED_LEVEL_LOW:
 903                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 904                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 905
 906                 ret = renoir_force_dpm_limit_value(smu, false);
 907                 break;
 908         case AMD_DPM_FORCED_LEVEL_AUTO:
 909                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 910                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 911
 912                 ret = renoir_unforce_dpm_levels(smu);
 913                 break;
 914         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 915                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 916                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 917
 918                 ret = smu_cmn_send_smc_msg_with_param(smu,
 919                                                       SMU_MSG_SetHardMinGfxClk,
 920                                                       RENOIR_UMD_PSTATE_GFXCLK,
 921                                                       NULL);
 922                 if (ret)
 923                         return ret;
 924                 ret = smu_cmn_send_smc_msg_with_param(smu,
 925                                                       SMU_MSG_SetHardMinFclkByFreq,
 926                                                       RENOIR_UMD_PSTATE_FCLK,
 927                                                       NULL);
 928                 if (ret)
 929                         return ret;
 930                 ret = smu_cmn_send_smc_msg_with_param(smu,
 931                                                       SMU_MSG_SetHardMinSocclkByFreq,
 932                                                       RENOIR_UMD_PSTATE_SOCCLK,
 933                                                       NULL);
 934                 if (ret)
 935                         return ret;
 936                 ret = smu_cmn_send_smc_msg_with_param(smu,
 937                                                       SMU_MSG_SetHardMinVcn,
 938                                                       RENOIR_UMD_PSTATE_VCNCLK,
 939                                                       NULL);
 940                 if (ret)
 941                         return ret;
 942
 943                 ret = smu_cmn_send_smc_msg_with_param(smu,
 944                                                       SMU_MSG_SetSoftMaxGfxClk,
 945                                                       RENOIR_UMD_PSTATE_GFXCLK,
 946                                                       NULL);
 947                 if (ret)
 948                         return ret;
 949                 ret = smu_cmn_send_smc_msg_with_param(smu,
 950                                                       SMU_MSG_SetSoftMaxFclkByFreq,
 951                                                       RENOIR_UMD_PSTATE_FCLK,
 952                                                       NULL);
 953                 if (ret)
 954                         return ret;
 955                 ret = smu_cmn_send_smc_msg_with_param(smu,
 956                                                       SMU_MSG_SetSoftMaxSocclkByFreq,
 957                                                       RENOIR_UMD_PSTATE_SOCCLK,
 958                                                       NULL);
 959                 if (ret)
 960                         return ret;
 961                 ret = smu_cmn_send_smc_msg_with_param(smu,
 962                                                       SMU_MSG_SetSoftMaxVcn,
 963                                                       RENOIR_UMD_PSTATE_VCNCLK,
 964                                                       NULL);
 965                 if (ret)
 966                         return ret;
 967                 break;
 968         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 969         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 970                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 971                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 972
 973                 ret = renoir_get_profiling_clk_mask(smu, level,
 974                                                     &sclk_mask,
 975                                                     &mclk_mask,
 976                                                     &soc_mask);
 977                 if (ret)
 978                         return ret;
 979                 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
 980                 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
 981                 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
 982                 break;
 983         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 984                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 985                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 986
 987                 ret = renoir_set_peak_clock_by_device(smu);
 988                 break;
 989         case AMD_DPM_FORCED_LEVEL_MANUAL:
 990         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 991         default:
 992                 break;
 993         }
 994         return ret;
 995 }
 996
 997 /* save watermark settings into pplib smu structure,
 998  * also pass data to smu controller
 999  */
1000 static int renoir_set_watermarks_table(
1001                 struct smu_context *smu,
1002                 struct pp_smu_wm_range_sets *clock_ranges)
1003 {
1004         Watermarks_t *table = smu->smu_table.watermarks_table;
1005         int ret = 0;
1006         int i;
1007
1008         if (clock_ranges) {
1009                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1010                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1011                         return -EINVAL;
1012
1013                 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1014                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1015                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
1016                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1017                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1018                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1019                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1020                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1021                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1022                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1023
1024                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1025                                 clock_ranges->reader_wm_sets[i].wm_inst;
1026                         table->WatermarkRow[WM_DCFCLK][i].WmType =
1027                                 clock_ranges->reader_wm_sets[i].wm_type;
1028                 }
1029
1030                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1031                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1032                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1033                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1034                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1035                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1036                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1037                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1038                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1039
1040                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1041                                 clock_ranges->writer_wm_sets[i].wm_inst;
1042                         table->WatermarkRow[WM_SOCCLK][i].WmType =
1043                                 clock_ranges->writer_wm_sets[i].wm_type;
1044                 }
1045
1046                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1047         }
1048
1049         /* pass data to smu controller */
1050         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1051              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1052                 ret = smu_cmn_write_watermarks_table(smu);
1053                 if (ret) {
1054                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1055                         return ret;
1056                 }
1057                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int renoir_get_power_profile_mode(struct smu_context *smu,
1064                                            char *buf)
1065 {
1066         static const char *profile_name[] = {
1067                                         "BOOTUP_DEFAULT",
1068                                         "3D_FULL_SCREEN",
1069                                         "POWER_SAVING",
1070                                         "VIDEO",
1071                                         "VR",
1072                                         "COMPUTE",
1073                                         "CUSTOM"};
1074         uint32_t i, size = 0;
1075         int16_t workload_type = 0;
1076
1077         if (!buf)
1078                 return -EINVAL;
1079
1080         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1081                 /*
1082                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1083                  * Not all profile modes are supported on arcturus.
1084                  */
1085                 workload_type = smu_cmn_to_asic_specific_index(smu,
1086                                                                CMN2ASIC_MAPPING_WORKLOAD,
1087                                                                i);
1088                 if (workload_type < 0)
1089                         continue;
1090
1091                 size += sprintf(buf + size, "%2d %14s%s\n",
1092                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1093         }
1094
1095         return size;
1096 }
1097
1098 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1099                                        MetricsMember_t member,
1100                                        uint32_t *value)
1101 {
1102         struct smu_table_context *smu_table = &smu->smu_table;
1103
1104         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
1105         int ret = 0;
1106
1107         mutex_lock(&smu->metrics_lock);
1108
1109         ret = smu_cmn_get_metrics_table_locked(smu,
1110                                                NULL,
1111                                                false);
1112         if (ret) {
1113                 mutex_unlock(&smu->metrics_lock);
1114                 return ret;
1115         }
1116
1117         switch (member) {
1118         case METRICS_AVERAGE_GFXCLK:
1119                 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
1120                 break;
1121         case METRICS_AVERAGE_SOCCLK:
1122                 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
1123                 break;
1124         case METRICS_AVERAGE_UCLK:
1125                 *value = metrics->ClockFrequency[CLOCK_FCLK];
1126                 break;
1127         case METRICS_AVERAGE_GFXACTIVITY:
1128                 *value = metrics->AverageGfxActivity / 100;
1129                 break;
1130         case METRICS_AVERAGE_VCNACTIVITY:
1131                 *value = metrics->AverageUvdActivity / 100;
1132                 break;
1133         case METRICS_AVERAGE_SOCKETPOWER:
1134                 *value = metrics->CurrentSocketPower << 8;
1135                 break;
1136         case METRICS_TEMPERATURE_EDGE:
1137                 *value = (metrics->GfxTemperature / 100) *
1138                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1139                 break;
1140         case METRICS_TEMPERATURE_HOTSPOT:
1141                 *value = (metrics->SocTemperature / 100) *
1142                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1143                 break;
1144         case METRICS_THROTTLER_STATUS:
1145                 *value = metrics->ThrottlerStatus;
1146                 break;
1147         case METRICS_VOLTAGE_VDDGFX:
1148                 *value = metrics->Voltage[0];
1149                 break;
1150         case METRICS_VOLTAGE_VDDSOC:
1151                 *value = metrics->Voltage[1];
1152                 break;
1153         default:
1154                 *value = UINT_MAX;
1155                 break;
1156         }
1157
1158         mutex_unlock(&smu->metrics_lock);
1159
1160         return ret;
1161 }
1162
1163 static int renoir_read_sensor(struct smu_context *smu,
1164                                  enum amd_pp_sensors sensor,
1165                                  void *data, uint32_t *size)
1166 {
1167         int ret = 0;
1168
1169         if (!data || !size)
1170                 return -EINVAL;
1171
1172         mutex_lock(&smu->sensor_lock);
1173         switch (sensor) {
1174         case AMDGPU_PP_SENSOR_GPU_LOAD:
1175                 ret = renoir_get_smu_metrics_data(smu,
1176                                                   METRICS_AVERAGE_GFXACTIVITY,
1177                                                   (uint32_t *)data);
1178                 *size = 4;
1179                 break;
1180         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1181                 ret = renoir_get_smu_metrics_data(smu,
1182                                                   METRICS_TEMPERATURE_EDGE,
1183                                                   (uint32_t *)data);
1184                 *size = 4;
1185                 break;
1186         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1187                 ret = renoir_get_smu_metrics_data(smu,
1188                                                   METRICS_TEMPERATURE_HOTSPOT,
1189                                                   (uint32_t *)data);
1190                 *size = 4;
1191                 break;
1192         case AMDGPU_PP_SENSOR_GFX_MCLK:
1193                 ret = renoir_get_smu_metrics_data(smu,
1194                                                   METRICS_AVERAGE_UCLK,
1195                                                   (uint32_t *)data);
1196                 *(uint32_t *)data *= 100;
1197                 *size = 4;
1198                 break;
1199         case AMDGPU_PP_SENSOR_GFX_SCLK:
1200                 ret = renoir_get_smu_metrics_data(smu,
1201                                                   METRICS_AVERAGE_GFXCLK,
1202                                                   (uint32_t *)data);
1203                 *(uint32_t *)data *= 100;
1204                 *size = 4;
1205                 break;
1206         case AMDGPU_PP_SENSOR_VDDGFX:
1207                 ret = renoir_get_smu_metrics_data(smu,
1208                                                   METRICS_VOLTAGE_VDDGFX,
1209                                                   (uint32_t *)data);
1210                 *size = 4;
1211                 break;
1212         case AMDGPU_PP_SENSOR_VDDNB:
1213                 ret = renoir_get_smu_metrics_data(smu,
1214                                                   METRICS_VOLTAGE_VDDSOC,
1215                                                   (uint32_t *)data);
1216                 *size = 4;
1217                 break;
1218         case AMDGPU_PP_SENSOR_GPU_POWER:
1219                 ret = renoir_get_smu_metrics_data(smu,
1220                                                   METRICS_AVERAGE_SOCKETPOWER,
1221                                                   (uint32_t *)data);
1222                 *size = 4;
1223                 break;
1224         default:
1225                 ret = -EOPNOTSUPP;
1226                 break;
1227         }
1228         mutex_unlock(&smu->sensor_lock);
1229
1230         return ret;
1231 }
1232
1233 static bool renoir_is_dpm_running(struct smu_context *smu)
1234 {
1235         struct amdgpu_device *adev = smu->adev;
1236
1237         /*
1238          * Until now, the pmfw hasn't exported the interface of SMU
1239          * feature mask to APU SKU so just force on all the feature
1240          * at early initial stage.
1241          */
1242         if (adev->in_suspend)
1243                 return false;
1244         else
1245                 return true;
1246
1247 }
1248
1249 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1250                                       void **table)
1251 {
1252         struct smu_table_context *smu_table = &smu->smu_table;
1253         struct gpu_metrics_v2_0 *gpu_metrics =
1254                 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
1255         SmuMetrics_t metrics;
1256         int ret = 0;
1257
1258         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1259         if (ret)
1260                 return ret;
1261
1262         smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics);
1263
1264         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1265         gpu_metrics->temperature_soc = metrics.SocTemperature;
1266         memcpy(&gpu_metrics->temperature_core[0],
1267                 &metrics.CoreTemperature[0],
1268                 sizeof(uint16_t) * 8);
1269         gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1270         gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1271
1272         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1273         gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1274
1275         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1276         gpu_metrics->average_cpu_power = metrics.Power[0];
1277         gpu_metrics->average_soc_power = metrics.Power[1];
1278         memcpy(&gpu_metrics->average_core_power[0],
1279                 &metrics.CorePower[0],
1280                 sizeof(uint16_t) * 8);
1281
1282         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1283         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1284         gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1285         gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1286
1287         gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1288         gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1289         gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1290         gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1291         gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1292         gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1293         memcpy(&gpu_metrics->current_coreclk[0],
1294                 &metrics.CoreFrequency[0],
1295                 sizeof(uint16_t) * 8);
1296         gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1297         gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1298
1299         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1300
1301         gpu_metrics->fan_pwm = metrics.FanPwm;
1302
1303         *table = (void *)gpu_metrics;
1304
1305         return sizeof(struct gpu_metrics_v2_0);
1306 }
1307
1308 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1309 {
1310
1311         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GpuChangeState, state, NULL);
1312 }
1313
1314 static const struct pptable_funcs renoir_ppt_funcs = {
1315         .set_power_state = NULL,
1316         .print_clk_levels = renoir_print_clk_levels,
1317         .get_current_power_state = renoir_get_current_power_state,
1318         .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1319         .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1320         .force_clk_levels = renoir_force_clk_levels,
1321         .set_power_profile_mode = renoir_set_power_profile_mode,
1322         .set_performance_level = renoir_set_performance_level,
1323         .get_dpm_clock_table = renoir_get_dpm_clock_table,
1324         .set_watermarks_table = renoir_set_watermarks_table,
1325         .get_power_profile_mode = renoir_get_power_profile_mode,
1326         .read_sensor = renoir_read_sensor,
1327         .check_fw_status = smu_v12_0_check_fw_status,
1328         .check_fw_version = smu_v12_0_check_fw_version,
1329         .powergate_sdma = smu_v12_0_powergate_sdma,
1330         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1331         .send_smc_msg = smu_cmn_send_smc_msg,
1332         .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1333         .gfx_off_control = smu_v12_0_gfx_off_control,
1334         .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1335         .init_smc_tables = renoir_init_smc_tables,
1336         .fini_smc_tables = smu_v12_0_fini_smc_tables,
1337         .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1338         .get_enabled_mask = smu_cmn_get_enabled_mask,
1339         .feature_is_enabled = smu_cmn_feature_is_enabled,
1340         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1341         .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1342         .mode2_reset = smu_v12_0_mode2_reset,
1343         .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1344         .set_driver_table_location = smu_v12_0_set_driver_table_location,
1345         .is_dpm_running = renoir_is_dpm_running,
1346         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1347         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1348         .get_gpu_metrics = renoir_get_gpu_metrics,
1349         .gfx_state_change_set = renoir_gfx_state_change_set,
1350         .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1351         .od_edit_dpm_table = renoir_od_edit_dpm_table,
1352 };
1353
1354 void renoir_set_ppt_funcs(struct smu_context *smu)
1355 {
1356         smu->ppt_funcs = &renoir_ppt_funcs;
1357         smu->message_map = renoir_message_map;
1358         smu->clock_map = renoir_clk_map;
1359         smu->table_map = renoir_table_map;
1360         smu->workload_map = renoir_workload_map;
1361         smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1362         smu->is_apu = true;
1363 }