2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
27 #include "amdgpu_smu.h"
28 #include "smu_v12_0_ppsmc.h"
29 #include "smu12_driver_if.h"
30 #include "smu_v12_0.h"
31 #include "renoir_ppt.h"
35 * DO NOT use these for err/warn/info/debug messages.
36 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37 * They are more MGPU friendly.
44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
107 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
108 CLK_MAP(SCLK, CLOCK_GFXCLK),
109 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
110 CLK_MAP(UCLK, CLOCK_FCLK),
111 CLK_MAP(MCLK, CLOCK_FCLK),
112 CLK_MAP(VCLK, CLOCK_VCLK),
113 CLK_MAP(DCLK, CLOCK_DCLK),
116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
117 TAB_MAP_VALID(WATERMARKS),
118 TAB_MAP_INVALID(CUSTOM_DPM),
119 TAB_MAP_VALID(DPMCLOCKS),
120 TAB_MAP_VALID(SMU_METRICS),
123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
131 static const uint8_t renoir_throttler_map[] = {
132 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
133 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
134 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
135 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
136 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
137 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
138 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
139 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
140 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
141 [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT),
142 [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
143 [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
144 [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
147 static int renoir_init_smc_tables(struct smu_context *smu)
149 struct smu_table_context *smu_table = &smu->smu_table;
150 struct smu_table *tables = smu_table->tables;
152 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
153 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
154 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
155 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
156 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
157 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
159 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
160 if (!smu_table->clocks_table)
163 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
164 if (!smu_table->metrics_table)
166 smu_table->metrics_time = 0;
168 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
169 if (!smu_table->watermarks_table)
172 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
173 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
174 if (!smu_table->gpu_metrics_table)
180 kfree(smu_table->watermarks_table);
182 kfree(smu_table->metrics_table);
184 kfree(smu_table->clocks_table);
190 * This interface just for getting uclk ultimate freq and should't introduce
191 * other likewise function result in overmuch callback.
193 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
194 uint32_t dpm_level, uint32_t *freq)
196 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
198 if (!clk_table || clk_type >= SMU_CLK_COUNT)
203 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
205 *freq = clk_table->SocClocks[dpm_level].Freq;
209 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
211 *freq = clk_table->FClocks[dpm_level].Freq;
214 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
216 *freq = clk_table->DcfClocks[dpm_level].Freq;
219 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
221 *freq = clk_table->FClocks[dpm_level].Freq;
224 if (dpm_level >= NUM_VCN_DPM_LEVELS)
226 *freq = clk_table->VClocks[dpm_level].Freq;
229 if (dpm_level >= NUM_VCN_DPM_LEVELS)
231 *freq = clk_table->DClocks[dpm_level].Freq;
241 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
242 enum amd_dpm_forced_level level,
248 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
251 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
253 /* mclk levels are in reverse order */
254 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
255 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
257 /* The sclk as gfxclk and has three level about max/min/current */
261 /* mclk levels are in reverse order */
265 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
271 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
272 enum smu_clk_type clk_type,
277 uint32_t mclk_mask, soc_mask;
278 uint32_t clock_limit;
280 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
284 clock_limit = smu->smu_table.boot_values.uclk;
288 clock_limit = smu->smu_table.boot_values.gfxclk;
291 clock_limit = smu->smu_table.boot_values.socclk;
298 /* clock in Mhz unit */
300 *min = clock_limit / 100;
302 *max = clock_limit / 100;
308 ret = renoir_get_profiling_clk_mask(smu,
309 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
319 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
321 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
328 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
333 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
347 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
349 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
356 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
361 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
374 static int renoir_od_edit_dpm_table(struct smu_context *smu,
375 enum PP_OD_DPM_TABLE_COMMAND type,
376 long input[], uint32_t size)
379 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
381 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
382 dev_warn(smu->adev->dev,
383 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
388 case PP_OD_EDIT_SCLK_VDDC_TABLE:
390 dev_err(smu->adev->dev, "Input parameter number not correct\n");
395 if (input[1] < smu->gfx_default_hard_min_freq) {
396 dev_warn(smu->adev->dev,
397 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
398 input[1], smu->gfx_default_hard_min_freq);
401 smu->gfx_actual_hard_min_freq = input[1];
402 } else if (input[0] == 1) {
403 if (input[1] > smu->gfx_default_soft_max_freq) {
404 dev_warn(smu->adev->dev,
405 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
406 input[1], smu->gfx_default_soft_max_freq);
409 smu->gfx_actual_soft_max_freq = input[1];
414 case PP_OD_RESTORE_DEFAULT_TABLE:
416 dev_err(smu->adev->dev, "Input parameter number not correct\n");
419 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
420 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
422 case PP_OD_COMMIT_DPM_TABLE:
424 dev_err(smu->adev->dev, "Input parameter number not correct\n");
427 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
428 dev_err(smu->adev->dev,
429 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
430 smu->gfx_actual_hard_min_freq,
431 smu->gfx_actual_soft_max_freq);
435 ret = smu_cmn_send_smc_msg_with_param(smu,
436 SMU_MSG_SetHardMinGfxClk,
437 smu->gfx_actual_hard_min_freq,
440 dev_err(smu->adev->dev, "Set hard min sclk failed!");
444 ret = smu_cmn_send_smc_msg_with_param(smu,
445 SMU_MSG_SetSoftMaxGfxClk,
446 smu->gfx_actual_soft_max_freq,
449 dev_err(smu->adev->dev, "Set soft max sclk failed!");
461 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
463 uint32_t min = 0, max = 0;
466 ret = smu_cmn_send_smc_msg_with_param(smu,
467 SMU_MSG_GetMinGfxclkFrequency,
471 ret = smu_cmn_send_smc_msg_with_param(smu,
472 SMU_MSG_GetMaxGfxclkFrequency,
477 smu->gfx_default_hard_min_freq = min;
478 smu->gfx_default_soft_max_freq = max;
479 smu->gfx_actual_hard_min_freq = 0;
480 smu->gfx_actual_soft_max_freq = 0;
485 static int renoir_print_clk_levels(struct smu_context *smu,
486 enum smu_clk_type clk_type, char *buf)
488 int i, size = 0, ret = 0;
489 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
490 SmuMetrics_t metrics;
491 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
492 bool cur_value_match_level = false;
494 memset(&metrics, 0, sizeof(metrics));
496 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
502 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
503 ret = smu_cmn_send_smc_msg_with_param(smu,
504 SMU_MSG_GetMinGfxclkFrequency,
508 ret = smu_cmn_send_smc_msg_with_param(smu,
509 SMU_MSG_GetMaxGfxclkFrequency,
513 size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
517 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
518 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
519 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
520 size += sysfs_emit_at(buf, size, "OD_SCLK\n");
521 size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
522 size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
527 /* retirve table returned paramters unit is MHz */
528 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
529 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
531 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
532 if (cur_value == max)
534 else if (cur_value == min)
539 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
541 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
542 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
544 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
549 count = NUM_SOCCLK_DPM_LEVELS;
550 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
553 count = NUM_MEMCLK_DPM_LEVELS;
554 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
557 count = NUM_DCFCLK_DPM_LEVELS;
558 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
561 count = NUM_FCLK_DPM_LEVELS;
562 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
565 count = NUM_VCN_DPM_LEVELS;
566 cur_value = metrics.ClockFrequency[CLOCK_VCLK];
569 count = NUM_VCN_DPM_LEVELS;
570 cur_value = metrics.ClockFrequency[CLOCK_DCLK];
585 for (i = 0; i < count; i++) {
586 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
591 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
592 cur_value == value ? "*" : "");
593 if (cur_value == value)
594 cur_value_match_level = true;
597 if (!cur_value_match_level)
598 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
608 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
610 enum amd_pm_state_type pm_type;
611 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
613 if (!smu_dpm_ctx->dpm_context ||
614 !smu_dpm_ctx->dpm_current_power_state)
617 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
618 case SMU_STATE_UI_LABEL_BATTERY:
619 pm_type = POWER_STATE_TYPE_BATTERY;
621 case SMU_STATE_UI_LABEL_BALLANCED:
622 pm_type = POWER_STATE_TYPE_BALANCED;
624 case SMU_STATE_UI_LABEL_PERFORMANCE:
625 pm_type = POWER_STATE_TYPE_PERFORMANCE;
628 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
629 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
631 pm_type = POWER_STATE_TYPE_DEFAULT;
638 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
643 /* vcn dpm on is a prerequisite for vcn power gate messages */
644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
645 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
650 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
651 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
660 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
665 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
666 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
671 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
672 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
681 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
684 uint32_t min_freq, max_freq, force_freq;
685 enum smu_clk_type clk_type;
687 enum smu_clk_type clks[] = {
693 for (i = 0; i < ARRAY_SIZE(clks); i++) {
695 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
699 force_freq = highest ? max_freq : min_freq;
700 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
708 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
711 uint32_t min_freq, max_freq;
712 enum smu_clk_type clk_type;
714 struct clk_feature_map {
715 enum smu_clk_type clk_type;
717 } clk_feature_map[] = {
718 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
719 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
720 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
723 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
724 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
727 clk_type = clk_feature_map[i].clk_type;
729 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
733 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
742 * This interface get dpm clock table for dc
744 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
746 DpmClocks_t *table = smu->smu_table.clocks_table;
749 if (!clock_table || !table)
752 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
753 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
754 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
757 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
758 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
759 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
762 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
763 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
764 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
767 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
768 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
769 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
772 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
773 clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
774 clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
777 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
778 clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
779 clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
785 static int renoir_force_clk_levels(struct smu_context *smu,
786 enum smu_clk_type clk_type, uint32_t mask)
790 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
792 soft_min_level = mask ? (ffs(mask) - 1) : 0;
793 soft_max_level = mask ? (fls(mask) - 1) : 0;
798 if (soft_min_level > 2 || soft_max_level > 2) {
799 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
803 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
806 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
807 soft_max_level == 0 ? min_freq :
808 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
812 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
813 soft_min_level == 2 ? max_freq :
814 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
820 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
823 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
826 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
829 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
835 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
838 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
841 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
844 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
855 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
857 int workload_type, ret;
858 uint32_t profile_mode = input[size];
860 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
861 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
865 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
866 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
869 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
870 workload_type = smu_cmn_to_asic_specific_index(smu,
871 CMN2ASIC_MAPPING_WORKLOAD,
873 if (workload_type < 0) {
875 * TODO: If some case need switch to powersave/default power mode
876 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
878 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
882 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
886 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
890 smu->power_profile_mode = profile_mode;
895 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
898 uint32_t sclk_freq = 0, uclk_freq = 0;
900 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
904 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
908 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
912 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
919 static int renoir_set_performance_level(struct smu_context *smu,
920 enum amd_dpm_forced_level level)
923 uint32_t sclk_mask, mclk_mask, soc_mask;
926 case AMD_DPM_FORCED_LEVEL_HIGH:
927 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
928 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
930 ret = renoir_force_dpm_limit_value(smu, true);
932 case AMD_DPM_FORCED_LEVEL_LOW:
933 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
934 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
936 ret = renoir_force_dpm_limit_value(smu, false);
938 case AMD_DPM_FORCED_LEVEL_AUTO:
939 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
940 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
942 ret = renoir_unforce_dpm_levels(smu);
944 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
945 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
946 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
948 ret = smu_cmn_send_smc_msg_with_param(smu,
949 SMU_MSG_SetHardMinGfxClk,
950 RENOIR_UMD_PSTATE_GFXCLK,
954 ret = smu_cmn_send_smc_msg_with_param(smu,
955 SMU_MSG_SetHardMinFclkByFreq,
956 RENOIR_UMD_PSTATE_FCLK,
960 ret = smu_cmn_send_smc_msg_with_param(smu,
961 SMU_MSG_SetHardMinSocclkByFreq,
962 RENOIR_UMD_PSTATE_SOCCLK,
966 ret = smu_cmn_send_smc_msg_with_param(smu,
967 SMU_MSG_SetHardMinVcn,
968 RENOIR_UMD_PSTATE_VCNCLK,
973 ret = smu_cmn_send_smc_msg_with_param(smu,
974 SMU_MSG_SetSoftMaxGfxClk,
975 RENOIR_UMD_PSTATE_GFXCLK,
979 ret = smu_cmn_send_smc_msg_with_param(smu,
980 SMU_MSG_SetSoftMaxFclkByFreq,
981 RENOIR_UMD_PSTATE_FCLK,
985 ret = smu_cmn_send_smc_msg_with_param(smu,
986 SMU_MSG_SetSoftMaxSocclkByFreq,
987 RENOIR_UMD_PSTATE_SOCCLK,
991 ret = smu_cmn_send_smc_msg_with_param(smu,
992 SMU_MSG_SetSoftMaxVcn,
993 RENOIR_UMD_PSTATE_VCNCLK,
998 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
999 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1000 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1001 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1003 ret = renoir_get_profiling_clk_mask(smu, level,
1009 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1010 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1011 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1013 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1014 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1015 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1017 ret = renoir_set_peak_clock_by_device(smu);
1019 case AMD_DPM_FORCED_LEVEL_MANUAL:
1020 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1027 /* save watermark settings into pplib smu structure,
1028 * also pass data to smu controller
1030 static int renoir_set_watermarks_table(
1031 struct smu_context *smu,
1032 struct pp_smu_wm_range_sets *clock_ranges)
1034 Watermarks_t *table = smu->smu_table.watermarks_table;
1039 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1040 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1043 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1044 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1045 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1046 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1047 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1048 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1049 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1050 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1051 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1052 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1054 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1055 clock_ranges->reader_wm_sets[i].wm_inst;
1056 table->WatermarkRow[WM_DCFCLK][i].WmType =
1057 clock_ranges->reader_wm_sets[i].wm_type;
1060 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1061 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1062 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1063 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1064 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1065 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1066 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1067 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1068 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1070 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1071 clock_ranges->writer_wm_sets[i].wm_inst;
1072 table->WatermarkRow[WM_SOCCLK][i].WmType =
1073 clock_ranges->writer_wm_sets[i].wm_type;
1076 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1079 /* pass data to smu controller */
1080 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1081 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1082 ret = smu_cmn_write_watermarks_table(smu);
1084 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1087 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1093 static int renoir_get_power_profile_mode(struct smu_context *smu,
1096 static const char *profile_name[] = {
1104 uint32_t i, size = 0;
1105 int16_t workload_type = 0;
1110 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1112 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1113 * Not all profile modes are supported on arcturus.
1115 workload_type = smu_cmn_to_asic_specific_index(smu,
1116 CMN2ASIC_MAPPING_WORKLOAD,
1118 if (workload_type < 0)
1121 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1122 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1128 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1129 MetricsMember_t member,
1132 struct smu_table_context *smu_table = &smu->smu_table;
1134 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
1137 mutex_lock(&smu->metrics_lock);
1139 ret = smu_cmn_get_metrics_table_locked(smu,
1143 mutex_unlock(&smu->metrics_lock);
1148 case METRICS_AVERAGE_GFXCLK:
1149 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
1151 case METRICS_AVERAGE_SOCCLK:
1152 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
1154 case METRICS_AVERAGE_UCLK:
1155 *value = metrics->ClockFrequency[CLOCK_FCLK];
1157 case METRICS_AVERAGE_GFXACTIVITY:
1158 *value = metrics->AverageGfxActivity / 100;
1160 case METRICS_AVERAGE_VCNACTIVITY:
1161 *value = metrics->AverageUvdActivity / 100;
1163 case METRICS_AVERAGE_SOCKETPOWER:
1164 *value = (metrics->CurrentSocketPower << 8) / 1000;
1166 case METRICS_TEMPERATURE_EDGE:
1167 *value = (metrics->GfxTemperature / 100) *
1168 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1170 case METRICS_TEMPERATURE_HOTSPOT:
1171 *value = (metrics->SocTemperature / 100) *
1172 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1174 case METRICS_THROTTLER_STATUS:
1175 *value = metrics->ThrottlerStatus;
1177 case METRICS_VOLTAGE_VDDGFX:
1178 *value = metrics->Voltage[0];
1180 case METRICS_VOLTAGE_VDDSOC:
1181 *value = metrics->Voltage[1];
1183 case METRICS_SS_APU_SHARE:
1184 /* return the percentage of APU power with respect to APU's power limit.
1185 * percentage is reported, this isn't boost value. Smartshift power
1186 * boost/shift is only when the percentage is more than 100.
1188 if (metrics->StapmOriginalLimit > 0)
1189 *value = (metrics->ApuPower * 100) / metrics->StapmOriginalLimit;
1193 case METRICS_SS_DGPU_SHARE:
1194 /* return the percentage of dGPU power with respect to dGPU's power limit.
1195 * percentage is reported, this isn't boost value. Smartshift power
1196 * boost/shift is only when the percentage is more than 100.
1198 if ((metrics->dGpuPower > 0) &&
1199 (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit))
1200 *value = (metrics->dGpuPower * 100) /
1201 (metrics->StapmCurrentLimit - metrics->StapmOriginalLimit);
1210 mutex_unlock(&smu->metrics_lock);
1215 static int renoir_read_sensor(struct smu_context *smu,
1216 enum amd_pp_sensors sensor,
1217 void *data, uint32_t *size)
1224 mutex_lock(&smu->sensor_lock);
1226 case AMDGPU_PP_SENSOR_GPU_LOAD:
1227 ret = renoir_get_smu_metrics_data(smu,
1228 METRICS_AVERAGE_GFXACTIVITY,
1232 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1233 ret = renoir_get_smu_metrics_data(smu,
1234 METRICS_TEMPERATURE_EDGE,
1238 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1239 ret = renoir_get_smu_metrics_data(smu,
1240 METRICS_TEMPERATURE_HOTSPOT,
1244 case AMDGPU_PP_SENSOR_GFX_MCLK:
1245 ret = renoir_get_smu_metrics_data(smu,
1246 METRICS_AVERAGE_UCLK,
1248 *(uint32_t *)data *= 100;
1251 case AMDGPU_PP_SENSOR_GFX_SCLK:
1252 ret = renoir_get_smu_metrics_data(smu,
1253 METRICS_AVERAGE_GFXCLK,
1255 *(uint32_t *)data *= 100;
1258 case AMDGPU_PP_SENSOR_VDDGFX:
1259 ret = renoir_get_smu_metrics_data(smu,
1260 METRICS_VOLTAGE_VDDGFX,
1264 case AMDGPU_PP_SENSOR_VDDNB:
1265 ret = renoir_get_smu_metrics_data(smu,
1266 METRICS_VOLTAGE_VDDSOC,
1270 case AMDGPU_PP_SENSOR_GPU_POWER:
1271 ret = renoir_get_smu_metrics_data(smu,
1272 METRICS_AVERAGE_SOCKETPOWER,
1276 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1277 ret = renoir_get_smu_metrics_data(smu,
1278 METRICS_SS_APU_SHARE,
1282 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1283 ret = renoir_get_smu_metrics_data(smu,
1284 METRICS_SS_DGPU_SHARE,
1292 mutex_unlock(&smu->sensor_lock);
1297 static bool renoir_is_dpm_running(struct smu_context *smu)
1299 struct amdgpu_device *adev = smu->adev;
1302 * Until now, the pmfw hasn't exported the interface of SMU
1303 * feature mask to APU SKU so just force on all the feature
1304 * at early initial stage.
1306 if (adev->in_suspend)
1313 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1316 struct smu_table_context *smu_table = &smu->smu_table;
1317 struct gpu_metrics_v2_2 *gpu_metrics =
1318 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1319 SmuMetrics_t metrics;
1322 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1326 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1328 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1329 gpu_metrics->temperature_soc = metrics.SocTemperature;
1330 memcpy(&gpu_metrics->temperature_core[0],
1331 &metrics.CoreTemperature[0],
1332 sizeof(uint16_t) * 8);
1333 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1334 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1336 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1337 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1339 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1340 gpu_metrics->average_cpu_power = metrics.Power[0];
1341 gpu_metrics->average_soc_power = metrics.Power[1];
1342 memcpy(&gpu_metrics->average_core_power[0],
1343 &metrics.CorePower[0],
1344 sizeof(uint16_t) * 8);
1346 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1347 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1348 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1349 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1351 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1352 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1353 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1354 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1355 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1356 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1357 memcpy(&gpu_metrics->current_coreclk[0],
1358 &metrics.CoreFrequency[0],
1359 sizeof(uint16_t) * 8);
1360 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1361 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1363 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1364 gpu_metrics->indep_throttle_status =
1365 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1366 renoir_throttler_map);
1368 gpu_metrics->fan_pwm = metrics.FanPwm;
1370 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1372 *table = (void *)gpu_metrics;
1374 return sizeof(struct gpu_metrics_v2_2);
1377 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1383 static const struct pptable_funcs renoir_ppt_funcs = {
1384 .set_power_state = NULL,
1385 .print_clk_levels = renoir_print_clk_levels,
1386 .get_current_power_state = renoir_get_current_power_state,
1387 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1388 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1389 .force_clk_levels = renoir_force_clk_levels,
1390 .set_power_profile_mode = renoir_set_power_profile_mode,
1391 .set_performance_level = renoir_set_performance_level,
1392 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1393 .set_watermarks_table = renoir_set_watermarks_table,
1394 .get_power_profile_mode = renoir_get_power_profile_mode,
1395 .read_sensor = renoir_read_sensor,
1396 .check_fw_status = smu_v12_0_check_fw_status,
1397 .check_fw_version = smu_v12_0_check_fw_version,
1398 .powergate_sdma = smu_v12_0_powergate_sdma,
1399 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1400 .send_smc_msg = smu_cmn_send_smc_msg,
1401 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1402 .gfx_off_control = smu_v12_0_gfx_off_control,
1403 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1404 .init_smc_tables = renoir_init_smc_tables,
1405 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1406 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1407 .get_enabled_mask = smu_cmn_get_enabled_mask,
1408 .feature_is_enabled = smu_cmn_feature_is_enabled,
1409 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1410 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1411 .mode2_reset = smu_v12_0_mode2_reset,
1412 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1413 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1414 .is_dpm_running = renoir_is_dpm_running,
1415 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1416 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1417 .get_gpu_metrics = renoir_get_gpu_metrics,
1418 .gfx_state_change_set = renoir_gfx_state_change_set,
1419 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1420 .od_edit_dpm_table = renoir_od_edit_dpm_table,
1421 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values,
1424 void renoir_set_ppt_funcs(struct smu_context *smu)
1426 smu->ppt_funcs = &renoir_ppt_funcs;
1427 smu->message_map = renoir_message_map;
1428 smu->clock_map = renoir_clk_map;
1429 smu->table_map = renoir_table_map;
1430 smu->workload_map = renoir_workload_map;
1431 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;