drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_11_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v11_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65
  66 #define SMU11_VOLTAGE_SCALE 4
  67
  68 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  69
  70 #define LINK_WIDTH_MAX                          6
  71 #define LINK_SPEED_MAX                          3
  72
  73 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  76 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  79
  80 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  81 static int link_speed[] = {25, 50, 80, 160};
  82
  83 int smu_v11_0_init_microcode(struct smu_context *smu)
  84 {
  85         struct amdgpu_device *adev = smu->adev;
  86         const char *chip_name;
  87         char fw_name[30];
  88         int err = 0;
  89         const struct smc_firmware_header_v1_0 *hdr;
  90         const struct common_firmware_header *header;
  91         struct amdgpu_firmware_info *ucode = NULL;
  92
  93         switch (adev->asic_type) {
  94         case CHIP_ARCTURUS:
  95                 chip_name = "arcturus";
  96                 break;
  97         case CHIP_NAVI10:
  98                 chip_name = "navi10";
  99                 break;
 100         case CHIP_NAVI14:
 101                 chip_name = "navi14";
 102                 break;
 103         case CHIP_NAVI12:
 104                 chip_name = "navi12";
 105                 break;
 106         case CHIP_SIENNA_CICHLID:
 107                 chip_name = "sienna_cichlid";
 108                 break;
 109         case CHIP_NAVY_FLOUNDER:
 110                 chip_name = "navy_flounder";
 111                 break;
 112         default:
 113                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 114                 return -EINVAL;
 115         }
 116
 117         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 118
 119         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 120         if (err)
 121                 goto out;
 122         err = amdgpu_ucode_validate(adev->pm.fw);
 123         if (err)
 124                 goto out;
 125
 126         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 127         amdgpu_ucode_print_smc_hdr(&hdr->header);
 128         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 129
 130         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 131                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 132                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 133                 ucode->fw = adev->pm.fw;
 134                 header = (const struct common_firmware_header *)ucode->fw->data;
 135                 adev->firmware.fw_size +=
 136                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 137         }
 138
 139 out:
 140         if (err) {
 141                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 142                           fw_name);
 143                 release_firmware(adev->pm.fw);
 144                 adev->pm.fw = NULL;
 145         }
 146         return err;
 147 }
 148
 149 void smu_v11_0_fini_microcode(struct smu_context *smu)
 150 {
 151         struct amdgpu_device *adev = smu->adev;
 152
 153         release_firmware(adev->pm.fw);
 154         adev->pm.fw = NULL;
 155         adev->pm.fw_version = 0;
 156 }
 157
 158 int smu_v11_0_load_microcode(struct smu_context *smu)
 159 {
 160         struct amdgpu_device *adev = smu->adev;
 161         const uint32_t *src;
 162         const struct smc_firmware_header_v1_0 *hdr;
 163         uint32_t addr_start = MP1_SRAM;
 164         uint32_t i;
 165         uint32_t smc_fw_size;
 166         uint32_t mp1_fw_flags;
 167
 168         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 169         src = (const uint32_t *)(adev->pm.fw->data +
 170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 171         smc_fw_size = hdr->header.ucode_size_bytes;
 172
 173         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 174                 WREG32_PCIE(addr_start, src[i]);
 175                 addr_start += 4;
 176         }
 177
 178         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 179                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 180         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 181                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 182
 183         for (i = 0; i < adev->usec_timeout; i++) {
 184                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 185                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 186                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 187                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 188                         break;
 189                 udelay(1);
 190         }
 191
 192         if (i == adev->usec_timeout)
 193                 return -ETIME;
 194
 195         return 0;
 196 }
 197
 198 int smu_v11_0_check_fw_status(struct smu_context *smu)
 199 {
 200         struct amdgpu_device *adev = smu->adev;
 201         uint32_t mp1_fw_flags;
 202
 203         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 204                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 205
 206         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 207             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 208                 return 0;
 209
 210         return -EIO;
 211 }
 212
 213 int smu_v11_0_check_fw_version(struct smu_context *smu)
 214 {
 215         uint32_t if_version = 0xff, smu_version = 0xff;
 216         uint16_t smu_major;
 217         uint8_t smu_minor, smu_debug;
 218         int ret = 0;
 219
 220         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 221         if (ret)
 222                 return ret;
 223
 224         smu_major = (smu_version >> 16) & 0xffff;
 225         smu_minor = (smu_version >> 8) & 0xff;
 226         smu_debug = (smu_version >> 0) & 0xff;
 227
 228         switch (smu->adev->asic_type) {
 229         case CHIP_ARCTURUS:
 230                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 231                 break;
 232         case CHIP_NAVI10:
 233                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 234                 break;
 235         case CHIP_NAVI12:
 236                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 237                 break;
 238         case CHIP_NAVI14:
 239                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 240                 break;
 241         case CHIP_SIENNA_CICHLID:
 242                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 243                 break;
 244         case CHIP_NAVY_FLOUNDER:
 245                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 246                 break;
 247         default:
 248                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 249                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 250                 break;
 251         }
 252
 253         /*
 254          * 1. if_version mismatch is not critical as our fw is designed
 255          * to be backward compatible.
 256          * 2. New fw usually brings some optimizations. But that's visible
 257          * only on the paired driver.
 258          * Considering above, we just leave user a warning message instead
 259          * of halt driver loading.
 260          */
 261         if (if_version != smu->smc_driver_if_version) {
 262                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 263                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 264                         smu->smc_driver_if_version, if_version,
 265                         smu_version, smu_major, smu_minor, smu_debug);
 266                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 267         }
 268
 269         return ret;
 270 }
 271
 272 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 273 {
 274         struct amdgpu_device *adev = smu->adev;
 275         uint32_t ppt_offset_bytes;
 276         const struct smc_firmware_header_v2_0 *v2;
 277
 278         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 279
 280         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 281         *size = le32_to_cpu(v2->ppt_size_bytes);
 282         *table = (uint8_t *)v2 + ppt_offset_bytes;
 283
 284         return 0;
 285 }
 286
 287 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 288                                       uint32_t *size, uint32_t pptable_id)
 289 {
 290         struct amdgpu_device *adev = smu->adev;
 291         const struct smc_firmware_header_v2_1 *v2_1;
 292         struct smc_soft_pptable_entry *entries;
 293         uint32_t pptable_count = 0;
 294         int i = 0;
 295
 296         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 297         entries = (struct smc_soft_pptable_entry *)
 298                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 299         pptable_count = le32_to_cpu(v2_1->pptable_count);
 300         for (i = 0; i < pptable_count; i++) {
 301                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 302                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 303                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 304                         break;
 305                 }
 306         }
 307
 308         if (i == pptable_count)
 309                 return -EINVAL;
 310
 311         return 0;
 312 }
 313
 314 int smu_v11_0_setup_pptable(struct smu_context *smu)
 315 {
 316         struct amdgpu_device *adev = smu->adev;
 317         const struct smc_firmware_header_v1_0 *hdr;
 318         int ret, index;
 319         uint32_t size = 0;
 320         uint16_t atom_table_size;
 321         uint8_t frev, crev;
 322         void *table;
 323         uint16_t version_major, version_minor;
 324
 325         if (!amdgpu_sriov_vf(adev)) {
 326                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 327                 version_major = le16_to_cpu(hdr->header.header_version_major);
 328                 version_minor = le16_to_cpu(hdr->header.header_version_minor);
 329                 if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
 330                         adev->asic_type == CHIP_NAVY_FLOUNDER) {
 331                         dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 332                         switch (version_minor) {
 333                         case 0:
 334                                 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 335                                 break;
 336                         case 1:
 337                                 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 338                                                                 smu->smu_table.boot_values.pp_table_id);
 339                                 break;
 340                         default:
 341                                 ret = -EINVAL;
 342                                 break;
 343                         }
 344                         if (ret)
 345                                 return ret;
 346                         goto out;
 347                 }
 348         }
 349
 350         dev_info(adev->dev, "use vbios provided pptable\n");
 351         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 352                                                 powerplayinfo);
 353
 354         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 355                                                 (uint8_t **)&table);
 356         if (ret)
 357                 return ret;
 358         size = atom_table_size;
 359
 360 out:
 361         if (!smu->smu_table.power_play_table)
 362                 smu->smu_table.power_play_table = table;
 363         if (!smu->smu_table.power_play_table_size)
 364                 smu->smu_table.power_play_table_size = size;
 365
 366         return 0;
 367 }
 368
 369 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 370 {
 371         struct smu_table_context *smu_table = &smu->smu_table;
 372         struct smu_table *tables = smu_table->tables;
 373         int ret = 0;
 374
 375         smu_table->driver_pptable =
 376                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 377         if (!smu_table->driver_pptable) {
 378                 ret = -ENOMEM;
 379                 goto err0_out;
 380         }
 381
 382         smu_table->max_sustainable_clocks =
 383                 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 384         if (!smu_table->max_sustainable_clocks) {
 385                 ret = -ENOMEM;
 386                 goto err1_out;
 387         }
 388
 389         /* Arcturus does not support OVERDRIVE */
 390         if (tables[SMU_TABLE_OVERDRIVE].size) {
 391                 smu_table->overdrive_table =
 392                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 393                 if (!smu_table->overdrive_table) {
 394                         ret = -ENOMEM;
 395                         goto err2_out;
 396                 }
 397
 398                 smu_table->boot_overdrive_table =
 399                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 400                 if (!smu_table->boot_overdrive_table) {
 401                         ret = -ENOMEM;
 402                         goto err3_out;
 403                 }
 404         }
 405
 406         return 0;
 407
 408 err3_out:
 409         kfree(smu_table->overdrive_table);
 410 err2_out:
 411         kfree(smu_table->max_sustainable_clocks);
 412 err1_out:
 413         kfree(smu_table->driver_pptable);
 414 err0_out:
 415         return ret;
 416 }
 417
 418 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 419 {
 420         struct smu_table_context *smu_table = &smu->smu_table;
 421         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 422
 423         kfree(smu_table->gpu_metrics_table);
 424         kfree(smu_table->boot_overdrive_table);
 425         kfree(smu_table->overdrive_table);
 426         kfree(smu_table->max_sustainable_clocks);
 427         kfree(smu_table->driver_pptable);
 428         smu_table->gpu_metrics_table = NULL;
 429         smu_table->boot_overdrive_table = NULL;
 430         smu_table->overdrive_table = NULL;
 431         smu_table->max_sustainable_clocks = NULL;
 432         smu_table->driver_pptable = NULL;
 433         kfree(smu_table->hardcode_pptable);
 434         smu_table->hardcode_pptable = NULL;
 435
 436         kfree(smu_table->metrics_table);
 437         kfree(smu_table->watermarks_table);
 438         smu_table->metrics_table = NULL;
 439         smu_table->watermarks_table = NULL;
 440         smu_table->metrics_time = 0;
 441
 442         kfree(smu_dpm->dpm_context);
 443         kfree(smu_dpm->golden_dpm_context);
 444         kfree(smu_dpm->dpm_current_power_state);
 445         kfree(smu_dpm->dpm_request_power_state);
 446         smu_dpm->dpm_context = NULL;
 447         smu_dpm->golden_dpm_context = NULL;
 448         smu_dpm->dpm_context_size = 0;
 449         smu_dpm->dpm_current_power_state = NULL;
 450         smu_dpm->dpm_request_power_state = NULL;
 451
 452         return 0;
 453 }
 454
 455 int smu_v11_0_init_power(struct smu_context *smu)
 456 {
 457         struct smu_power_context *smu_power = &smu->smu_power;
 458
 459         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 460                                            GFP_KERNEL);
 461         if (!smu_power->power_context)
 462                 return -ENOMEM;
 463         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 464
 465         return 0;
 466 }
 467
 468 int smu_v11_0_fini_power(struct smu_context *smu)
 469 {
 470         struct smu_power_context *smu_power = &smu->smu_power;
 471
 472         kfree(smu_power->power_context);
 473         smu_power->power_context = NULL;
 474         smu_power->power_context_size = 0;
 475
 476         return 0;
 477 }
 478
 479 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 480                                             uint8_t clk_id,
 481                                             uint8_t syspll_id,
 482                                             uint32_t *clk_freq)
 483 {
 484         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 485         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 486         int ret, index;
 487
 488         input.clk_id = clk_id;
 489         input.syspll_id = syspll_id;
 490         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 491         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 492                                             getsmuclockinfo);
 493
 494         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 495                                         (uint32_t *)&input);
 496         if (ret)
 497                 return -EINVAL;
 498
 499         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 500         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 501
 502         return 0;
 503 }
 504
 505 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 506 {
 507         int ret, index;
 508         uint16_t size;
 509         uint8_t frev, crev;
 510         struct atom_common_table_header *header;
 511         struct atom_firmware_info_v3_3 *v_3_3;
 512         struct atom_firmware_info_v3_1 *v_3_1;
 513
 514         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 515                                             firmwareinfo);
 516
 517         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 518                                       (uint8_t **)&header);
 519         if (ret)
 520                 return ret;
 521
 522         if (header->format_revision != 3) {
 523                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 524                 return -EINVAL;
 525         }
 526
 527         switch (header->content_revision) {
 528         case 0:
 529         case 1:
 530         case 2:
 531                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 532                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 533                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 534                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 535                 smu->smu_table.boot_values.socclk = 0;
 536                 smu->smu_table.boot_values.dcefclk = 0;
 537                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 538                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 539                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 540                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 541                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 542                 smu->smu_table.boot_values.pp_table_id = 0;
 543                 break;
 544         case 3:
 545         default:
 546                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 547                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 548                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 549                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 550                 smu->smu_table.boot_values.socclk = 0;
 551                 smu->smu_table.boot_values.dcefclk = 0;
 552                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 553                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 554                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 555                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 556                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 557                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 558         }
 559
 560         smu->smu_table.boot_values.format_revision = header->format_revision;
 561         smu->smu_table.boot_values.content_revision = header->content_revision;
 562
 563         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 564                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 565                                          (uint8_t)0,
 566                                          &smu->smu_table.boot_values.socclk);
 567
 568         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 569                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 570                                          (uint8_t)0,
 571                                          &smu->smu_table.boot_values.dcefclk);
 572
 573         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 574                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 575                                          (uint8_t)0,
 576                                          &smu->smu_table.boot_values.eclk);
 577
 578         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 579                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 580                                          (uint8_t)0,
 581                                          &smu->smu_table.boot_values.vclk);
 582
 583         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 584                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 585                                          (uint8_t)0,
 586                                          &smu->smu_table.boot_values.dclk);
 587
 588         if ((smu->smu_table.boot_values.format_revision == 3) &&
 589             (smu->smu_table.boot_values.content_revision >= 2))
 590                 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 591                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 592                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 593                                                  &smu->smu_table.boot_values.fclk);
 594
 595         return 0;
 596 }
 597
 598 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 599 {
 600         struct smu_table_context *smu_table = &smu->smu_table;
 601         struct smu_table *memory_pool = &smu_table->memory_pool;
 602         int ret = 0;
 603         uint64_t address;
 604         uint32_t address_low, address_high;
 605
 606         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 607                 return ret;
 608
 609         address = (uintptr_t)memory_pool->cpu_addr;
 610         address_high = (uint32_t)upper_32_bits(address);
 611         address_low  = (uint32_t)lower_32_bits(address);
 612
 613         ret = smu_cmn_send_smc_msg_with_param(smu,
 614                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 615                                           address_high,
 616                                           NULL);
 617         if (ret)
 618                 return ret;
 619         ret = smu_cmn_send_smc_msg_with_param(smu,
 620                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 621                                           address_low,
 622                                           NULL);
 623         if (ret)
 624                 return ret;
 625
 626         address = memory_pool->mc_address;
 627         address_high = (uint32_t)upper_32_bits(address);
 628         address_low  = (uint32_t)lower_32_bits(address);
 629
 630         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 631                                           address_high, NULL);
 632         if (ret)
 633                 return ret;
 634         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 635                                           address_low, NULL);
 636         if (ret)
 637                 return ret;
 638         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 639                                           (uint32_t)memory_pool->size, NULL);
 640         if (ret)
 641                 return ret;
 642
 643         return ret;
 644 }
 645
 646 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 647 {
 648         int ret;
 649
 650         ret = smu_cmn_send_smc_msg_with_param(smu,
 651                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 652         if (ret)
 653                 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 654
 655         return ret;
 656 }
 657
 658 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 659 {
 660         struct smu_table *driver_table = &smu->smu_table.driver_table;
 661         int ret = 0;
 662
 663         if (driver_table->mc_address) {
 664                 ret = smu_cmn_send_smc_msg_with_param(smu,
 665                                 SMU_MSG_SetDriverDramAddrHigh,
 666                                 upper_32_bits(driver_table->mc_address),
 667                                 NULL);
 668                 if (!ret)
 669                         ret = smu_cmn_send_smc_msg_with_param(smu,
 670                                 SMU_MSG_SetDriverDramAddrLow,
 671                                 lower_32_bits(driver_table->mc_address),
 672                                 NULL);
 673         }
 674
 675         return ret;
 676 }
 677
 678 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 679 {
 680         int ret = 0;
 681         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 682
 683         if (tool_table->mc_address) {
 684                 ret = smu_cmn_send_smc_msg_with_param(smu,
 685                                 SMU_MSG_SetToolsDramAddrHigh,
 686                                 upper_32_bits(tool_table->mc_address),
 687                                 NULL);
 688                 if (!ret)
 689                         ret = smu_cmn_send_smc_msg_with_param(smu,
 690                                 SMU_MSG_SetToolsDramAddrLow,
 691                                 lower_32_bits(tool_table->mc_address),
 692                                 NULL);
 693         }
 694
 695         return ret;
 696 }
 697
 698 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 699 {
 700         struct amdgpu_device *adev = smu->adev;
 701
 702         /* Navy_Flounder do not support to change display num currently */
 703         if (adev->asic_type == CHIP_NAVY_FLOUNDER)
 704                 return 0;
 705
 706         return smu_cmn_send_smc_msg_with_param(smu,
 707                                                SMU_MSG_NumOfDisplays,
 708                                                count,
 709                                                NULL);
 710 }
 711
 712
 713 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 714 {
 715         struct smu_feature *feature = &smu->smu_feature;
 716         int ret = 0;
 717         uint32_t feature_mask[2];
 718
 719         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 720                 goto failed;
 721
 722         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 723
 724         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 725                                           feature_mask[1], NULL);
 726         if (ret)
 727                 goto failed;
 728
 729         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 730                                           feature_mask[0], NULL);
 731         if (ret)
 732                 goto failed;
 733
 734 failed:
 735         return ret;
 736 }
 737
 738 int smu_v11_0_system_features_control(struct smu_context *smu,
 739                                              bool en)
 740 {
 741         struct smu_feature *feature = &smu->smu_feature;
 742         uint32_t feature_mask[2];
 743         int ret = 0;
 744
 745         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 746                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 747         if (ret)
 748                 return ret;
 749
 750         bitmap_zero(feature->enabled, feature->feature_num);
 751         bitmap_zero(feature->supported, feature->feature_num);
 752
 753         if (en) {
 754                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 755                 if (ret)
 756                         return ret;
 757
 758                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 759                             feature->feature_num);
 760                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 761                             feature->feature_num);
 762         }
 763
 764         return ret;
 765 }
 766
 767 int smu_v11_0_notify_display_change(struct smu_context *smu)
 768 {
 769         int ret = 0;
 770
 771         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 772             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 773                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 774
 775         return ret;
 776 }
 777
 778 static int
 779 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 780                                     enum smu_clk_type clock_select)
 781 {
 782         int ret = 0;
 783         int clk_id;
 784
 785         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 786             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 787                 return 0;
 788
 789         clk_id = smu_cmn_to_asic_specific_index(smu,
 790                                                 CMN2ASIC_MAPPING_CLK,
 791                                                 clock_select);
 792         if (clk_id < 0)
 793                 return -EINVAL;
 794
 795         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 796                                           clk_id << 16, clock);
 797         if (ret) {
 798                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 799                 return ret;
 800         }
 801
 802         if (*clock != 0)
 803                 return 0;
 804
 805         /* if DC limit is zero, return AC limit */
 806         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 807                                           clk_id << 16, clock);
 808         if (ret) {
 809                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 810                 return ret;
 811         }
 812
 813         return 0;
 814 }
 815
 816 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 817 {
 818         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 819                         smu->smu_table.max_sustainable_clocks;
 820         int ret = 0;
 821
 822         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 823         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 824         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 825         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 826         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 827         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 828
 829         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 830                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 831                                                           &(max_sustainable_clocks->uclock),
 832                                                           SMU_UCLK);
 833                 if (ret) {
 834                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 835                                __func__);
 836                         return ret;
 837                 }
 838         }
 839
 840         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 841                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 842                                                           &(max_sustainable_clocks->soc_clock),
 843                                                           SMU_SOCCLK);
 844                 if (ret) {
 845                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 846                                __func__);
 847                         return ret;
 848                 }
 849         }
 850
 851         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 852                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 853                                                           &(max_sustainable_clocks->dcef_clock),
 854                                                           SMU_DCEFCLK);
 855                 if (ret) {
 856                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 857                                __func__);
 858                         return ret;
 859                 }
 860
 861                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 862                                                           &(max_sustainable_clocks->display_clock),
 863                                                           SMU_DISPCLK);
 864                 if (ret) {
 865                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 866                                __func__);
 867                         return ret;
 868                 }
 869                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 870                                                           &(max_sustainable_clocks->phy_clock),
 871                                                           SMU_PHYCLK);
 872                 if (ret) {
 873                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 874                                __func__);
 875                         return ret;
 876                 }
 877                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 878                                                           &(max_sustainable_clocks->pixel_clock),
 879                                                           SMU_PIXCLK);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 882                                __func__);
 883                         return ret;
 884                 }
 885         }
 886
 887         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 888                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 889
 890         return 0;
 891 }
 892
 893 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 894                                       uint32_t *power_limit)
 895 {
 896         int power_src;
 897         int ret = 0;
 898
 899         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 900                 return -EINVAL;
 901
 902         power_src = smu_cmn_to_asic_specific_index(smu,
 903                                         CMN2ASIC_MAPPING_PWR,
 904                                         smu->adev->pm.ac_power ?
 905                                         SMU_POWER_SOURCE_AC :
 906                                         SMU_POWER_SOURCE_DC);
 907         if (power_src < 0)
 908                 return -EINVAL;
 909
 910         ret = smu_cmn_send_smc_msg_with_param(smu,
 911                                           SMU_MSG_GetPptLimit,
 912                                           power_src << 16,
 913                                           power_limit);
 914         if (ret)
 915                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 916
 917         return ret;
 918 }
 919
 920 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 921 {
 922         int ret = 0;
 923
 924         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 925                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 926                 return -EOPNOTSUPP;
 927         }
 928
 929         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 930         if (ret) {
 931                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 932                 return ret;
 933         }
 934
 935         smu->current_power_limit = n;
 936
 937         return 0;
 938 }
 939
 940 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
 941 {
 942         return smu_cmn_send_smc_msg(smu,
 943                                 SMU_MSG_ReenableAcDcInterrupt,
 944                                 NULL);
 945 }
 946
 947 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
 948 {
 949         int ret = 0;
 950
 951         if (smu->dc_controlled_by_gpio &&
 952             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
 953                 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
 954
 955         return ret;
 956 }
 957
 958 void smu_v11_0_interrupt_work(struct smu_context *smu)
 959 {
 960         if (smu_v11_0_ack_ac_dc_interrupt(smu))
 961                 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
 962 }
 963
 964 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
 965 {
 966         int ret = 0;
 967
 968         if (smu->smu_table.thermal_controller_type) {
 969                 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 970                 if (ret)
 971                         return ret;
 972         }
 973
 974         /*
 975          * After init there might have been missed interrupts triggered
 976          * before driver registers for interrupt (Ex. AC/DC).
 977          */
 978         return smu_v11_0_process_pending_interrupt(smu);
 979 }
 980
 981 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
 982 {
 983         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 984 }
 985
 986 static uint16_t convert_to_vddc(uint8_t vid)
 987 {
 988         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
 989 }
 990
 991 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 992 {
 993         struct amdgpu_device *adev = smu->adev;
 994         uint32_t vdd = 0, val_vid = 0;
 995
 996         if (!value)
 997                 return -EINVAL;
 998         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
 999                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1000                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1001
1002         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1003
1004         *value = vdd;
1005
1006         return 0;
1007
1008 }
1009
1010 int
1011 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1012                                         struct pp_display_clock_request
1013                                         *clock_req)
1014 {
1015         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1016         int ret = 0;
1017         enum smu_clk_type clk_select = 0;
1018         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1019
1020         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1021                 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1022                 switch (clk_type) {
1023                 case amd_pp_dcef_clock:
1024                         clk_select = SMU_DCEFCLK;
1025                         break;
1026                 case amd_pp_disp_clock:
1027                         clk_select = SMU_DISPCLK;
1028                         break;
1029                 case amd_pp_pixel_clock:
1030                         clk_select = SMU_PIXCLK;
1031                         break;
1032                 case amd_pp_phy_clock:
1033                         clk_select = SMU_PHYCLK;
1034                         break;
1035                 case amd_pp_mem_clock:
1036                         clk_select = SMU_UCLK;
1037                         break;
1038                 default:
1039                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1040                         ret = -EINVAL;
1041                         break;
1042                 }
1043
1044                 if (ret)
1045                         goto failed;
1046
1047                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1048                         return 0;
1049
1050                 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1051
1052                 if(clk_select == SMU_UCLK)
1053                         smu->hard_min_uclk_req_from_dal = clk_freq;
1054         }
1055
1056 failed:
1057         return ret;
1058 }
1059
1060 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1061 {
1062         int ret = 0;
1063         struct amdgpu_device *adev = smu->adev;
1064
1065         switch (adev->asic_type) {
1066         case CHIP_NAVI10:
1067         case CHIP_NAVI14:
1068         case CHIP_NAVI12:
1069         case CHIP_SIENNA_CICHLID:
1070         case CHIP_NAVY_FLOUNDER:
1071                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1072                         return 0;
1073                 if (enable)
1074                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1075                 else
1076                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1077                 break;
1078         default:
1079                 break;
1080         }
1081
1082         return ret;
1083 }
1084
1085 uint32_t
1086 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1087 {
1088         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1089                 return AMD_FAN_CTRL_MANUAL;
1090         else
1091                 return AMD_FAN_CTRL_AUTO;
1092 }
1093
1094 static int
1095 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1096 {
1097         int ret = 0;
1098
1099         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1100                 return 0;
1101
1102         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1103         if (ret)
1104                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1105                        __func__, (auto_fan_control ? "Start" : "Stop"));
1106
1107         return ret;
1108 }
1109
1110 static int
1111 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1112 {
1113         struct amdgpu_device *adev = smu->adev;
1114
1115         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1116                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1117                                    CG_FDO_CTRL2, TMIN, 0));
1118         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1119                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1120                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1121
1122         return 0;
1123 }
1124
1125 int
1126 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1127                                uint32_t mode)
1128 {
1129         int ret = 0;
1130
1131         switch (mode) {
1132         case AMD_FAN_CTRL_NONE:
1133                 ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
1134                 break;
1135         case AMD_FAN_CTRL_MANUAL:
1136                 ret = smu_v11_0_auto_fan_control(smu, 0);
1137                 break;
1138         case AMD_FAN_CTRL_AUTO:
1139                 ret = smu_v11_0_auto_fan_control(smu, 1);
1140                 break;
1141         default:
1142                 break;
1143         }
1144
1145         if (ret) {
1146                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1147                 return -EINVAL;
1148         }
1149
1150         return ret;
1151 }
1152
1153 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1154                                        uint32_t speed)
1155 {
1156         struct amdgpu_device *adev = smu->adev;
1157         int ret;
1158         uint32_t tach_period, crystal_clock_freq;
1159
1160         if (!speed)
1161                 return -EINVAL;
1162
1163         ret = smu_v11_0_auto_fan_control(smu, 0);
1164         if (ret)
1165                 return ret;
1166
1167         /*
1168          * crystal_clock_freq div by 4 is required since the fan control
1169          * module refers to 25MHz
1170          */
1171
1172         crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
1173         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1174         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1175                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1176                                    CG_TACH_CTRL, TARGET_PERIOD,
1177                                    tach_period));
1178
1179         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1180
1181         return ret;
1182 }
1183
1184 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1185                                 uint32_t *speed)
1186 {
1187         struct amdgpu_device *adev = smu->adev;
1188         uint32_t tach_period, crystal_clock_freq;
1189         uint64_t tmp64;
1190
1191         tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1192                                     CG_TACH_CTRL, TARGET_PERIOD);
1193         if (!tach_period)
1194                 return -EINVAL;
1195
1196         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1197
1198         tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1199         do_div(tmp64, (tach_period * 8));
1200         *speed = (uint32_t)tmp64;
1201
1202         return 0;
1203 }
1204
1205 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1206                                      uint32_t pstate)
1207 {
1208         return smu_cmn_send_smc_msg_with_param(smu,
1209                                                SMU_MSG_SetXgmiMode,
1210                                                pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1211                                           NULL);
1212 }
1213
1214 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1215                                    struct amdgpu_irq_src *source,
1216                                    unsigned tyep,
1217                                    enum amdgpu_interrupt_state state)
1218 {
1219         struct smu_context *smu = &adev->smu;
1220         uint32_t low, high;
1221         uint32_t val = 0;
1222
1223         switch (state) {
1224         case AMDGPU_IRQ_STATE_DISABLE:
1225                 /* For THM irqs */
1226                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1227                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1228                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1229                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1230
1231                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1232
1233                 /* For MP1 SW irqs */
1234                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1235                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1236                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1237
1238                 break;
1239         case AMDGPU_IRQ_STATE_ENABLE:
1240                 /* For THM irqs */
1241                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1242                                 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1243                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1244                                 smu->thermal_range.software_shutdown_temp);
1245
1246                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1247                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1248                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1249                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1250                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1251                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1252                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1253                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1254                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1255
1256                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1257                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1258                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1259                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1260
1261                 /* For MP1 SW irqs */
1262                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1263                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1264                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1265                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1266
1267                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1268                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1269                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1270
1271                 break;
1272         default:
1273                 break;
1274         }
1275
1276         return 0;
1277 }
1278
1279 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1280 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1281
1282 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1283
1284 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1285                                  struct amdgpu_irq_src *source,
1286                                  struct amdgpu_iv_entry *entry)
1287 {
1288         struct smu_context *smu = &adev->smu;
1289         uint32_t client_id = entry->client_id;
1290         uint32_t src_id = entry->src_id;
1291         /*
1292          * ctxid is used to distinguish different
1293          * events for SMCToHost interrupt.
1294          */
1295         uint32_t ctxid = entry->src_data[0];
1296         uint32_t data;
1297
1298         if (client_id == SOC15_IH_CLIENTID_THM) {
1299                 switch (src_id) {
1300                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1301                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1302                         /*
1303                          * SW CTF just occurred.
1304                          * Try to do a graceful shutdown to prevent further damage.
1305                          */
1306                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1307                         orderly_poweroff(true);
1308                 break;
1309                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1310                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1311                 break;
1312                 default:
1313                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1314                                 src_id);
1315                 break;
1316                 }
1317         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1318                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1319                 /*
1320                  * HW CTF just occurred. Shutdown to prevent further damage.
1321                  */
1322                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1323                 orderly_poweroff(true);
1324         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1325                 if (src_id == 0xfe) {
1326                         /* ACK SMUToHost interrupt */
1327                         data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1328                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1329                         WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1330
1331                         switch (ctxid) {
1332                         case 0x3:
1333                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1334                                 schedule_work(&smu->interrupt_work);
1335                                 break;
1336                         case 0x4:
1337                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1338                                 schedule_work(&smu->interrupt_work);
1339                                 break;
1340                         case 0x7:
1341                                 /*
1342                                  * Increment the throttle interrupt counter
1343                                  */
1344                                 atomic64_inc(&smu->throttle_int_counter);
1345
1346                                 if (!atomic_read(&adev->throttling_logging_enabled))
1347                                         return 0;
1348
1349                                 if (__ratelimit(&adev->throttling_logging_rs))
1350                                         schedule_work(&smu->throttling_logging_work);
1351
1352                                 break;
1353                         }
1354                 }
1355         }
1356
1357         return 0;
1358 }
1359
1360 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1361 {
1362         .set = smu_v11_0_set_irq_state,
1363         .process = smu_v11_0_irq_process,
1364 };
1365
1366 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1367 {
1368         struct amdgpu_device *adev = smu->adev;
1369         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1370         int ret = 0;
1371
1372         irq_src->num_types = 1;
1373         irq_src->funcs = &smu_v11_0_irq_funcs;
1374
1375         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1376                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1377                                 irq_src);
1378         if (ret)
1379                 return ret;
1380
1381         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1382                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1383                                 irq_src);
1384         if (ret)
1385                 return ret;
1386
1387         /* Register CTF(GPIO_19) interrupt */
1388         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1389                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1390                                 irq_src);
1391         if (ret)
1392                 return ret;
1393
1394         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1395                                 0xfe,
1396                                 irq_src);
1397         if (ret)
1398                 return ret;
1399
1400         return ret;
1401 }
1402
1403 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1404                 struct pp_smu_nv_clock_table *max_clocks)
1405 {
1406         struct smu_table_context *table_context = &smu->smu_table;
1407         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1408
1409         if (!max_clocks || !table_context->max_sustainable_clocks)
1410                 return -EINVAL;
1411
1412         sustainable_clocks = table_context->max_sustainable_clocks;
1413
1414         max_clocks->dcfClockInKhz =
1415                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1416         max_clocks->displayClockInKhz =
1417                         (unsigned int) sustainable_clocks->display_clock * 1000;
1418         max_clocks->phyClockInKhz =
1419                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1420         max_clocks->pixelClockInKhz =
1421                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1422         max_clocks->uClockInKhz =
1423                         (unsigned int) sustainable_clocks->uclock * 1000;
1424         max_clocks->socClockInKhz =
1425                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1426         max_clocks->dscClockInKhz = 0;
1427         max_clocks->dppClockInKhz = 0;
1428         max_clocks->fabricClockInKhz = 0;
1429
1430         return 0;
1431 }
1432
1433 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1434 {
1435         return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1436 }
1437
1438 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1439 {
1440         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1441 }
1442
1443 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1444 {
1445         struct smu_baco_context *smu_baco = &smu->smu_baco;
1446
1447         if (!smu_baco->platform_support)
1448                 return false;
1449
1450         /* Arcturus does not support this bit mask */
1451         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1452            !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1453                 return false;
1454
1455         return true;
1456 }
1457
1458 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1459 {
1460         struct smu_baco_context *smu_baco = &smu->smu_baco;
1461         enum smu_baco_state baco_state;
1462
1463         mutex_lock(&smu_baco->mutex);
1464         baco_state = smu_baco->state;
1465         mutex_unlock(&smu_baco->mutex);
1466
1467         return baco_state;
1468 }
1469
1470 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1471 {
1472         struct smu_baco_context *smu_baco = &smu->smu_baco;
1473         struct amdgpu_device *adev = smu->adev;
1474         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1475         uint32_t data;
1476         int ret = 0;
1477
1478         if (smu_v11_0_baco_get_state(smu) == state)
1479                 return 0;
1480
1481         mutex_lock(&smu_baco->mutex);
1482
1483         if (state == SMU_BACO_STATE_ENTER) {
1484                 if (!ras || !ras->supported) {
1485                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1486                         data |= 0x80000000;
1487                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1488
1489                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1490                 } else {
1491                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1492                 }
1493         } else {
1494                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1495                 if (ret)
1496                         goto out;
1497
1498                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1499                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1500                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1501         }
1502         if (ret)
1503                 goto out;
1504
1505         smu_baco->state = state;
1506 out:
1507         mutex_unlock(&smu_baco->mutex);
1508         return ret;
1509 }
1510
1511 int smu_v11_0_baco_enter(struct smu_context *smu)
1512 {
1513         struct amdgpu_device *adev = smu->adev;
1514         int ret = 0;
1515
1516         /* Arcturus does not need this audio workaround */
1517         if (adev->asic_type != CHIP_ARCTURUS) {
1518                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1519                 if (ret)
1520                         return ret;
1521         }
1522
1523         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1524         if (ret)
1525                 return ret;
1526
1527         msleep(10);
1528
1529         return ret;
1530 }
1531
1532 int smu_v11_0_baco_exit(struct smu_context *smu)
1533 {
1534         return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1535 }
1536
1537 int smu_v11_0_mode1_reset(struct smu_context *smu)
1538 {
1539         int ret = 0;
1540
1541         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1542         if (!ret)
1543                 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1544
1545         return ret;
1546 }
1547
1548 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1549                                                  uint32_t *min, uint32_t *max)
1550 {
1551         int ret = 0, clk_id = 0;
1552         uint32_t param = 0;
1553         uint32_t clock_limit;
1554
1555         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1556                 switch (clk_type) {
1557                 case SMU_MCLK:
1558                 case SMU_UCLK:
1559                         clock_limit = smu->smu_table.boot_values.uclk;
1560                         break;
1561                 case SMU_GFXCLK:
1562                 case SMU_SCLK:
1563                         clock_limit = smu->smu_table.boot_values.gfxclk;
1564                         break;
1565                 case SMU_SOCCLK:
1566                         clock_limit = smu->smu_table.boot_values.socclk;
1567                         break;
1568                 default:
1569                         clock_limit = 0;
1570                         break;
1571                 }
1572
1573                 /* clock in Mhz unit */
1574                 if (min)
1575                         *min = clock_limit / 100;
1576                 if (max)
1577                         *max = clock_limit / 100;
1578
1579                 return 0;
1580         }
1581
1582         clk_id = smu_cmn_to_asic_specific_index(smu,
1583                                                 CMN2ASIC_MAPPING_CLK,
1584                                                 clk_type);
1585         if (clk_id < 0) {
1586                 ret = -EINVAL;
1587                 goto failed;
1588         }
1589         param = (clk_id & 0xffff) << 16;
1590
1591         if (max) {
1592                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1593                 if (ret)
1594                         goto failed;
1595         }
1596
1597         if (min) {
1598                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1599                 if (ret)
1600                         goto failed;
1601         }
1602
1603 failed:
1604         return ret;
1605 }
1606
1607 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1608                                           enum smu_clk_type clk_type,
1609                                           uint32_t min,
1610                                           uint32_t max)
1611 {
1612         struct amdgpu_device *adev = smu->adev;
1613         int ret = 0, clk_id = 0;
1614         uint32_t param;
1615
1616         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1617                 return 0;
1618
1619         clk_id = smu_cmn_to_asic_specific_index(smu,
1620                                                 CMN2ASIC_MAPPING_CLK,
1621                                                 clk_type);
1622         if (clk_id < 0)
1623                 return clk_id;
1624
1625         if (clk_type == SMU_GFXCLK)
1626                 amdgpu_gfx_off_ctrl(adev, false);
1627
1628         if (max > 0) {
1629                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1630                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1631                                                   param, NULL);
1632                 if (ret)
1633                         goto out;
1634         }
1635
1636         if (min > 0) {
1637                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1638                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1639                                                   param, NULL);
1640                 if (ret)
1641                         goto out;
1642         }
1643
1644 out:
1645         if (clk_type == SMU_GFXCLK)
1646                 amdgpu_gfx_off_ctrl(adev, true);
1647
1648         return ret;
1649 }
1650
1651 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1652                                           enum smu_clk_type clk_type,
1653                                           uint32_t min,
1654                                           uint32_t max)
1655 {
1656         int ret = 0, clk_id = 0;
1657         uint32_t param;
1658
1659         if (min <= 0 && max <= 0)
1660                 return -EINVAL;
1661
1662         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1663                 return 0;
1664
1665         clk_id = smu_cmn_to_asic_specific_index(smu,
1666                                                 CMN2ASIC_MAPPING_CLK,
1667                                                 clk_type);
1668         if (clk_id < 0)
1669                 return clk_id;
1670
1671         if (max > 0) {
1672                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1673                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1674                                                   param, NULL);
1675                 if (ret)
1676                         return ret;
1677         }
1678
1679         if (min > 0) {
1680                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1681                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1682                                                   param, NULL);
1683                 if (ret)
1684                         return ret;
1685         }
1686
1687         return ret;
1688 }
1689
1690 int smu_v11_0_set_performance_level(struct smu_context *smu,
1691                                     enum amd_dpm_forced_level level)
1692 {
1693         struct smu_11_0_dpm_context *dpm_context =
1694                                 smu->smu_dpm.dpm_context;
1695         struct smu_11_0_dpm_table *gfx_table =
1696                                 &dpm_context->dpm_tables.gfx_table;
1697         struct smu_11_0_dpm_table *mem_table =
1698                                 &dpm_context->dpm_tables.uclk_table;
1699         struct smu_11_0_dpm_table *soc_table =
1700                                 &dpm_context->dpm_tables.soc_table;
1701         struct smu_umd_pstate_table *pstate_table =
1702                                 &smu->pstate_table;
1703         struct amdgpu_device *adev = smu->adev;
1704         uint32_t sclk_min = 0, sclk_max = 0;
1705         uint32_t mclk_min = 0, mclk_max = 0;
1706         uint32_t socclk_min = 0, socclk_max = 0;
1707         int ret = 0;
1708
1709         switch (level) {
1710         case AMD_DPM_FORCED_LEVEL_HIGH:
1711                 sclk_min = sclk_max = gfx_table->max;
1712                 mclk_min = mclk_max = mem_table->max;
1713                 socclk_min = socclk_max = soc_table->max;
1714                 break;
1715         case AMD_DPM_FORCED_LEVEL_LOW:
1716                 sclk_min = sclk_max = gfx_table->min;
1717                 mclk_min = mclk_max = mem_table->min;
1718                 socclk_min = socclk_max = soc_table->min;
1719                 break;
1720         case AMD_DPM_FORCED_LEVEL_AUTO:
1721                 sclk_min = gfx_table->min;
1722                 sclk_max = gfx_table->max;
1723                 mclk_min = mem_table->min;
1724                 mclk_max = mem_table->max;
1725                 socclk_min = soc_table->min;
1726                 socclk_max = soc_table->max;
1727                 break;
1728         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1729                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1730                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1731                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1732                 break;
1733         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1734                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1735                 break;
1736         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1737                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1738                 break;
1739         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1740                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1741                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1742                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1743                 break;
1744         case AMD_DPM_FORCED_LEVEL_MANUAL:
1745         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1746                 return 0;
1747         default:
1748                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1749                 return -EINVAL;
1750         }
1751
1752         /*
1753          * Separate MCLK and SOCCLK soft min/max settings are not allowed
1754          * on Arcturus.
1755          */
1756         if (adev->asic_type == CHIP_ARCTURUS) {
1757                 mclk_min = mclk_max = 0;
1758                 socclk_min = socclk_max = 0;
1759         }
1760
1761         if (sclk_min && sclk_max) {
1762                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1763                                                             SMU_GFXCLK,
1764                                                             sclk_min,
1765                                                             sclk_max);
1766                 if (ret)
1767                         return ret;
1768         }
1769
1770         if (mclk_min && mclk_max) {
1771                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1772                                                             SMU_MCLK,
1773                                                             mclk_min,
1774                                                             mclk_max);
1775                 if (ret)
1776                         return ret;
1777         }
1778
1779         if (socclk_min && socclk_max) {
1780                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1781                                                             SMU_SOCCLK,
1782                                                             socclk_min,
1783                                                             socclk_max);
1784                 if (ret)
1785                         return ret;
1786         }
1787
1788         return ret;
1789 }
1790
1791 int smu_v11_0_set_power_source(struct smu_context *smu,
1792                                enum smu_power_src_type power_src)
1793 {
1794         int pwr_source;
1795
1796         pwr_source = smu_cmn_to_asic_specific_index(smu,
1797                                                     CMN2ASIC_MAPPING_PWR,
1798                                                     (uint32_t)power_src);
1799         if (pwr_source < 0)
1800                 return -EINVAL;
1801
1802         return smu_cmn_send_smc_msg_with_param(smu,
1803                                         SMU_MSG_NotifyPowerSource,
1804                                         pwr_source,
1805                                         NULL);
1806 }
1807
1808 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1809                                     enum smu_clk_type clk_type,
1810                                     uint16_t level,
1811                                     uint32_t *value)
1812 {
1813         int ret = 0, clk_id = 0;
1814         uint32_t param;
1815
1816         if (!value)
1817                 return -EINVAL;
1818
1819         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1820                 return 0;
1821
1822         clk_id = smu_cmn_to_asic_specific_index(smu,
1823                                                 CMN2ASIC_MAPPING_CLK,
1824                                                 clk_type);
1825         if (clk_id < 0)
1826                 return clk_id;
1827
1828         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1829
1830         ret = smu_cmn_send_smc_msg_with_param(smu,
1831                                           SMU_MSG_GetDpmFreqByIndex,
1832                                           param,
1833                                           value);
1834         if (ret)
1835                 return ret;
1836
1837         /*
1838          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1839          * now, we un-support it
1840          */
1841         *value = *value & 0x7fffffff;
1842
1843         return ret;
1844 }
1845
1846 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1847                                   enum smu_clk_type clk_type,
1848                                   uint32_t *value)
1849 {
1850         return smu_v11_0_get_dpm_freq_by_index(smu,
1851                                                clk_type,
1852                                                0xff,
1853                                                value);
1854 }
1855
1856 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1857                                    enum smu_clk_type clk_type,
1858                                    struct smu_11_0_dpm_table *single_dpm_table)
1859 {
1860         int ret = 0;
1861         uint32_t clk;
1862         int i;
1863
1864         ret = smu_v11_0_get_dpm_level_count(smu,
1865                                             clk_type,
1866                                             &single_dpm_table->count);
1867         if (ret) {
1868                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1869                 return ret;
1870         }
1871
1872         for (i = 0; i < single_dpm_table->count; i++) {
1873                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1874                                                       clk_type,
1875                                                       i,
1876                                                       &clk);
1877                 if (ret) {
1878                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1879                         return ret;
1880                 }
1881
1882                 single_dpm_table->dpm_levels[i].value = clk;
1883                 single_dpm_table->dpm_levels[i].enabled = true;
1884
1885                 if (i == 0)
1886                         single_dpm_table->min = clk;
1887                 else if (i == single_dpm_table->count - 1)
1888                         single_dpm_table->max = clk;
1889         }
1890
1891         return 0;
1892 }
1893
1894 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1895                                   enum smu_clk_type clk_type,
1896                                   uint32_t *min_value,
1897                                   uint32_t *max_value)
1898 {
1899         uint32_t level_count = 0;
1900         int ret = 0;
1901
1902         if (!min_value && !max_value)
1903                 return -EINVAL;
1904
1905         if (min_value) {
1906                 /* by default, level 0 clock value as min value */
1907                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1908                                                       clk_type,
1909                                                       0,
1910                                                       min_value);
1911                 if (ret)
1912                         return ret;
1913         }
1914
1915         if (max_value) {
1916                 ret = smu_v11_0_get_dpm_level_count(smu,
1917                                                     clk_type,
1918                                                     &level_count);
1919                 if (ret)
1920                         return ret;
1921
1922                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1923                                                       clk_type,
1924                                                       level_count - 1,
1925                                                       max_value);
1926                 if (ret)
1927                         return ret;
1928         }
1929
1930         return ret;
1931 }
1932
1933 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1934 {
1935         struct amdgpu_device *adev = smu->adev;
1936
1937         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1938                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1939                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1940 }
1941
1942 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
1943 {
1944         uint32_t width_level;
1945
1946         width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
1947         if (width_level > LINK_WIDTH_MAX)
1948                 width_level = 0;
1949
1950         return link_width[width_level];
1951 }
1952
1953 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1954 {
1955         struct amdgpu_device *adev = smu->adev;
1956
1957         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1958                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1959                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1960 }
1961
1962 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
1963 {
1964         uint32_t speed_level;
1965
1966         speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
1967         if (speed_level > LINK_SPEED_MAX)
1968                 speed_level = 0;
1969
1970         return link_speed[speed_level];
1971 }
1972
1973 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
1974 {
1975         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
1976
1977         gpu_metrics->common_header.structure_size =
1978                                 sizeof(struct gpu_metrics_v1_0);
1979         gpu_metrics->common_header.format_revision = 1;
1980         gpu_metrics->common_header.content_revision = 0;
1981
1982         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1983 }
1984
1985 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
1986                               bool enablement)
1987 {
1988         int ret = 0;
1989
1990         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1991                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1992
1993         return ret;
1994 }
1995
1996 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
1997                                  bool enablement)
1998 {
1999         struct amdgpu_device *adev = smu->adev;
2000         int ret = 0;
2001
2002         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2003                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2004                 if (ret) {
2005                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2006                         return ret;
2007                 }
2008         }
2009
2010         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2011                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2012                 if (ret) {
2013                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2014                         return ret;
2015                 }
2016         }
2017
2018         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2019                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2020                 if (ret) {
2021                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2022                         return ret;
2023                 }
2024         }
2025
2026         return ret;
2027 }