drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_11_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v11_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
  66
  67 #define SMU11_VOLTAGE_SCALE 4
  68
  69 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  70
  71 #define LINK_WIDTH_MAX                          6
  72 #define LINK_SPEED_MAX                          3
  73
  74 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  76 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  77 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  79 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  80
  81 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  82 static int link_speed[] = {25, 50, 80, 160};
  83
  84 int smu_v11_0_init_microcode(struct smu_context *smu)
  85 {
  86         struct amdgpu_device *adev = smu->adev;
  87         const char *chip_name;
  88         char fw_name[SMU_FW_NAME_LEN];
  89         int err = 0;
  90         const struct smc_firmware_header_v1_0 *hdr;
  91         const struct common_firmware_header *header;
  92         struct amdgpu_firmware_info *ucode = NULL;
  93
  94         if (amdgpu_sriov_vf(adev) &&
  95                         ((adev->asic_type == CHIP_NAVI12) ||
  96                          (adev->asic_type == CHIP_SIENNA_CICHLID)))
  97                 return 0;
  98
  99         switch (adev->asic_type) {
 100         case CHIP_ARCTURUS:
 101                 chip_name = "arcturus";
 102                 break;
 103         case CHIP_NAVI10:
 104                 chip_name = "navi10";
 105                 break;
 106         case CHIP_NAVI14:
 107                 chip_name = "navi14";
 108                 break;
 109         case CHIP_NAVI12:
 110                 chip_name = "navi12";
 111                 break;
 112         case CHIP_SIENNA_CICHLID:
 113                 chip_name = "sienna_cichlid";
 114                 break;
 115         case CHIP_NAVY_FLOUNDER:
 116                 chip_name = "navy_flounder";
 117                 break;
 118         case CHIP_DIMGREY_CAVEFISH:
 119                 chip_name = "dimgrey_cavefish";
 120                 break;
 121         default:
 122                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 123                 return -EINVAL;
 124         }
 125
 126         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 127
 128         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 129         if (err)
 130                 goto out;
 131         err = amdgpu_ucode_validate(adev->pm.fw);
 132         if (err)
 133                 goto out;
 134
 135         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 136         amdgpu_ucode_print_smc_hdr(&hdr->header);
 137         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 138
 139         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 140                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 141                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 142                 ucode->fw = adev->pm.fw;
 143                 header = (const struct common_firmware_header *)ucode->fw->data;
 144                 adev->firmware.fw_size +=
 145                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 146         }
 147
 148 out:
 149         if (err) {
 150                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 151                           fw_name);
 152                 release_firmware(adev->pm.fw);
 153                 adev->pm.fw = NULL;
 154         }
 155         return err;
 156 }
 157
 158 void smu_v11_0_fini_microcode(struct smu_context *smu)
 159 {
 160         struct amdgpu_device *adev = smu->adev;
 161
 162         release_firmware(adev->pm.fw);
 163         adev->pm.fw = NULL;
 164         adev->pm.fw_version = 0;
 165 }
 166
 167 int smu_v11_0_load_microcode(struct smu_context *smu)
 168 {
 169         struct amdgpu_device *adev = smu->adev;
 170         const uint32_t *src;
 171         const struct smc_firmware_header_v1_0 *hdr;
 172         uint32_t addr_start = MP1_SRAM;
 173         uint32_t i;
 174         uint32_t smc_fw_size;
 175         uint32_t mp1_fw_flags;
 176
 177         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 178         src = (const uint32_t *)(adev->pm.fw->data +
 179                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 180         smc_fw_size = hdr->header.ucode_size_bytes;
 181
 182         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 183                 WREG32_PCIE(addr_start, src[i]);
 184                 addr_start += 4;
 185         }
 186
 187         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 188                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 189         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 190                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 191
 192         for (i = 0; i < adev->usec_timeout; i++) {
 193                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 194                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 195                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 196                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 197                         break;
 198                 udelay(1);
 199         }
 200
 201         if (i == adev->usec_timeout)
 202                 return -ETIME;
 203
 204         return 0;
 205 }
 206
 207 int smu_v11_0_check_fw_status(struct smu_context *smu)
 208 {
 209         struct amdgpu_device *adev = smu->adev;
 210         uint32_t mp1_fw_flags;
 211
 212         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 213                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 214
 215         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 216             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 217                 return 0;
 218
 219         return -EIO;
 220 }
 221
 222 int smu_v11_0_check_fw_version(struct smu_context *smu)
 223 {
 224         struct amdgpu_device *adev = smu->adev;
 225         uint32_t if_version = 0xff, smu_version = 0xff;
 226         uint16_t smu_major;
 227         uint8_t smu_minor, smu_debug;
 228         int ret = 0;
 229
 230         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 231         if (ret)
 232                 return ret;
 233
 234         smu_major = (smu_version >> 16) & 0xffff;
 235         smu_minor = (smu_version >> 8) & 0xff;
 236         smu_debug = (smu_version >> 0) & 0xff;
 237         if (smu->is_apu)
 238                 adev->pm.fw_version = smu_version;
 239
 240         switch (smu->adev->asic_type) {
 241         case CHIP_ARCTURUS:
 242                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 243                 break;
 244         case CHIP_NAVI10:
 245                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 246                 break;
 247         case CHIP_NAVI12:
 248                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 249                 break;
 250         case CHIP_NAVI14:
 251                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 252                 break;
 253         case CHIP_SIENNA_CICHLID:
 254                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 255                 break;
 256         case CHIP_NAVY_FLOUNDER:
 257                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 258                 break;
 259         case CHIP_VANGOGH:
 260                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
 261                 break;
 262         case CHIP_DIMGREY_CAVEFISH:
 263                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
 264                 break;
 265         default:
 266                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 267                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 268                 break;
 269         }
 270
 271         /*
 272          * 1. if_version mismatch is not critical as our fw is designed
 273          * to be backward compatible.
 274          * 2. New fw usually brings some optimizations. But that's visible
 275          * only on the paired driver.
 276          * Considering above, we just leave user a warning message instead
 277          * of halt driver loading.
 278          */
 279         if (if_version != smu->smc_driver_if_version) {
 280                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 281                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 282                         smu->smc_driver_if_version, if_version,
 283                         smu_version, smu_major, smu_minor, smu_debug);
 284                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 285         }
 286
 287         return ret;
 288 }
 289
 290 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 291 {
 292         struct amdgpu_device *adev = smu->adev;
 293         uint32_t ppt_offset_bytes;
 294         const struct smc_firmware_header_v2_0 *v2;
 295
 296         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 297
 298         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 299         *size = le32_to_cpu(v2->ppt_size_bytes);
 300         *table = (uint8_t *)v2 + ppt_offset_bytes;
 301
 302         return 0;
 303 }
 304
 305 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 306                                       uint32_t *size, uint32_t pptable_id)
 307 {
 308         struct amdgpu_device *adev = smu->adev;
 309         const struct smc_firmware_header_v2_1 *v2_1;
 310         struct smc_soft_pptable_entry *entries;
 311         uint32_t pptable_count = 0;
 312         int i = 0;
 313
 314         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 315         entries = (struct smc_soft_pptable_entry *)
 316                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 317         pptable_count = le32_to_cpu(v2_1->pptable_count);
 318         for (i = 0; i < pptable_count; i++) {
 319                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 320                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 321                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 322                         break;
 323                 }
 324         }
 325
 326         if (i == pptable_count)
 327                 return -EINVAL;
 328
 329         return 0;
 330 }
 331
 332 int smu_v11_0_setup_pptable(struct smu_context *smu)
 333 {
 334         struct amdgpu_device *adev = smu->adev;
 335         const struct smc_firmware_header_v1_0 *hdr;
 336         int ret, index;
 337         uint32_t size = 0;
 338         uint16_t atom_table_size;
 339         uint8_t frev, crev;
 340         void *table;
 341         uint16_t version_major, version_minor;
 342
 343         if (!amdgpu_sriov_vf(adev)) {
 344                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 345                 version_major = le16_to_cpu(hdr->header.header_version_major);
 346                 version_minor = le16_to_cpu(hdr->header.header_version_minor);
 347                 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 348                         dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 349                         switch (version_minor) {
 350                         case 0:
 351                                 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 352                                 break;
 353                         case 1:
 354                                 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 355                                                                 smu->smu_table.boot_values.pp_table_id);
 356                                 break;
 357                         default:
 358                                 ret = -EINVAL;
 359                                 break;
 360                         }
 361                         if (ret)
 362                                 return ret;
 363                         goto out;
 364                 }
 365         }
 366
 367         dev_info(adev->dev, "use vbios provided pptable\n");
 368         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 369                                                 powerplayinfo);
 370
 371         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 372                                                 (uint8_t **)&table);
 373         if (ret)
 374                 return ret;
 375         size = atom_table_size;
 376
 377 out:
 378         if (!smu->smu_table.power_play_table)
 379                 smu->smu_table.power_play_table = table;
 380         if (!smu->smu_table.power_play_table_size)
 381                 smu->smu_table.power_play_table_size = size;
 382
 383         return 0;
 384 }
 385
 386 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 387 {
 388         struct smu_table_context *smu_table = &smu->smu_table;
 389         struct smu_table *tables = smu_table->tables;
 390         int ret = 0;
 391
 392         smu_table->driver_pptable =
 393                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 394         if (!smu_table->driver_pptable) {
 395                 ret = -ENOMEM;
 396                 goto err0_out;
 397         }
 398
 399         smu_table->max_sustainable_clocks =
 400                 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 401         if (!smu_table->max_sustainable_clocks) {
 402                 ret = -ENOMEM;
 403                 goto err1_out;
 404         }
 405
 406         /* Arcturus does not support OVERDRIVE */
 407         if (tables[SMU_TABLE_OVERDRIVE].size) {
 408                 smu_table->overdrive_table =
 409                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 410                 if (!smu_table->overdrive_table) {
 411                         ret = -ENOMEM;
 412                         goto err2_out;
 413                 }
 414
 415                 smu_table->boot_overdrive_table =
 416                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 417                 if (!smu_table->boot_overdrive_table) {
 418                         ret = -ENOMEM;
 419                         goto err3_out;
 420                 }
 421         }
 422
 423         return 0;
 424
 425 err3_out:
 426         kfree(smu_table->overdrive_table);
 427 err2_out:
 428         kfree(smu_table->max_sustainable_clocks);
 429 err1_out:
 430         kfree(smu_table->driver_pptable);
 431 err0_out:
 432         return ret;
 433 }
 434
 435 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 436 {
 437         struct smu_table_context *smu_table = &smu->smu_table;
 438         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 439
 440         kfree(smu_table->gpu_metrics_table);
 441         kfree(smu_table->boot_overdrive_table);
 442         kfree(smu_table->overdrive_table);
 443         kfree(smu_table->max_sustainable_clocks);
 444         kfree(smu_table->driver_pptable);
 445         kfree(smu_table->clocks_table);
 446         smu_table->gpu_metrics_table = NULL;
 447         smu_table->boot_overdrive_table = NULL;
 448         smu_table->overdrive_table = NULL;
 449         smu_table->max_sustainable_clocks = NULL;
 450         smu_table->driver_pptable = NULL;
 451         smu_table->clocks_table = NULL;
 452         kfree(smu_table->hardcode_pptable);
 453         smu_table->hardcode_pptable = NULL;
 454
 455         kfree(smu_table->metrics_table);
 456         kfree(smu_table->watermarks_table);
 457         smu_table->metrics_table = NULL;
 458         smu_table->watermarks_table = NULL;
 459         smu_table->metrics_time = 0;
 460
 461         kfree(smu_dpm->dpm_context);
 462         kfree(smu_dpm->golden_dpm_context);
 463         kfree(smu_dpm->dpm_current_power_state);
 464         kfree(smu_dpm->dpm_request_power_state);
 465         smu_dpm->dpm_context = NULL;
 466         smu_dpm->golden_dpm_context = NULL;
 467         smu_dpm->dpm_context_size = 0;
 468         smu_dpm->dpm_current_power_state = NULL;
 469         smu_dpm->dpm_request_power_state = NULL;
 470
 471         return 0;
 472 }
 473
 474 int smu_v11_0_init_power(struct smu_context *smu)
 475 {
 476         struct smu_power_context *smu_power = &smu->smu_power;
 477
 478         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context),
 479                                            GFP_KERNEL);
 480         if (!smu_power->power_context)
 481                 return -ENOMEM;
 482         smu_power->power_context_size = sizeof(struct smu_11_0_power_context);
 483
 484         return 0;
 485 }
 486
 487 int smu_v11_0_fini_power(struct smu_context *smu)
 488 {
 489         struct smu_power_context *smu_power = &smu->smu_power;
 490
 491         kfree(smu_power->power_context);
 492         smu_power->power_context = NULL;
 493         smu_power->power_context_size = 0;
 494
 495         return 0;
 496 }
 497
 498 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 499                                             uint8_t clk_id,
 500                                             uint8_t syspll_id,
 501                                             uint32_t *clk_freq)
 502 {
 503         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 504         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 505         int ret, index;
 506
 507         input.clk_id = clk_id;
 508         input.syspll_id = syspll_id;
 509         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 510         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 511                                             getsmuclockinfo);
 512
 513         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 514                                         (uint32_t *)&input);
 515         if (ret)
 516                 return -EINVAL;
 517
 518         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 519         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 520
 521         return 0;
 522 }
 523
 524 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 525 {
 526         int ret, index;
 527         uint16_t size;
 528         uint8_t frev, crev;
 529         struct atom_common_table_header *header;
 530         struct atom_firmware_info_v3_3 *v_3_3;
 531         struct atom_firmware_info_v3_1 *v_3_1;
 532
 533         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 534                                             firmwareinfo);
 535
 536         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 537                                       (uint8_t **)&header);
 538         if (ret)
 539                 return ret;
 540
 541         if (header->format_revision != 3) {
 542                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 543                 return -EINVAL;
 544         }
 545
 546         switch (header->content_revision) {
 547         case 0:
 548         case 1:
 549         case 2:
 550                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 551                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 552                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 553                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 554                 smu->smu_table.boot_values.socclk = 0;
 555                 smu->smu_table.boot_values.dcefclk = 0;
 556                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 557                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 558                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 559                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 560                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 561                 smu->smu_table.boot_values.pp_table_id = 0;
 562                 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
 563                 break;
 564         case 3:
 565         default:
 566                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 567                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 568                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 569                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 570                 smu->smu_table.boot_values.socclk = 0;
 571                 smu->smu_table.boot_values.dcefclk = 0;
 572                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 573                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 574                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 575                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 576                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 577                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 578                 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
 579         }
 580
 581         smu->smu_table.boot_values.format_revision = header->format_revision;
 582         smu->smu_table.boot_values.content_revision = header->content_revision;
 583
 584         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 585                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 586                                          (uint8_t)0,
 587                                          &smu->smu_table.boot_values.socclk);
 588
 589         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 590                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 591                                          (uint8_t)0,
 592                                          &smu->smu_table.boot_values.dcefclk);
 593
 594         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 595                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 596                                          (uint8_t)0,
 597                                          &smu->smu_table.boot_values.eclk);
 598
 599         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 600                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 601                                          (uint8_t)0,
 602                                          &smu->smu_table.boot_values.vclk);
 603
 604         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 605                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 606                                          (uint8_t)0,
 607                                          &smu->smu_table.boot_values.dclk);
 608
 609         if ((smu->smu_table.boot_values.format_revision == 3) &&
 610             (smu->smu_table.boot_values.content_revision >= 2))
 611                 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 612                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 613                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 614                                                  &smu->smu_table.boot_values.fclk);
 615
 616         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 617                                          (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
 618                                          (uint8_t)SMU11_SYSPLL3_1_ID,
 619                                          &smu->smu_table.boot_values.lclk);
 620
 621         return 0;
 622 }
 623
 624 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 625 {
 626         struct smu_table_context *smu_table = &smu->smu_table;
 627         struct smu_table *memory_pool = &smu_table->memory_pool;
 628         int ret = 0;
 629         uint64_t address;
 630         uint32_t address_low, address_high;
 631
 632         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 633                 return ret;
 634
 635         address = (uintptr_t)memory_pool->cpu_addr;
 636         address_high = (uint32_t)upper_32_bits(address);
 637         address_low  = (uint32_t)lower_32_bits(address);
 638
 639         ret = smu_cmn_send_smc_msg_with_param(smu,
 640                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 641                                           address_high,
 642                                           NULL);
 643         if (ret)
 644                 return ret;
 645         ret = smu_cmn_send_smc_msg_with_param(smu,
 646                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 647                                           address_low,
 648                                           NULL);
 649         if (ret)
 650                 return ret;
 651
 652         address = memory_pool->mc_address;
 653         address_high = (uint32_t)upper_32_bits(address);
 654         address_low  = (uint32_t)lower_32_bits(address);
 655
 656         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 657                                           address_high, NULL);
 658         if (ret)
 659                 return ret;
 660         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 661                                           address_low, NULL);
 662         if (ret)
 663                 return ret;
 664         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 665                                           (uint32_t)memory_pool->size, NULL);
 666         if (ret)
 667                 return ret;
 668
 669         return ret;
 670 }
 671
 672 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 673 {
 674         int ret;
 675
 676         ret = smu_cmn_send_smc_msg_with_param(smu,
 677                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 678         if (ret)
 679                 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 680
 681         return ret;
 682 }
 683
 684 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 685 {
 686         struct smu_table *driver_table = &smu->smu_table.driver_table;
 687         int ret = 0;
 688
 689         if (driver_table->mc_address) {
 690                 ret = smu_cmn_send_smc_msg_with_param(smu,
 691                                 SMU_MSG_SetDriverDramAddrHigh,
 692                                 upper_32_bits(driver_table->mc_address),
 693                                 NULL);
 694                 if (!ret)
 695                         ret = smu_cmn_send_smc_msg_with_param(smu,
 696                                 SMU_MSG_SetDriverDramAddrLow,
 697                                 lower_32_bits(driver_table->mc_address),
 698                                 NULL);
 699         }
 700
 701         return ret;
 702 }
 703
 704 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 705 {
 706         int ret = 0;
 707         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 708
 709         if (tool_table->mc_address) {
 710                 ret = smu_cmn_send_smc_msg_with_param(smu,
 711                                 SMU_MSG_SetToolsDramAddrHigh,
 712                                 upper_32_bits(tool_table->mc_address),
 713                                 NULL);
 714                 if (!ret)
 715                         ret = smu_cmn_send_smc_msg_with_param(smu,
 716                                 SMU_MSG_SetToolsDramAddrLow,
 717                                 lower_32_bits(tool_table->mc_address),
 718                                 NULL);
 719         }
 720
 721         return ret;
 722 }
 723
 724 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 725 {
 726         struct amdgpu_device *adev = smu->adev;
 727
 728         /* Navy_Flounder/Dimgrey_Cavefish do not support to change
 729          * display num currently
 730          */
 731         if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
 732             adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
 733                 return 0;
 734
 735         return smu_cmn_send_smc_msg_with_param(smu,
 736                                                SMU_MSG_NumOfDisplays,
 737                                                count,
 738                                                NULL);
 739 }
 740
 741
 742 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 743 {
 744         struct smu_feature *feature = &smu->smu_feature;
 745         int ret = 0;
 746         uint32_t feature_mask[2];
 747
 748         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 749                 goto failed;
 750
 751         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 752
 753         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 754                                           feature_mask[1], NULL);
 755         if (ret)
 756                 goto failed;
 757
 758         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 759                                           feature_mask[0], NULL);
 760         if (ret)
 761                 goto failed;
 762
 763 failed:
 764         return ret;
 765 }
 766
 767 int smu_v11_0_system_features_control(struct smu_context *smu,
 768                                              bool en)
 769 {
 770         struct smu_feature *feature = &smu->smu_feature;
 771         uint32_t feature_mask[2];
 772         int ret = 0;
 773
 774         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 775                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 776         if (ret)
 777                 return ret;
 778
 779         bitmap_zero(feature->enabled, feature->feature_num);
 780         bitmap_zero(feature->supported, feature->feature_num);
 781
 782         if (en) {
 783                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 784                 if (ret)
 785                         return ret;
 786
 787                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 788                             feature->feature_num);
 789                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 790                             feature->feature_num);
 791         }
 792
 793         return ret;
 794 }
 795
 796 int smu_v11_0_notify_display_change(struct smu_context *smu)
 797 {
 798         int ret = 0;
 799
 800         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 801             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 802                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 803
 804         return ret;
 805 }
 806
 807 static int
 808 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 809                                     enum smu_clk_type clock_select)
 810 {
 811         int ret = 0;
 812         int clk_id;
 813
 814         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 815             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 816                 return 0;
 817
 818         clk_id = smu_cmn_to_asic_specific_index(smu,
 819                                                 CMN2ASIC_MAPPING_CLK,
 820                                                 clock_select);
 821         if (clk_id < 0)
 822                 return -EINVAL;
 823
 824         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 825                                           clk_id << 16, clock);
 826         if (ret) {
 827                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 828                 return ret;
 829         }
 830
 831         if (*clock != 0)
 832                 return 0;
 833
 834         /* if DC limit is zero, return AC limit */
 835         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 836                                           clk_id << 16, clock);
 837         if (ret) {
 838                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 839                 return ret;
 840         }
 841
 842         return 0;
 843 }
 844
 845 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 846 {
 847         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 848                         smu->smu_table.max_sustainable_clocks;
 849         int ret = 0;
 850
 851         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 852         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 853         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 854         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 855         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 856         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 857
 858         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 859                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 860                                                           &(max_sustainable_clocks->uclock),
 861                                                           SMU_UCLK);
 862                 if (ret) {
 863                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 864                                __func__);
 865                         return ret;
 866                 }
 867         }
 868
 869         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 870                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 871                                                           &(max_sustainable_clocks->soc_clock),
 872                                                           SMU_SOCCLK);
 873                 if (ret) {
 874                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 875                                __func__);
 876                         return ret;
 877                 }
 878         }
 879
 880         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 881                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 882                                                           &(max_sustainable_clocks->dcef_clock),
 883                                                           SMU_DCEFCLK);
 884                 if (ret) {
 885                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 886                                __func__);
 887                         return ret;
 888                 }
 889
 890                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 891                                                           &(max_sustainable_clocks->display_clock),
 892                                                           SMU_DISPCLK);
 893                 if (ret) {
 894                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 895                                __func__);
 896                         return ret;
 897                 }
 898                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 899                                                           &(max_sustainable_clocks->phy_clock),
 900                                                           SMU_PHYCLK);
 901                 if (ret) {
 902                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 903                                __func__);
 904                         return ret;
 905                 }
 906                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 907                                                           &(max_sustainable_clocks->pixel_clock),
 908                                                           SMU_PIXCLK);
 909                 if (ret) {
 910                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 911                                __func__);
 912                         return ret;
 913                 }
 914         }
 915
 916         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 917                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 918
 919         return 0;
 920 }
 921
 922 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 923                                       uint32_t *power_limit)
 924 {
 925         int power_src;
 926         int ret = 0;
 927
 928         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 929                 return -EINVAL;
 930
 931         power_src = smu_cmn_to_asic_specific_index(smu,
 932                                         CMN2ASIC_MAPPING_PWR,
 933                                         smu->adev->pm.ac_power ?
 934                                         SMU_POWER_SOURCE_AC :
 935                                         SMU_POWER_SOURCE_DC);
 936         if (power_src < 0)
 937                 return -EINVAL;
 938
 939         /*
 940          * BIT 24-31: ControllerId (only PPT0 is supported for now)
 941          * BIT 16-23: PowerSource
 942          */
 943         ret = smu_cmn_send_smc_msg_with_param(smu,
 944                                           SMU_MSG_GetPptLimit,
 945                                           (0 << 24) | (power_src << 16),
 946                                           power_limit);
 947         if (ret)
 948                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 949
 950         return ret;
 951 }
 952
 953 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 954 {
 955         int power_src;
 956         int ret = 0;
 957
 958         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 959                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 960                 return -EOPNOTSUPP;
 961         }
 962
 963         power_src = smu_cmn_to_asic_specific_index(smu,
 964                                         CMN2ASIC_MAPPING_PWR,
 965                                         smu->adev->pm.ac_power ?
 966                                         SMU_POWER_SOURCE_AC :
 967                                         SMU_POWER_SOURCE_DC);
 968         if (power_src < 0)
 969                 return -EINVAL;
 970
 971         /*
 972          * BIT 24-31: ControllerId (only PPT0 is supported for now)
 973          * BIT 16-23: PowerSource
 974          * BIT 0-15: PowerLimit
 975          */
 976         n &= 0xFFFF;
 977         n |= 0 << 24;
 978         n |= (power_src) << 16;
 979         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 980         if (ret) {
 981                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 982                 return ret;
 983         }
 984
 985         smu->current_power_limit = n;
 986
 987         return 0;
 988 }
 989
 990 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
 991 {
 992         return smu_cmn_send_smc_msg(smu,
 993                                 SMU_MSG_ReenableAcDcInterrupt,
 994                                 NULL);
 995 }
 996
 997 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
 998 {
 999         int ret = 0;
1000
1001         if (smu->dc_controlled_by_gpio &&
1002             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1003                 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1004
1005         return ret;
1006 }
1007
1008 void smu_v11_0_interrupt_work(struct smu_context *smu)
1009 {
1010         if (smu_v11_0_ack_ac_dc_interrupt(smu))
1011                 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1012 }
1013
1014 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1015 {
1016         int ret = 0;
1017
1018         if (smu->smu_table.thermal_controller_type) {
1019                 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1020                 if (ret)
1021                         return ret;
1022         }
1023
1024         /*
1025          * After init there might have been missed interrupts triggered
1026          * before driver registers for interrupt (Ex. AC/DC).
1027          */
1028         return smu_v11_0_process_pending_interrupt(smu);
1029 }
1030
1031 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1032 {
1033         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1034 }
1035
1036 static uint16_t convert_to_vddc(uint8_t vid)
1037 {
1038         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1039 }
1040
1041 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1042 {
1043         struct amdgpu_device *adev = smu->adev;
1044         uint32_t vdd = 0, val_vid = 0;
1045
1046         if (!value)
1047                 return -EINVAL;
1048         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1049                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1050                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1051
1052         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1053
1054         *value = vdd;
1055
1056         return 0;
1057
1058 }
1059
1060 int
1061 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1062                                         struct pp_display_clock_request
1063                                         *clock_req)
1064 {
1065         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1066         int ret = 0;
1067         enum smu_clk_type clk_select = 0;
1068         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1069
1070         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1071                 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1072                 switch (clk_type) {
1073                 case amd_pp_dcef_clock:
1074                         clk_select = SMU_DCEFCLK;
1075                         break;
1076                 case amd_pp_disp_clock:
1077                         clk_select = SMU_DISPCLK;
1078                         break;
1079                 case amd_pp_pixel_clock:
1080                         clk_select = SMU_PIXCLK;
1081                         break;
1082                 case amd_pp_phy_clock:
1083                         clk_select = SMU_PHYCLK;
1084                         break;
1085                 case amd_pp_mem_clock:
1086                         clk_select = SMU_UCLK;
1087                         break;
1088                 default:
1089                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1090                         ret = -EINVAL;
1091                         break;
1092                 }
1093
1094                 if (ret)
1095                         goto failed;
1096
1097                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1098                         return 0;
1099
1100                 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1101
1102                 if(clk_select == SMU_UCLK)
1103                         smu->hard_min_uclk_req_from_dal = clk_freq;
1104         }
1105
1106 failed:
1107         return ret;
1108 }
1109
1110 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1111 {
1112         int ret = 0;
1113         struct amdgpu_device *adev = smu->adev;
1114
1115         switch (adev->asic_type) {
1116         case CHIP_NAVI10:
1117         case CHIP_NAVI14:
1118         case CHIP_NAVI12:
1119         case CHIP_SIENNA_CICHLID:
1120         case CHIP_NAVY_FLOUNDER:
1121         case CHIP_DIMGREY_CAVEFISH:
1122         case CHIP_VANGOGH:
1123                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1124                         return 0;
1125                 if (enable)
1126                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1127                 else
1128                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1129                 break;
1130         default:
1131                 break;
1132         }
1133
1134         return ret;
1135 }
1136
1137 uint32_t
1138 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1139 {
1140         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1141                 return AMD_FAN_CTRL_MANUAL;
1142         else
1143                 return AMD_FAN_CTRL_AUTO;
1144 }
1145
1146 static int
1147 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1148 {
1149         int ret = 0;
1150
1151         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1152                 return 0;
1153
1154         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1155         if (ret)
1156                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1157                        __func__, (auto_fan_control ? "Start" : "Stop"));
1158
1159         return ret;
1160 }
1161
1162 static int
1163 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1164 {
1165         struct amdgpu_device *adev = smu->adev;
1166
1167         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1168                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1169                                    CG_FDO_CTRL2, TMIN, 0));
1170         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1171                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1172                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1173
1174         return 0;
1175 }
1176
1177 int
1178 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1179                                uint32_t mode)
1180 {
1181         int ret = 0;
1182
1183         switch (mode) {
1184         case AMD_FAN_CTRL_NONE:
1185                 ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
1186                 break;
1187         case AMD_FAN_CTRL_MANUAL:
1188                 ret = smu_v11_0_auto_fan_control(smu, 0);
1189                 break;
1190         case AMD_FAN_CTRL_AUTO:
1191                 ret = smu_v11_0_auto_fan_control(smu, 1);
1192                 break;
1193         default:
1194                 break;
1195         }
1196
1197         if (ret) {
1198                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1199                 return -EINVAL;
1200         }
1201
1202         return ret;
1203 }
1204
1205 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1206                                        uint32_t speed)
1207 {
1208         struct amdgpu_device *adev = smu->adev;
1209         int ret;
1210         uint32_t tach_period, crystal_clock_freq;
1211
1212         if (!speed)
1213                 return -EINVAL;
1214
1215         ret = smu_v11_0_auto_fan_control(smu, 0);
1216         if (ret)
1217                 return ret;
1218
1219         /*
1220          * crystal_clock_freq div by 4 is required since the fan control
1221          * module refers to 25MHz
1222          */
1223
1224         crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
1225         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1226         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1227                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1228                                    CG_TACH_CTRL, TARGET_PERIOD,
1229                                    tach_period));
1230
1231         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1232
1233         return ret;
1234 }
1235
1236 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1237                                 uint32_t *speed)
1238 {
1239         struct amdgpu_device *adev = smu->adev;
1240         uint32_t tach_period, crystal_clock_freq;
1241         uint64_t tmp64;
1242
1243         tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1244                                     CG_TACH_CTRL, TARGET_PERIOD);
1245         if (!tach_period)
1246                 return -EINVAL;
1247
1248         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1249
1250         tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1251         do_div(tmp64, (tach_period * 8));
1252         *speed = (uint32_t)tmp64;
1253
1254         return 0;
1255 }
1256
1257 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1258                                      uint32_t pstate)
1259 {
1260         return smu_cmn_send_smc_msg_with_param(smu,
1261                                                SMU_MSG_SetXgmiMode,
1262                                                pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1263                                           NULL);
1264 }
1265
1266 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1267                                    struct amdgpu_irq_src *source,
1268                                    unsigned tyep,
1269                                    enum amdgpu_interrupt_state state)
1270 {
1271         struct smu_context *smu = &adev->smu;
1272         uint32_t low, high;
1273         uint32_t val = 0;
1274
1275         switch (state) {
1276         case AMDGPU_IRQ_STATE_DISABLE:
1277                 /* For THM irqs */
1278                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1279                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1280                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1281                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1282
1283                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1284
1285                 /* For MP1 SW irqs */
1286                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1287                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1288                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1289
1290                 break;
1291         case AMDGPU_IRQ_STATE_ENABLE:
1292                 /* For THM irqs */
1293                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1294                                 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1295                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1296                                 smu->thermal_range.software_shutdown_temp);
1297
1298                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1299                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1300                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1301                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1302                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1303                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1304                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1305                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1306                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1307
1308                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1309                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1310                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1311                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1312
1313                 /* For MP1 SW irqs */
1314                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1315                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1316                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1317                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1318
1319                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1320                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1321                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1322
1323                 break;
1324         default:
1325                 break;
1326         }
1327
1328         return 0;
1329 }
1330
1331 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1332 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1333
1334 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1335
1336 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1337                                  struct amdgpu_irq_src *source,
1338                                  struct amdgpu_iv_entry *entry)
1339 {
1340         struct smu_context *smu = &adev->smu;
1341         uint32_t client_id = entry->client_id;
1342         uint32_t src_id = entry->src_id;
1343         /*
1344          * ctxid is used to distinguish different
1345          * events for SMCToHost interrupt.
1346          */
1347         uint32_t ctxid = entry->src_data[0];
1348         uint32_t data;
1349
1350         if (client_id == SOC15_IH_CLIENTID_THM) {
1351                 switch (src_id) {
1352                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1353                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1354                         /*
1355                          * SW CTF just occurred.
1356                          * Try to do a graceful shutdown to prevent further damage.
1357                          */
1358                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1359                         orderly_poweroff(true);
1360                 break;
1361                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1362                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1363                 break;
1364                 default:
1365                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1366                                 src_id);
1367                 break;
1368                 }
1369         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1370                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1371                 /*
1372                  * HW CTF just occurred. Shutdown to prevent further damage.
1373                  */
1374                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1375                 orderly_poweroff(true);
1376         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1377                 if (src_id == 0xfe) {
1378                         /* ACK SMUToHost interrupt */
1379                         data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1380                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1381                         WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1382
1383                         switch (ctxid) {
1384                         case 0x3:
1385                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1386                                 schedule_work(&smu->interrupt_work);
1387                                 break;
1388                         case 0x4:
1389                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1390                                 schedule_work(&smu->interrupt_work);
1391                                 break;
1392                         case 0x7:
1393                                 /*
1394                                  * Increment the throttle interrupt counter
1395                                  */
1396                                 atomic64_inc(&smu->throttle_int_counter);
1397
1398                                 if (!atomic_read(&adev->throttling_logging_enabled))
1399                                         return 0;
1400
1401                                 if (__ratelimit(&adev->throttling_logging_rs))
1402                                         schedule_work(&smu->throttling_logging_work);
1403
1404                                 break;
1405                         }
1406                 }
1407         }
1408
1409         return 0;
1410 }
1411
1412 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1413 {
1414         .set = smu_v11_0_set_irq_state,
1415         .process = smu_v11_0_irq_process,
1416 };
1417
1418 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1419 {
1420         struct amdgpu_device *adev = smu->adev;
1421         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1422         int ret = 0;
1423
1424         irq_src->num_types = 1;
1425         irq_src->funcs = &smu_v11_0_irq_funcs;
1426
1427         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1428                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1429                                 irq_src);
1430         if (ret)
1431                 return ret;
1432
1433         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1434                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1435                                 irq_src);
1436         if (ret)
1437                 return ret;
1438
1439         /* Register CTF(GPIO_19) interrupt */
1440         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1441                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1442                                 irq_src);
1443         if (ret)
1444                 return ret;
1445
1446         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1447                                 0xfe,
1448                                 irq_src);
1449         if (ret)
1450                 return ret;
1451
1452         return ret;
1453 }
1454
1455 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1456                 struct pp_smu_nv_clock_table *max_clocks)
1457 {
1458         struct smu_table_context *table_context = &smu->smu_table;
1459         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1460
1461         if (!max_clocks || !table_context->max_sustainable_clocks)
1462                 return -EINVAL;
1463
1464         sustainable_clocks = table_context->max_sustainable_clocks;
1465
1466         max_clocks->dcfClockInKhz =
1467                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1468         max_clocks->displayClockInKhz =
1469                         (unsigned int) sustainable_clocks->display_clock * 1000;
1470         max_clocks->phyClockInKhz =
1471                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1472         max_clocks->pixelClockInKhz =
1473                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1474         max_clocks->uClockInKhz =
1475                         (unsigned int) sustainable_clocks->uclock * 1000;
1476         max_clocks->socClockInKhz =
1477                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1478         max_clocks->dscClockInKhz = 0;
1479         max_clocks->dppClockInKhz = 0;
1480         max_clocks->fabricClockInKhz = 0;
1481
1482         return 0;
1483 }
1484
1485 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1486 {
1487         return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1488 }
1489
1490 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1491 {
1492         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1493 }
1494
1495 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1496 {
1497         struct smu_baco_context *smu_baco = &smu->smu_baco;
1498
1499         if (!smu_baco->platform_support)
1500                 return false;
1501
1502         /* Arcturus does not support this bit mask */
1503         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1504            !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1505                 return false;
1506
1507         return true;
1508 }
1509
1510 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1511 {
1512         struct smu_baco_context *smu_baco = &smu->smu_baco;
1513         enum smu_baco_state baco_state;
1514
1515         mutex_lock(&smu_baco->mutex);
1516         baco_state = smu_baco->state;
1517         mutex_unlock(&smu_baco->mutex);
1518
1519         return baco_state;
1520 }
1521
1522 #define D3HOT_BACO_SEQUENCE 0
1523 #define D3HOT_BAMACO_SEQUENCE 2
1524
1525 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1526 {
1527         struct smu_baco_context *smu_baco = &smu->smu_baco;
1528         struct amdgpu_device *adev = smu->adev;
1529         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1530         uint32_t data;
1531         int ret = 0;
1532
1533         if (smu_v11_0_baco_get_state(smu) == state)
1534                 return 0;
1535
1536         mutex_lock(&smu_baco->mutex);
1537
1538         if (state == SMU_BACO_STATE_ENTER) {
1539                 switch (adev->asic_type) {
1540                 case CHIP_SIENNA_CICHLID:
1541                 case CHIP_NAVY_FLOUNDER:
1542                 case CHIP_DIMGREY_CAVEFISH:
1543                         if (amdgpu_runtime_pm == 2)
1544                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1545                                                                       SMU_MSG_EnterBaco,
1546                                                                       D3HOT_BAMACO_SEQUENCE,
1547                                                                       NULL);
1548                         else
1549                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1550                                                                       SMU_MSG_EnterBaco,
1551                                                                       D3HOT_BACO_SEQUENCE,
1552                                                                       NULL);
1553                         break;
1554                 default:
1555                         if (!ras || !ras->supported) {
1556                                 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1557                                 data |= 0x80000000;
1558                                 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1559
1560                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1561                         } else {
1562                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1563                         }
1564                         break;
1565                 }
1566
1567         } else {
1568                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1569                 if (ret)
1570                         goto out;
1571
1572                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1573                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1574                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1575         }
1576         if (ret)
1577                 goto out;
1578
1579         smu_baco->state = state;
1580 out:
1581         mutex_unlock(&smu_baco->mutex);
1582         return ret;
1583 }
1584
1585 int smu_v11_0_baco_enter(struct smu_context *smu)
1586 {
1587         struct amdgpu_device *adev = smu->adev;
1588         int ret = 0;
1589
1590         /* Arcturus does not need this audio workaround */
1591         if (adev->asic_type != CHIP_ARCTURUS) {
1592                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1593                 if (ret)
1594                         return ret;
1595         }
1596
1597         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1598         if (ret)
1599                 return ret;
1600
1601         msleep(10);
1602
1603         return ret;
1604 }
1605
1606 int smu_v11_0_baco_exit(struct smu_context *smu)
1607 {
1608         return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1609 }
1610
1611 int smu_v11_0_mode1_reset(struct smu_context *smu)
1612 {
1613         int ret = 0;
1614
1615         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1616         if (!ret)
1617                 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1618
1619         return ret;
1620 }
1621
1622 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1623                                                  uint32_t *min, uint32_t *max)
1624 {
1625         int ret = 0, clk_id = 0;
1626         uint32_t param = 0;
1627         uint32_t clock_limit;
1628
1629         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1630                 switch (clk_type) {
1631                 case SMU_MCLK:
1632                 case SMU_UCLK:
1633                         clock_limit = smu->smu_table.boot_values.uclk;
1634                         break;
1635                 case SMU_GFXCLK:
1636                 case SMU_SCLK:
1637                         clock_limit = smu->smu_table.boot_values.gfxclk;
1638                         break;
1639                 case SMU_SOCCLK:
1640                         clock_limit = smu->smu_table.boot_values.socclk;
1641                         break;
1642                 default:
1643                         clock_limit = 0;
1644                         break;
1645                 }
1646
1647                 /* clock in Mhz unit */
1648                 if (min)
1649                         *min = clock_limit / 100;
1650                 if (max)
1651                         *max = clock_limit / 100;
1652
1653                 return 0;
1654         }
1655
1656         clk_id = smu_cmn_to_asic_specific_index(smu,
1657                                                 CMN2ASIC_MAPPING_CLK,
1658                                                 clk_type);
1659         if (clk_id < 0) {
1660                 ret = -EINVAL;
1661                 goto failed;
1662         }
1663         param = (clk_id & 0xffff) << 16;
1664
1665         if (max) {
1666                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1667                 if (ret)
1668                         goto failed;
1669         }
1670
1671         if (min) {
1672                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1673                 if (ret)
1674                         goto failed;
1675         }
1676
1677 failed:
1678         return ret;
1679 }
1680
1681 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1682                                           enum smu_clk_type clk_type,
1683                                           uint32_t min,
1684                                           uint32_t max)
1685 {
1686         struct amdgpu_device *adev = smu->adev;
1687         int ret = 0, clk_id = 0;
1688         uint32_t param;
1689
1690         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1691                 return 0;
1692
1693         clk_id = smu_cmn_to_asic_specific_index(smu,
1694                                                 CMN2ASIC_MAPPING_CLK,
1695                                                 clk_type);
1696         if (clk_id < 0)
1697                 return clk_id;
1698
1699         if (clk_type == SMU_GFXCLK)
1700                 amdgpu_gfx_off_ctrl(adev, false);
1701
1702         if (max > 0) {
1703                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1704                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1705                                                   param, NULL);
1706                 if (ret)
1707                         goto out;
1708         }
1709
1710         if (min > 0) {
1711                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1712                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1713                                                   param, NULL);
1714                 if (ret)
1715                         goto out;
1716         }
1717
1718 out:
1719         if (clk_type == SMU_GFXCLK)
1720                 amdgpu_gfx_off_ctrl(adev, true);
1721
1722         return ret;
1723 }
1724
1725 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1726                                           enum smu_clk_type clk_type,
1727                                           uint32_t min,
1728                                           uint32_t max)
1729 {
1730         int ret = 0, clk_id = 0;
1731         uint32_t param;
1732
1733         if (min <= 0 && max <= 0)
1734                 return -EINVAL;
1735
1736         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1737                 return 0;
1738
1739         clk_id = smu_cmn_to_asic_specific_index(smu,
1740                                                 CMN2ASIC_MAPPING_CLK,
1741                                                 clk_type);
1742         if (clk_id < 0)
1743                 return clk_id;
1744
1745         if (max > 0) {
1746                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1747                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1748                                                   param, NULL);
1749                 if (ret)
1750                         return ret;
1751         }
1752
1753         if (min > 0) {
1754                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1755                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1756                                                   param, NULL);
1757                 if (ret)
1758                         return ret;
1759         }
1760
1761         return ret;
1762 }
1763
1764 int smu_v11_0_set_performance_level(struct smu_context *smu,
1765                                     enum amd_dpm_forced_level level)
1766 {
1767         struct smu_11_0_dpm_context *dpm_context =
1768                                 smu->smu_dpm.dpm_context;
1769         struct smu_11_0_dpm_table *gfx_table =
1770                                 &dpm_context->dpm_tables.gfx_table;
1771         struct smu_11_0_dpm_table *mem_table =
1772                                 &dpm_context->dpm_tables.uclk_table;
1773         struct smu_11_0_dpm_table *soc_table =
1774                                 &dpm_context->dpm_tables.soc_table;
1775         struct smu_umd_pstate_table *pstate_table =
1776                                 &smu->pstate_table;
1777         struct amdgpu_device *adev = smu->adev;
1778         uint32_t sclk_min = 0, sclk_max = 0;
1779         uint32_t mclk_min = 0, mclk_max = 0;
1780         uint32_t socclk_min = 0, socclk_max = 0;
1781         int ret = 0;
1782
1783         switch (level) {
1784         case AMD_DPM_FORCED_LEVEL_HIGH:
1785                 sclk_min = sclk_max = gfx_table->max;
1786                 mclk_min = mclk_max = mem_table->max;
1787                 socclk_min = socclk_max = soc_table->max;
1788                 break;
1789         case AMD_DPM_FORCED_LEVEL_LOW:
1790                 sclk_min = sclk_max = gfx_table->min;
1791                 mclk_min = mclk_max = mem_table->min;
1792                 socclk_min = socclk_max = soc_table->min;
1793                 break;
1794         case AMD_DPM_FORCED_LEVEL_AUTO:
1795                 sclk_min = gfx_table->min;
1796                 sclk_max = gfx_table->max;
1797                 mclk_min = mem_table->min;
1798                 mclk_max = mem_table->max;
1799                 socclk_min = soc_table->min;
1800                 socclk_max = soc_table->max;
1801                 break;
1802         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1803                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1804                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1805                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1806                 break;
1807         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1808                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1809                 break;
1810         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1811                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1812                 break;
1813         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1814                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1815                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1816                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1817                 break;
1818         case AMD_DPM_FORCED_LEVEL_MANUAL:
1819         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1820                 return 0;
1821         default:
1822                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1823                 return -EINVAL;
1824         }
1825
1826         /*
1827          * Separate MCLK and SOCCLK soft min/max settings are not allowed
1828          * on Arcturus.
1829          */
1830         if (adev->asic_type == CHIP_ARCTURUS) {
1831                 mclk_min = mclk_max = 0;
1832                 socclk_min = socclk_max = 0;
1833         }
1834
1835         if (sclk_min && sclk_max) {
1836                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1837                                                             SMU_GFXCLK,
1838                                                             sclk_min,
1839                                                             sclk_max);
1840                 if (ret)
1841                         return ret;
1842         }
1843
1844         if (mclk_min && mclk_max) {
1845                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1846                                                             SMU_MCLK,
1847                                                             mclk_min,
1848                                                             mclk_max);
1849                 if (ret)
1850                         return ret;
1851         }
1852
1853         if (socclk_min && socclk_max) {
1854                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1855                                                             SMU_SOCCLK,
1856                                                             socclk_min,
1857                                                             socclk_max);
1858                 if (ret)
1859                         return ret;
1860         }
1861
1862         return ret;
1863 }
1864
1865 int smu_v11_0_set_power_source(struct smu_context *smu,
1866                                enum smu_power_src_type power_src)
1867 {
1868         int pwr_source;
1869
1870         pwr_source = smu_cmn_to_asic_specific_index(smu,
1871                                                     CMN2ASIC_MAPPING_PWR,
1872                                                     (uint32_t)power_src);
1873         if (pwr_source < 0)
1874                 return -EINVAL;
1875
1876         return smu_cmn_send_smc_msg_with_param(smu,
1877                                         SMU_MSG_NotifyPowerSource,
1878                                         pwr_source,
1879                                         NULL);
1880 }
1881
1882 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1883                                     enum smu_clk_type clk_type,
1884                                     uint16_t level,
1885                                     uint32_t *value)
1886 {
1887         int ret = 0, clk_id = 0;
1888         uint32_t param;
1889
1890         if (!value)
1891                 return -EINVAL;
1892
1893         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1894                 return 0;
1895
1896         clk_id = smu_cmn_to_asic_specific_index(smu,
1897                                                 CMN2ASIC_MAPPING_CLK,
1898                                                 clk_type);
1899         if (clk_id < 0)
1900                 return clk_id;
1901
1902         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1903
1904         ret = smu_cmn_send_smc_msg_with_param(smu,
1905                                           SMU_MSG_GetDpmFreqByIndex,
1906                                           param,
1907                                           value);
1908         if (ret)
1909                 return ret;
1910
1911         /*
1912          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1913          * now, we un-support it
1914          */
1915         *value = *value & 0x7fffffff;
1916
1917         return ret;
1918 }
1919
1920 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1921                                   enum smu_clk_type clk_type,
1922                                   uint32_t *value)
1923 {
1924         return smu_v11_0_get_dpm_freq_by_index(smu,
1925                                                clk_type,
1926                                                0xff,
1927                                                value);
1928 }
1929
1930 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1931                                    enum smu_clk_type clk_type,
1932                                    struct smu_11_0_dpm_table *single_dpm_table)
1933 {
1934         int ret = 0;
1935         uint32_t clk;
1936         int i;
1937
1938         ret = smu_v11_0_get_dpm_level_count(smu,
1939                                             clk_type,
1940                                             &single_dpm_table->count);
1941         if (ret) {
1942                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1943                 return ret;
1944         }
1945
1946         for (i = 0; i < single_dpm_table->count; i++) {
1947                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1948                                                       clk_type,
1949                                                       i,
1950                                                       &clk);
1951                 if (ret) {
1952                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1953                         return ret;
1954                 }
1955
1956                 single_dpm_table->dpm_levels[i].value = clk;
1957                 single_dpm_table->dpm_levels[i].enabled = true;
1958
1959                 if (i == 0)
1960                         single_dpm_table->min = clk;
1961                 else if (i == single_dpm_table->count - 1)
1962                         single_dpm_table->max = clk;
1963         }
1964
1965         return 0;
1966 }
1967
1968 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1969                                   enum smu_clk_type clk_type,
1970                                   uint32_t *min_value,
1971                                   uint32_t *max_value)
1972 {
1973         uint32_t level_count = 0;
1974         int ret = 0;
1975
1976         if (!min_value && !max_value)
1977                 return -EINVAL;
1978
1979         if (min_value) {
1980                 /* by default, level 0 clock value as min value */
1981                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1982                                                       clk_type,
1983                                                       0,
1984                                                       min_value);
1985                 if (ret)
1986                         return ret;
1987         }
1988
1989         if (max_value) {
1990                 ret = smu_v11_0_get_dpm_level_count(smu,
1991                                                     clk_type,
1992                                                     &level_count);
1993                 if (ret)
1994                         return ret;
1995
1996                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1997                                                       clk_type,
1998                                                       level_count - 1,
1999                                                       max_value);
2000                 if (ret)
2001                         return ret;
2002         }
2003
2004         return ret;
2005 }
2006
2007 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2008 {
2009         struct amdgpu_device *adev = smu->adev;
2010
2011         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2012                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2013                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2014 }
2015
2016 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2017 {
2018         uint32_t width_level;
2019
2020         width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2021         if (width_level > LINK_WIDTH_MAX)
2022                 width_level = 0;
2023
2024         return link_width[width_level];
2025 }
2026
2027 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2028 {
2029         struct amdgpu_device *adev = smu->adev;
2030
2031         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2032                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2033                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2034 }
2035
2036 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2037 {
2038         uint32_t speed_level;
2039
2040         speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2041         if (speed_level > LINK_SPEED_MAX)
2042                 speed_level = 0;
2043
2044         return link_speed[speed_level];
2045 }
2046
2047 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2048 {
2049         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2050
2051         gpu_metrics->common_header.structure_size =
2052                                 sizeof(struct gpu_metrics_v1_0);
2053         gpu_metrics->common_header.format_revision = 1;
2054         gpu_metrics->common_header.content_revision = 0;
2055
2056         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2057 }
2058
2059 void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
2060 {
2061         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
2062
2063         gpu_metrics->common_header.structure_size =
2064                                 sizeof(struct gpu_metrics_v2_0);
2065         gpu_metrics->common_header.format_revision = 2;
2066         gpu_metrics->common_header.content_revision = 0;
2067
2068         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2069 }
2070
2071 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2072                               bool enablement)
2073 {
2074         int ret = 0;
2075
2076         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2077                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2078
2079         return ret;
2080 }
2081
2082 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2083                                  bool enablement)
2084 {
2085         struct amdgpu_device *adev = smu->adev;
2086         int ret = 0;
2087
2088         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2089                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2090                 if (ret) {
2091                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2092                         return ret;
2093                 }
2094         }
2095
2096         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2097                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2098                 if (ret) {
2099                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2100                         return ret;
2101                 }
2102         }
2103
2104         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2105                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2106                 if (ret) {
2107                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2108                         return ret;
2109                 }
2110         }
2111
2112         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2113                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2114                 if (ret) {
2115                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2116                         return ret;
2117                 }
2118         }
2119
2120         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2121                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2122                 if (ret) {
2123                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2124                         return ret;
2125                 }
2126         }
2127
2128         return ret;
2129 }