drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_11_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v11_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
  66
  67 #define SMU11_VOLTAGE_SCALE 4
  68
  69 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  70
  71 #define LINK_WIDTH_MAX                          6
  72 #define LINK_SPEED_MAX                          3
  73
  74 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  76 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  77 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  79 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  80
  81 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  82 static int link_speed[] = {25, 50, 80, 160};
  83
  84 int smu_v11_0_init_microcode(struct smu_context *smu)
  85 {
  86         struct amdgpu_device *adev = smu->adev;
  87         const char *chip_name;
  88         char fw_name[SMU_FW_NAME_LEN];
  89         int err = 0;
  90         const struct smc_firmware_header_v1_0 *hdr;
  91         const struct common_firmware_header *header;
  92         struct amdgpu_firmware_info *ucode = NULL;
  93
  94         switch (adev->asic_type) {
  95         case CHIP_ARCTURUS:
  96                 chip_name = "arcturus";
  97                 break;
  98         case CHIP_NAVI10:
  99                 chip_name = "navi10";
 100                 break;
 101         case CHIP_NAVI14:
 102                 chip_name = "navi14";
 103                 break;
 104         case CHIP_NAVI12:
 105                 chip_name = "navi12";
 106                 break;
 107         case CHIP_SIENNA_CICHLID:
 108                 chip_name = "sienna_cichlid";
 109                 break;
 110         case CHIP_NAVY_FLOUNDER:
 111                 chip_name = "navy_flounder";
 112                 break;
 113         case CHIP_DIMGREY_CAVEFISH:
 114                 chip_name = "dimgrey_cavefish";
 115                 break;
 116         default:
 117                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 118                 return -EINVAL;
 119         }
 120
 121         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 122
 123         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 124         if (err)
 125                 goto out;
 126         err = amdgpu_ucode_validate(adev->pm.fw);
 127         if (err)
 128                 goto out;
 129
 130         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 131         amdgpu_ucode_print_smc_hdr(&hdr->header);
 132         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 133
 134         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 135                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 136                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 137                 ucode->fw = adev->pm.fw;
 138                 header = (const struct common_firmware_header *)ucode->fw->data;
 139                 adev->firmware.fw_size +=
 140                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 141         }
 142
 143 out:
 144         if (err) {
 145                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 146                           fw_name);
 147                 release_firmware(adev->pm.fw);
 148                 adev->pm.fw = NULL;
 149         }
 150         return err;
 151 }
 152
 153 void smu_v11_0_fini_microcode(struct smu_context *smu)
 154 {
 155         struct amdgpu_device *adev = smu->adev;
 156
 157         release_firmware(adev->pm.fw);
 158         adev->pm.fw = NULL;
 159         adev->pm.fw_version = 0;
 160 }
 161
 162 int smu_v11_0_load_microcode(struct smu_context *smu)
 163 {
 164         struct amdgpu_device *adev = smu->adev;
 165         const uint32_t *src;
 166         const struct smc_firmware_header_v1_0 *hdr;
 167         uint32_t addr_start = MP1_SRAM;
 168         uint32_t i;
 169         uint32_t smc_fw_size;
 170         uint32_t mp1_fw_flags;
 171
 172         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 173         src = (const uint32_t *)(adev->pm.fw->data +
 174                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 175         smc_fw_size = hdr->header.ucode_size_bytes;
 176
 177         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 178                 WREG32_PCIE(addr_start, src[i]);
 179                 addr_start += 4;
 180         }
 181
 182         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 183                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 184         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 185                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 186
 187         for (i = 0; i < adev->usec_timeout; i++) {
 188                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 189                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 190                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 191                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 192                         break;
 193                 udelay(1);
 194         }
 195
 196         if (i == adev->usec_timeout)
 197                 return -ETIME;
 198
 199         return 0;
 200 }
 201
 202 int smu_v11_0_check_fw_status(struct smu_context *smu)
 203 {
 204         struct amdgpu_device *adev = smu->adev;
 205         uint32_t mp1_fw_flags;
 206
 207         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 208                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 209
 210         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 211             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 212                 return 0;
 213
 214         return -EIO;
 215 }
 216
 217 int smu_v11_0_check_fw_version(struct smu_context *smu)
 218 {
 219         struct amdgpu_device *adev = smu->adev;
 220         uint32_t if_version = 0xff, smu_version = 0xff;
 221         uint16_t smu_major;
 222         uint8_t smu_minor, smu_debug;
 223         int ret = 0;
 224
 225         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 226         if (ret)
 227                 return ret;
 228
 229         smu_major = (smu_version >> 16) & 0xffff;
 230         smu_minor = (smu_version >> 8) & 0xff;
 231         smu_debug = (smu_version >> 0) & 0xff;
 232         if (smu->is_apu)
 233                 adev->pm.fw_version = smu_version;
 234
 235         switch (smu->adev->asic_type) {
 236         case CHIP_ARCTURUS:
 237                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 238                 break;
 239         case CHIP_NAVI10:
 240                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 241                 break;
 242         case CHIP_NAVI12:
 243                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 244                 break;
 245         case CHIP_NAVI14:
 246                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 247                 break;
 248         case CHIP_SIENNA_CICHLID:
 249                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 250                 break;
 251         case CHIP_NAVY_FLOUNDER:
 252                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 253                 break;
 254         case CHIP_VANGOGH:
 255                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
 256                 break;
 257         case CHIP_DIMGREY_CAVEFISH:
 258                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 262                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 263                 break;
 264         }
 265
 266         /*
 267          * 1. if_version mismatch is not critical as our fw is designed
 268          * to be backward compatible.
 269          * 2. New fw usually brings some optimizations. But that's visible
 270          * only on the paired driver.
 271          * Considering above, we just leave user a warning message instead
 272          * of halt driver loading.
 273          */
 274         if (if_version != smu->smc_driver_if_version) {
 275                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 276                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 277                         smu->smc_driver_if_version, if_version,
 278                         smu_version, smu_major, smu_minor, smu_debug);
 279                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 280         }
 281
 282         return ret;
 283 }
 284
 285 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 286 {
 287         struct amdgpu_device *adev = smu->adev;
 288         uint32_t ppt_offset_bytes;
 289         const struct smc_firmware_header_v2_0 *v2;
 290
 291         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 292
 293         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 294         *size = le32_to_cpu(v2->ppt_size_bytes);
 295         *table = (uint8_t *)v2 + ppt_offset_bytes;
 296
 297         return 0;
 298 }
 299
 300 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 301                                       uint32_t *size, uint32_t pptable_id)
 302 {
 303         struct amdgpu_device *adev = smu->adev;
 304         const struct smc_firmware_header_v2_1 *v2_1;
 305         struct smc_soft_pptable_entry *entries;
 306         uint32_t pptable_count = 0;
 307         int i = 0;
 308
 309         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 310         entries = (struct smc_soft_pptable_entry *)
 311                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 312         pptable_count = le32_to_cpu(v2_1->pptable_count);
 313         for (i = 0; i < pptable_count; i++) {
 314                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 315                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 316                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 317                         break;
 318                 }
 319         }
 320
 321         if (i == pptable_count)
 322                 return -EINVAL;
 323
 324         return 0;
 325 }
 326
 327 int smu_v11_0_setup_pptable(struct smu_context *smu)
 328 {
 329         struct amdgpu_device *adev = smu->adev;
 330         const struct smc_firmware_header_v1_0 *hdr;
 331         int ret, index;
 332         uint32_t size = 0;
 333         uint16_t atom_table_size;
 334         uint8_t frev, crev;
 335         void *table;
 336         uint16_t version_major, version_minor;
 337
 338         if (!amdgpu_sriov_vf(adev)) {
 339                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 340                 version_major = le16_to_cpu(hdr->header.header_version_major);
 341                 version_minor = le16_to_cpu(hdr->header.header_version_minor);
 342                 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 343                         dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 344                         switch (version_minor) {
 345                         case 0:
 346                                 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 347                                 break;
 348                         case 1:
 349                                 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 350                                                                 smu->smu_table.boot_values.pp_table_id);
 351                                 break;
 352                         default:
 353                                 ret = -EINVAL;
 354                                 break;
 355                         }
 356                         if (ret)
 357                                 return ret;
 358                         goto out;
 359                 }
 360         }
 361
 362         dev_info(adev->dev, "use vbios provided pptable\n");
 363         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 364                                                 powerplayinfo);
 365
 366         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 367                                                 (uint8_t **)&table);
 368         if (ret)
 369                 return ret;
 370         size = atom_table_size;
 371
 372 out:
 373         if (!smu->smu_table.power_play_table)
 374                 smu->smu_table.power_play_table = table;
 375         if (!smu->smu_table.power_play_table_size)
 376                 smu->smu_table.power_play_table_size = size;
 377
 378         return 0;
 379 }
 380
 381 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 382 {
 383         struct smu_table_context *smu_table = &smu->smu_table;
 384         struct smu_table *tables = smu_table->tables;
 385         int ret = 0;
 386
 387         smu_table->driver_pptable =
 388                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 389         if (!smu_table->driver_pptable) {
 390                 ret = -ENOMEM;
 391                 goto err0_out;
 392         }
 393
 394         smu_table->max_sustainable_clocks =
 395                 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 396         if (!smu_table->max_sustainable_clocks) {
 397                 ret = -ENOMEM;
 398                 goto err1_out;
 399         }
 400
 401         /* Arcturus does not support OVERDRIVE */
 402         if (tables[SMU_TABLE_OVERDRIVE].size) {
 403                 smu_table->overdrive_table =
 404                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 405                 if (!smu_table->overdrive_table) {
 406                         ret = -ENOMEM;
 407                         goto err2_out;
 408                 }
 409
 410                 smu_table->boot_overdrive_table =
 411                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 412                 if (!smu_table->boot_overdrive_table) {
 413                         ret = -ENOMEM;
 414                         goto err3_out;
 415                 }
 416         }
 417
 418         return 0;
 419
 420 err3_out:
 421         kfree(smu_table->overdrive_table);
 422 err2_out:
 423         kfree(smu_table->max_sustainable_clocks);
 424 err1_out:
 425         kfree(smu_table->driver_pptable);
 426 err0_out:
 427         return ret;
 428 }
 429
 430 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 431 {
 432         struct smu_table_context *smu_table = &smu->smu_table;
 433         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 434
 435         kfree(smu_table->gpu_metrics_table);
 436         kfree(smu_table->boot_overdrive_table);
 437         kfree(smu_table->overdrive_table);
 438         kfree(smu_table->max_sustainable_clocks);
 439         kfree(smu_table->driver_pptable);
 440         kfree(smu_table->clocks_table);
 441         smu_table->gpu_metrics_table = NULL;
 442         smu_table->boot_overdrive_table = NULL;
 443         smu_table->overdrive_table = NULL;
 444         smu_table->max_sustainable_clocks = NULL;
 445         smu_table->driver_pptable = NULL;
 446         smu_table->clocks_table = NULL;
 447         kfree(smu_table->hardcode_pptable);
 448         smu_table->hardcode_pptable = NULL;
 449
 450         kfree(smu_table->metrics_table);
 451         kfree(smu_table->watermarks_table);
 452         smu_table->metrics_table = NULL;
 453         smu_table->watermarks_table = NULL;
 454         smu_table->metrics_time = 0;
 455
 456         kfree(smu_dpm->dpm_context);
 457         kfree(smu_dpm->golden_dpm_context);
 458         kfree(smu_dpm->dpm_current_power_state);
 459         kfree(smu_dpm->dpm_request_power_state);
 460         smu_dpm->dpm_context = NULL;
 461         smu_dpm->golden_dpm_context = NULL;
 462         smu_dpm->dpm_context_size = 0;
 463         smu_dpm->dpm_current_power_state = NULL;
 464         smu_dpm->dpm_request_power_state = NULL;
 465
 466         return 0;
 467 }
 468
 469 int smu_v11_0_init_power(struct smu_context *smu)
 470 {
 471         struct smu_power_context *smu_power = &smu->smu_power;
 472
 473         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context),
 474                                            GFP_KERNEL);
 475         if (!smu_power->power_context)
 476                 return -ENOMEM;
 477         smu_power->power_context_size = sizeof(struct smu_11_0_power_context);
 478
 479         return 0;
 480 }
 481
 482 int smu_v11_0_fini_power(struct smu_context *smu)
 483 {
 484         struct smu_power_context *smu_power = &smu->smu_power;
 485
 486         kfree(smu_power->power_context);
 487         smu_power->power_context = NULL;
 488         smu_power->power_context_size = 0;
 489
 490         return 0;
 491 }
 492
 493 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 494                                             uint8_t clk_id,
 495                                             uint8_t syspll_id,
 496                                             uint32_t *clk_freq)
 497 {
 498         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 499         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 500         int ret, index;
 501
 502         input.clk_id = clk_id;
 503         input.syspll_id = syspll_id;
 504         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 505         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 506                                             getsmuclockinfo);
 507
 508         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 509                                         (uint32_t *)&input);
 510         if (ret)
 511                 return -EINVAL;
 512
 513         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 514         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 515
 516         return 0;
 517 }
 518
 519 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 520 {
 521         int ret, index;
 522         uint16_t size;
 523         uint8_t frev, crev;
 524         struct atom_common_table_header *header;
 525         struct atom_firmware_info_v3_3 *v_3_3;
 526         struct atom_firmware_info_v3_1 *v_3_1;
 527
 528         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 529                                             firmwareinfo);
 530
 531         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 532                                       (uint8_t **)&header);
 533         if (ret)
 534                 return ret;
 535
 536         if (header->format_revision != 3) {
 537                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 538                 return -EINVAL;
 539         }
 540
 541         switch (header->content_revision) {
 542         case 0:
 543         case 1:
 544         case 2:
 545                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 546                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 547                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 548                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 549                 smu->smu_table.boot_values.socclk = 0;
 550                 smu->smu_table.boot_values.dcefclk = 0;
 551                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 552                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 553                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 554                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 555                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 556                 smu->smu_table.boot_values.pp_table_id = 0;
 557                 break;
 558         case 3:
 559         default:
 560                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 561                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 562                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 563                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 564                 smu->smu_table.boot_values.socclk = 0;
 565                 smu->smu_table.boot_values.dcefclk = 0;
 566                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 567                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 568                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 569                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 570                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 571                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 572         }
 573
 574         smu->smu_table.boot_values.format_revision = header->format_revision;
 575         smu->smu_table.boot_values.content_revision = header->content_revision;
 576
 577         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 578                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 579                                          (uint8_t)0,
 580                                          &smu->smu_table.boot_values.socclk);
 581
 582         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 583                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 584                                          (uint8_t)0,
 585                                          &smu->smu_table.boot_values.dcefclk);
 586
 587         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 588                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 589                                          (uint8_t)0,
 590                                          &smu->smu_table.boot_values.eclk);
 591
 592         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 593                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 594                                          (uint8_t)0,
 595                                          &smu->smu_table.boot_values.vclk);
 596
 597         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 598                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 599                                          (uint8_t)0,
 600                                          &smu->smu_table.boot_values.dclk);
 601
 602         if ((smu->smu_table.boot_values.format_revision == 3) &&
 603             (smu->smu_table.boot_values.content_revision >= 2))
 604                 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 605                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 606                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 607                                                  &smu->smu_table.boot_values.fclk);
 608
 609         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 610                                          (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
 611                                          (uint8_t)SMU11_SYSPLL3_1_ID,
 612                                          &smu->smu_table.boot_values.lclk);
 613
 614         return 0;
 615 }
 616
 617 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 618 {
 619         struct smu_table_context *smu_table = &smu->smu_table;
 620         struct smu_table *memory_pool = &smu_table->memory_pool;
 621         int ret = 0;
 622         uint64_t address;
 623         uint32_t address_low, address_high;
 624
 625         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 626                 return ret;
 627
 628         address = (uintptr_t)memory_pool->cpu_addr;
 629         address_high = (uint32_t)upper_32_bits(address);
 630         address_low  = (uint32_t)lower_32_bits(address);
 631
 632         ret = smu_cmn_send_smc_msg_with_param(smu,
 633                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 634                                           address_high,
 635                                           NULL);
 636         if (ret)
 637                 return ret;
 638         ret = smu_cmn_send_smc_msg_with_param(smu,
 639                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 640                                           address_low,
 641                                           NULL);
 642         if (ret)
 643                 return ret;
 644
 645         address = memory_pool->mc_address;
 646         address_high = (uint32_t)upper_32_bits(address);
 647         address_low  = (uint32_t)lower_32_bits(address);
 648
 649         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 650                                           address_high, NULL);
 651         if (ret)
 652                 return ret;
 653         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 654                                           address_low, NULL);
 655         if (ret)
 656                 return ret;
 657         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 658                                           (uint32_t)memory_pool->size, NULL);
 659         if (ret)
 660                 return ret;
 661
 662         return ret;
 663 }
 664
 665 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 666 {
 667         int ret;
 668
 669         ret = smu_cmn_send_smc_msg_with_param(smu,
 670                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 671         if (ret)
 672                 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 673
 674         return ret;
 675 }
 676
 677 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 678 {
 679         struct smu_table *driver_table = &smu->smu_table.driver_table;
 680         int ret = 0;
 681
 682         if (driver_table->mc_address) {
 683                 ret = smu_cmn_send_smc_msg_with_param(smu,
 684                                 SMU_MSG_SetDriverDramAddrHigh,
 685                                 upper_32_bits(driver_table->mc_address),
 686                                 NULL);
 687                 if (!ret)
 688                         ret = smu_cmn_send_smc_msg_with_param(smu,
 689                                 SMU_MSG_SetDriverDramAddrLow,
 690                                 lower_32_bits(driver_table->mc_address),
 691                                 NULL);
 692         }
 693
 694         return ret;
 695 }
 696
 697 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 698 {
 699         int ret = 0;
 700         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 701
 702         if (tool_table->mc_address) {
 703                 ret = smu_cmn_send_smc_msg_with_param(smu,
 704                                 SMU_MSG_SetToolsDramAddrHigh,
 705                                 upper_32_bits(tool_table->mc_address),
 706                                 NULL);
 707                 if (!ret)
 708                         ret = smu_cmn_send_smc_msg_with_param(smu,
 709                                 SMU_MSG_SetToolsDramAddrLow,
 710                                 lower_32_bits(tool_table->mc_address),
 711                                 NULL);
 712         }
 713
 714         return ret;
 715 }
 716
 717 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 718 {
 719         struct amdgpu_device *adev = smu->adev;
 720
 721         /* Navy_Flounder/Dimgrey_Cavefish do not support to change
 722          * display num currently
 723          */
 724         if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
 725             adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
 726                 return 0;
 727
 728         return smu_cmn_send_smc_msg_with_param(smu,
 729                                                SMU_MSG_NumOfDisplays,
 730                                                count,
 731                                                NULL);
 732 }
 733
 734
 735 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 736 {
 737         struct smu_feature *feature = &smu->smu_feature;
 738         int ret = 0;
 739         uint32_t feature_mask[2];
 740
 741         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 742                 goto failed;
 743
 744         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 745
 746         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 747                                           feature_mask[1], NULL);
 748         if (ret)
 749                 goto failed;
 750
 751         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 752                                           feature_mask[0], NULL);
 753         if (ret)
 754                 goto failed;
 755
 756 failed:
 757         return ret;
 758 }
 759
 760 int smu_v11_0_system_features_control(struct smu_context *smu,
 761                                              bool en)
 762 {
 763         struct smu_feature *feature = &smu->smu_feature;
 764         uint32_t feature_mask[2];
 765         int ret = 0;
 766
 767         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 768                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 769         if (ret)
 770                 return ret;
 771
 772         bitmap_zero(feature->enabled, feature->feature_num);
 773         bitmap_zero(feature->supported, feature->feature_num);
 774
 775         if (en) {
 776                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 777                 if (ret)
 778                         return ret;
 779
 780                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 781                             feature->feature_num);
 782                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 783                             feature->feature_num);
 784         }
 785
 786         return ret;
 787 }
 788
 789 int smu_v11_0_notify_display_change(struct smu_context *smu)
 790 {
 791         int ret = 0;
 792
 793         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 794             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 795                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 796
 797         return ret;
 798 }
 799
 800 static int
 801 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 802                                     enum smu_clk_type clock_select)
 803 {
 804         int ret = 0;
 805         int clk_id;
 806
 807         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 808             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 809                 return 0;
 810
 811         clk_id = smu_cmn_to_asic_specific_index(smu,
 812                                                 CMN2ASIC_MAPPING_CLK,
 813                                                 clock_select);
 814         if (clk_id < 0)
 815                 return -EINVAL;
 816
 817         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 818                                           clk_id << 16, clock);
 819         if (ret) {
 820                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 821                 return ret;
 822         }
 823
 824         if (*clock != 0)
 825                 return 0;
 826
 827         /* if DC limit is zero, return AC limit */
 828         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 829                                           clk_id << 16, clock);
 830         if (ret) {
 831                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 832                 return ret;
 833         }
 834
 835         return 0;
 836 }
 837
 838 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 839 {
 840         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 841                         smu->smu_table.max_sustainable_clocks;
 842         int ret = 0;
 843
 844         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 845         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 846         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 847         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 848         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 849         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 850
 851         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 852                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 853                                                           &(max_sustainable_clocks->uclock),
 854                                                           SMU_UCLK);
 855                 if (ret) {
 856                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 857                                __func__);
 858                         return ret;
 859                 }
 860         }
 861
 862         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 863                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 864                                                           &(max_sustainable_clocks->soc_clock),
 865                                                           SMU_SOCCLK);
 866                 if (ret) {
 867                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 868                                __func__);
 869                         return ret;
 870                 }
 871         }
 872
 873         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 874                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 875                                                           &(max_sustainable_clocks->dcef_clock),
 876                                                           SMU_DCEFCLK);
 877                 if (ret) {
 878                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 879                                __func__);
 880                         return ret;
 881                 }
 882
 883                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 884                                                           &(max_sustainable_clocks->display_clock),
 885                                                           SMU_DISPCLK);
 886                 if (ret) {
 887                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 888                                __func__);
 889                         return ret;
 890                 }
 891                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 892                                                           &(max_sustainable_clocks->phy_clock),
 893                                                           SMU_PHYCLK);
 894                 if (ret) {
 895                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 896                                __func__);
 897                         return ret;
 898                 }
 899                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 900                                                           &(max_sustainable_clocks->pixel_clock),
 901                                                           SMU_PIXCLK);
 902                 if (ret) {
 903                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 904                                __func__);
 905                         return ret;
 906                 }
 907         }
 908
 909         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 910                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 911
 912         return 0;
 913 }
 914
 915 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 916                                       uint32_t *power_limit)
 917 {
 918         int power_src;
 919         int ret = 0;
 920
 921         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 922                 return -EINVAL;
 923
 924         power_src = smu_cmn_to_asic_specific_index(smu,
 925                                         CMN2ASIC_MAPPING_PWR,
 926                                         smu->adev->pm.ac_power ?
 927                                         SMU_POWER_SOURCE_AC :
 928                                         SMU_POWER_SOURCE_DC);
 929         if (power_src < 0)
 930                 return -EINVAL;
 931
 932         ret = smu_cmn_send_smc_msg_with_param(smu,
 933                                           SMU_MSG_GetPptLimit,
 934                                           power_src << 16,
 935                                           power_limit);
 936         if (ret)
 937                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 938
 939         return ret;
 940 }
 941
 942 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 943 {
 944         int ret = 0;
 945
 946         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 947                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 948                 return -EOPNOTSUPP;
 949         }
 950
 951         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 952         if (ret) {
 953                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 954                 return ret;
 955         }
 956
 957         smu->current_power_limit = n;
 958
 959         return 0;
 960 }
 961
 962 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
 963 {
 964         return smu_cmn_send_smc_msg(smu,
 965                                 SMU_MSG_ReenableAcDcInterrupt,
 966                                 NULL);
 967 }
 968
 969 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
 970 {
 971         int ret = 0;
 972
 973         if (smu->dc_controlled_by_gpio &&
 974             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
 975                 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
 976
 977         return ret;
 978 }
 979
 980 void smu_v11_0_interrupt_work(struct smu_context *smu)
 981 {
 982         if (smu_v11_0_ack_ac_dc_interrupt(smu))
 983                 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
 984 }
 985
 986 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
 987 {
 988         int ret = 0;
 989
 990         if (smu->smu_table.thermal_controller_type) {
 991                 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 992                 if (ret)
 993                         return ret;
 994         }
 995
 996         /*
 997          * After init there might have been missed interrupts triggered
 998          * before driver registers for interrupt (Ex. AC/DC).
 999          */
1000         return smu_v11_0_process_pending_interrupt(smu);
1001 }
1002
1003 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1004 {
1005         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1006 }
1007
1008 static uint16_t convert_to_vddc(uint8_t vid)
1009 {
1010         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1011 }
1012
1013 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1014 {
1015         struct amdgpu_device *adev = smu->adev;
1016         uint32_t vdd = 0, val_vid = 0;
1017
1018         if (!value)
1019                 return -EINVAL;
1020         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1021                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1022                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1023
1024         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1025
1026         *value = vdd;
1027
1028         return 0;
1029
1030 }
1031
1032 int
1033 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1034                                         struct pp_display_clock_request
1035                                         *clock_req)
1036 {
1037         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1038         int ret = 0;
1039         enum smu_clk_type clk_select = 0;
1040         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1041
1042         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1043                 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1044                 switch (clk_type) {
1045                 case amd_pp_dcef_clock:
1046                         clk_select = SMU_DCEFCLK;
1047                         break;
1048                 case amd_pp_disp_clock:
1049                         clk_select = SMU_DISPCLK;
1050                         break;
1051                 case amd_pp_pixel_clock:
1052                         clk_select = SMU_PIXCLK;
1053                         break;
1054                 case amd_pp_phy_clock:
1055                         clk_select = SMU_PHYCLK;
1056                         break;
1057                 case amd_pp_mem_clock:
1058                         clk_select = SMU_UCLK;
1059                         break;
1060                 default:
1061                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1062                         ret = -EINVAL;
1063                         break;
1064                 }
1065
1066                 if (ret)
1067                         goto failed;
1068
1069                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1070                         return 0;
1071
1072                 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1073
1074                 if(clk_select == SMU_UCLK)
1075                         smu->hard_min_uclk_req_from_dal = clk_freq;
1076         }
1077
1078 failed:
1079         return ret;
1080 }
1081
1082 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1083 {
1084         int ret = 0;
1085         struct amdgpu_device *adev = smu->adev;
1086
1087         switch (adev->asic_type) {
1088         case CHIP_NAVI10:
1089         case CHIP_NAVI14:
1090         case CHIP_NAVI12:
1091         case CHIP_SIENNA_CICHLID:
1092         case CHIP_NAVY_FLOUNDER:
1093         case CHIP_DIMGREY_CAVEFISH:
1094                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1095                         return 0;
1096                 if (enable)
1097                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1098                 else
1099                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1100                 break;
1101         default:
1102                 break;
1103         }
1104
1105         return ret;
1106 }
1107
1108 uint32_t
1109 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1110 {
1111         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1112                 return AMD_FAN_CTRL_MANUAL;
1113         else
1114                 return AMD_FAN_CTRL_AUTO;
1115 }
1116
1117 static int
1118 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1119 {
1120         int ret = 0;
1121
1122         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1123                 return 0;
1124
1125         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1126         if (ret)
1127                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1128                        __func__, (auto_fan_control ? "Start" : "Stop"));
1129
1130         return ret;
1131 }
1132
1133 static int
1134 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1135 {
1136         struct amdgpu_device *adev = smu->adev;
1137
1138         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1139                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1140                                    CG_FDO_CTRL2, TMIN, 0));
1141         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1142                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1143                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1144
1145         return 0;
1146 }
1147
1148 int
1149 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1150                                uint32_t mode)
1151 {
1152         int ret = 0;
1153
1154         switch (mode) {
1155         case AMD_FAN_CTRL_NONE:
1156                 ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
1157                 break;
1158         case AMD_FAN_CTRL_MANUAL:
1159                 ret = smu_v11_0_auto_fan_control(smu, 0);
1160                 break;
1161         case AMD_FAN_CTRL_AUTO:
1162                 ret = smu_v11_0_auto_fan_control(smu, 1);
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         if (ret) {
1169                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1170                 return -EINVAL;
1171         }
1172
1173         return ret;
1174 }
1175
1176 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1177                                        uint32_t speed)
1178 {
1179         struct amdgpu_device *adev = smu->adev;
1180         int ret;
1181         uint32_t tach_period, crystal_clock_freq;
1182
1183         if (!speed)
1184                 return -EINVAL;
1185
1186         ret = smu_v11_0_auto_fan_control(smu, 0);
1187         if (ret)
1188                 return ret;
1189
1190         /*
1191          * crystal_clock_freq div by 4 is required since the fan control
1192          * module refers to 25MHz
1193          */
1194
1195         crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
1196         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1197         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1198                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1199                                    CG_TACH_CTRL, TARGET_PERIOD,
1200                                    tach_period));
1201
1202         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1203
1204         return ret;
1205 }
1206
1207 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1208                                 uint32_t *speed)
1209 {
1210         struct amdgpu_device *adev = smu->adev;
1211         uint32_t tach_period, crystal_clock_freq;
1212         uint64_t tmp64;
1213
1214         tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1215                                     CG_TACH_CTRL, TARGET_PERIOD);
1216         if (!tach_period)
1217                 return -EINVAL;
1218
1219         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1220
1221         tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1222         do_div(tmp64, (tach_period * 8));
1223         *speed = (uint32_t)tmp64;
1224
1225         return 0;
1226 }
1227
1228 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1229                                      uint32_t pstate)
1230 {
1231         return smu_cmn_send_smc_msg_with_param(smu,
1232                                                SMU_MSG_SetXgmiMode,
1233                                                pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1234                                           NULL);
1235 }
1236
1237 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1238                                    struct amdgpu_irq_src *source,
1239                                    unsigned tyep,
1240                                    enum amdgpu_interrupt_state state)
1241 {
1242         struct smu_context *smu = &adev->smu;
1243         uint32_t low, high;
1244         uint32_t val = 0;
1245
1246         switch (state) {
1247         case AMDGPU_IRQ_STATE_DISABLE:
1248                 /* For THM irqs */
1249                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1250                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1251                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1252                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1253
1254                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1255
1256                 /* For MP1 SW irqs */
1257                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1258                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1259                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1260
1261                 break;
1262         case AMDGPU_IRQ_STATE_ENABLE:
1263                 /* For THM irqs */
1264                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1265                                 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1266                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1267                                 smu->thermal_range.software_shutdown_temp);
1268
1269                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1270                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1271                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1272                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1273                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1274                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1275                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1276                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1277                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1278
1279                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1280                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1281                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1282                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1283
1284                 /* For MP1 SW irqs */
1285                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1286                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1287                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1288                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1289
1290                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1291                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1292                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1293
1294                 break;
1295         default:
1296                 break;
1297         }
1298
1299         return 0;
1300 }
1301
1302 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1303 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1304
1305 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1306
1307 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1308                                  struct amdgpu_irq_src *source,
1309                                  struct amdgpu_iv_entry *entry)
1310 {
1311         struct smu_context *smu = &adev->smu;
1312         uint32_t client_id = entry->client_id;
1313         uint32_t src_id = entry->src_id;
1314         /*
1315          * ctxid is used to distinguish different
1316          * events for SMCToHost interrupt.
1317          */
1318         uint32_t ctxid = entry->src_data[0];
1319         uint32_t data;
1320
1321         if (client_id == SOC15_IH_CLIENTID_THM) {
1322                 switch (src_id) {
1323                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1324                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1325                         /*
1326                          * SW CTF just occurred.
1327                          * Try to do a graceful shutdown to prevent further damage.
1328                          */
1329                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1330                         orderly_poweroff(true);
1331                 break;
1332                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1333                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1334                 break;
1335                 default:
1336                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1337                                 src_id);
1338                 break;
1339                 }
1340         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1341                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1342                 /*
1343                  * HW CTF just occurred. Shutdown to prevent further damage.
1344                  */
1345                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1346                 orderly_poweroff(true);
1347         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1348                 if (src_id == 0xfe) {
1349                         /* ACK SMUToHost interrupt */
1350                         data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1351                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1352                         WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1353
1354                         switch (ctxid) {
1355                         case 0x3:
1356                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1357                                 schedule_work(&smu->interrupt_work);
1358                                 break;
1359                         case 0x4:
1360                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1361                                 schedule_work(&smu->interrupt_work);
1362                                 break;
1363                         case 0x7:
1364                                 /*
1365                                  * Increment the throttle interrupt counter
1366                                  */
1367                                 atomic64_inc(&smu->throttle_int_counter);
1368
1369                                 if (!atomic_read(&adev->throttling_logging_enabled))
1370                                         return 0;
1371
1372                                 if (__ratelimit(&adev->throttling_logging_rs))
1373                                         schedule_work(&smu->throttling_logging_work);
1374
1375                                 break;
1376                         }
1377                 }
1378         }
1379
1380         return 0;
1381 }
1382
1383 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1384 {
1385         .set = smu_v11_0_set_irq_state,
1386         .process = smu_v11_0_irq_process,
1387 };
1388
1389 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1390 {
1391         struct amdgpu_device *adev = smu->adev;
1392         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1393         int ret = 0;
1394
1395         irq_src->num_types = 1;
1396         irq_src->funcs = &smu_v11_0_irq_funcs;
1397
1398         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1399                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1400                                 irq_src);
1401         if (ret)
1402                 return ret;
1403
1404         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1405                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1406                                 irq_src);
1407         if (ret)
1408                 return ret;
1409
1410         /* Register CTF(GPIO_19) interrupt */
1411         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1412                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1413                                 irq_src);
1414         if (ret)
1415                 return ret;
1416
1417         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1418                                 0xfe,
1419                                 irq_src);
1420         if (ret)
1421                 return ret;
1422
1423         return ret;
1424 }
1425
1426 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1427                 struct pp_smu_nv_clock_table *max_clocks)
1428 {
1429         struct smu_table_context *table_context = &smu->smu_table;
1430         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1431
1432         if (!max_clocks || !table_context->max_sustainable_clocks)
1433                 return -EINVAL;
1434
1435         sustainable_clocks = table_context->max_sustainable_clocks;
1436
1437         max_clocks->dcfClockInKhz =
1438                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1439         max_clocks->displayClockInKhz =
1440                         (unsigned int) sustainable_clocks->display_clock * 1000;
1441         max_clocks->phyClockInKhz =
1442                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1443         max_clocks->pixelClockInKhz =
1444                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1445         max_clocks->uClockInKhz =
1446                         (unsigned int) sustainable_clocks->uclock * 1000;
1447         max_clocks->socClockInKhz =
1448                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1449         max_clocks->dscClockInKhz = 0;
1450         max_clocks->dppClockInKhz = 0;
1451         max_clocks->fabricClockInKhz = 0;
1452
1453         return 0;
1454 }
1455
1456 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1457 {
1458         return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1459 }
1460
1461 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1462 {
1463         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1464 }
1465
1466 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1467 {
1468         struct smu_baco_context *smu_baco = &smu->smu_baco;
1469
1470         if (!smu_baco->platform_support)
1471                 return false;
1472
1473         /* Arcturus does not support this bit mask */
1474         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1475            !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1476                 return false;
1477
1478         return true;
1479 }
1480
1481 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1482 {
1483         struct smu_baco_context *smu_baco = &smu->smu_baco;
1484         enum smu_baco_state baco_state;
1485
1486         mutex_lock(&smu_baco->mutex);
1487         baco_state = smu_baco->state;
1488         mutex_unlock(&smu_baco->mutex);
1489
1490         return baco_state;
1491 }
1492
1493 #define D3HOT_BACO_SEQUENCE 0
1494 #define D3HOT_BAMACO_SEQUENCE 2
1495
1496 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1497 {
1498         struct smu_baco_context *smu_baco = &smu->smu_baco;
1499         struct amdgpu_device *adev = smu->adev;
1500         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1501         uint32_t data;
1502         int ret = 0;
1503
1504         if (smu_v11_0_baco_get_state(smu) == state)
1505                 return 0;
1506
1507         mutex_lock(&smu_baco->mutex);
1508
1509         if (state == SMU_BACO_STATE_ENTER) {
1510                 switch (adev->asic_type) {
1511                 case CHIP_SIENNA_CICHLID:
1512                 case CHIP_NAVY_FLOUNDER:
1513                 case CHIP_DIMGREY_CAVEFISH:
1514                         if (amdgpu_runtime_pm == 2)
1515                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1516                                                                       SMU_MSG_EnterBaco,
1517                                                                       D3HOT_BAMACO_SEQUENCE,
1518                                                                       NULL);
1519                         else
1520                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1521                                                                       SMU_MSG_EnterBaco,
1522                                                                       D3HOT_BACO_SEQUENCE,
1523                                                                       NULL);
1524                         break;
1525                 default:
1526                         if (!ras || !ras->supported) {
1527                                 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1528                                 data |= 0x80000000;
1529                                 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1530
1531                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1532                         } else {
1533                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1534                         }
1535                         break;
1536                 }
1537
1538         } else {
1539                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1540                 if (ret)
1541                         goto out;
1542
1543                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1544                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1545                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1546         }
1547         if (ret)
1548                 goto out;
1549
1550         smu_baco->state = state;
1551 out:
1552         mutex_unlock(&smu_baco->mutex);
1553         return ret;
1554 }
1555
1556 int smu_v11_0_baco_enter(struct smu_context *smu)
1557 {
1558         struct amdgpu_device *adev = smu->adev;
1559         int ret = 0;
1560
1561         /* Arcturus does not need this audio workaround */
1562         if (adev->asic_type != CHIP_ARCTURUS) {
1563                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1564                 if (ret)
1565                         return ret;
1566         }
1567
1568         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1569         if (ret)
1570                 return ret;
1571
1572         msleep(10);
1573
1574         return ret;
1575 }
1576
1577 int smu_v11_0_baco_exit(struct smu_context *smu)
1578 {
1579         return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1580 }
1581
1582 int smu_v11_0_mode1_reset(struct smu_context *smu)
1583 {
1584         int ret = 0;
1585
1586         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1587         if (!ret)
1588                 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1589
1590         return ret;
1591 }
1592
1593 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1594                                                  uint32_t *min, uint32_t *max)
1595 {
1596         int ret = 0, clk_id = 0;
1597         uint32_t param = 0;
1598         uint32_t clock_limit;
1599
1600         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1601                 switch (clk_type) {
1602                 case SMU_MCLK:
1603                 case SMU_UCLK:
1604                         clock_limit = smu->smu_table.boot_values.uclk;
1605                         break;
1606                 case SMU_GFXCLK:
1607                 case SMU_SCLK:
1608                         clock_limit = smu->smu_table.boot_values.gfxclk;
1609                         break;
1610                 case SMU_SOCCLK:
1611                         clock_limit = smu->smu_table.boot_values.socclk;
1612                         break;
1613                 default:
1614                         clock_limit = 0;
1615                         break;
1616                 }
1617
1618                 /* clock in Mhz unit */
1619                 if (min)
1620                         *min = clock_limit / 100;
1621                 if (max)
1622                         *max = clock_limit / 100;
1623
1624                 return 0;
1625         }
1626
1627         clk_id = smu_cmn_to_asic_specific_index(smu,
1628                                                 CMN2ASIC_MAPPING_CLK,
1629                                                 clk_type);
1630         if (clk_id < 0) {
1631                 ret = -EINVAL;
1632                 goto failed;
1633         }
1634         param = (clk_id & 0xffff) << 16;
1635
1636         if (max) {
1637                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1638                 if (ret)
1639                         goto failed;
1640         }
1641
1642         if (min) {
1643                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1644                 if (ret)
1645                         goto failed;
1646         }
1647
1648 failed:
1649         return ret;
1650 }
1651
1652 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1653                                           enum smu_clk_type clk_type,
1654                                           uint32_t min,
1655                                           uint32_t max)
1656 {
1657         struct amdgpu_device *adev = smu->adev;
1658         int ret = 0, clk_id = 0;
1659         uint32_t param;
1660
1661         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1662                 return 0;
1663
1664         clk_id = smu_cmn_to_asic_specific_index(smu,
1665                                                 CMN2ASIC_MAPPING_CLK,
1666                                                 clk_type);
1667         if (clk_id < 0)
1668                 return clk_id;
1669
1670         if (clk_type == SMU_GFXCLK)
1671                 amdgpu_gfx_off_ctrl(adev, false);
1672
1673         if (max > 0) {
1674                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1675                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1676                                                   param, NULL);
1677                 if (ret)
1678                         goto out;
1679         }
1680
1681         if (min > 0) {
1682                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1683                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1684                                                   param, NULL);
1685                 if (ret)
1686                         goto out;
1687         }
1688
1689 out:
1690         if (clk_type == SMU_GFXCLK)
1691                 amdgpu_gfx_off_ctrl(adev, true);
1692
1693         return ret;
1694 }
1695
1696 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1697                                           enum smu_clk_type clk_type,
1698                                           uint32_t min,
1699                                           uint32_t max)
1700 {
1701         int ret = 0, clk_id = 0;
1702         uint32_t param;
1703
1704         if (min <= 0 && max <= 0)
1705                 return -EINVAL;
1706
1707         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1708                 return 0;
1709
1710         clk_id = smu_cmn_to_asic_specific_index(smu,
1711                                                 CMN2ASIC_MAPPING_CLK,
1712                                                 clk_type);
1713         if (clk_id < 0)
1714                 return clk_id;
1715
1716         if (max > 0) {
1717                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1718                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1719                                                   param, NULL);
1720                 if (ret)
1721                         return ret;
1722         }
1723
1724         if (min > 0) {
1725                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1726                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1727                                                   param, NULL);
1728                 if (ret)
1729                         return ret;
1730         }
1731
1732         return ret;
1733 }
1734
1735 int smu_v11_0_set_performance_level(struct smu_context *smu,
1736                                     enum amd_dpm_forced_level level)
1737 {
1738         struct smu_11_0_dpm_context *dpm_context =
1739                                 smu->smu_dpm.dpm_context;
1740         struct smu_11_0_dpm_table *gfx_table =
1741                                 &dpm_context->dpm_tables.gfx_table;
1742         struct smu_11_0_dpm_table *mem_table =
1743                                 &dpm_context->dpm_tables.uclk_table;
1744         struct smu_11_0_dpm_table *soc_table =
1745                                 &dpm_context->dpm_tables.soc_table;
1746         struct smu_umd_pstate_table *pstate_table =
1747                                 &smu->pstate_table;
1748         struct amdgpu_device *adev = smu->adev;
1749         uint32_t sclk_min = 0, sclk_max = 0;
1750         uint32_t mclk_min = 0, mclk_max = 0;
1751         uint32_t socclk_min = 0, socclk_max = 0;
1752         int ret = 0;
1753
1754         switch (level) {
1755         case AMD_DPM_FORCED_LEVEL_HIGH:
1756                 sclk_min = sclk_max = gfx_table->max;
1757                 mclk_min = mclk_max = mem_table->max;
1758                 socclk_min = socclk_max = soc_table->max;
1759                 break;
1760         case AMD_DPM_FORCED_LEVEL_LOW:
1761                 sclk_min = sclk_max = gfx_table->min;
1762                 mclk_min = mclk_max = mem_table->min;
1763                 socclk_min = socclk_max = soc_table->min;
1764                 break;
1765         case AMD_DPM_FORCED_LEVEL_AUTO:
1766                 sclk_min = gfx_table->min;
1767                 sclk_max = gfx_table->max;
1768                 mclk_min = mem_table->min;
1769                 mclk_max = mem_table->max;
1770                 socclk_min = soc_table->min;
1771                 socclk_max = soc_table->max;
1772                 break;
1773         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1774                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1775                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1776                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1777                 break;
1778         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1779                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1780                 break;
1781         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1782                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1783                 break;
1784         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1785                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1786                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1787                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1788                 break;
1789         case AMD_DPM_FORCED_LEVEL_MANUAL:
1790         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1791                 return 0;
1792         default:
1793                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1794                 return -EINVAL;
1795         }
1796
1797         /*
1798          * Separate MCLK and SOCCLK soft min/max settings are not allowed
1799          * on Arcturus.
1800          */
1801         if (adev->asic_type == CHIP_ARCTURUS) {
1802                 mclk_min = mclk_max = 0;
1803                 socclk_min = socclk_max = 0;
1804         }
1805
1806         if (sclk_min && sclk_max) {
1807                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1808                                                             SMU_GFXCLK,
1809                                                             sclk_min,
1810                                                             sclk_max);
1811                 if (ret)
1812                         return ret;
1813         }
1814
1815         if (mclk_min && mclk_max) {
1816                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1817                                                             SMU_MCLK,
1818                                                             mclk_min,
1819                                                             mclk_max);
1820                 if (ret)
1821                         return ret;
1822         }
1823
1824         if (socclk_min && socclk_max) {
1825                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1826                                                             SMU_SOCCLK,
1827                                                             socclk_min,
1828                                                             socclk_max);
1829                 if (ret)
1830                         return ret;
1831         }
1832
1833         return ret;
1834 }
1835
1836 int smu_v11_0_set_power_source(struct smu_context *smu,
1837                                enum smu_power_src_type power_src)
1838 {
1839         int pwr_source;
1840
1841         pwr_source = smu_cmn_to_asic_specific_index(smu,
1842                                                     CMN2ASIC_MAPPING_PWR,
1843                                                     (uint32_t)power_src);
1844         if (pwr_source < 0)
1845                 return -EINVAL;
1846
1847         return smu_cmn_send_smc_msg_with_param(smu,
1848                                         SMU_MSG_NotifyPowerSource,
1849                                         pwr_source,
1850                                         NULL);
1851 }
1852
1853 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1854                                     enum smu_clk_type clk_type,
1855                                     uint16_t level,
1856                                     uint32_t *value)
1857 {
1858         int ret = 0, clk_id = 0;
1859         uint32_t param;
1860
1861         if (!value)
1862                 return -EINVAL;
1863
1864         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1865                 return 0;
1866
1867         clk_id = smu_cmn_to_asic_specific_index(smu,
1868                                                 CMN2ASIC_MAPPING_CLK,
1869                                                 clk_type);
1870         if (clk_id < 0)
1871                 return clk_id;
1872
1873         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1874
1875         ret = smu_cmn_send_smc_msg_with_param(smu,
1876                                           SMU_MSG_GetDpmFreqByIndex,
1877                                           param,
1878                                           value);
1879         if (ret)
1880                 return ret;
1881
1882         /*
1883          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1884          * now, we un-support it
1885          */
1886         *value = *value & 0x7fffffff;
1887
1888         return ret;
1889 }
1890
1891 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1892                                   enum smu_clk_type clk_type,
1893                                   uint32_t *value)
1894 {
1895         return smu_v11_0_get_dpm_freq_by_index(smu,
1896                                                clk_type,
1897                                                0xff,
1898                                                value);
1899 }
1900
1901 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1902                                    enum smu_clk_type clk_type,
1903                                    struct smu_11_0_dpm_table *single_dpm_table)
1904 {
1905         int ret = 0;
1906         uint32_t clk;
1907         int i;
1908
1909         ret = smu_v11_0_get_dpm_level_count(smu,
1910                                             clk_type,
1911                                             &single_dpm_table->count);
1912         if (ret) {
1913                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1914                 return ret;
1915         }
1916
1917         for (i = 0; i < single_dpm_table->count; i++) {
1918                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1919                                                       clk_type,
1920                                                       i,
1921                                                       &clk);
1922                 if (ret) {
1923                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1924                         return ret;
1925                 }
1926
1927                 single_dpm_table->dpm_levels[i].value = clk;
1928                 single_dpm_table->dpm_levels[i].enabled = true;
1929
1930                 if (i == 0)
1931                         single_dpm_table->min = clk;
1932                 else if (i == single_dpm_table->count - 1)
1933                         single_dpm_table->max = clk;
1934         }
1935
1936         return 0;
1937 }
1938
1939 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1940                                   enum smu_clk_type clk_type,
1941                                   uint32_t *min_value,
1942                                   uint32_t *max_value)
1943 {
1944         uint32_t level_count = 0;
1945         int ret = 0;
1946
1947         if (!min_value && !max_value)
1948                 return -EINVAL;
1949
1950         if (min_value) {
1951                 /* by default, level 0 clock value as min value */
1952                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1953                                                       clk_type,
1954                                                       0,
1955                                                       min_value);
1956                 if (ret)
1957                         return ret;
1958         }
1959
1960         if (max_value) {
1961                 ret = smu_v11_0_get_dpm_level_count(smu,
1962                                                     clk_type,
1963                                                     &level_count);
1964                 if (ret)
1965                         return ret;
1966
1967                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1968                                                       clk_type,
1969                                                       level_count - 1,
1970                                                       max_value);
1971                 if (ret)
1972                         return ret;
1973         }
1974
1975         return ret;
1976 }
1977
1978 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1979 {
1980         struct amdgpu_device *adev = smu->adev;
1981
1982         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1983                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1984                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1985 }
1986
1987 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
1988 {
1989         uint32_t width_level;
1990
1991         width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
1992         if (width_level > LINK_WIDTH_MAX)
1993                 width_level = 0;
1994
1995         return link_width[width_level];
1996 }
1997
1998 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1999 {
2000         struct amdgpu_device *adev = smu->adev;
2001
2002         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2003                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2004                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2005 }
2006
2007 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2008 {
2009         uint32_t speed_level;
2010
2011         speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2012         if (speed_level > LINK_SPEED_MAX)
2013                 speed_level = 0;
2014
2015         return link_speed[speed_level];
2016 }
2017
2018 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2019 {
2020         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2021
2022         gpu_metrics->common_header.structure_size =
2023                                 sizeof(struct gpu_metrics_v1_0);
2024         gpu_metrics->common_header.format_revision = 1;
2025         gpu_metrics->common_header.content_revision = 0;
2026
2027         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2028 }
2029
2030 void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
2031 {
2032         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
2033
2034         gpu_metrics->common_header.structure_size =
2035                                 sizeof(struct gpu_metrics_v2_0);
2036         gpu_metrics->common_header.format_revision = 2;
2037         gpu_metrics->common_header.content_revision = 0;
2038
2039         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2040 }
2041
2042 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2043                               bool enablement)
2044 {
2045         int ret = 0;
2046
2047         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2048                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2049
2050         return ret;
2051 }
2052
2053 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2054                                  bool enablement)
2055 {
2056         struct amdgpu_device *adev = smu->adev;
2057         int ret = 0;
2058
2059         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2060                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2061                 if (ret) {
2062                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2063                         return ret;
2064                 }
2065         }
2066
2067         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2068                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2069                 if (ret) {
2070                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2071                         return ret;
2072                 }
2073         }
2074
2075         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2076                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2077                 if (ret) {
2078                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2079                         return ret;
2080                 }
2081         }
2082
2083         return ret;
2084 }