2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
68 #define SMU11_VOLTAGE_SCALE 4
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
82 int smu_v11_0_init_microcode(struct smu_context *smu)
84 struct amdgpu_device *adev = smu->adev;
85 const char *chip_name;
86 char fw_name[SMU_FW_NAME_LEN];
88 const struct smc_firmware_header_v1_0 *hdr;
89 const struct common_firmware_header *header;
90 struct amdgpu_firmware_info *ucode = NULL;
92 if (amdgpu_sriov_vf(adev) &&
93 ((adev->asic_type == CHIP_NAVI12) ||
94 (adev->asic_type == CHIP_SIENNA_CICHLID)))
97 switch (adev->asic_type) {
99 chip_name = "arcturus";
102 chip_name = "navi10";
105 chip_name = "navi14";
108 chip_name = "navi12";
110 case CHIP_SIENNA_CICHLID:
111 chip_name = "sienna_cichlid";
113 case CHIP_NAVY_FLOUNDER:
114 chip_name = "navy_flounder";
116 case CHIP_DIMGREY_CAVEFISH:
117 chip_name = "dimgrey_cavefish";
119 case CHIP_BEIGE_GOBY:
120 chip_name = "beige_goby";
123 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
127 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
129 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
132 err = amdgpu_ucode_validate(adev->pm.fw);
136 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
137 amdgpu_ucode_print_smc_hdr(&hdr->header);
138 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
140 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
141 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
142 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
143 ucode->fw = adev->pm.fw;
144 header = (const struct common_firmware_header *)ucode->fw->data;
145 adev->firmware.fw_size +=
146 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
151 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
153 release_firmware(adev->pm.fw);
159 void smu_v11_0_fini_microcode(struct smu_context *smu)
161 struct amdgpu_device *adev = smu->adev;
163 release_firmware(adev->pm.fw);
165 adev->pm.fw_version = 0;
168 int smu_v11_0_load_microcode(struct smu_context *smu)
170 struct amdgpu_device *adev = smu->adev;
172 const struct smc_firmware_header_v1_0 *hdr;
173 uint32_t addr_start = MP1_SRAM;
175 uint32_t smc_fw_size;
176 uint32_t mp1_fw_flags;
178 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
179 src = (const uint32_t *)(adev->pm.fw->data +
180 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
181 smc_fw_size = hdr->header.ucode_size_bytes;
183 for (i = 1; i < smc_fw_size/4 - 1; i++) {
184 WREG32_PCIE(addr_start, src[i]);
188 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
189 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
190 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
191 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
193 for (i = 0; i < adev->usec_timeout; i++) {
194 mp1_fw_flags = RREG32_PCIE(MP1_Public |
195 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
196 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
197 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
202 if (i == adev->usec_timeout)
208 int smu_v11_0_check_fw_status(struct smu_context *smu)
210 struct amdgpu_device *adev = smu->adev;
211 uint32_t mp1_fw_flags;
213 mp1_fw_flags = RREG32_PCIE(MP1_Public |
214 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
216 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
217 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
223 int smu_v11_0_check_fw_version(struct smu_context *smu)
225 struct amdgpu_device *adev = smu->adev;
226 uint32_t if_version = 0xff, smu_version = 0xff;
228 uint8_t smu_minor, smu_debug;
231 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
235 smu_major = (smu_version >> 16) & 0xffff;
236 smu_minor = (smu_version >> 8) & 0xff;
237 smu_debug = (smu_version >> 0) & 0xff;
239 adev->pm.fw_version = smu_version;
241 switch (smu->adev->asic_type) {
243 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
246 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
249 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
252 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
254 case CHIP_SIENNA_CICHLID:
255 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
257 case CHIP_NAVY_FLOUNDER:
258 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
261 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
263 case CHIP_DIMGREY_CAVEFISH:
264 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
266 case CHIP_BEIGE_GOBY:
267 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
270 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
271 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
276 * 1. if_version mismatch is not critical as our fw is designed
277 * to be backward compatible.
278 * 2. New fw usually brings some optimizations. But that's visible
279 * only on the paired driver.
280 * Considering above, we just leave user a warning message instead
281 * of halt driver loading.
283 if (if_version != smu->smc_driver_if_version) {
284 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
285 "smu fw version = 0x%08x (%d.%d.%d)\n",
286 smu->smc_driver_if_version, if_version,
287 smu_version, smu_major, smu_minor, smu_debug);
288 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
294 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
296 struct amdgpu_device *adev = smu->adev;
297 uint32_t ppt_offset_bytes;
298 const struct smc_firmware_header_v2_0 *v2;
300 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
302 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
303 *size = le32_to_cpu(v2->ppt_size_bytes);
304 *table = (uint8_t *)v2 + ppt_offset_bytes;
309 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
310 uint32_t *size, uint32_t pptable_id)
312 struct amdgpu_device *adev = smu->adev;
313 const struct smc_firmware_header_v2_1 *v2_1;
314 struct smc_soft_pptable_entry *entries;
315 uint32_t pptable_count = 0;
318 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
319 entries = (struct smc_soft_pptable_entry *)
320 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
321 pptable_count = le32_to_cpu(v2_1->pptable_count);
322 for (i = 0; i < pptable_count; i++) {
323 if (le32_to_cpu(entries[i].id) == pptable_id) {
324 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
325 *size = le32_to_cpu(entries[i].ppt_size_bytes);
330 if (i == pptable_count)
336 int smu_v11_0_setup_pptable(struct smu_context *smu)
338 struct amdgpu_device *adev = smu->adev;
339 const struct smc_firmware_header_v1_0 *hdr;
342 uint16_t atom_table_size;
345 uint16_t version_major, version_minor;
347 if (!amdgpu_sriov_vf(adev)) {
348 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
349 version_major = le16_to_cpu(hdr->header.header_version_major);
350 version_minor = le16_to_cpu(hdr->header.header_version_minor);
351 if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
352 adev->asic_type == CHIP_BEIGE_GOBY) {
353 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
354 switch (version_minor) {
356 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
359 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
360 smu->smu_table.boot_values.pp_table_id);
372 dev_info(adev->dev, "use vbios provided pptable\n");
373 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
376 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
380 size = atom_table_size;
383 if (!smu->smu_table.power_play_table)
384 smu->smu_table.power_play_table = table;
385 if (!smu->smu_table.power_play_table_size)
386 smu->smu_table.power_play_table_size = size;
391 int smu_v11_0_init_smc_tables(struct smu_context *smu)
393 struct smu_table_context *smu_table = &smu->smu_table;
394 struct smu_table *tables = smu_table->tables;
397 smu_table->driver_pptable =
398 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
399 if (!smu_table->driver_pptable) {
404 smu_table->max_sustainable_clocks =
405 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
406 if (!smu_table->max_sustainable_clocks) {
411 /* Arcturus does not support OVERDRIVE */
412 if (tables[SMU_TABLE_OVERDRIVE].size) {
413 smu_table->overdrive_table =
414 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
415 if (!smu_table->overdrive_table) {
420 smu_table->boot_overdrive_table =
421 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
422 if (!smu_table->boot_overdrive_table) {
431 kfree(smu_table->overdrive_table);
433 kfree(smu_table->max_sustainable_clocks);
435 kfree(smu_table->driver_pptable);
440 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
442 struct smu_table_context *smu_table = &smu->smu_table;
443 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
445 kfree(smu_table->gpu_metrics_table);
446 kfree(smu_table->boot_overdrive_table);
447 kfree(smu_table->overdrive_table);
448 kfree(smu_table->max_sustainable_clocks);
449 kfree(smu_table->driver_pptable);
450 kfree(smu_table->clocks_table);
451 smu_table->gpu_metrics_table = NULL;
452 smu_table->boot_overdrive_table = NULL;
453 smu_table->overdrive_table = NULL;
454 smu_table->max_sustainable_clocks = NULL;
455 smu_table->driver_pptable = NULL;
456 smu_table->clocks_table = NULL;
457 kfree(smu_table->hardcode_pptable);
458 smu_table->hardcode_pptable = NULL;
460 kfree(smu_table->metrics_table);
461 kfree(smu_table->watermarks_table);
462 smu_table->metrics_table = NULL;
463 smu_table->watermarks_table = NULL;
464 smu_table->metrics_time = 0;
466 kfree(smu_dpm->dpm_context);
467 kfree(smu_dpm->golden_dpm_context);
468 kfree(smu_dpm->dpm_current_power_state);
469 kfree(smu_dpm->dpm_request_power_state);
470 smu_dpm->dpm_context = NULL;
471 smu_dpm->golden_dpm_context = NULL;
472 smu_dpm->dpm_context_size = 0;
473 smu_dpm->dpm_current_power_state = NULL;
474 smu_dpm->dpm_request_power_state = NULL;
479 int smu_v11_0_init_power(struct smu_context *smu)
481 struct smu_power_context *smu_power = &smu->smu_power;
482 size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
483 sizeof(struct smu_11_5_power_context) :
484 sizeof(struct smu_11_0_power_context);
486 smu_power->power_context = kzalloc(size, GFP_KERNEL);
487 if (!smu_power->power_context)
489 smu_power->power_context_size = size;
494 int smu_v11_0_fini_power(struct smu_context *smu)
496 struct smu_power_context *smu_power = &smu->smu_power;
498 kfree(smu_power->power_context);
499 smu_power->power_context = NULL;
500 smu_power->power_context_size = 0;
505 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
510 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
511 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
514 input.clk_id = clk_id;
515 input.syspll_id = syspll_id;
516 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
517 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
520 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
525 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
526 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
531 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
536 struct atom_common_table_header *header;
537 struct atom_firmware_info_v3_3 *v_3_3;
538 struct atom_firmware_info_v3_1 *v_3_1;
540 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
543 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
544 (uint8_t **)&header);
548 if (header->format_revision != 3) {
549 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
553 switch (header->content_revision) {
557 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
558 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
559 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
560 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
561 smu->smu_table.boot_values.socclk = 0;
562 smu->smu_table.boot_values.dcefclk = 0;
563 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
564 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
565 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
566 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
567 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
568 smu->smu_table.boot_values.pp_table_id = 0;
569 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
574 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
575 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
576 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
577 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
578 smu->smu_table.boot_values.socclk = 0;
579 smu->smu_table.boot_values.dcefclk = 0;
580 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
581 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
582 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
583 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
584 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
585 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
586 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
589 smu->smu_table.boot_values.format_revision = header->format_revision;
590 smu->smu_table.boot_values.content_revision = header->content_revision;
592 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
593 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
595 &smu->smu_table.boot_values.socclk);
597 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
598 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
600 &smu->smu_table.boot_values.dcefclk);
602 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
603 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
605 &smu->smu_table.boot_values.eclk);
607 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
608 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
610 &smu->smu_table.boot_values.vclk);
612 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
613 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
615 &smu->smu_table.boot_values.dclk);
617 if ((smu->smu_table.boot_values.format_revision == 3) &&
618 (smu->smu_table.boot_values.content_revision >= 2))
619 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
620 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
621 (uint8_t)SMU11_SYSPLL1_2_ID,
622 &smu->smu_table.boot_values.fclk);
624 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
625 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
626 (uint8_t)SMU11_SYSPLL3_1_ID,
627 &smu->smu_table.boot_values.lclk);
632 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
634 struct smu_table_context *smu_table = &smu->smu_table;
635 struct smu_table *memory_pool = &smu_table->memory_pool;
638 uint32_t address_low, address_high;
640 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
643 address = (uintptr_t)memory_pool->cpu_addr;
644 address_high = (uint32_t)upper_32_bits(address);
645 address_low = (uint32_t)lower_32_bits(address);
647 ret = smu_cmn_send_smc_msg_with_param(smu,
648 SMU_MSG_SetSystemVirtualDramAddrHigh,
653 ret = smu_cmn_send_smc_msg_with_param(smu,
654 SMU_MSG_SetSystemVirtualDramAddrLow,
660 address = memory_pool->mc_address;
661 address_high = (uint32_t)upper_32_bits(address);
662 address_low = (uint32_t)lower_32_bits(address);
664 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
668 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
672 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
673 (uint32_t)memory_pool->size, NULL);
680 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
684 ret = smu_cmn_send_smc_msg_with_param(smu,
685 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
687 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
692 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
694 struct smu_table *driver_table = &smu->smu_table.driver_table;
697 if (driver_table->mc_address) {
698 ret = smu_cmn_send_smc_msg_with_param(smu,
699 SMU_MSG_SetDriverDramAddrHigh,
700 upper_32_bits(driver_table->mc_address),
703 ret = smu_cmn_send_smc_msg_with_param(smu,
704 SMU_MSG_SetDriverDramAddrLow,
705 lower_32_bits(driver_table->mc_address),
712 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
715 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
717 if (tool_table->mc_address) {
718 ret = smu_cmn_send_smc_msg_with_param(smu,
719 SMU_MSG_SetToolsDramAddrHigh,
720 upper_32_bits(tool_table->mc_address),
723 ret = smu_cmn_send_smc_msg_with_param(smu,
724 SMU_MSG_SetToolsDramAddrLow,
725 lower_32_bits(tool_table->mc_address),
732 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
734 struct amdgpu_device *adev = smu->adev;
736 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
737 * display num currently
739 if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
740 adev->asic_type <= CHIP_BEIGE_GOBY)
743 return smu_cmn_send_smc_msg_with_param(smu,
744 SMU_MSG_NumOfDisplays,
750 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
752 struct smu_feature *feature = &smu->smu_feature;
754 uint32_t feature_mask[2];
756 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
761 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
764 feature_mask[1], NULL);
768 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
769 feature_mask[0], NULL);
777 int smu_v11_0_system_features_control(struct smu_context *smu,
780 struct smu_feature *feature = &smu->smu_feature;
781 uint32_t feature_mask[2];
784 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
785 SMU_MSG_DisableAllSmuFeatures), NULL);
789 bitmap_zero(feature->enabled, feature->feature_num);
790 bitmap_zero(feature->supported, feature->feature_num);
793 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
797 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
798 feature->feature_num);
799 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
800 feature->feature_num);
806 int smu_v11_0_notify_display_change(struct smu_context *smu)
810 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
811 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
812 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
818 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
819 enum smu_clk_type clock_select)
824 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
825 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
828 clk_id = smu_cmn_to_asic_specific_index(smu,
829 CMN2ASIC_MAPPING_CLK,
834 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
835 clk_id << 16, clock);
837 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
844 /* if DC limit is zero, return AC limit */
845 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
846 clk_id << 16, clock);
848 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
855 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
857 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
858 smu->smu_table.max_sustainable_clocks;
861 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
862 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
863 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
864 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
865 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
866 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
868 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
869 ret = smu_v11_0_get_max_sustainable_clock(smu,
870 &(max_sustainable_clocks->uclock),
873 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
879 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
880 ret = smu_v11_0_get_max_sustainable_clock(smu,
881 &(max_sustainable_clocks->soc_clock),
884 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
890 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
891 ret = smu_v11_0_get_max_sustainable_clock(smu,
892 &(max_sustainable_clocks->dcef_clock),
895 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
900 ret = smu_v11_0_get_max_sustainable_clock(smu,
901 &(max_sustainable_clocks->display_clock),
904 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
908 ret = smu_v11_0_get_max_sustainable_clock(smu,
909 &(max_sustainable_clocks->phy_clock),
912 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
916 ret = smu_v11_0_get_max_sustainable_clock(smu,
917 &(max_sustainable_clocks->pixel_clock),
920 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
926 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
927 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
932 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
933 uint32_t *power_limit)
938 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
941 power_src = smu_cmn_to_asic_specific_index(smu,
942 CMN2ASIC_MAPPING_PWR,
943 smu->adev->pm.ac_power ?
944 SMU_POWER_SOURCE_AC :
945 SMU_POWER_SOURCE_DC);
950 * BIT 24-31: ControllerId (only PPT0 is supported for now)
951 * BIT 16-23: PowerSource
953 ret = smu_cmn_send_smc_msg_with_param(smu,
955 (0 << 24) | (power_src << 16),
958 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
963 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
968 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
969 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
973 power_src = smu_cmn_to_asic_specific_index(smu,
974 CMN2ASIC_MAPPING_PWR,
975 smu->adev->pm.ac_power ?
976 SMU_POWER_SOURCE_AC :
977 SMU_POWER_SOURCE_DC);
982 * BIT 24-31: ControllerId (only PPT0 is supported for now)
983 * BIT 16-23: PowerSource
984 * BIT 0-15: PowerLimit
988 n |= (power_src) << 16;
989 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
991 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
995 smu->current_power_limit = n;
1000 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1002 return smu_cmn_send_smc_msg(smu,
1003 SMU_MSG_ReenableAcDcInterrupt,
1007 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1011 if (smu->dc_controlled_by_gpio &&
1012 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1013 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1018 void smu_v11_0_interrupt_work(struct smu_context *smu)
1020 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1021 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1024 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1028 if (smu->smu_table.thermal_controller_type) {
1029 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1035 * After init there might have been missed interrupts triggered
1036 * before driver registers for interrupt (Ex. AC/DC).
1038 return smu_v11_0_process_pending_interrupt(smu);
1041 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1043 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1046 static uint16_t convert_to_vddc(uint8_t vid)
1048 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1051 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1053 struct amdgpu_device *adev = smu->adev;
1054 uint32_t vdd = 0, val_vid = 0;
1058 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1059 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1060 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1062 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1071 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1072 struct pp_display_clock_request
1075 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1077 enum smu_clk_type clk_select = 0;
1078 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1080 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1081 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1083 case amd_pp_dcef_clock:
1084 clk_select = SMU_DCEFCLK;
1086 case amd_pp_disp_clock:
1087 clk_select = SMU_DISPCLK;
1089 case amd_pp_pixel_clock:
1090 clk_select = SMU_PIXCLK;
1092 case amd_pp_phy_clock:
1093 clk_select = SMU_PHYCLK;
1095 case amd_pp_mem_clock:
1096 clk_select = SMU_UCLK;
1099 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1107 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1110 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1112 if(clk_select == SMU_UCLK)
1113 smu->hard_min_uclk_req_from_dal = clk_freq;
1120 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1123 struct amdgpu_device *adev = smu->adev;
1125 switch (adev->asic_type) {
1129 case CHIP_SIENNA_CICHLID:
1130 case CHIP_NAVY_FLOUNDER:
1131 case CHIP_DIMGREY_CAVEFISH:
1133 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1136 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1138 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1148 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1150 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1151 return AMD_FAN_CTRL_AUTO;
1153 return smu->user_dpm_profile.fan_mode;
1157 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1161 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1164 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1166 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1167 __func__, (auto_fan_control ? "Start" : "Stop"));
1173 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1175 struct amdgpu_device *adev = smu->adev;
1177 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1178 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1179 CG_FDO_CTRL2, TMIN, 0));
1180 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1181 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1182 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1188 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1190 struct amdgpu_device *adev = smu->adev;
1191 uint32_t duty100, duty;
1197 if (smu_v11_0_auto_fan_control(smu, 0))
1200 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1201 CG_FDO_CTRL1, FMAX_DUTY100);
1205 tmp64 = (uint64_t)speed * duty100;
1207 duty = (uint32_t)tmp64;
1209 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1210 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1211 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1213 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1217 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1223 case AMD_FAN_CTRL_NONE:
1224 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1226 case AMD_FAN_CTRL_MANUAL:
1227 ret = smu_v11_0_auto_fan_control(smu, 0);
1229 case AMD_FAN_CTRL_AUTO:
1230 ret = smu_v11_0_auto_fan_control(smu, 1);
1237 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1244 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1247 return smu_cmn_send_smc_msg_with_param(smu,
1248 SMU_MSG_SetXgmiMode,
1249 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1253 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1254 struct amdgpu_irq_src *source,
1256 enum amdgpu_interrupt_state state)
1258 struct smu_context *smu = &adev->smu;
1263 case AMDGPU_IRQ_STATE_DISABLE:
1265 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1266 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1267 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1268 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1270 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1272 /* For MP1 SW irqs */
1273 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1274 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1275 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1278 case AMDGPU_IRQ_STATE_ENABLE:
1280 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1281 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1282 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1283 smu->thermal_range.software_shutdown_temp);
1285 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1286 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1287 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1288 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1289 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1290 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1291 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1292 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1293 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1295 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1296 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1297 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1298 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1300 /* For MP1 SW irqs */
1301 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1302 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1303 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1304 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1306 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1307 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1308 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1318 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1319 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1321 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1323 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1324 struct amdgpu_irq_src *source,
1325 struct amdgpu_iv_entry *entry)
1327 struct smu_context *smu = &adev->smu;
1328 uint32_t client_id = entry->client_id;
1329 uint32_t src_id = entry->src_id;
1331 * ctxid is used to distinguish different
1332 * events for SMCToHost interrupt.
1334 uint32_t ctxid = entry->src_data[0];
1337 if (client_id == SOC15_IH_CLIENTID_THM) {
1339 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1340 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1342 * SW CTF just occurred.
1343 * Try to do a graceful shutdown to prevent further damage.
1345 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1346 orderly_poweroff(true);
1348 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1349 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1352 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1356 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1357 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1359 * HW CTF just occurred. Shutdown to prevent further damage.
1361 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1362 orderly_poweroff(true);
1363 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1364 if (src_id == 0xfe) {
1365 /* ACK SMUToHost interrupt */
1366 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1367 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1368 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1372 dev_dbg(adev->dev, "Switched to AC mode!\n");
1373 schedule_work(&smu->interrupt_work);
1376 dev_dbg(adev->dev, "Switched to DC mode!\n");
1377 schedule_work(&smu->interrupt_work);
1381 * Increment the throttle interrupt counter
1383 atomic64_inc(&smu->throttle_int_counter);
1385 if (!atomic_read(&adev->throttling_logging_enabled))
1388 if (__ratelimit(&adev->throttling_logging_rs))
1389 schedule_work(&smu->throttling_logging_work);
1399 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1401 .set = smu_v11_0_set_irq_state,
1402 .process = smu_v11_0_irq_process,
1405 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1407 struct amdgpu_device *adev = smu->adev;
1408 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1411 irq_src->num_types = 1;
1412 irq_src->funcs = &smu_v11_0_irq_funcs;
1414 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1415 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1420 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1421 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1426 /* Register CTF(GPIO_19) interrupt */
1427 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1428 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1433 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1442 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1443 struct pp_smu_nv_clock_table *max_clocks)
1445 struct smu_table_context *table_context = &smu->smu_table;
1446 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1448 if (!max_clocks || !table_context->max_sustainable_clocks)
1451 sustainable_clocks = table_context->max_sustainable_clocks;
1453 max_clocks->dcfClockInKhz =
1454 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1455 max_clocks->displayClockInKhz =
1456 (unsigned int) sustainable_clocks->display_clock * 1000;
1457 max_clocks->phyClockInKhz =
1458 (unsigned int) sustainable_clocks->phy_clock * 1000;
1459 max_clocks->pixelClockInKhz =
1460 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1461 max_clocks->uClockInKhz =
1462 (unsigned int) sustainable_clocks->uclock * 1000;
1463 max_clocks->socClockInKhz =
1464 (unsigned int) sustainable_clocks->soc_clock * 1000;
1465 max_clocks->dscClockInKhz = 0;
1466 max_clocks->dppClockInKhz = 0;
1467 max_clocks->fabricClockInKhz = 0;
1472 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1474 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1477 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1479 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1482 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1484 struct smu_baco_context *smu_baco = &smu->smu_baco;
1486 if (!smu_baco->platform_support)
1489 /* Arcturus does not support this bit mask */
1490 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1491 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1497 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1499 struct smu_baco_context *smu_baco = &smu->smu_baco;
1500 enum smu_baco_state baco_state;
1502 mutex_lock(&smu_baco->mutex);
1503 baco_state = smu_baco->state;
1504 mutex_unlock(&smu_baco->mutex);
1509 #define D3HOT_BACO_SEQUENCE 0
1510 #define D3HOT_BAMACO_SEQUENCE 2
1512 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1514 struct smu_baco_context *smu_baco = &smu->smu_baco;
1515 struct amdgpu_device *adev = smu->adev;
1516 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1520 if (smu_v11_0_baco_get_state(smu) == state)
1523 mutex_lock(&smu_baco->mutex);
1525 if (state == SMU_BACO_STATE_ENTER) {
1526 switch (adev->asic_type) {
1527 case CHIP_SIENNA_CICHLID:
1528 case CHIP_NAVY_FLOUNDER:
1529 case CHIP_DIMGREY_CAVEFISH:
1530 if (amdgpu_runtime_pm == 2)
1531 ret = smu_cmn_send_smc_msg_with_param(smu,
1533 D3HOT_BAMACO_SEQUENCE,
1536 ret = smu_cmn_send_smc_msg_with_param(smu,
1538 D3HOT_BACO_SEQUENCE,
1542 if (!ras || !adev->ras_enabled ||
1543 adev->gmc.xgmi.pending_reset) {
1544 if (adev->asic_type == CHIP_ARCTURUS) {
1545 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1547 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1549 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1551 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1554 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1556 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1562 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1566 /* clear vbios scratch 6 and 7 for coming asic reinit */
1567 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1568 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1573 smu_baco->state = state;
1575 mutex_unlock(&smu_baco->mutex);
1579 int smu_v11_0_baco_enter(struct smu_context *smu)
1581 struct amdgpu_device *adev = smu->adev;
1584 /* Arcturus does not need this audio workaround */
1585 if (adev->asic_type != CHIP_ARCTURUS) {
1586 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1591 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1600 int smu_v11_0_baco_exit(struct smu_context *smu)
1602 return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1605 int smu_v11_0_mode1_reset(struct smu_context *smu)
1609 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1611 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1616 int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
1620 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1626 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1627 uint32_t *min, uint32_t *max)
1629 int ret = 0, clk_id = 0;
1631 uint32_t clock_limit;
1633 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1637 clock_limit = smu->smu_table.boot_values.uclk;
1641 clock_limit = smu->smu_table.boot_values.gfxclk;
1644 clock_limit = smu->smu_table.boot_values.socclk;
1651 /* clock in Mhz unit */
1653 *min = clock_limit / 100;
1655 *max = clock_limit / 100;
1660 clk_id = smu_cmn_to_asic_specific_index(smu,
1661 CMN2ASIC_MAPPING_CLK,
1667 param = (clk_id & 0xffff) << 16;
1670 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1676 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1685 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1686 enum smu_clk_type clk_type,
1690 struct amdgpu_device *adev = smu->adev;
1691 int ret = 0, clk_id = 0;
1694 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1697 clk_id = smu_cmn_to_asic_specific_index(smu,
1698 CMN2ASIC_MAPPING_CLK,
1703 if (clk_type == SMU_GFXCLK)
1704 amdgpu_gfx_off_ctrl(adev, false);
1707 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1708 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1715 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1716 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1723 if (clk_type == SMU_GFXCLK)
1724 amdgpu_gfx_off_ctrl(adev, true);
1729 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1730 enum smu_clk_type clk_type,
1734 int ret = 0, clk_id = 0;
1737 if (min <= 0 && max <= 0)
1740 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1743 clk_id = smu_cmn_to_asic_specific_index(smu,
1744 CMN2ASIC_MAPPING_CLK,
1750 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1751 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1758 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1759 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1768 int smu_v11_0_set_performance_level(struct smu_context *smu,
1769 enum amd_dpm_forced_level level)
1771 struct smu_11_0_dpm_context *dpm_context =
1772 smu->smu_dpm.dpm_context;
1773 struct smu_11_0_dpm_table *gfx_table =
1774 &dpm_context->dpm_tables.gfx_table;
1775 struct smu_11_0_dpm_table *mem_table =
1776 &dpm_context->dpm_tables.uclk_table;
1777 struct smu_11_0_dpm_table *soc_table =
1778 &dpm_context->dpm_tables.soc_table;
1779 struct smu_umd_pstate_table *pstate_table =
1781 struct amdgpu_device *adev = smu->adev;
1782 uint32_t sclk_min = 0, sclk_max = 0;
1783 uint32_t mclk_min = 0, mclk_max = 0;
1784 uint32_t socclk_min = 0, socclk_max = 0;
1788 case AMD_DPM_FORCED_LEVEL_HIGH:
1789 sclk_min = sclk_max = gfx_table->max;
1790 mclk_min = mclk_max = mem_table->max;
1791 socclk_min = socclk_max = soc_table->max;
1793 case AMD_DPM_FORCED_LEVEL_LOW:
1794 sclk_min = sclk_max = gfx_table->min;
1795 mclk_min = mclk_max = mem_table->min;
1796 socclk_min = socclk_max = soc_table->min;
1798 case AMD_DPM_FORCED_LEVEL_AUTO:
1799 sclk_min = gfx_table->min;
1800 sclk_max = gfx_table->max;
1801 mclk_min = mem_table->min;
1802 mclk_max = mem_table->max;
1803 socclk_min = soc_table->min;
1804 socclk_max = soc_table->max;
1806 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1807 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1808 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1809 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1811 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1812 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1814 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1815 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1817 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1818 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1819 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1820 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1822 case AMD_DPM_FORCED_LEVEL_MANUAL:
1823 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1826 dev_err(adev->dev, "Invalid performance level %d\n", level);
1831 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1834 if (adev->asic_type == CHIP_ARCTURUS) {
1835 mclk_min = mclk_max = 0;
1836 socclk_min = socclk_max = 0;
1839 if (sclk_min && sclk_max) {
1840 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1848 if (mclk_min && mclk_max) {
1849 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1857 if (socclk_min && socclk_max) {
1858 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1869 int smu_v11_0_set_power_source(struct smu_context *smu,
1870 enum smu_power_src_type power_src)
1874 pwr_source = smu_cmn_to_asic_specific_index(smu,
1875 CMN2ASIC_MAPPING_PWR,
1876 (uint32_t)power_src);
1880 return smu_cmn_send_smc_msg_with_param(smu,
1881 SMU_MSG_NotifyPowerSource,
1886 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1887 enum smu_clk_type clk_type,
1891 int ret = 0, clk_id = 0;
1897 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1900 clk_id = smu_cmn_to_asic_specific_index(smu,
1901 CMN2ASIC_MAPPING_CLK,
1906 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1908 ret = smu_cmn_send_smc_msg_with_param(smu,
1909 SMU_MSG_GetDpmFreqByIndex,
1916 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1917 * now, we un-support it
1919 *value = *value & 0x7fffffff;
1924 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1925 enum smu_clk_type clk_type,
1928 return smu_v11_0_get_dpm_freq_by_index(smu,
1934 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1935 enum smu_clk_type clk_type,
1936 struct smu_11_0_dpm_table *single_dpm_table)
1942 ret = smu_v11_0_get_dpm_level_count(smu,
1944 &single_dpm_table->count);
1946 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1950 for (i = 0; i < single_dpm_table->count; i++) {
1951 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1956 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1960 single_dpm_table->dpm_levels[i].value = clk;
1961 single_dpm_table->dpm_levels[i].enabled = true;
1964 single_dpm_table->min = clk;
1965 else if (i == single_dpm_table->count - 1)
1966 single_dpm_table->max = clk;
1972 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1973 enum smu_clk_type clk_type,
1974 uint32_t *min_value,
1975 uint32_t *max_value)
1977 uint32_t level_count = 0;
1980 if (!min_value && !max_value)
1984 /* by default, level 0 clock value as min value */
1985 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1994 ret = smu_v11_0_get_dpm_level_count(smu,
2000 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2011 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2013 struct amdgpu_device *adev = smu->adev;
2015 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2016 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2017 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2020 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2022 uint32_t width_level;
2024 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2025 if (width_level > LINK_WIDTH_MAX)
2028 return link_width[width_level];
2031 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2033 struct amdgpu_device *adev = smu->adev;
2035 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2036 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2037 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2040 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2042 uint32_t speed_level;
2044 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2045 if (speed_level > LINK_SPEED_MAX)
2048 return link_speed[speed_level];
2051 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2056 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2057 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2062 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2065 struct amdgpu_device *adev = smu->adev;
2068 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2069 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2071 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2076 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2077 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2079 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2084 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2085 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2087 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2092 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2093 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2095 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2100 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2101 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2103 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");