2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
68 #define SMU11_VOLTAGE_SCALE 4
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
82 int smu_v11_0_init_microcode(struct smu_context *smu)
84 struct amdgpu_device *adev = smu->adev;
85 const char *chip_name;
86 char fw_name[SMU_FW_NAME_LEN];
88 const struct smc_firmware_header_v1_0 *hdr;
89 const struct common_firmware_header *header;
90 struct amdgpu_firmware_info *ucode = NULL;
92 if (amdgpu_sriov_vf(adev) &&
93 ((adev->asic_type == CHIP_NAVI12) ||
94 (adev->asic_type == CHIP_SIENNA_CICHLID)))
97 switch (adev->asic_type) {
99 chip_name = "arcturus";
102 chip_name = "navi10";
105 chip_name = "navi14";
108 chip_name = "navi12";
110 case CHIP_SIENNA_CICHLID:
111 chip_name = "sienna_cichlid";
113 case CHIP_NAVY_FLOUNDER:
114 chip_name = "navy_flounder";
116 case CHIP_DIMGREY_CAVEFISH:
117 chip_name = "dimgrey_cavefish";
119 case CHIP_BEIGE_GOBY:
120 chip_name = "beige_goby";
123 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
127 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
129 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
132 err = amdgpu_ucode_validate(adev->pm.fw);
136 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
137 amdgpu_ucode_print_smc_hdr(&hdr->header);
138 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
140 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
141 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
142 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
143 ucode->fw = adev->pm.fw;
144 header = (const struct common_firmware_header *)ucode->fw->data;
145 adev->firmware.fw_size +=
146 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
151 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
153 release_firmware(adev->pm.fw);
159 void smu_v11_0_fini_microcode(struct smu_context *smu)
161 struct amdgpu_device *adev = smu->adev;
163 release_firmware(adev->pm.fw);
165 adev->pm.fw_version = 0;
168 int smu_v11_0_load_microcode(struct smu_context *smu)
170 struct amdgpu_device *adev = smu->adev;
172 const struct smc_firmware_header_v1_0 *hdr;
173 uint32_t addr_start = MP1_SRAM;
175 uint32_t smc_fw_size;
176 uint32_t mp1_fw_flags;
178 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
179 src = (const uint32_t *)(adev->pm.fw->data +
180 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
181 smc_fw_size = hdr->header.ucode_size_bytes;
183 for (i = 1; i < smc_fw_size/4 - 1; i++) {
184 WREG32_PCIE(addr_start, src[i]);
188 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
189 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
190 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
191 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
193 for (i = 0; i < adev->usec_timeout; i++) {
194 mp1_fw_flags = RREG32_PCIE(MP1_Public |
195 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
196 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
197 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
202 if (i == adev->usec_timeout)
208 int smu_v11_0_check_fw_status(struct smu_context *smu)
210 struct amdgpu_device *adev = smu->adev;
211 uint32_t mp1_fw_flags;
213 mp1_fw_flags = RREG32_PCIE(MP1_Public |
214 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
216 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
217 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
223 int smu_v11_0_check_fw_version(struct smu_context *smu)
225 struct amdgpu_device *adev = smu->adev;
226 uint32_t if_version = 0xff, smu_version = 0xff;
228 uint8_t smu_minor, smu_debug;
231 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
235 smu_major = (smu_version >> 16) & 0xffff;
236 smu_minor = (smu_version >> 8) & 0xff;
237 smu_debug = (smu_version >> 0) & 0xff;
239 adev->pm.fw_version = smu_version;
241 switch (smu->adev->asic_type) {
243 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
246 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
249 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
252 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
254 case CHIP_SIENNA_CICHLID:
255 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
257 case CHIP_NAVY_FLOUNDER:
258 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
261 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
263 case CHIP_DIMGREY_CAVEFISH:
264 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
266 case CHIP_BEIGE_GOBY:
267 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
269 case CHIP_CYAN_SKILLFISH:
270 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
273 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
274 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
279 * 1. if_version mismatch is not critical as our fw is designed
280 * to be backward compatible.
281 * 2. New fw usually brings some optimizations. But that's visible
282 * only on the paired driver.
283 * Considering above, we just leave user a warning message instead
284 * of halt driver loading.
286 if (if_version != smu->smc_driver_if_version) {
287 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
288 "smu fw version = 0x%08x (%d.%d.%d)\n",
289 smu->smc_driver_if_version, if_version,
290 smu_version, smu_major, smu_minor, smu_debug);
291 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
297 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
299 struct amdgpu_device *adev = smu->adev;
300 uint32_t ppt_offset_bytes;
301 const struct smc_firmware_header_v2_0 *v2;
303 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
305 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
306 *size = le32_to_cpu(v2->ppt_size_bytes);
307 *table = (uint8_t *)v2 + ppt_offset_bytes;
312 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
313 uint32_t *size, uint32_t pptable_id)
315 struct amdgpu_device *adev = smu->adev;
316 const struct smc_firmware_header_v2_1 *v2_1;
317 struct smc_soft_pptable_entry *entries;
318 uint32_t pptable_count = 0;
321 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
322 entries = (struct smc_soft_pptable_entry *)
323 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
324 pptable_count = le32_to_cpu(v2_1->pptable_count);
325 for (i = 0; i < pptable_count; i++) {
326 if (le32_to_cpu(entries[i].id) == pptable_id) {
327 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
328 *size = le32_to_cpu(entries[i].ppt_size_bytes);
333 if (i == pptable_count)
339 int smu_v11_0_setup_pptable(struct smu_context *smu)
341 struct amdgpu_device *adev = smu->adev;
342 const struct smc_firmware_header_v1_0 *hdr;
345 uint16_t atom_table_size;
348 uint16_t version_major, version_minor;
350 if (!amdgpu_sriov_vf(adev)) {
351 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
352 version_major = le16_to_cpu(hdr->header.header_version_major);
353 version_minor = le16_to_cpu(hdr->header.header_version_minor);
354 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
355 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
356 switch (version_minor) {
358 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
361 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
362 smu->smu_table.boot_values.pp_table_id);
374 dev_info(adev->dev, "use vbios provided pptable\n");
375 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
378 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
382 size = atom_table_size;
385 if (!smu->smu_table.power_play_table)
386 smu->smu_table.power_play_table = table;
387 if (!smu->smu_table.power_play_table_size)
388 smu->smu_table.power_play_table_size = size;
393 int smu_v11_0_init_smc_tables(struct smu_context *smu)
395 struct smu_table_context *smu_table = &smu->smu_table;
396 struct smu_table *tables = smu_table->tables;
399 smu_table->driver_pptable =
400 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
401 if (!smu_table->driver_pptable) {
406 smu_table->max_sustainable_clocks =
407 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
408 if (!smu_table->max_sustainable_clocks) {
413 /* Arcturus does not support OVERDRIVE */
414 if (tables[SMU_TABLE_OVERDRIVE].size) {
415 smu_table->overdrive_table =
416 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
417 if (!smu_table->overdrive_table) {
422 smu_table->boot_overdrive_table =
423 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
424 if (!smu_table->boot_overdrive_table) {
429 smu_table->user_overdrive_table =
430 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
431 if (!smu_table->user_overdrive_table) {
441 kfree(smu_table->boot_overdrive_table);
443 kfree(smu_table->overdrive_table);
445 kfree(smu_table->max_sustainable_clocks);
447 kfree(smu_table->driver_pptable);
452 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
454 struct smu_table_context *smu_table = &smu->smu_table;
455 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
457 kfree(smu_table->gpu_metrics_table);
458 kfree(smu_table->user_overdrive_table);
459 kfree(smu_table->boot_overdrive_table);
460 kfree(smu_table->overdrive_table);
461 kfree(smu_table->max_sustainable_clocks);
462 kfree(smu_table->driver_pptable);
463 kfree(smu_table->clocks_table);
464 smu_table->gpu_metrics_table = NULL;
465 smu_table->user_overdrive_table = NULL;
466 smu_table->boot_overdrive_table = NULL;
467 smu_table->overdrive_table = NULL;
468 smu_table->max_sustainable_clocks = NULL;
469 smu_table->driver_pptable = NULL;
470 smu_table->clocks_table = NULL;
471 kfree(smu_table->hardcode_pptable);
472 smu_table->hardcode_pptable = NULL;
474 kfree(smu_table->metrics_table);
475 kfree(smu_table->watermarks_table);
476 smu_table->metrics_table = NULL;
477 smu_table->watermarks_table = NULL;
478 smu_table->metrics_time = 0;
480 kfree(smu_dpm->dpm_context);
481 kfree(smu_dpm->golden_dpm_context);
482 kfree(smu_dpm->dpm_current_power_state);
483 kfree(smu_dpm->dpm_request_power_state);
484 smu_dpm->dpm_context = NULL;
485 smu_dpm->golden_dpm_context = NULL;
486 smu_dpm->dpm_context_size = 0;
487 smu_dpm->dpm_current_power_state = NULL;
488 smu_dpm->dpm_request_power_state = NULL;
493 int smu_v11_0_init_power(struct smu_context *smu)
495 struct smu_power_context *smu_power = &smu->smu_power;
496 size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
497 sizeof(struct smu_11_5_power_context) :
498 sizeof(struct smu_11_0_power_context);
500 smu_power->power_context = kzalloc(size, GFP_KERNEL);
501 if (!smu_power->power_context)
503 smu_power->power_context_size = size;
508 int smu_v11_0_fini_power(struct smu_context *smu)
510 struct smu_power_context *smu_power = &smu->smu_power;
512 kfree(smu_power->power_context);
513 smu_power->power_context = NULL;
514 smu_power->power_context_size = 0;
519 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
524 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
525 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
528 input.clk_id = clk_id;
529 input.syspll_id = syspll_id;
530 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
531 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
534 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
539 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
540 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
545 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
550 struct atom_common_table_header *header;
551 struct atom_firmware_info_v3_3 *v_3_3;
552 struct atom_firmware_info_v3_1 *v_3_1;
554 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
557 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
558 (uint8_t **)&header);
562 if (header->format_revision != 3) {
563 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
567 switch (header->content_revision) {
571 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
572 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
573 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
574 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
575 smu->smu_table.boot_values.socclk = 0;
576 smu->smu_table.boot_values.dcefclk = 0;
577 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
578 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
579 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
580 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
581 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
582 smu->smu_table.boot_values.pp_table_id = 0;
583 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
588 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
589 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
590 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
591 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
592 smu->smu_table.boot_values.socclk = 0;
593 smu->smu_table.boot_values.dcefclk = 0;
594 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
595 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
596 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
597 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
598 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
599 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
600 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
603 smu->smu_table.boot_values.format_revision = header->format_revision;
604 smu->smu_table.boot_values.content_revision = header->content_revision;
606 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
607 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
609 &smu->smu_table.boot_values.socclk);
611 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
612 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
614 &smu->smu_table.boot_values.dcefclk);
616 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
617 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
619 &smu->smu_table.boot_values.eclk);
621 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
622 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
624 &smu->smu_table.boot_values.vclk);
626 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
627 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
629 &smu->smu_table.boot_values.dclk);
631 if ((smu->smu_table.boot_values.format_revision == 3) &&
632 (smu->smu_table.boot_values.content_revision >= 2))
633 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
634 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
635 (uint8_t)SMU11_SYSPLL1_2_ID,
636 &smu->smu_table.boot_values.fclk);
638 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
639 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
640 (uint8_t)SMU11_SYSPLL3_1_ID,
641 &smu->smu_table.boot_values.lclk);
646 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
648 struct smu_table_context *smu_table = &smu->smu_table;
649 struct smu_table *memory_pool = &smu_table->memory_pool;
652 uint32_t address_low, address_high;
654 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
657 address = (uintptr_t)memory_pool->cpu_addr;
658 address_high = (uint32_t)upper_32_bits(address);
659 address_low = (uint32_t)lower_32_bits(address);
661 ret = smu_cmn_send_smc_msg_with_param(smu,
662 SMU_MSG_SetSystemVirtualDramAddrHigh,
667 ret = smu_cmn_send_smc_msg_with_param(smu,
668 SMU_MSG_SetSystemVirtualDramAddrLow,
674 address = memory_pool->mc_address;
675 address_high = (uint32_t)upper_32_bits(address);
676 address_low = (uint32_t)lower_32_bits(address);
678 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
682 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
686 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
687 (uint32_t)memory_pool->size, NULL);
694 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
698 ret = smu_cmn_send_smc_msg_with_param(smu,
699 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
701 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
706 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
708 struct smu_table *driver_table = &smu->smu_table.driver_table;
711 if (driver_table->mc_address) {
712 ret = smu_cmn_send_smc_msg_with_param(smu,
713 SMU_MSG_SetDriverDramAddrHigh,
714 upper_32_bits(driver_table->mc_address),
717 ret = smu_cmn_send_smc_msg_with_param(smu,
718 SMU_MSG_SetDriverDramAddrLow,
719 lower_32_bits(driver_table->mc_address),
726 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
729 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
731 if (tool_table->mc_address) {
732 ret = smu_cmn_send_smc_msg_with_param(smu,
733 SMU_MSG_SetToolsDramAddrHigh,
734 upper_32_bits(tool_table->mc_address),
737 ret = smu_cmn_send_smc_msg_with_param(smu,
738 SMU_MSG_SetToolsDramAddrLow,
739 lower_32_bits(tool_table->mc_address),
746 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
748 struct amdgpu_device *adev = smu->adev;
750 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
751 * display num currently
753 if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
754 adev->asic_type <= CHIP_BEIGE_GOBY)
757 return smu_cmn_send_smc_msg_with_param(smu,
758 SMU_MSG_NumOfDisplays,
764 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
766 struct smu_feature *feature = &smu->smu_feature;
768 uint32_t feature_mask[2];
770 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
775 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
778 feature_mask[1], NULL);
782 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
783 feature_mask[0], NULL);
791 int smu_v11_0_system_features_control(struct smu_context *smu,
794 struct smu_feature *feature = &smu->smu_feature;
795 uint32_t feature_mask[2];
798 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
799 SMU_MSG_DisableAllSmuFeatures), NULL);
803 bitmap_zero(feature->enabled, feature->feature_num);
804 bitmap_zero(feature->supported, feature->feature_num);
807 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
811 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
812 feature->feature_num);
813 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
814 feature->feature_num);
820 int smu_v11_0_notify_display_change(struct smu_context *smu)
824 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
825 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
826 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
832 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
833 enum smu_clk_type clock_select)
838 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
839 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
842 clk_id = smu_cmn_to_asic_specific_index(smu,
843 CMN2ASIC_MAPPING_CLK,
848 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
849 clk_id << 16, clock);
851 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
858 /* if DC limit is zero, return AC limit */
859 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
860 clk_id << 16, clock);
862 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
869 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
871 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
872 smu->smu_table.max_sustainable_clocks;
875 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
876 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
877 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
878 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
879 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
880 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
882 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
883 ret = smu_v11_0_get_max_sustainable_clock(smu,
884 &(max_sustainable_clocks->uclock),
887 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
893 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
894 ret = smu_v11_0_get_max_sustainable_clock(smu,
895 &(max_sustainable_clocks->soc_clock),
898 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
904 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
905 ret = smu_v11_0_get_max_sustainable_clock(smu,
906 &(max_sustainable_clocks->dcef_clock),
909 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
914 ret = smu_v11_0_get_max_sustainable_clock(smu,
915 &(max_sustainable_clocks->display_clock),
918 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
922 ret = smu_v11_0_get_max_sustainable_clock(smu,
923 &(max_sustainable_clocks->phy_clock),
926 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
930 ret = smu_v11_0_get_max_sustainable_clock(smu,
931 &(max_sustainable_clocks->pixel_clock),
934 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
940 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
941 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
946 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
947 uint32_t *power_limit)
952 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
955 power_src = smu_cmn_to_asic_specific_index(smu,
956 CMN2ASIC_MAPPING_PWR,
957 smu->adev->pm.ac_power ?
958 SMU_POWER_SOURCE_AC :
959 SMU_POWER_SOURCE_DC);
964 * BIT 24-31: ControllerId (only PPT0 is supported for now)
965 * BIT 16-23: PowerSource
967 ret = smu_cmn_send_smc_msg_with_param(smu,
969 (0 << 24) | (power_src << 16),
972 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
977 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
982 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
983 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
987 power_src = smu_cmn_to_asic_specific_index(smu,
988 CMN2ASIC_MAPPING_PWR,
989 smu->adev->pm.ac_power ?
990 SMU_POWER_SOURCE_AC :
991 SMU_POWER_SOURCE_DC);
996 * BIT 24-31: ControllerId (only PPT0 is supported for now)
997 * BIT 16-23: PowerSource
998 * BIT 0-15: PowerLimit
1002 n |= (power_src) << 16;
1003 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
1005 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1009 smu->current_power_limit = n;
1014 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1016 return smu_cmn_send_smc_msg(smu,
1017 SMU_MSG_ReenableAcDcInterrupt,
1021 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1025 if (smu->dc_controlled_by_gpio &&
1026 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1027 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1032 void smu_v11_0_interrupt_work(struct smu_context *smu)
1034 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1035 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1038 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1042 if (smu->smu_table.thermal_controller_type) {
1043 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1049 * After init there might have been missed interrupts triggered
1050 * before driver registers for interrupt (Ex. AC/DC).
1052 return smu_v11_0_process_pending_interrupt(smu);
1055 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1057 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1060 static uint16_t convert_to_vddc(uint8_t vid)
1062 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1065 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1067 struct amdgpu_device *adev = smu->adev;
1068 uint32_t vdd = 0, val_vid = 0;
1072 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1073 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1074 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1076 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1085 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1086 struct pp_display_clock_request
1089 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1091 enum smu_clk_type clk_select = 0;
1092 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1094 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1095 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1097 case amd_pp_dcef_clock:
1098 clk_select = SMU_DCEFCLK;
1100 case amd_pp_disp_clock:
1101 clk_select = SMU_DISPCLK;
1103 case amd_pp_pixel_clock:
1104 clk_select = SMU_PIXCLK;
1106 case amd_pp_phy_clock:
1107 clk_select = SMU_PHYCLK;
1109 case amd_pp_mem_clock:
1110 clk_select = SMU_UCLK;
1113 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1121 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1124 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1126 if(clk_select == SMU_UCLK)
1127 smu->hard_min_uclk_req_from_dal = clk_freq;
1134 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1137 struct amdgpu_device *adev = smu->adev;
1139 switch (adev->asic_type) {
1143 case CHIP_SIENNA_CICHLID:
1144 case CHIP_NAVY_FLOUNDER:
1145 case CHIP_DIMGREY_CAVEFISH:
1146 case CHIP_BEIGE_GOBY:
1148 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1151 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1153 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1163 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1165 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1166 return AMD_FAN_CTRL_AUTO;
1168 return smu->user_dpm_profile.fan_mode;
1172 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1176 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1179 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1181 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1182 __func__, (auto_fan_control ? "Start" : "Stop"));
1188 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1190 struct amdgpu_device *adev = smu->adev;
1192 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1193 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1194 CG_FDO_CTRL2, TMIN, 0));
1195 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1196 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1197 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1203 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1205 struct amdgpu_device *adev = smu->adev;
1206 uint32_t duty100, duty;
1212 if (smu_v11_0_auto_fan_control(smu, 0))
1215 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1216 CG_FDO_CTRL1, FMAX_DUTY100);
1220 tmp64 = (uint64_t)speed * duty100;
1222 duty = (uint32_t)tmp64;
1224 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1225 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1226 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1228 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1232 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1238 case AMD_FAN_CTRL_NONE:
1239 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1241 case AMD_FAN_CTRL_MANUAL:
1242 ret = smu_v11_0_auto_fan_control(smu, 0);
1244 case AMD_FAN_CTRL_AUTO:
1245 ret = smu_v11_0_auto_fan_control(smu, 1);
1252 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1259 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1262 return smu_cmn_send_smc_msg_with_param(smu,
1263 SMU_MSG_SetXgmiMode,
1264 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1268 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1269 struct amdgpu_irq_src *source,
1271 enum amdgpu_interrupt_state state)
1273 struct smu_context *smu = &adev->smu;
1278 case AMDGPU_IRQ_STATE_DISABLE:
1280 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1281 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1282 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1283 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1285 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1287 /* For MP1 SW irqs */
1288 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1289 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1290 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1293 case AMDGPU_IRQ_STATE_ENABLE:
1295 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1296 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1297 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1298 smu->thermal_range.software_shutdown_temp);
1300 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1301 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1302 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1303 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1304 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1305 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1306 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1307 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1308 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1310 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1311 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1312 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1313 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1315 /* For MP1 SW irqs */
1316 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1317 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1318 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1319 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1321 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1322 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1323 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1333 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1334 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1336 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1338 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1339 struct amdgpu_irq_src *source,
1340 struct amdgpu_iv_entry *entry)
1342 struct smu_context *smu = &adev->smu;
1343 uint32_t client_id = entry->client_id;
1344 uint32_t src_id = entry->src_id;
1346 * ctxid is used to distinguish different
1347 * events for SMCToHost interrupt.
1349 uint32_t ctxid = entry->src_data[0];
1352 if (client_id == SOC15_IH_CLIENTID_THM) {
1354 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1355 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1357 * SW CTF just occurred.
1358 * Try to do a graceful shutdown to prevent further damage.
1360 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1361 orderly_poweroff(true);
1363 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1364 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1367 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1371 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1372 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1374 * HW CTF just occurred. Shutdown to prevent further damage.
1376 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1377 orderly_poweroff(true);
1378 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1379 if (src_id == 0xfe) {
1380 /* ACK SMUToHost interrupt */
1381 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1382 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1383 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1387 dev_dbg(adev->dev, "Switched to AC mode!\n");
1388 schedule_work(&smu->interrupt_work);
1391 dev_dbg(adev->dev, "Switched to DC mode!\n");
1392 schedule_work(&smu->interrupt_work);
1396 * Increment the throttle interrupt counter
1398 atomic64_inc(&smu->throttle_int_counter);
1400 if (!atomic_read(&adev->throttling_logging_enabled))
1403 if (__ratelimit(&adev->throttling_logging_rs))
1404 schedule_work(&smu->throttling_logging_work);
1414 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1416 .set = smu_v11_0_set_irq_state,
1417 .process = smu_v11_0_irq_process,
1420 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1422 struct amdgpu_device *adev = smu->adev;
1423 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1426 irq_src->num_types = 1;
1427 irq_src->funcs = &smu_v11_0_irq_funcs;
1429 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1430 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1435 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1436 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1441 /* Register CTF(GPIO_19) interrupt */
1442 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1443 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1448 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1457 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1458 struct pp_smu_nv_clock_table *max_clocks)
1460 struct smu_table_context *table_context = &smu->smu_table;
1461 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1463 if (!max_clocks || !table_context->max_sustainable_clocks)
1466 sustainable_clocks = table_context->max_sustainable_clocks;
1468 max_clocks->dcfClockInKhz =
1469 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1470 max_clocks->displayClockInKhz =
1471 (unsigned int) sustainable_clocks->display_clock * 1000;
1472 max_clocks->phyClockInKhz =
1473 (unsigned int) sustainable_clocks->phy_clock * 1000;
1474 max_clocks->pixelClockInKhz =
1475 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1476 max_clocks->uClockInKhz =
1477 (unsigned int) sustainable_clocks->uclock * 1000;
1478 max_clocks->socClockInKhz =
1479 (unsigned int) sustainable_clocks->soc_clock * 1000;
1480 max_clocks->dscClockInKhz = 0;
1481 max_clocks->dppClockInKhz = 0;
1482 max_clocks->fabricClockInKhz = 0;
1487 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1489 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1492 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1493 enum smu_v11_0_baco_seq baco_seq)
1495 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1498 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1500 struct smu_baco_context *smu_baco = &smu->smu_baco;
1502 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1505 /* Arcturus does not support this bit mask */
1506 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1507 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1513 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1515 struct smu_baco_context *smu_baco = &smu->smu_baco;
1516 enum smu_baco_state baco_state;
1518 mutex_lock(&smu_baco->mutex);
1519 baco_state = smu_baco->state;
1520 mutex_unlock(&smu_baco->mutex);
1525 #define D3HOT_BACO_SEQUENCE 0
1526 #define D3HOT_BAMACO_SEQUENCE 2
1528 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1530 struct smu_baco_context *smu_baco = &smu->smu_baco;
1531 struct amdgpu_device *adev = smu->adev;
1532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1536 if (smu_v11_0_baco_get_state(smu) == state)
1539 mutex_lock(&smu_baco->mutex);
1541 if (state == SMU_BACO_STATE_ENTER) {
1542 switch (adev->asic_type) {
1543 case CHIP_SIENNA_CICHLID:
1544 case CHIP_NAVY_FLOUNDER:
1545 case CHIP_DIMGREY_CAVEFISH:
1546 case CHIP_BEIGE_GOBY:
1547 if (amdgpu_runtime_pm == 2)
1548 ret = smu_cmn_send_smc_msg_with_param(smu,
1550 D3HOT_BAMACO_SEQUENCE,
1553 ret = smu_cmn_send_smc_msg_with_param(smu,
1555 D3HOT_BACO_SEQUENCE,
1559 if (!ras || !adev->ras_enabled ||
1560 adev->gmc.xgmi.pending_reset) {
1561 if (adev->asic_type == CHIP_ARCTURUS) {
1562 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1564 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1566 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1568 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1571 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1573 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1579 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1583 /* clear vbios scratch 6 and 7 for coming asic reinit */
1584 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1585 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1590 smu_baco->state = state;
1592 mutex_unlock(&smu_baco->mutex);
1596 int smu_v11_0_baco_enter(struct smu_context *smu)
1600 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1609 int smu_v11_0_baco_exit(struct smu_context *smu)
1611 return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1614 int smu_v11_0_mode1_reset(struct smu_context *smu)
1618 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1620 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1625 int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
1629 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1635 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1636 uint32_t *min, uint32_t *max)
1638 int ret = 0, clk_id = 0;
1640 uint32_t clock_limit;
1642 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1646 clock_limit = smu->smu_table.boot_values.uclk;
1650 clock_limit = smu->smu_table.boot_values.gfxclk;
1653 clock_limit = smu->smu_table.boot_values.socclk;
1660 /* clock in Mhz unit */
1662 *min = clock_limit / 100;
1664 *max = clock_limit / 100;
1669 clk_id = smu_cmn_to_asic_specific_index(smu,
1670 CMN2ASIC_MAPPING_CLK,
1676 param = (clk_id & 0xffff) << 16;
1679 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1685 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1694 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1695 enum smu_clk_type clk_type,
1699 struct amdgpu_device *adev = smu->adev;
1700 int ret = 0, clk_id = 0;
1703 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1706 clk_id = smu_cmn_to_asic_specific_index(smu,
1707 CMN2ASIC_MAPPING_CLK,
1712 if (clk_type == SMU_GFXCLK)
1713 amdgpu_gfx_off_ctrl(adev, false);
1716 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1717 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1724 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1725 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1732 if (clk_type == SMU_GFXCLK)
1733 amdgpu_gfx_off_ctrl(adev, true);
1738 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1739 enum smu_clk_type clk_type,
1743 int ret = 0, clk_id = 0;
1746 if (min <= 0 && max <= 0)
1749 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1752 clk_id = smu_cmn_to_asic_specific_index(smu,
1753 CMN2ASIC_MAPPING_CLK,
1759 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1760 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1767 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1768 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1777 int smu_v11_0_set_performance_level(struct smu_context *smu,
1778 enum amd_dpm_forced_level level)
1780 struct smu_11_0_dpm_context *dpm_context =
1781 smu->smu_dpm.dpm_context;
1782 struct smu_11_0_dpm_table *gfx_table =
1783 &dpm_context->dpm_tables.gfx_table;
1784 struct smu_11_0_dpm_table *mem_table =
1785 &dpm_context->dpm_tables.uclk_table;
1786 struct smu_11_0_dpm_table *soc_table =
1787 &dpm_context->dpm_tables.soc_table;
1788 struct smu_umd_pstate_table *pstate_table =
1790 struct amdgpu_device *adev = smu->adev;
1791 uint32_t sclk_min = 0, sclk_max = 0;
1792 uint32_t mclk_min = 0, mclk_max = 0;
1793 uint32_t socclk_min = 0, socclk_max = 0;
1797 case AMD_DPM_FORCED_LEVEL_HIGH:
1798 sclk_min = sclk_max = gfx_table->max;
1799 mclk_min = mclk_max = mem_table->max;
1800 socclk_min = socclk_max = soc_table->max;
1802 case AMD_DPM_FORCED_LEVEL_LOW:
1803 sclk_min = sclk_max = gfx_table->min;
1804 mclk_min = mclk_max = mem_table->min;
1805 socclk_min = socclk_max = soc_table->min;
1807 case AMD_DPM_FORCED_LEVEL_AUTO:
1808 sclk_min = gfx_table->min;
1809 sclk_max = gfx_table->max;
1810 mclk_min = mem_table->min;
1811 mclk_max = mem_table->max;
1812 socclk_min = soc_table->min;
1813 socclk_max = soc_table->max;
1815 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1816 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1817 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1818 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1820 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1821 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1823 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1824 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1826 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1827 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1828 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1829 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1831 case AMD_DPM_FORCED_LEVEL_MANUAL:
1832 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1835 dev_err(adev->dev, "Invalid performance level %d\n", level);
1840 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1843 if (adev->asic_type == CHIP_ARCTURUS) {
1844 mclk_min = mclk_max = 0;
1845 socclk_min = socclk_max = 0;
1848 if (sclk_min && sclk_max) {
1849 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1857 if (mclk_min && mclk_max) {
1858 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1866 if (socclk_min && socclk_max) {
1867 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1878 int smu_v11_0_set_power_source(struct smu_context *smu,
1879 enum smu_power_src_type power_src)
1883 pwr_source = smu_cmn_to_asic_specific_index(smu,
1884 CMN2ASIC_MAPPING_PWR,
1885 (uint32_t)power_src);
1889 return smu_cmn_send_smc_msg_with_param(smu,
1890 SMU_MSG_NotifyPowerSource,
1895 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1896 enum smu_clk_type clk_type,
1900 int ret = 0, clk_id = 0;
1906 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1909 clk_id = smu_cmn_to_asic_specific_index(smu,
1910 CMN2ASIC_MAPPING_CLK,
1915 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1917 ret = smu_cmn_send_smc_msg_with_param(smu,
1918 SMU_MSG_GetDpmFreqByIndex,
1925 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1926 * now, we un-support it
1928 *value = *value & 0x7fffffff;
1933 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1934 enum smu_clk_type clk_type,
1937 return smu_v11_0_get_dpm_freq_by_index(smu,
1943 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1944 enum smu_clk_type clk_type,
1945 struct smu_11_0_dpm_table *single_dpm_table)
1951 ret = smu_v11_0_get_dpm_level_count(smu,
1953 &single_dpm_table->count);
1955 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1959 for (i = 0; i < single_dpm_table->count; i++) {
1960 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1965 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1969 single_dpm_table->dpm_levels[i].value = clk;
1970 single_dpm_table->dpm_levels[i].enabled = true;
1973 single_dpm_table->min = clk;
1974 else if (i == single_dpm_table->count - 1)
1975 single_dpm_table->max = clk;
1981 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1982 enum smu_clk_type clk_type,
1983 uint32_t *min_value,
1984 uint32_t *max_value)
1986 uint32_t level_count = 0;
1989 if (!min_value && !max_value)
1993 /* by default, level 0 clock value as min value */
1994 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2003 ret = smu_v11_0_get_dpm_level_count(smu,
2009 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2020 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2022 struct amdgpu_device *adev = smu->adev;
2024 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2025 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2026 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2029 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2031 uint32_t width_level;
2033 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2034 if (width_level > LINK_WIDTH_MAX)
2037 return link_width[width_level];
2040 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2042 struct amdgpu_device *adev = smu->adev;
2044 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2045 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2046 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2049 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2051 uint32_t speed_level;
2053 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2054 if (speed_level > LINK_SPEED_MAX)
2057 return link_speed[speed_level];
2060 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2065 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2066 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2071 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2074 struct amdgpu_device *adev = smu->adev;
2077 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2078 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2080 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2085 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2086 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2088 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2093 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2094 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2096 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2101 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2102 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2104 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2109 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2110 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2112 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2120 int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2122 struct smu_table_context *table_context = &smu->smu_table;
2123 void *user_od_table = table_context->user_overdrive_table;
2126 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2128 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");