2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
67 #define SMU11_VOLTAGE_SCALE 4
69 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71 #define LINK_WIDTH_MAX 6
72 #define LINK_SPEED_MAX 3
74 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
76 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
77 #define smnPCIE_LC_SPEED_CNTL 0x11140290
78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
79 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
81 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
82 static int link_speed[] = {25, 50, 80, 160};
84 int smu_v11_0_init_microcode(struct smu_context *smu)
86 struct amdgpu_device *adev = smu->adev;
87 const char *chip_name;
88 char fw_name[SMU_FW_NAME_LEN];
90 const struct smc_firmware_header_v1_0 *hdr;
91 const struct common_firmware_header *header;
92 struct amdgpu_firmware_info *ucode = NULL;
94 if (amdgpu_sriov_vf(adev) &&
95 ((adev->asic_type == CHIP_NAVI12) ||
96 (adev->asic_type == CHIP_SIENNA_CICHLID)))
99 switch (adev->asic_type) {
101 chip_name = "arcturus";
104 chip_name = "navi10";
107 chip_name = "navi14";
110 chip_name = "navi12";
112 case CHIP_SIENNA_CICHLID:
113 chip_name = "sienna_cichlid";
115 case CHIP_NAVY_FLOUNDER:
116 chip_name = "navy_flounder";
118 case CHIP_DIMGREY_CAVEFISH:
119 chip_name = "dimgrey_cavefish";
122 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
126 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
128 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
131 err = amdgpu_ucode_validate(adev->pm.fw);
135 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
136 amdgpu_ucode_print_smc_hdr(&hdr->header);
137 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
139 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
140 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
141 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
142 ucode->fw = adev->pm.fw;
143 header = (const struct common_firmware_header *)ucode->fw->data;
144 adev->firmware.fw_size +=
145 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
150 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
152 release_firmware(adev->pm.fw);
158 void smu_v11_0_fini_microcode(struct smu_context *smu)
160 struct amdgpu_device *adev = smu->adev;
162 release_firmware(adev->pm.fw);
164 adev->pm.fw_version = 0;
167 int smu_v11_0_load_microcode(struct smu_context *smu)
169 struct amdgpu_device *adev = smu->adev;
171 const struct smc_firmware_header_v1_0 *hdr;
172 uint32_t addr_start = MP1_SRAM;
174 uint32_t smc_fw_size;
175 uint32_t mp1_fw_flags;
177 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
178 src = (const uint32_t *)(adev->pm.fw->data +
179 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
180 smc_fw_size = hdr->header.ucode_size_bytes;
182 for (i = 1; i < smc_fw_size/4 - 1; i++) {
183 WREG32_PCIE(addr_start, src[i]);
187 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
188 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
189 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
190 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
192 for (i = 0; i < adev->usec_timeout; i++) {
193 mp1_fw_flags = RREG32_PCIE(MP1_Public |
194 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
195 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
196 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
201 if (i == adev->usec_timeout)
207 int smu_v11_0_check_fw_status(struct smu_context *smu)
209 struct amdgpu_device *adev = smu->adev;
210 uint32_t mp1_fw_flags;
212 mp1_fw_flags = RREG32_PCIE(MP1_Public |
213 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
215 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
216 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
222 int smu_v11_0_check_fw_version(struct smu_context *smu)
224 struct amdgpu_device *adev = smu->adev;
225 uint32_t if_version = 0xff, smu_version = 0xff;
227 uint8_t smu_minor, smu_debug;
230 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
234 smu_major = (smu_version >> 16) & 0xffff;
235 smu_minor = (smu_version >> 8) & 0xff;
236 smu_debug = (smu_version >> 0) & 0xff;
238 adev->pm.fw_version = smu_version;
240 switch (smu->adev->asic_type) {
242 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
245 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
248 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
251 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
253 case CHIP_SIENNA_CICHLID:
254 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
256 case CHIP_NAVY_FLOUNDER:
257 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
260 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
262 case CHIP_DIMGREY_CAVEFISH:
263 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
266 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
267 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
272 * 1. if_version mismatch is not critical as our fw is designed
273 * to be backward compatible.
274 * 2. New fw usually brings some optimizations. But that's visible
275 * only on the paired driver.
276 * Considering above, we just leave user a warning message instead
277 * of halt driver loading.
279 if (if_version != smu->smc_driver_if_version) {
280 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
281 "smu fw version = 0x%08x (%d.%d.%d)\n",
282 smu->smc_driver_if_version, if_version,
283 smu_version, smu_major, smu_minor, smu_debug);
284 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
290 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
292 struct amdgpu_device *adev = smu->adev;
293 uint32_t ppt_offset_bytes;
294 const struct smc_firmware_header_v2_0 *v2;
296 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
298 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
299 *size = le32_to_cpu(v2->ppt_size_bytes);
300 *table = (uint8_t *)v2 + ppt_offset_bytes;
305 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
306 uint32_t *size, uint32_t pptable_id)
308 struct amdgpu_device *adev = smu->adev;
309 const struct smc_firmware_header_v2_1 *v2_1;
310 struct smc_soft_pptable_entry *entries;
311 uint32_t pptable_count = 0;
314 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
315 entries = (struct smc_soft_pptable_entry *)
316 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
317 pptable_count = le32_to_cpu(v2_1->pptable_count);
318 for (i = 0; i < pptable_count; i++) {
319 if (le32_to_cpu(entries[i].id) == pptable_id) {
320 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
321 *size = le32_to_cpu(entries[i].ppt_size_bytes);
326 if (i == pptable_count)
332 int smu_v11_0_setup_pptable(struct smu_context *smu)
334 struct amdgpu_device *adev = smu->adev;
335 const struct smc_firmware_header_v1_0 *hdr;
338 uint16_t atom_table_size;
341 uint16_t version_major, version_minor;
343 if (!amdgpu_sriov_vf(adev)) {
344 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
345 version_major = le16_to_cpu(hdr->header.header_version_major);
346 version_minor = le16_to_cpu(hdr->header.header_version_minor);
347 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
348 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
349 switch (version_minor) {
351 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
354 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
355 smu->smu_table.boot_values.pp_table_id);
367 dev_info(adev->dev, "use vbios provided pptable\n");
368 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
371 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
375 size = atom_table_size;
378 if (!smu->smu_table.power_play_table)
379 smu->smu_table.power_play_table = table;
380 if (!smu->smu_table.power_play_table_size)
381 smu->smu_table.power_play_table_size = size;
386 int smu_v11_0_init_smc_tables(struct smu_context *smu)
388 struct smu_table_context *smu_table = &smu->smu_table;
389 struct smu_table *tables = smu_table->tables;
392 smu_table->driver_pptable =
393 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
394 if (!smu_table->driver_pptable) {
399 smu_table->max_sustainable_clocks =
400 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
401 if (!smu_table->max_sustainable_clocks) {
406 /* Arcturus does not support OVERDRIVE */
407 if (tables[SMU_TABLE_OVERDRIVE].size) {
408 smu_table->overdrive_table =
409 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
410 if (!smu_table->overdrive_table) {
415 smu_table->boot_overdrive_table =
416 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
417 if (!smu_table->boot_overdrive_table) {
426 kfree(smu_table->overdrive_table);
428 kfree(smu_table->max_sustainable_clocks);
430 kfree(smu_table->driver_pptable);
435 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
437 struct smu_table_context *smu_table = &smu->smu_table;
438 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
440 kfree(smu_table->gpu_metrics_table);
441 kfree(smu_table->boot_overdrive_table);
442 kfree(smu_table->overdrive_table);
443 kfree(smu_table->max_sustainable_clocks);
444 kfree(smu_table->driver_pptable);
445 kfree(smu_table->clocks_table);
446 smu_table->gpu_metrics_table = NULL;
447 smu_table->boot_overdrive_table = NULL;
448 smu_table->overdrive_table = NULL;
449 smu_table->max_sustainable_clocks = NULL;
450 smu_table->driver_pptable = NULL;
451 smu_table->clocks_table = NULL;
452 kfree(smu_table->hardcode_pptable);
453 smu_table->hardcode_pptable = NULL;
455 kfree(smu_table->metrics_table);
456 kfree(smu_table->watermarks_table);
457 smu_table->metrics_table = NULL;
458 smu_table->watermarks_table = NULL;
459 smu_table->metrics_time = 0;
461 kfree(smu_dpm->dpm_context);
462 kfree(smu_dpm->golden_dpm_context);
463 kfree(smu_dpm->dpm_current_power_state);
464 kfree(smu_dpm->dpm_request_power_state);
465 smu_dpm->dpm_context = NULL;
466 smu_dpm->golden_dpm_context = NULL;
467 smu_dpm->dpm_context_size = 0;
468 smu_dpm->dpm_current_power_state = NULL;
469 smu_dpm->dpm_request_power_state = NULL;
474 int smu_v11_0_init_power(struct smu_context *smu)
476 struct smu_power_context *smu_power = &smu->smu_power;
478 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context),
480 if (!smu_power->power_context)
482 smu_power->power_context_size = sizeof(struct smu_11_0_power_context);
487 int smu_v11_0_fini_power(struct smu_context *smu)
489 struct smu_power_context *smu_power = &smu->smu_power;
491 kfree(smu_power->power_context);
492 smu_power->power_context = NULL;
493 smu_power->power_context_size = 0;
498 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
503 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
504 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
507 input.clk_id = clk_id;
508 input.syspll_id = syspll_id;
509 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
510 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
513 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
518 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
519 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
524 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
529 struct atom_common_table_header *header;
530 struct atom_firmware_info_v3_3 *v_3_3;
531 struct atom_firmware_info_v3_1 *v_3_1;
533 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
536 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
537 (uint8_t **)&header);
541 if (header->format_revision != 3) {
542 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
546 switch (header->content_revision) {
550 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
551 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
552 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
553 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
554 smu->smu_table.boot_values.socclk = 0;
555 smu->smu_table.boot_values.dcefclk = 0;
556 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
557 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
558 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
559 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
560 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
561 smu->smu_table.boot_values.pp_table_id = 0;
562 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
566 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
567 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
568 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
569 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
570 smu->smu_table.boot_values.socclk = 0;
571 smu->smu_table.boot_values.dcefclk = 0;
572 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
573 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
574 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
575 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
576 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
577 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
578 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
581 smu->smu_table.boot_values.format_revision = header->format_revision;
582 smu->smu_table.boot_values.content_revision = header->content_revision;
584 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
585 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
587 &smu->smu_table.boot_values.socclk);
589 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
590 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
592 &smu->smu_table.boot_values.dcefclk);
594 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
595 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
597 &smu->smu_table.boot_values.eclk);
599 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
600 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
602 &smu->smu_table.boot_values.vclk);
604 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
605 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
607 &smu->smu_table.boot_values.dclk);
609 if ((smu->smu_table.boot_values.format_revision == 3) &&
610 (smu->smu_table.boot_values.content_revision >= 2))
611 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
612 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
613 (uint8_t)SMU11_SYSPLL1_2_ID,
614 &smu->smu_table.boot_values.fclk);
616 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
617 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
618 (uint8_t)SMU11_SYSPLL3_1_ID,
619 &smu->smu_table.boot_values.lclk);
624 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
626 struct smu_table_context *smu_table = &smu->smu_table;
627 struct smu_table *memory_pool = &smu_table->memory_pool;
630 uint32_t address_low, address_high;
632 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
635 address = (uintptr_t)memory_pool->cpu_addr;
636 address_high = (uint32_t)upper_32_bits(address);
637 address_low = (uint32_t)lower_32_bits(address);
639 ret = smu_cmn_send_smc_msg_with_param(smu,
640 SMU_MSG_SetSystemVirtualDramAddrHigh,
645 ret = smu_cmn_send_smc_msg_with_param(smu,
646 SMU_MSG_SetSystemVirtualDramAddrLow,
652 address = memory_pool->mc_address;
653 address_high = (uint32_t)upper_32_bits(address);
654 address_low = (uint32_t)lower_32_bits(address);
656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
664 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
665 (uint32_t)memory_pool->size, NULL);
672 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
676 ret = smu_cmn_send_smc_msg_with_param(smu,
677 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
679 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
684 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
686 struct smu_table *driver_table = &smu->smu_table.driver_table;
689 if (driver_table->mc_address) {
690 ret = smu_cmn_send_smc_msg_with_param(smu,
691 SMU_MSG_SetDriverDramAddrHigh,
692 upper_32_bits(driver_table->mc_address),
695 ret = smu_cmn_send_smc_msg_with_param(smu,
696 SMU_MSG_SetDriverDramAddrLow,
697 lower_32_bits(driver_table->mc_address),
704 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
707 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
709 if (tool_table->mc_address) {
710 ret = smu_cmn_send_smc_msg_with_param(smu,
711 SMU_MSG_SetToolsDramAddrHigh,
712 upper_32_bits(tool_table->mc_address),
715 ret = smu_cmn_send_smc_msg_with_param(smu,
716 SMU_MSG_SetToolsDramAddrLow,
717 lower_32_bits(tool_table->mc_address),
724 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
726 struct amdgpu_device *adev = smu->adev;
728 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
729 * display num currently
731 if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
732 adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
735 return smu_cmn_send_smc_msg_with_param(smu,
736 SMU_MSG_NumOfDisplays,
742 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
744 struct smu_feature *feature = &smu->smu_feature;
746 uint32_t feature_mask[2];
748 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
751 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
753 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
754 feature_mask[1], NULL);
758 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
759 feature_mask[0], NULL);
767 int smu_v11_0_system_features_control(struct smu_context *smu,
770 struct smu_feature *feature = &smu->smu_feature;
771 uint32_t feature_mask[2];
774 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
775 SMU_MSG_DisableAllSmuFeatures), NULL);
779 bitmap_zero(feature->enabled, feature->feature_num);
780 bitmap_zero(feature->supported, feature->feature_num);
783 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
787 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
788 feature->feature_num);
789 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
790 feature->feature_num);
796 int smu_v11_0_notify_display_change(struct smu_context *smu)
800 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
801 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
802 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
808 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
809 enum smu_clk_type clock_select)
814 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
815 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
818 clk_id = smu_cmn_to_asic_specific_index(smu,
819 CMN2ASIC_MAPPING_CLK,
824 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
825 clk_id << 16, clock);
827 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
834 /* if DC limit is zero, return AC limit */
835 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
836 clk_id << 16, clock);
838 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
845 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
847 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
848 smu->smu_table.max_sustainable_clocks;
851 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
852 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
853 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
854 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
855 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
856 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
858 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
859 ret = smu_v11_0_get_max_sustainable_clock(smu,
860 &(max_sustainable_clocks->uclock),
863 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
869 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
870 ret = smu_v11_0_get_max_sustainable_clock(smu,
871 &(max_sustainable_clocks->soc_clock),
874 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
880 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
881 ret = smu_v11_0_get_max_sustainable_clock(smu,
882 &(max_sustainable_clocks->dcef_clock),
885 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
890 ret = smu_v11_0_get_max_sustainable_clock(smu,
891 &(max_sustainable_clocks->display_clock),
894 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
898 ret = smu_v11_0_get_max_sustainable_clock(smu,
899 &(max_sustainable_clocks->phy_clock),
902 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
906 ret = smu_v11_0_get_max_sustainable_clock(smu,
907 &(max_sustainable_clocks->pixel_clock),
910 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
916 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
917 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
922 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
923 uint32_t *power_limit)
928 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
931 power_src = smu_cmn_to_asic_specific_index(smu,
932 CMN2ASIC_MAPPING_PWR,
933 smu->adev->pm.ac_power ?
934 SMU_POWER_SOURCE_AC :
935 SMU_POWER_SOURCE_DC);
940 * BIT 24-31: ControllerId (only PPT0 is supported for now)
941 * BIT 16-23: PowerSource
943 ret = smu_cmn_send_smc_msg_with_param(smu,
945 (0 << 24) | (power_src << 16),
948 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
953 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
958 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
959 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
963 power_src = smu_cmn_to_asic_specific_index(smu,
964 CMN2ASIC_MAPPING_PWR,
965 smu->adev->pm.ac_power ?
966 SMU_POWER_SOURCE_AC :
967 SMU_POWER_SOURCE_DC);
972 * BIT 24-31: ControllerId (only PPT0 is supported for now)
973 * BIT 16-23: PowerSource
974 * BIT 0-15: PowerLimit
978 n |= (power_src) << 16;
979 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
981 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
985 smu->current_power_limit = n;
990 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
992 return smu_cmn_send_smc_msg(smu,
993 SMU_MSG_ReenableAcDcInterrupt,
997 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1001 if (smu->dc_controlled_by_gpio &&
1002 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1003 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1008 void smu_v11_0_interrupt_work(struct smu_context *smu)
1010 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1011 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1014 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1018 if (smu->smu_table.thermal_controller_type) {
1019 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1025 * After init there might have been missed interrupts triggered
1026 * before driver registers for interrupt (Ex. AC/DC).
1028 return smu_v11_0_process_pending_interrupt(smu);
1031 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1033 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1036 static uint16_t convert_to_vddc(uint8_t vid)
1038 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1041 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1043 struct amdgpu_device *adev = smu->adev;
1044 uint32_t vdd = 0, val_vid = 0;
1048 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1049 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1050 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1052 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1061 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1062 struct pp_display_clock_request
1065 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1067 enum smu_clk_type clk_select = 0;
1068 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1071 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1073 case amd_pp_dcef_clock:
1074 clk_select = SMU_DCEFCLK;
1076 case amd_pp_disp_clock:
1077 clk_select = SMU_DISPCLK;
1079 case amd_pp_pixel_clock:
1080 clk_select = SMU_PIXCLK;
1082 case amd_pp_phy_clock:
1083 clk_select = SMU_PHYCLK;
1085 case amd_pp_mem_clock:
1086 clk_select = SMU_UCLK;
1089 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1097 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1100 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1102 if(clk_select == SMU_UCLK)
1103 smu->hard_min_uclk_req_from_dal = clk_freq;
1110 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1113 struct amdgpu_device *adev = smu->adev;
1115 switch (adev->asic_type) {
1119 case CHIP_SIENNA_CICHLID:
1120 case CHIP_NAVY_FLOUNDER:
1121 case CHIP_DIMGREY_CAVEFISH:
1122 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1125 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1127 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1137 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1139 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1140 return AMD_FAN_CTRL_MANUAL;
1142 return AMD_FAN_CTRL_AUTO;
1146 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1150 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1153 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1155 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1156 __func__, (auto_fan_control ? "Start" : "Stop"));
1162 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1164 struct amdgpu_device *adev = smu->adev;
1166 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1167 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1168 CG_FDO_CTRL2, TMIN, 0));
1169 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1170 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1171 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1177 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1183 case AMD_FAN_CTRL_NONE:
1184 ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
1186 case AMD_FAN_CTRL_MANUAL:
1187 ret = smu_v11_0_auto_fan_control(smu, 0);
1189 case AMD_FAN_CTRL_AUTO:
1190 ret = smu_v11_0_auto_fan_control(smu, 1);
1197 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1204 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1207 struct amdgpu_device *adev = smu->adev;
1209 uint32_t tach_period, crystal_clock_freq;
1214 ret = smu_v11_0_auto_fan_control(smu, 0);
1219 * crystal_clock_freq div by 4 is required since the fan control
1220 * module refers to 25MHz
1223 crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
1224 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1225 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1226 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1227 CG_TACH_CTRL, TARGET_PERIOD,
1230 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1235 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1238 struct amdgpu_device *adev = smu->adev;
1239 uint32_t tach_period, crystal_clock_freq;
1242 tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1243 CG_TACH_CTRL, TARGET_PERIOD);
1247 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1249 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1250 do_div(tmp64, (tach_period * 8));
1251 *speed = (uint32_t)tmp64;
1256 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1259 return smu_cmn_send_smc_msg_with_param(smu,
1260 SMU_MSG_SetXgmiMode,
1261 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1265 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1266 struct amdgpu_irq_src *source,
1268 enum amdgpu_interrupt_state state)
1270 struct smu_context *smu = &adev->smu;
1275 case AMDGPU_IRQ_STATE_DISABLE:
1277 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1278 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1279 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1280 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1282 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1284 /* For MP1 SW irqs */
1285 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1286 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1287 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1290 case AMDGPU_IRQ_STATE_ENABLE:
1292 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1293 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1294 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1295 smu->thermal_range.software_shutdown_temp);
1297 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1298 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1299 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1300 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1301 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1302 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1303 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1304 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1305 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1307 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1308 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1309 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1310 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1312 /* For MP1 SW irqs */
1313 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1314 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1315 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1316 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1318 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1319 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1320 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1330 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1331 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1333 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1335 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1336 struct amdgpu_irq_src *source,
1337 struct amdgpu_iv_entry *entry)
1339 struct smu_context *smu = &adev->smu;
1340 uint32_t client_id = entry->client_id;
1341 uint32_t src_id = entry->src_id;
1343 * ctxid is used to distinguish different
1344 * events for SMCToHost interrupt.
1346 uint32_t ctxid = entry->src_data[0];
1349 if (client_id == SOC15_IH_CLIENTID_THM) {
1351 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1352 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1354 * SW CTF just occurred.
1355 * Try to do a graceful shutdown to prevent further damage.
1357 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1358 orderly_poweroff(true);
1360 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1361 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1364 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1368 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1369 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1371 * HW CTF just occurred. Shutdown to prevent further damage.
1373 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1374 orderly_poweroff(true);
1375 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1376 if (src_id == 0xfe) {
1377 /* ACK SMUToHost interrupt */
1378 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1379 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1380 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1384 dev_dbg(adev->dev, "Switched to AC mode!\n");
1385 schedule_work(&smu->interrupt_work);
1388 dev_dbg(adev->dev, "Switched to DC mode!\n");
1389 schedule_work(&smu->interrupt_work);
1393 * Increment the throttle interrupt counter
1395 atomic64_inc(&smu->throttle_int_counter);
1397 if (!atomic_read(&adev->throttling_logging_enabled))
1400 if (__ratelimit(&adev->throttling_logging_rs))
1401 schedule_work(&smu->throttling_logging_work);
1411 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1413 .set = smu_v11_0_set_irq_state,
1414 .process = smu_v11_0_irq_process,
1417 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1419 struct amdgpu_device *adev = smu->adev;
1420 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1423 irq_src->num_types = 1;
1424 irq_src->funcs = &smu_v11_0_irq_funcs;
1426 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1427 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1432 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1433 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1438 /* Register CTF(GPIO_19) interrupt */
1439 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1440 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1445 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1454 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1455 struct pp_smu_nv_clock_table *max_clocks)
1457 struct smu_table_context *table_context = &smu->smu_table;
1458 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1460 if (!max_clocks || !table_context->max_sustainable_clocks)
1463 sustainable_clocks = table_context->max_sustainable_clocks;
1465 max_clocks->dcfClockInKhz =
1466 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1467 max_clocks->displayClockInKhz =
1468 (unsigned int) sustainable_clocks->display_clock * 1000;
1469 max_clocks->phyClockInKhz =
1470 (unsigned int) sustainable_clocks->phy_clock * 1000;
1471 max_clocks->pixelClockInKhz =
1472 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1473 max_clocks->uClockInKhz =
1474 (unsigned int) sustainable_clocks->uclock * 1000;
1475 max_clocks->socClockInKhz =
1476 (unsigned int) sustainable_clocks->soc_clock * 1000;
1477 max_clocks->dscClockInKhz = 0;
1478 max_clocks->dppClockInKhz = 0;
1479 max_clocks->fabricClockInKhz = 0;
1484 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1486 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1489 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1491 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1494 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1496 struct smu_baco_context *smu_baco = &smu->smu_baco;
1498 if (!smu_baco->platform_support)
1501 /* Arcturus does not support this bit mask */
1502 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1503 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1509 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1511 struct smu_baco_context *smu_baco = &smu->smu_baco;
1512 enum smu_baco_state baco_state;
1514 mutex_lock(&smu_baco->mutex);
1515 baco_state = smu_baco->state;
1516 mutex_unlock(&smu_baco->mutex);
1521 #define D3HOT_BACO_SEQUENCE 0
1522 #define D3HOT_BAMACO_SEQUENCE 2
1524 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1526 struct smu_baco_context *smu_baco = &smu->smu_baco;
1527 struct amdgpu_device *adev = smu->adev;
1528 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1532 if (smu_v11_0_baco_get_state(smu) == state)
1535 mutex_lock(&smu_baco->mutex);
1537 if (state == SMU_BACO_STATE_ENTER) {
1538 switch (adev->asic_type) {
1539 case CHIP_SIENNA_CICHLID:
1540 case CHIP_NAVY_FLOUNDER:
1541 case CHIP_DIMGREY_CAVEFISH:
1542 if (amdgpu_runtime_pm == 2)
1543 ret = smu_cmn_send_smc_msg_with_param(smu,
1545 D3HOT_BAMACO_SEQUENCE,
1548 ret = smu_cmn_send_smc_msg_with_param(smu,
1550 D3HOT_BACO_SEQUENCE,
1554 if (!ras || !ras->supported) {
1555 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1557 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1559 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1561 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1567 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1571 /* clear vbios scratch 6 and 7 for coming asic reinit */
1572 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1573 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1578 smu_baco->state = state;
1580 mutex_unlock(&smu_baco->mutex);
1584 int smu_v11_0_baco_enter(struct smu_context *smu)
1586 struct amdgpu_device *adev = smu->adev;
1589 /* Arcturus does not need this audio workaround */
1590 if (adev->asic_type != CHIP_ARCTURUS) {
1591 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1596 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1605 int smu_v11_0_baco_exit(struct smu_context *smu)
1607 return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1610 int smu_v11_0_mode1_reset(struct smu_context *smu)
1614 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1616 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1621 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1622 uint32_t *min, uint32_t *max)
1624 int ret = 0, clk_id = 0;
1626 uint32_t clock_limit;
1628 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1632 clock_limit = smu->smu_table.boot_values.uclk;
1636 clock_limit = smu->smu_table.boot_values.gfxclk;
1639 clock_limit = smu->smu_table.boot_values.socclk;
1646 /* clock in Mhz unit */
1648 *min = clock_limit / 100;
1650 *max = clock_limit / 100;
1655 clk_id = smu_cmn_to_asic_specific_index(smu,
1656 CMN2ASIC_MAPPING_CLK,
1662 param = (clk_id & 0xffff) << 16;
1665 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1671 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1680 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1681 enum smu_clk_type clk_type,
1685 struct amdgpu_device *adev = smu->adev;
1686 int ret = 0, clk_id = 0;
1689 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1692 clk_id = smu_cmn_to_asic_specific_index(smu,
1693 CMN2ASIC_MAPPING_CLK,
1698 if (clk_type == SMU_GFXCLK)
1699 amdgpu_gfx_off_ctrl(adev, false);
1702 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1703 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1710 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1711 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1718 if (clk_type == SMU_GFXCLK)
1719 amdgpu_gfx_off_ctrl(adev, true);
1724 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1725 enum smu_clk_type clk_type,
1729 int ret = 0, clk_id = 0;
1732 if (min <= 0 && max <= 0)
1735 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1738 clk_id = smu_cmn_to_asic_specific_index(smu,
1739 CMN2ASIC_MAPPING_CLK,
1745 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1746 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1753 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1754 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1763 int smu_v11_0_set_performance_level(struct smu_context *smu,
1764 enum amd_dpm_forced_level level)
1766 struct smu_11_0_dpm_context *dpm_context =
1767 smu->smu_dpm.dpm_context;
1768 struct smu_11_0_dpm_table *gfx_table =
1769 &dpm_context->dpm_tables.gfx_table;
1770 struct smu_11_0_dpm_table *mem_table =
1771 &dpm_context->dpm_tables.uclk_table;
1772 struct smu_11_0_dpm_table *soc_table =
1773 &dpm_context->dpm_tables.soc_table;
1774 struct smu_umd_pstate_table *pstate_table =
1776 struct amdgpu_device *adev = smu->adev;
1777 uint32_t sclk_min = 0, sclk_max = 0;
1778 uint32_t mclk_min = 0, mclk_max = 0;
1779 uint32_t socclk_min = 0, socclk_max = 0;
1783 case AMD_DPM_FORCED_LEVEL_HIGH:
1784 sclk_min = sclk_max = gfx_table->max;
1785 mclk_min = mclk_max = mem_table->max;
1786 socclk_min = socclk_max = soc_table->max;
1788 case AMD_DPM_FORCED_LEVEL_LOW:
1789 sclk_min = sclk_max = gfx_table->min;
1790 mclk_min = mclk_max = mem_table->min;
1791 socclk_min = socclk_max = soc_table->min;
1793 case AMD_DPM_FORCED_LEVEL_AUTO:
1794 sclk_min = gfx_table->min;
1795 sclk_max = gfx_table->max;
1796 mclk_min = mem_table->min;
1797 mclk_max = mem_table->max;
1798 socclk_min = soc_table->min;
1799 socclk_max = soc_table->max;
1801 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1802 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1803 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1804 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1806 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1807 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1809 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1810 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1812 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1813 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1814 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1815 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1817 case AMD_DPM_FORCED_LEVEL_MANUAL:
1818 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1821 dev_err(adev->dev, "Invalid performance level %d\n", level);
1826 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1829 if (adev->asic_type == CHIP_ARCTURUS) {
1830 mclk_min = mclk_max = 0;
1831 socclk_min = socclk_max = 0;
1834 if (sclk_min && sclk_max) {
1835 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1843 if (mclk_min && mclk_max) {
1844 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1852 if (socclk_min && socclk_max) {
1853 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1864 int smu_v11_0_set_power_source(struct smu_context *smu,
1865 enum smu_power_src_type power_src)
1869 pwr_source = smu_cmn_to_asic_specific_index(smu,
1870 CMN2ASIC_MAPPING_PWR,
1871 (uint32_t)power_src);
1875 return smu_cmn_send_smc_msg_with_param(smu,
1876 SMU_MSG_NotifyPowerSource,
1881 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1882 enum smu_clk_type clk_type,
1886 int ret = 0, clk_id = 0;
1892 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1895 clk_id = smu_cmn_to_asic_specific_index(smu,
1896 CMN2ASIC_MAPPING_CLK,
1901 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1903 ret = smu_cmn_send_smc_msg_with_param(smu,
1904 SMU_MSG_GetDpmFreqByIndex,
1911 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1912 * now, we un-support it
1914 *value = *value & 0x7fffffff;
1919 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1920 enum smu_clk_type clk_type,
1923 return smu_v11_0_get_dpm_freq_by_index(smu,
1929 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1930 enum smu_clk_type clk_type,
1931 struct smu_11_0_dpm_table *single_dpm_table)
1937 ret = smu_v11_0_get_dpm_level_count(smu,
1939 &single_dpm_table->count);
1941 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1945 for (i = 0; i < single_dpm_table->count; i++) {
1946 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1951 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1955 single_dpm_table->dpm_levels[i].value = clk;
1956 single_dpm_table->dpm_levels[i].enabled = true;
1959 single_dpm_table->min = clk;
1960 else if (i == single_dpm_table->count - 1)
1961 single_dpm_table->max = clk;
1967 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1968 enum smu_clk_type clk_type,
1969 uint32_t *min_value,
1970 uint32_t *max_value)
1972 uint32_t level_count = 0;
1975 if (!min_value && !max_value)
1979 /* by default, level 0 clock value as min value */
1980 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1989 ret = smu_v11_0_get_dpm_level_count(smu,
1995 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2006 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2008 struct amdgpu_device *adev = smu->adev;
2010 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2011 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2012 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2015 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2017 uint32_t width_level;
2019 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2020 if (width_level > LINK_WIDTH_MAX)
2023 return link_width[width_level];
2026 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2028 struct amdgpu_device *adev = smu->adev;
2030 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2031 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2032 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2035 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2037 uint32_t speed_level;
2039 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2040 if (speed_level > LINK_SPEED_MAX)
2043 return link_speed[speed_level];
2046 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2048 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2050 gpu_metrics->common_header.structure_size =
2051 sizeof(struct gpu_metrics_v1_0);
2052 gpu_metrics->common_header.format_revision = 1;
2053 gpu_metrics->common_header.content_revision = 0;
2055 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2058 void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics)
2060 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0));
2062 gpu_metrics->common_header.structure_size =
2063 sizeof(struct gpu_metrics_v2_0);
2064 gpu_metrics->common_header.format_revision = 2;
2065 gpu_metrics->common_header.content_revision = 0;
2067 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2070 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2075 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2076 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2081 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2084 struct amdgpu_device *adev = smu->adev;
2087 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2088 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2090 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2095 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2096 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2098 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2103 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2104 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2106 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2111 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2112 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2114 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2119 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2120 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2122 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");