drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_11_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v11_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65
  66 #define SMU11_VOLTAGE_SCALE 4
  67
  68 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  69
  70 #define LINK_WIDTH_MAX                          6
  71 #define LINK_SPEED_MAX                          3
  72
  73 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  76 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  79
  80 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  81 static int link_speed[] = {25, 50, 80, 160};
  82
  83 int smu_v11_0_init_microcode(struct smu_context *smu)
  84 {
  85         struct amdgpu_device *adev = smu->adev;
  86         const char *chip_name;
  87         char fw_name[30];
  88         int err = 0;
  89         const struct smc_firmware_header_v1_0 *hdr;
  90         const struct common_firmware_header *header;
  91         struct amdgpu_firmware_info *ucode = NULL;
  92
  93         switch (adev->asic_type) {
  94         case CHIP_ARCTURUS:
  95                 chip_name = "arcturus";
  96                 break;
  97         case CHIP_NAVI10:
  98                 chip_name = "navi10";
  99                 break;
 100         case CHIP_NAVI14:
 101                 chip_name = "navi14";
 102                 break;
 103         case CHIP_NAVI12:
 104                 chip_name = "navi12";
 105                 break;
 106         case CHIP_SIENNA_CICHLID:
 107                 chip_name = "sienna_cichlid";
 108                 break;
 109         case CHIP_NAVY_FLOUNDER:
 110                 chip_name = "navy_flounder";
 111                 break;
 112         default:
 113                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 114                 return -EINVAL;
 115         }
 116
 117         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 118
 119         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 120         if (err)
 121                 goto out;
 122         err = amdgpu_ucode_validate(adev->pm.fw);
 123         if (err)
 124                 goto out;
 125
 126         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 127         amdgpu_ucode_print_smc_hdr(&hdr->header);
 128         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 129
 130         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 131                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 132                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 133                 ucode->fw = adev->pm.fw;
 134                 header = (const struct common_firmware_header *)ucode->fw->data;
 135                 adev->firmware.fw_size +=
 136                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 137         }
 138
 139 out:
 140         if (err) {
 141                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 142                           fw_name);
 143                 release_firmware(adev->pm.fw);
 144                 adev->pm.fw = NULL;
 145         }
 146         return err;
 147 }
 148
 149 void smu_v11_0_fini_microcode(struct smu_context *smu)
 150 {
 151         struct amdgpu_device *adev = smu->adev;
 152
 153         release_firmware(adev->pm.fw);
 154         adev->pm.fw = NULL;
 155         adev->pm.fw_version = 0;
 156 }
 157
 158 int smu_v11_0_load_microcode(struct smu_context *smu)
 159 {
 160         struct amdgpu_device *adev = smu->adev;
 161         const uint32_t *src;
 162         const struct smc_firmware_header_v1_0 *hdr;
 163         uint32_t addr_start = MP1_SRAM;
 164         uint32_t i;
 165         uint32_t smc_fw_size;
 166         uint32_t mp1_fw_flags;
 167
 168         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 169         src = (const uint32_t *)(adev->pm.fw->data +
 170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 171         smc_fw_size = hdr->header.ucode_size_bytes;
 172
 173         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 174                 WREG32_PCIE(addr_start, src[i]);
 175                 addr_start += 4;
 176         }
 177
 178         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 179                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 180         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 181                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 182
 183         for (i = 0; i < adev->usec_timeout; i++) {
 184                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 185                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 186                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 187                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 188                         break;
 189                 udelay(1);
 190         }
 191
 192         if (i == adev->usec_timeout)
 193                 return -ETIME;
 194
 195         return 0;
 196 }
 197
 198 int smu_v11_0_check_fw_status(struct smu_context *smu)
 199 {
 200         struct amdgpu_device *adev = smu->adev;
 201         uint32_t mp1_fw_flags;
 202
 203         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 204                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 205
 206         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 207             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 208                 return 0;
 209
 210         return -EIO;
 211 }
 212
 213 int smu_v11_0_check_fw_version(struct smu_context *smu)
 214 {
 215         uint32_t if_version = 0xff, smu_version = 0xff;
 216         uint16_t smu_major;
 217         uint8_t smu_minor, smu_debug;
 218         int ret = 0;
 219
 220         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 221         if (ret)
 222                 return ret;
 223
 224         smu_major = (smu_version >> 16) & 0xffff;
 225         smu_minor = (smu_version >> 8) & 0xff;
 226         smu_debug = (smu_version >> 0) & 0xff;
 227
 228         switch (smu->adev->asic_type) {
 229         case CHIP_ARCTURUS:
 230                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 231                 break;
 232         case CHIP_NAVI10:
 233                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 234                 break;
 235         case CHIP_NAVI12:
 236                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 237                 break;
 238         case CHIP_NAVI14:
 239                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 240                 break;
 241         case CHIP_SIENNA_CICHLID:
 242                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 243                 break;
 244         case CHIP_NAVY_FLOUNDER:
 245                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 246                 break;
 247         default:
 248                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 249                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 250                 break;
 251         }
 252
 253         /*
 254          * 1. if_version mismatch is not critical as our fw is designed
 255          * to be backward compatible.
 256          * 2. New fw usually brings some optimizations. But that's visible
 257          * only on the paired driver.
 258          * Considering above, we just leave user a warning message instead
 259          * of halt driver loading.
 260          */
 261         if (if_version != smu->smc_driver_if_version) {
 262                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 263                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 264                         smu->smc_driver_if_version, if_version,
 265                         smu_version, smu_major, smu_minor, smu_debug);
 266                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 267         }
 268
 269         return ret;
 270 }
 271
 272 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 273 {
 274         struct amdgpu_device *adev = smu->adev;
 275         uint32_t ppt_offset_bytes;
 276         const struct smc_firmware_header_v2_0 *v2;
 277
 278         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 279
 280         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 281         *size = le32_to_cpu(v2->ppt_size_bytes);
 282         *table = (uint8_t *)v2 + ppt_offset_bytes;
 283
 284         return 0;
 285 }
 286
 287 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 288                                       uint32_t *size, uint32_t pptable_id)
 289 {
 290         struct amdgpu_device *adev = smu->adev;
 291         const struct smc_firmware_header_v2_1 *v2_1;
 292         struct smc_soft_pptable_entry *entries;
 293         uint32_t pptable_count = 0;
 294         int i = 0;
 295
 296         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 297         entries = (struct smc_soft_pptable_entry *)
 298                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 299         pptable_count = le32_to_cpu(v2_1->pptable_count);
 300         for (i = 0; i < pptable_count; i++) {
 301                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 302                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 303                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 304                         break;
 305                 }
 306         }
 307
 308         if (i == pptable_count)
 309                 return -EINVAL;
 310
 311         return 0;
 312 }
 313
 314 int smu_v11_0_setup_pptable(struct smu_context *smu)
 315 {
 316         struct amdgpu_device *adev = smu->adev;
 317         const struct smc_firmware_header_v1_0 *hdr;
 318         int ret, index;
 319         uint32_t size = 0;
 320         uint16_t atom_table_size;
 321         uint8_t frev, crev;
 322         void *table;
 323         uint16_t version_major, version_minor;
 324
 325         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 326         version_major = le16_to_cpu(hdr->header.header_version_major);
 327         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 328         if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
 329             adev->asic_type == CHIP_NAVY_FLOUNDER) {
 330                 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 331                 switch (version_minor) {
 332                 case 0:
 333                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 334                         break;
 335                 case 1:
 336                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 337                                                          smu->smu_table.boot_values.pp_table_id);
 338                         break;
 339                 default:
 340                         ret = -EINVAL;
 341                         break;
 342                 }
 343                 if (ret)
 344                         return ret;
 345
 346         } else {
 347                 dev_info(adev->dev, "use vbios provided pptable\n");
 348                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 349                                                     powerplayinfo);
 350
 351                 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 352                                               (uint8_t **)&table);
 353                 if (ret)
 354                         return ret;
 355                 size = atom_table_size;
 356         }
 357
 358         if (!smu->smu_table.power_play_table)
 359                 smu->smu_table.power_play_table = table;
 360         if (!smu->smu_table.power_play_table_size)
 361                 smu->smu_table.power_play_table_size = size;
 362
 363         return 0;
 364 }
 365
 366 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 367 {
 368         struct smu_table_context *smu_table = &smu->smu_table;
 369         struct smu_table *tables = smu_table->tables;
 370         int ret = 0;
 371
 372         smu_table->driver_pptable =
 373                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 374         if (!smu_table->driver_pptable) {
 375                 ret = -ENOMEM;
 376                 goto err0_out;
 377         }
 378
 379         smu_table->max_sustainable_clocks =
 380                 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 381         if (!smu_table->max_sustainable_clocks) {
 382                 ret = -ENOMEM;
 383                 goto err1_out;
 384         }
 385
 386         /* Arcturus does not support OVERDRIVE */
 387         if (tables[SMU_TABLE_OVERDRIVE].size) {
 388                 smu_table->overdrive_table =
 389                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 390                 if (!smu_table->overdrive_table) {
 391                         ret = -ENOMEM;
 392                         goto err2_out;
 393                 }
 394
 395                 smu_table->boot_overdrive_table =
 396                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 397                 if (!smu_table->boot_overdrive_table) {
 398                         ret = -ENOMEM;
 399                         goto err3_out;
 400                 }
 401         }
 402
 403         return 0;
 404
 405 err3_out:
 406         kfree(smu_table->overdrive_table);
 407 err2_out:
 408         kfree(smu_table->max_sustainable_clocks);
 409 err1_out:
 410         kfree(smu_table->driver_pptable);
 411 err0_out:
 412         return ret;
 413 }
 414
 415 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 416 {
 417         struct smu_table_context *smu_table = &smu->smu_table;
 418         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 419
 420         kfree(smu_table->gpu_metrics_table);
 421         kfree(smu_table->boot_overdrive_table);
 422         kfree(smu_table->overdrive_table);
 423         kfree(smu_table->max_sustainable_clocks);
 424         kfree(smu_table->driver_pptable);
 425         smu_table->gpu_metrics_table = NULL;
 426         smu_table->boot_overdrive_table = NULL;
 427         smu_table->overdrive_table = NULL;
 428         smu_table->max_sustainable_clocks = NULL;
 429         smu_table->driver_pptable = NULL;
 430         kfree(smu_table->hardcode_pptable);
 431         smu_table->hardcode_pptable = NULL;
 432
 433         kfree(smu_table->metrics_table);
 434         kfree(smu_table->watermarks_table);
 435         smu_table->metrics_table = NULL;
 436         smu_table->watermarks_table = NULL;
 437         smu_table->metrics_time = 0;
 438
 439         kfree(smu_dpm->dpm_context);
 440         kfree(smu_dpm->golden_dpm_context);
 441         kfree(smu_dpm->dpm_current_power_state);
 442         kfree(smu_dpm->dpm_request_power_state);
 443         smu_dpm->dpm_context = NULL;
 444         smu_dpm->golden_dpm_context = NULL;
 445         smu_dpm->dpm_context_size = 0;
 446         smu_dpm->dpm_current_power_state = NULL;
 447         smu_dpm->dpm_request_power_state = NULL;
 448
 449         return 0;
 450 }
 451
 452 int smu_v11_0_init_power(struct smu_context *smu)
 453 {
 454         struct smu_power_context *smu_power = &smu->smu_power;
 455
 456         if (smu_power->power_context || smu_power->power_context_size != 0)
 457                 return -EINVAL;
 458
 459         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 460                                            GFP_KERNEL);
 461         if (!smu_power->power_context)
 462                 return -ENOMEM;
 463         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 464
 465         return 0;
 466 }
 467
 468 int smu_v11_0_fini_power(struct smu_context *smu)
 469 {
 470         struct smu_power_context *smu_power = &smu->smu_power;
 471
 472         if (!smu_power->power_context || smu_power->power_context_size == 0)
 473                 return -EINVAL;
 474
 475         kfree(smu_power->power_context);
 476         smu_power->power_context = NULL;
 477         smu_power->power_context_size = 0;
 478
 479         return 0;
 480 }
 481
 482 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 483                                             uint8_t clk_id,
 484                                             uint8_t syspll_id,
 485                                             uint32_t *clk_freq)
 486 {
 487         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 488         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 489         int ret, index;
 490
 491         input.clk_id = clk_id;
 492         input.syspll_id = syspll_id;
 493         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 494         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 495                                             getsmuclockinfo);
 496
 497         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 498                                         (uint32_t *)&input);
 499         if (ret)
 500                 return -EINVAL;
 501
 502         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 503         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 504
 505         return 0;
 506 }
 507
 508 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 509 {
 510         int ret, index;
 511         uint16_t size;
 512         uint8_t frev, crev;
 513         struct atom_common_table_header *header;
 514         struct atom_firmware_info_v3_3 *v_3_3;
 515         struct atom_firmware_info_v3_1 *v_3_1;
 516
 517         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 518                                             firmwareinfo);
 519
 520         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 521                                       (uint8_t **)&header);
 522         if (ret)
 523                 return ret;
 524
 525         if (header->format_revision != 3) {
 526                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 527                 return -EINVAL;
 528         }
 529
 530         switch (header->content_revision) {
 531         case 0:
 532         case 1:
 533         case 2:
 534                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 535                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 536                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 537                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 538                 smu->smu_table.boot_values.socclk = 0;
 539                 smu->smu_table.boot_values.dcefclk = 0;
 540                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 541                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 542                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 543                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 544                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 545                 smu->smu_table.boot_values.pp_table_id = 0;
 546                 break;
 547         case 3:
 548         default:
 549                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 550                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 551                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 552                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 553                 smu->smu_table.boot_values.socclk = 0;
 554                 smu->smu_table.boot_values.dcefclk = 0;
 555                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 556                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 557                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 558                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 559                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 560                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 561         }
 562
 563         smu->smu_table.boot_values.format_revision = header->format_revision;
 564         smu->smu_table.boot_values.content_revision = header->content_revision;
 565
 566         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 567                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 568                                          (uint8_t)0,
 569                                          &smu->smu_table.boot_values.socclk);
 570
 571         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 572                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 573                                          (uint8_t)0,
 574                                          &smu->smu_table.boot_values.dcefclk);
 575
 576         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 577                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 578                                          (uint8_t)0,
 579                                          &smu->smu_table.boot_values.eclk);
 580
 581         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 582                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 583                                          (uint8_t)0,
 584                                          &smu->smu_table.boot_values.vclk);
 585
 586         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 587                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 588                                          (uint8_t)0,
 589                                          &smu->smu_table.boot_values.dclk);
 590
 591         if ((smu->smu_table.boot_values.format_revision == 3) &&
 592             (smu->smu_table.boot_values.content_revision >= 2))
 593                 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 594                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 595                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 596                                                  &smu->smu_table.boot_values.fclk);
 597
 598         return 0;
 599 }
 600
 601 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 602 {
 603         struct smu_table_context *smu_table = &smu->smu_table;
 604         struct smu_table *memory_pool = &smu_table->memory_pool;
 605         int ret = 0;
 606         uint64_t address;
 607         uint32_t address_low, address_high;
 608
 609         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 610                 return ret;
 611
 612         address = (uintptr_t)memory_pool->cpu_addr;
 613         address_high = (uint32_t)upper_32_bits(address);
 614         address_low  = (uint32_t)lower_32_bits(address);
 615
 616         ret = smu_cmn_send_smc_msg_with_param(smu,
 617                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 618                                           address_high,
 619                                           NULL);
 620         if (ret)
 621                 return ret;
 622         ret = smu_cmn_send_smc_msg_with_param(smu,
 623                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 624                                           address_low,
 625                                           NULL);
 626         if (ret)
 627                 return ret;
 628
 629         address = memory_pool->mc_address;
 630         address_high = (uint32_t)upper_32_bits(address);
 631         address_low  = (uint32_t)lower_32_bits(address);
 632
 633         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 634                                           address_high, NULL);
 635         if (ret)
 636                 return ret;
 637         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 638                                           address_low, NULL);
 639         if (ret)
 640                 return ret;
 641         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 642                                           (uint32_t)memory_pool->size, NULL);
 643         if (ret)
 644                 return ret;
 645
 646         return ret;
 647 }
 648
 649 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 650 {
 651         int ret;
 652
 653         ret = smu_cmn_send_smc_msg_with_param(smu,
 654                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 655         if (ret)
 656                 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 657
 658         return ret;
 659 }
 660
 661 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 662 {
 663         struct smu_table *driver_table = &smu->smu_table.driver_table;
 664         int ret = 0;
 665
 666         if (driver_table->mc_address) {
 667                 ret = smu_cmn_send_smc_msg_with_param(smu,
 668                                 SMU_MSG_SetDriverDramAddrHigh,
 669                                 upper_32_bits(driver_table->mc_address),
 670                                 NULL);
 671                 if (!ret)
 672                         ret = smu_cmn_send_smc_msg_with_param(smu,
 673                                 SMU_MSG_SetDriverDramAddrLow,
 674                                 lower_32_bits(driver_table->mc_address),
 675                                 NULL);
 676         }
 677
 678         return ret;
 679 }
 680
 681 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 682 {
 683         int ret = 0;
 684         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 685
 686         if (tool_table->mc_address) {
 687                 ret = smu_cmn_send_smc_msg_with_param(smu,
 688                                 SMU_MSG_SetToolsDramAddrHigh,
 689                                 upper_32_bits(tool_table->mc_address),
 690                                 NULL);
 691                 if (!ret)
 692                         ret = smu_cmn_send_smc_msg_with_param(smu,
 693                                 SMU_MSG_SetToolsDramAddrLow,
 694                                 lower_32_bits(tool_table->mc_address),
 695                                 NULL);
 696         }
 697
 698         return ret;
 699 }
 700
 701 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 702 {
 703         int ret = 0;
 704         struct amdgpu_device *adev = smu->adev;
 705
 706         /* Navy_Flounder do not support to change display num currently */
 707         if (adev->asic_type == CHIP_NAVY_FLOUNDER)
 708                 return 0;
 709
 710         if (!smu->pm_enabled)
 711                 return ret;
 712
 713         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 714         return ret;
 715 }
 716
 717
 718 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 719 {
 720         struct smu_feature *feature = &smu->smu_feature;
 721         int ret = 0;
 722         uint32_t feature_mask[2];
 723
 724         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 725                 goto failed;
 726
 727         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 728
 729         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 730                                           feature_mask[1], NULL);
 731         if (ret)
 732                 goto failed;
 733
 734         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 735                                           feature_mask[0], NULL);
 736         if (ret)
 737                 goto failed;
 738
 739 failed:
 740         return ret;
 741 }
 742
 743 int smu_v11_0_system_features_control(struct smu_context *smu,
 744                                              bool en)
 745 {
 746         struct smu_feature *feature = &smu->smu_feature;
 747         uint32_t feature_mask[2];
 748         int ret = 0;
 749
 750         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 751                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 752         if (ret)
 753                 return ret;
 754
 755         bitmap_zero(feature->enabled, feature->feature_num);
 756         bitmap_zero(feature->supported, feature->feature_num);
 757
 758         if (en) {
 759                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 760                 if (ret)
 761                         return ret;
 762
 763                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 764                             feature->feature_num);
 765                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 766                             feature->feature_num);
 767         }
 768
 769         return ret;
 770 }
 771
 772 int smu_v11_0_notify_display_change(struct smu_context *smu)
 773 {
 774         int ret = 0;
 775
 776         if (!smu->pm_enabled)
 777                 return ret;
 778
 779         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 780             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 781                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 782
 783         return ret;
 784 }
 785
 786 static int
 787 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 788                                     enum smu_clk_type clock_select)
 789 {
 790         int ret = 0;
 791         int clk_id;
 792
 793         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 794             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 795                 return 0;
 796
 797         clk_id = smu_cmn_to_asic_specific_index(smu,
 798                                                 CMN2ASIC_MAPPING_CLK,
 799                                                 clock_select);
 800         if (clk_id < 0)
 801                 return -EINVAL;
 802
 803         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 804                                           clk_id << 16, clock);
 805         if (ret) {
 806                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 807                 return ret;
 808         }
 809
 810         if (*clock != 0)
 811                 return 0;
 812
 813         /* if DC limit is zero, return AC limit */
 814         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 815                                           clk_id << 16, clock);
 816         if (ret) {
 817                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 818                 return ret;
 819         }
 820
 821         return 0;
 822 }
 823
 824 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 825 {
 826         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 827                         smu->smu_table.max_sustainable_clocks;
 828         int ret = 0;
 829
 830         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 831         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 832         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 833         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 834         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 835         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 836
 837         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 838                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 839                                                           &(max_sustainable_clocks->uclock),
 840                                                           SMU_UCLK);
 841                 if (ret) {
 842                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 843                                __func__);
 844                         return ret;
 845                 }
 846         }
 847
 848         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 849                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 850                                                           &(max_sustainable_clocks->soc_clock),
 851                                                           SMU_SOCCLK);
 852                 if (ret) {
 853                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 854                                __func__);
 855                         return ret;
 856                 }
 857         }
 858
 859         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 860                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 861                                                           &(max_sustainable_clocks->dcef_clock),
 862                                                           SMU_DCEFCLK);
 863                 if (ret) {
 864                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 865                                __func__);
 866                         return ret;
 867                 }
 868
 869                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 870                                                           &(max_sustainable_clocks->display_clock),
 871                                                           SMU_DISPCLK);
 872                 if (ret) {
 873                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 874                                __func__);
 875                         return ret;
 876                 }
 877                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 878                                                           &(max_sustainable_clocks->phy_clock),
 879                                                           SMU_PHYCLK);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 882                                __func__);
 883                         return ret;
 884                 }
 885                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 886                                                           &(max_sustainable_clocks->pixel_clock),
 887                                                           SMU_PIXCLK);
 888                 if (ret) {
 889                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 890                                __func__);
 891                         return ret;
 892                 }
 893         }
 894
 895         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 896                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 897
 898         return 0;
 899 }
 900
 901 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 902                                       uint32_t *power_limit)
 903 {
 904         int power_src;
 905         int ret = 0;
 906
 907         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 908                 return -EINVAL;
 909
 910         power_src = smu_cmn_to_asic_specific_index(smu,
 911                                         CMN2ASIC_MAPPING_PWR,
 912                                         smu->adev->pm.ac_power ?
 913                                         SMU_POWER_SOURCE_AC :
 914                                         SMU_POWER_SOURCE_DC);
 915         if (power_src < 0)
 916                 return -EINVAL;
 917
 918         ret = smu_cmn_send_smc_msg_with_param(smu,
 919                                           SMU_MSG_GetPptLimit,
 920                                           power_src << 16,
 921                                           power_limit);
 922         if (ret)
 923                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 924
 925         return ret;
 926 }
 927
 928 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 929 {
 930         int ret = 0;
 931
 932         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 933                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 934                 return -EOPNOTSUPP;
 935         }
 936
 937         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 938         if (ret) {
 939                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 940                 return ret;
 941         }
 942
 943         smu->current_power_limit = n;
 944
 945         return 0;
 946 }
 947
 948 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
 949 {
 950         if (smu->smu_table.thermal_controller_type)
 951                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 952
 953         return 0;
 954 }
 955
 956 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
 957 {
 958         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 959 }
 960
 961 static uint16_t convert_to_vddc(uint8_t vid)
 962 {
 963         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
 964 }
 965
 966 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 967 {
 968         struct amdgpu_device *adev = smu->adev;
 969         uint32_t vdd = 0, val_vid = 0;
 970
 971         if (!value)
 972                 return -EINVAL;
 973         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
 974                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 975                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 976
 977         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 978
 979         *value = vdd;
 980
 981         return 0;
 982
 983 }
 984
 985 int
 986 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
 987                                         struct pp_display_clock_request
 988                                         *clock_req)
 989 {
 990         enum amd_pp_clock_type clk_type = clock_req->clock_type;
 991         int ret = 0;
 992         enum smu_clk_type clk_select = 0;
 993         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
 994
 995         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
 996                 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 997                 switch (clk_type) {
 998                 case amd_pp_dcef_clock:
 999                         clk_select = SMU_DCEFCLK;
1000                         break;
1001                 case amd_pp_disp_clock:
1002                         clk_select = SMU_DISPCLK;
1003                         break;
1004                 case amd_pp_pixel_clock:
1005                         clk_select = SMU_PIXCLK;
1006                         break;
1007                 case amd_pp_phy_clock:
1008                         clk_select = SMU_PHYCLK;
1009                         break;
1010                 case amd_pp_mem_clock:
1011                         clk_select = SMU_UCLK;
1012                         break;
1013                 default:
1014                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1015                         ret = -EINVAL;
1016                         break;
1017                 }
1018
1019                 if (ret)
1020                         goto failed;
1021
1022                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1023                         return 0;
1024
1025                 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1026
1027                 if(clk_select == SMU_UCLK)
1028                         smu->hard_min_uclk_req_from_dal = clk_freq;
1029         }
1030
1031 failed:
1032         return ret;
1033 }
1034
1035 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1036 {
1037         int ret = 0;
1038         struct amdgpu_device *adev = smu->adev;
1039
1040         switch (adev->asic_type) {
1041         case CHIP_NAVI10:
1042         case CHIP_NAVI14:
1043         case CHIP_NAVI12:
1044         case CHIP_SIENNA_CICHLID:
1045         case CHIP_NAVY_FLOUNDER:
1046                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1047                         return 0;
1048                 if (enable)
1049                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1050                 else
1051                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1052                 break;
1053         default:
1054                 break;
1055         }
1056
1057         return ret;
1058 }
1059
1060 uint32_t
1061 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1062 {
1063         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1064                 return AMD_FAN_CTRL_MANUAL;
1065         else
1066                 return AMD_FAN_CTRL_AUTO;
1067 }
1068
1069 static int
1070 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1071 {
1072         int ret = 0;
1073
1074         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1075                 return 0;
1076
1077         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1078         if (ret)
1079                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1080                        __func__, (auto_fan_control ? "Start" : "Stop"));
1081
1082         return ret;
1083 }
1084
1085 static int
1086 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1087 {
1088         struct amdgpu_device *adev = smu->adev;
1089
1090         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1091                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1092                                    CG_FDO_CTRL2, TMIN, 0));
1093         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1094                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1095                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1096
1097         return 0;
1098 }
1099
1100 int
1101 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1102                                uint32_t mode)
1103 {
1104         int ret = 0;
1105
1106         switch (mode) {
1107         case AMD_FAN_CTRL_NONE:
1108                 ret = smu_v11_0_set_fan_speed_rpm(smu, smu->fan_max_rpm);
1109                 break;
1110         case AMD_FAN_CTRL_MANUAL:
1111                 ret = smu_v11_0_auto_fan_control(smu, 0);
1112                 break;
1113         case AMD_FAN_CTRL_AUTO:
1114                 ret = smu_v11_0_auto_fan_control(smu, 1);
1115                 break;
1116         default:
1117                 break;
1118         }
1119
1120         if (ret) {
1121                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1122                 return -EINVAL;
1123         }
1124
1125         return ret;
1126 }
1127
1128 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1129                                        uint32_t speed)
1130 {
1131         struct amdgpu_device *adev = smu->adev;
1132         int ret;
1133         uint32_t tach_period, crystal_clock_freq;
1134
1135         if (!speed)
1136                 return -EINVAL;
1137
1138         ret = smu_v11_0_auto_fan_control(smu, 0);
1139         if (ret)
1140                 return ret;
1141
1142         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1143         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1144         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1145                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1146                                    CG_TACH_CTRL, TARGET_PERIOD,
1147                                    tach_period));
1148
1149         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1150
1151         return ret;
1152 }
1153
1154 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1155                                 uint32_t *speed)
1156 {
1157         struct amdgpu_device *adev = smu->adev;
1158         uint32_t tach_period, crystal_clock_freq;
1159         uint64_t tmp64;
1160
1161         tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1162                                     CG_TACH_CTRL, TARGET_PERIOD);
1163         if (!tach_period)
1164                 return -EINVAL;
1165
1166         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1167
1168         tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1169         do_div(tmp64, (tach_period * 8));
1170         *speed = (uint32_t)tmp64;
1171
1172         return 0;
1173 }
1174
1175 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1176                                      uint32_t pstate)
1177 {
1178         int ret = 0;
1179         ret = smu_cmn_send_smc_msg_with_param(smu,
1180                                           SMU_MSG_SetXgmiMode,
1181                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1182                                           NULL);
1183         return ret;
1184 }
1185
1186 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1187                                    struct amdgpu_irq_src *source,
1188                                    unsigned tyep,
1189                                    enum amdgpu_interrupt_state state)
1190 {
1191         struct smu_context *smu = &adev->smu;
1192         uint32_t low, high;
1193         uint32_t val = 0;
1194
1195         switch (state) {
1196         case AMDGPU_IRQ_STATE_DISABLE:
1197                 /* For THM irqs */
1198                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1199                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1200                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1201                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1202
1203                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1204
1205                 /* For MP1 SW irqs */
1206                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1207                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1208                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1209
1210                 break;
1211         case AMDGPU_IRQ_STATE_ENABLE:
1212                 /* For THM irqs */
1213                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1214                                 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1215                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1216                                 smu->thermal_range.software_shutdown_temp);
1217
1218                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1219                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1220                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1221                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1222                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1223                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1224                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1225                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1226                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1227
1228                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1229                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1230                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1231                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1232
1233                 /* For MP1 SW irqs */
1234                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1235                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1236                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1237                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1238
1239                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1240                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1241                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1242
1243                 break;
1244         default:
1245                 break;
1246         }
1247
1248         return 0;
1249 }
1250
1251 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1252 {
1253         return smu_cmn_send_smc_msg(smu,
1254                                 SMU_MSG_ReenableAcDcInterrupt,
1255                                 NULL);
1256 }
1257
1258 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1259 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1260
1261 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1262
1263 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1264                                  struct amdgpu_irq_src *source,
1265                                  struct amdgpu_iv_entry *entry)
1266 {
1267         struct smu_context *smu = &adev->smu;
1268         uint32_t client_id = entry->client_id;
1269         uint32_t src_id = entry->src_id;
1270         /*
1271          * ctxid is used to distinguish different
1272          * events for SMCToHost interrupt.
1273          */
1274         uint32_t ctxid = entry->src_data[0];
1275         uint32_t data;
1276
1277         if (client_id == SOC15_IH_CLIENTID_THM) {
1278                 switch (src_id) {
1279                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1280                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1281                         /*
1282                          * SW CTF just occurred.
1283                          * Try to do a graceful shutdown to prevent further damage.
1284                          */
1285                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1286                         orderly_poweroff(true);
1287                 break;
1288                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1289                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1290                 break;
1291                 default:
1292                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1293                                 src_id);
1294                 break;
1295                 }
1296         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1297                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1298                 /*
1299                  * HW CTF just occurred. Shutdown to prevent further damage.
1300                  */
1301                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1302                 orderly_poweroff(true);
1303         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1304                 if (src_id == 0xfe) {
1305                         /* ACK SMUToHost interrupt */
1306                         data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1307                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1308                         WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1309
1310                         switch (ctxid) {
1311                         case 0x3:
1312                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1313                                 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1314                                 break;
1315                         case 0x4:
1316                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1317                                 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1318                                 break;
1319                         case 0x7:
1320                                 /*
1321                                  * Increment the throttle interrupt counter
1322                                  */
1323                                 atomic64_inc(&smu->throttle_int_counter);
1324
1325                                 if (!atomic_read(&adev->throttling_logging_enabled))
1326                                         return 0;
1327
1328                                 if (__ratelimit(&adev->throttling_logging_rs))
1329                                         schedule_work(&smu->throttling_logging_work);
1330
1331                                 break;
1332                         }
1333                 }
1334         }
1335
1336         return 0;
1337 }
1338
1339 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1340 {
1341         .set = smu_v11_0_set_irq_state,
1342         .process = smu_v11_0_irq_process,
1343 };
1344
1345 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1346 {
1347         struct amdgpu_device *adev = smu->adev;
1348         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1349         int ret = 0;
1350
1351         irq_src->num_types = 1;
1352         irq_src->funcs = &smu_v11_0_irq_funcs;
1353
1354         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1355                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1356                                 irq_src);
1357         if (ret)
1358                 return ret;
1359
1360         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1361                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1362                                 irq_src);
1363         if (ret)
1364                 return ret;
1365
1366         /* Register CTF(GPIO_19) interrupt */
1367         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1368                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1369                                 irq_src);
1370         if (ret)
1371                 return ret;
1372
1373         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1374                                 0xfe,
1375                                 irq_src);
1376         if (ret)
1377                 return ret;
1378
1379         return ret;
1380 }
1381
1382 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1383                 struct pp_smu_nv_clock_table *max_clocks)
1384 {
1385         struct smu_table_context *table_context = &smu->smu_table;
1386         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1387
1388         if (!max_clocks || !table_context->max_sustainable_clocks)
1389                 return -EINVAL;
1390
1391         sustainable_clocks = table_context->max_sustainable_clocks;
1392
1393         max_clocks->dcfClockInKhz =
1394                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1395         max_clocks->displayClockInKhz =
1396                         (unsigned int) sustainable_clocks->display_clock * 1000;
1397         max_clocks->phyClockInKhz =
1398                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1399         max_clocks->pixelClockInKhz =
1400                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1401         max_clocks->uClockInKhz =
1402                         (unsigned int) sustainable_clocks->uclock * 1000;
1403         max_clocks->socClockInKhz =
1404                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1405         max_clocks->dscClockInKhz = 0;
1406         max_clocks->dppClockInKhz = 0;
1407         max_clocks->fabricClockInKhz = 0;
1408
1409         return 0;
1410 }
1411
1412 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1413 {
1414         int ret = 0;
1415
1416         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1417
1418         return ret;
1419 }
1420
1421 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1422 {
1423         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1424 }
1425
1426 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1427 {
1428         struct smu_baco_context *smu_baco = &smu->smu_baco;
1429         bool baco_support;
1430
1431         mutex_lock(&smu_baco->mutex);
1432         baco_support = smu_baco->platform_support;
1433         mutex_unlock(&smu_baco->mutex);
1434
1435         if (!baco_support)
1436                 return false;
1437
1438         /* Arcturus does not support this bit mask */
1439         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1440            !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1441                 return false;
1442
1443         return true;
1444 }
1445
1446 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1447 {
1448         struct smu_baco_context *smu_baco = &smu->smu_baco;
1449         enum smu_baco_state baco_state;
1450
1451         mutex_lock(&smu_baco->mutex);
1452         baco_state = smu_baco->state;
1453         mutex_unlock(&smu_baco->mutex);
1454
1455         return baco_state;
1456 }
1457
1458 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1459 {
1460         struct smu_baco_context *smu_baco = &smu->smu_baco;
1461         struct amdgpu_device *adev = smu->adev;
1462         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1463         uint32_t data;
1464         int ret = 0;
1465
1466         if (smu_v11_0_baco_get_state(smu) == state)
1467                 return 0;
1468
1469         mutex_lock(&smu_baco->mutex);
1470
1471         if (state == SMU_BACO_STATE_ENTER) {
1472                 if (!ras || !ras->supported) {
1473                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1474                         data |= 0x80000000;
1475                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1476
1477                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1478                 } else {
1479                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1480                 }
1481         } else {
1482                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1483                 if (ret)
1484                         goto out;
1485
1486                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1487                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1488                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1489         }
1490         if (ret)
1491                 goto out;
1492
1493         smu_baco->state = state;
1494 out:
1495         mutex_unlock(&smu_baco->mutex);
1496         return ret;
1497 }
1498
1499 int smu_v11_0_baco_enter(struct smu_context *smu)
1500 {
1501         struct amdgpu_device *adev = smu->adev;
1502         int ret = 0;
1503
1504         /* Arcturus does not need this audio workaround */
1505         if (adev->asic_type != CHIP_ARCTURUS) {
1506                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1507                 if (ret)
1508                         return ret;
1509         }
1510
1511         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1512         if (ret)
1513                 return ret;
1514
1515         msleep(10);
1516
1517         return ret;
1518 }
1519
1520 int smu_v11_0_baco_exit(struct smu_context *smu)
1521 {
1522         int ret = 0;
1523
1524         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1525         if (ret)
1526                 return ret;
1527
1528         return ret;
1529 }
1530
1531 int smu_v11_0_mode1_reset(struct smu_context *smu)
1532 {
1533         int ret = 0;
1534
1535         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1536         if (!ret)
1537                 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1538
1539         return ret;
1540 }
1541
1542 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1543                                                  uint32_t *min, uint32_t *max)
1544 {
1545         int ret = 0, clk_id = 0;
1546         uint32_t param = 0;
1547         uint32_t clock_limit;
1548
1549         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1550                 switch (clk_type) {
1551                 case SMU_MCLK:
1552                 case SMU_UCLK:
1553                         clock_limit = smu->smu_table.boot_values.uclk;
1554                         break;
1555                 case SMU_GFXCLK:
1556                 case SMU_SCLK:
1557                         clock_limit = smu->smu_table.boot_values.gfxclk;
1558                         break;
1559                 case SMU_SOCCLK:
1560                         clock_limit = smu->smu_table.boot_values.socclk;
1561                         break;
1562                 default:
1563                         clock_limit = 0;
1564                         break;
1565                 }
1566
1567                 /* clock in Mhz unit */
1568                 if (min)
1569                         *min = clock_limit / 100;
1570                 if (max)
1571                         *max = clock_limit / 100;
1572
1573                 return 0;
1574         }
1575
1576         clk_id = smu_cmn_to_asic_specific_index(smu,
1577                                                 CMN2ASIC_MAPPING_CLK,
1578                                                 clk_type);
1579         if (clk_id < 0) {
1580                 ret = -EINVAL;
1581                 goto failed;
1582         }
1583         param = (clk_id & 0xffff) << 16;
1584
1585         if (max) {
1586                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1587                 if (ret)
1588                         goto failed;
1589         }
1590
1591         if (min) {
1592                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1593                 if (ret)
1594                         goto failed;
1595         }
1596
1597 failed:
1598         return ret;
1599 }
1600
1601 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1602                                           enum smu_clk_type clk_type,
1603                                           uint32_t min,
1604                                           uint32_t max)
1605 {
1606         struct amdgpu_device *adev = smu->adev;
1607         int ret = 0, clk_id = 0;
1608         uint32_t param;
1609
1610         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1611                 return 0;
1612
1613         clk_id = smu_cmn_to_asic_specific_index(smu,
1614                                                 CMN2ASIC_MAPPING_CLK,
1615                                                 clk_type);
1616         if (clk_id < 0)
1617                 return clk_id;
1618
1619         if (clk_type == SMU_GFXCLK)
1620                 amdgpu_gfx_off_ctrl(adev, false);
1621
1622         if (max > 0) {
1623                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1624                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1625                                                   param, NULL);
1626                 if (ret)
1627                         goto out;
1628         }
1629
1630         if (min > 0) {
1631                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1632                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1633                                                   param, NULL);
1634                 if (ret)
1635                         goto out;
1636         }
1637
1638 out:
1639         if (clk_type == SMU_GFXCLK)
1640                 amdgpu_gfx_off_ctrl(adev, true);
1641
1642         return ret;
1643 }
1644
1645 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1646                                           enum smu_clk_type clk_type,
1647                                           uint32_t min,
1648                                           uint32_t max)
1649 {
1650         int ret = 0, clk_id = 0;
1651         uint32_t param;
1652
1653         if (min <= 0 && max <= 0)
1654                 return -EINVAL;
1655
1656         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1657                 return 0;
1658
1659         clk_id = smu_cmn_to_asic_specific_index(smu,
1660                                                 CMN2ASIC_MAPPING_CLK,
1661                                                 clk_type);
1662         if (clk_id < 0)
1663                 return clk_id;
1664
1665         if (max > 0) {
1666                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1667                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1668                                                   param, NULL);
1669                 if (ret)
1670                         return ret;
1671         }
1672
1673         if (min > 0) {
1674                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1675                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1676                                                   param, NULL);
1677                 if (ret)
1678                         return ret;
1679         }
1680
1681         return ret;
1682 }
1683
1684 int smu_v11_0_set_performance_level(struct smu_context *smu,
1685                                     enum amd_dpm_forced_level level)
1686 {
1687         struct smu_11_0_dpm_context *dpm_context =
1688                                 smu->smu_dpm.dpm_context;
1689         struct smu_11_0_dpm_table *gfx_table =
1690                                 &dpm_context->dpm_tables.gfx_table;
1691         struct smu_11_0_dpm_table *mem_table =
1692                                 &dpm_context->dpm_tables.uclk_table;
1693         struct smu_11_0_dpm_table *soc_table =
1694                                 &dpm_context->dpm_tables.soc_table;
1695         struct smu_umd_pstate_table *pstate_table =
1696                                 &smu->pstate_table;
1697         struct amdgpu_device *adev = smu->adev;
1698         uint32_t sclk_min = 0, sclk_max = 0;
1699         uint32_t mclk_min = 0, mclk_max = 0;
1700         uint32_t socclk_min = 0, socclk_max = 0;
1701         int ret = 0;
1702
1703         switch (level) {
1704         case AMD_DPM_FORCED_LEVEL_HIGH:
1705                 sclk_min = sclk_max = gfx_table->max;
1706                 mclk_min = mclk_max = mem_table->max;
1707                 socclk_min = socclk_max = soc_table->max;
1708                 break;
1709         case AMD_DPM_FORCED_LEVEL_LOW:
1710                 sclk_min = sclk_max = gfx_table->min;
1711                 mclk_min = mclk_max = mem_table->min;
1712                 socclk_min = socclk_max = soc_table->min;
1713                 break;
1714         case AMD_DPM_FORCED_LEVEL_AUTO:
1715                 sclk_min = gfx_table->min;
1716                 sclk_max = gfx_table->max;
1717                 mclk_min = mem_table->min;
1718                 mclk_max = mem_table->max;
1719                 socclk_min = soc_table->min;
1720                 socclk_max = soc_table->max;
1721                 break;
1722         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1723                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1724                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1725                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1726                 break;
1727         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1728                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1729                 break;
1730         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1731                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1732                 break;
1733         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1734                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1735                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1736                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1737                 break;
1738         case AMD_DPM_FORCED_LEVEL_MANUAL:
1739         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1740                 return 0;
1741         default:
1742                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1743                 return -EINVAL;
1744         }
1745
1746         /*
1747          * Separate MCLK and SOCCLK soft min/max settings are not allowed
1748          * on Arcturus.
1749          */
1750         if (adev->asic_type == CHIP_ARCTURUS) {
1751                 mclk_min = mclk_max = 0;
1752                 socclk_min = socclk_max = 0;
1753         }
1754
1755         if (sclk_min && sclk_max) {
1756                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1757                                                             SMU_GFXCLK,
1758                                                             sclk_min,
1759                                                             sclk_max);
1760                 if (ret)
1761                         return ret;
1762         }
1763
1764         if (mclk_min && mclk_max) {
1765                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1766                                                             SMU_MCLK,
1767                                                             mclk_min,
1768                                                             mclk_max);
1769                 if (ret)
1770                         return ret;
1771         }
1772
1773         if (socclk_min && socclk_max) {
1774                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1775                                                             SMU_SOCCLK,
1776                                                             socclk_min,
1777                                                             socclk_max);
1778                 if (ret)
1779                         return ret;
1780         }
1781
1782         return ret;
1783 }
1784
1785 int smu_v11_0_set_power_source(struct smu_context *smu,
1786                                enum smu_power_src_type power_src)
1787 {
1788         int pwr_source;
1789
1790         pwr_source = smu_cmn_to_asic_specific_index(smu,
1791                                                     CMN2ASIC_MAPPING_PWR,
1792                                                     (uint32_t)power_src);
1793         if (pwr_source < 0)
1794                 return -EINVAL;
1795
1796         return smu_cmn_send_smc_msg_with_param(smu,
1797                                         SMU_MSG_NotifyPowerSource,
1798                                         pwr_source,
1799                                         NULL);
1800 }
1801
1802 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1803                                     enum smu_clk_type clk_type,
1804                                     uint16_t level,
1805                                     uint32_t *value)
1806 {
1807         int ret = 0, clk_id = 0;
1808         uint32_t param;
1809
1810         if (!value)
1811                 return -EINVAL;
1812
1813         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1814                 return 0;
1815
1816         clk_id = smu_cmn_to_asic_specific_index(smu,
1817                                                 CMN2ASIC_MAPPING_CLK,
1818                                                 clk_type);
1819         if (clk_id < 0)
1820                 return clk_id;
1821
1822         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1823
1824         ret = smu_cmn_send_smc_msg_with_param(smu,
1825                                           SMU_MSG_GetDpmFreqByIndex,
1826                                           param,
1827                                           value);
1828         if (ret)
1829                 return ret;
1830
1831         /*
1832          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1833          * now, we un-support it
1834          */
1835         *value = *value & 0x7fffffff;
1836
1837         return ret;
1838 }
1839
1840 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1841                                   enum smu_clk_type clk_type,
1842                                   uint32_t *value)
1843 {
1844         return smu_v11_0_get_dpm_freq_by_index(smu,
1845                                                clk_type,
1846                                                0xff,
1847                                                value);
1848 }
1849
1850 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1851                                    enum smu_clk_type clk_type,
1852                                    struct smu_11_0_dpm_table *single_dpm_table)
1853 {
1854         int ret = 0;
1855         uint32_t clk;
1856         int i;
1857
1858         ret = smu_v11_0_get_dpm_level_count(smu,
1859                                             clk_type,
1860                                             &single_dpm_table->count);
1861         if (ret) {
1862                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1863                 return ret;
1864         }
1865
1866         for (i = 0; i < single_dpm_table->count; i++) {
1867                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1868                                                       clk_type,
1869                                                       i,
1870                                                       &clk);
1871                 if (ret) {
1872                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1873                         return ret;
1874                 }
1875
1876                 single_dpm_table->dpm_levels[i].value = clk;
1877                 single_dpm_table->dpm_levels[i].enabled = true;
1878
1879                 if (i == 0)
1880                         single_dpm_table->min = clk;
1881                 else if (i == single_dpm_table->count - 1)
1882                         single_dpm_table->max = clk;
1883         }
1884
1885         return 0;
1886 }
1887
1888 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1889                                   enum smu_clk_type clk_type,
1890                                   uint32_t *min_value,
1891                                   uint32_t *max_value)
1892 {
1893         uint32_t level_count = 0;
1894         int ret = 0;
1895
1896         if (!min_value && !max_value)
1897                 return -EINVAL;
1898
1899         if (min_value) {
1900                 /* by default, level 0 clock value as min value */
1901                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1902                                                       clk_type,
1903                                                       0,
1904                                                       min_value);
1905                 if (ret)
1906                         return ret;
1907         }
1908
1909         if (max_value) {
1910                 ret = smu_v11_0_get_dpm_level_count(smu,
1911                                                     clk_type,
1912                                                     &level_count);
1913                 if (ret)
1914                         return ret;
1915
1916                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1917                                                       clk_type,
1918                                                       level_count - 1,
1919                                                       max_value);
1920                 if (ret)
1921                         return ret;
1922         }
1923
1924         return ret;
1925 }
1926
1927 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1928 {
1929         struct amdgpu_device *adev = smu->adev;
1930
1931         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1932                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1933                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1934 }
1935
1936 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
1937 {
1938         uint32_t width_level;
1939
1940         width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
1941         if (width_level > LINK_WIDTH_MAX)
1942                 width_level = 0;
1943
1944         return link_width[width_level];
1945 }
1946
1947 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1948 {
1949         struct amdgpu_device *adev = smu->adev;
1950
1951         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1952                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1953                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1954 }
1955
1956 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
1957 {
1958         uint32_t speed_level;
1959
1960         speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
1961         if (speed_level > LINK_SPEED_MAX)
1962                 speed_level = 0;
1963
1964         return link_speed[speed_level];
1965 }
1966
1967 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
1968 {
1969         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
1970
1971         gpu_metrics->common_header.structure_size =
1972                                 sizeof(struct gpu_metrics_v1_0);
1973         gpu_metrics->common_header.format_revision = 1;
1974         gpu_metrics->common_header.content_revision = 0;
1975
1976         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1977 }
1978
1979 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
1980                               bool enablement)
1981 {
1982         int ret = 0;
1983
1984         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1985                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1986
1987         return ret;
1988 }
1989
1990 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
1991                                  bool enablement)
1992 {
1993         struct amdgpu_device *adev = smu->adev;
1994         int ret = 0;
1995
1996         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1997                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1998                 if (ret) {
1999                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2000                         return ret;
2001                 }
2002         }
2003
2004         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2005                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2006                 if (ret) {
2007                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2008                         return ret;
2009                 }
2010         }
2011
2012         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2013                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2014                 if (ret) {
2015                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2016                         return ret;
2017                 }
2018         }
2019
2020         return ret;
2021 }