drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  77         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  78         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  79         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  80         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  81         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  82         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  83         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  84         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  85         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  86         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  87         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  88         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  89         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  90         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  91         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  92         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  93         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  94         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  95         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  96         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  97         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  98         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  99         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 113         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 114         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 115         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 116         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 117         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 118         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 119         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 120         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 121         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 122         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 123         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 124         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 125         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 126         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 127         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 128         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 129         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 130 };
 131
 132 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 133         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 134         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 135         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 136         CLK_MAP(FCLK,           PPCLK_FCLK),
 137         CLK_MAP(UCLK,           PPCLK_UCLK),
 138         CLK_MAP(MCLK,           PPCLK_UCLK),
 139         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 140         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 141         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 142         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 143         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 144         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 145         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 146         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 147 };
 148
 149 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 150         FEA_MAP(DPM_PREFETCHER),
 151         FEA_MAP(DPM_GFXCLK),
 152         FEA_MAP(DPM_GFX_GPO),
 153         FEA_MAP(DPM_UCLK),
 154         FEA_MAP(DPM_FCLK),
 155         FEA_MAP(DPM_SOCCLK),
 156         FEA_MAP(DPM_MP0CLK),
 157         FEA_MAP(DPM_LINK),
 158         FEA_MAP(DPM_DCEFCLK),
 159         FEA_MAP(DPM_XGMI),
 160         FEA_MAP(MEM_VDDCI_SCALING),
 161         FEA_MAP(MEM_MVDD_SCALING),
 162         FEA_MAP(DS_GFXCLK),
 163         FEA_MAP(DS_SOCCLK),
 164         FEA_MAP(DS_FCLK),
 165         FEA_MAP(DS_LCLK),
 166         FEA_MAP(DS_DCEFCLK),
 167         FEA_MAP(DS_UCLK),
 168         FEA_MAP(GFX_ULV),
 169         FEA_MAP(FW_DSTATE),
 170         FEA_MAP(GFXOFF),
 171         FEA_MAP(BACO),
 172         FEA_MAP(MM_DPM_PG),
 173         FEA_MAP(RSMU_SMN_CG),
 174         FEA_MAP(PPT),
 175         FEA_MAP(TDC),
 176         FEA_MAP(APCC_PLUS),
 177         FEA_MAP(GTHR),
 178         FEA_MAP(ACDC),
 179         FEA_MAP(VR0HOT),
 180         FEA_MAP(VR1HOT),
 181         FEA_MAP(FW_CTF),
 182         FEA_MAP(FAN_CONTROL),
 183         FEA_MAP(THERMAL),
 184         FEA_MAP(GFX_DCS),
 185         FEA_MAP(RM),
 186         FEA_MAP(LED_DISPLAY),
 187         FEA_MAP(GFX_SS),
 188         FEA_MAP(OUT_OF_BAND_MONITOR),
 189         FEA_MAP(TEMP_DEPENDENT_VMIN),
 190         FEA_MAP(MMHUB_PG),
 191         FEA_MAP(ATHUB_PG),
 192         FEA_MAP(APCC_DFLL),
 193 };
 194
 195 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 196         TAB_MAP(PPTABLE),
 197         TAB_MAP(WATERMARKS),
 198         TAB_MAP(AVFS_PSM_DEBUG),
 199         TAB_MAP(AVFS_FUSE_OVERRIDE),
 200         TAB_MAP(PMSTATUSLOG),
 201         TAB_MAP(SMU_METRICS),
 202         TAB_MAP(DRIVER_SMU_CONFIG),
 203         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 204         TAB_MAP(OVERDRIVE),
 205         TAB_MAP(I2C_COMMANDS),
 206         TAB_MAP(PACE),
 207 };
 208
 209 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 210         PWR_MAP(AC),
 211         PWR_MAP(DC),
 212 };
 213
 214 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 222 };
 223
 224 static int
 225 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 226                                   uint32_t *feature_mask, uint32_t num)
 227 {
 228         struct amdgpu_device *adev = smu->adev;
 229
 230         if (num > 2)
 231                 return -EINVAL;
 232
 233         memset(feature_mask, 0, sizeof(uint32_t) * num);
 234
 235         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 236                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 237                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 238                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 239                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 240                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 241                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 242                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 243                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 244                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 245                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 246                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 247                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 248                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 249                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 250                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 251                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 252                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 253                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 254                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 255
 256         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 257                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 258                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 259         }
 260
 261         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 262                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 263                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 264                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 265
 266         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 267                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 268
 269         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 270                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 271
 272         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 273                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 274
 275         if (adev->pm.pp_feature & PP_ULV_MASK)
 276                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 277
 278         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 279                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 280
 281         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 282                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 283
 284         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 285                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 286
 287         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 288                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 289
 290         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 291             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 292                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 293
 294         return 0;
 295 }
 296
 297 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 298 {
 299         struct smu_table_context *table_context = &smu->smu_table;
 300         struct smu_11_0_7_powerplay_table *powerplay_table =
 301                 table_context->power_play_table;
 302         struct smu_baco_context *smu_baco = &smu->smu_baco;
 303
 304         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 305             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 306                 smu_baco->platform_support = true;
 307
 308         table_context->thermal_controller_type =
 309                 powerplay_table->thermal_controller_type;
 310
 311         return 0;
 312 }
 313
 314 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 315 {
 316         struct smu_table_context *table_context = &smu->smu_table;
 317         PPTable_t *smc_pptable = table_context->driver_pptable;
 318         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 319         int index, ret;
 320
 321         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 322                                             smc_dpm_info);
 323
 324         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 325                                       (uint8_t **)&smc_dpm_table);
 326         if (ret)
 327                 return ret;
 328
 329         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 330                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 331
 332         return 0;
 333 }
 334
 335 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 336 {
 337         struct smu_table_context *table_context = &smu->smu_table;
 338         struct smu_11_0_7_powerplay_table *powerplay_table =
 339                 table_context->power_play_table;
 340
 341         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 342                sizeof(PPTable_t));
 343
 344         return 0;
 345 }
 346
 347 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 348 {
 349         int ret = 0;
 350
 351         ret = smu_v11_0_setup_pptable(smu);
 352         if (ret)
 353                 return ret;
 354
 355         ret = sienna_cichlid_store_powerplay_table(smu);
 356         if (ret)
 357                 return ret;
 358
 359         ret = sienna_cichlid_append_powerplay_table(smu);
 360         if (ret)
 361                 return ret;
 362
 363         ret = sienna_cichlid_check_powerplay_table(smu);
 364         if (ret)
 365                 return ret;
 366
 367         return ret;
 368 }
 369
 370 static int sienna_cichlid_tables_init(struct smu_context *smu)
 371 {
 372         struct smu_table_context *smu_table = &smu->smu_table;
 373         struct smu_table *tables = smu_table->tables;
 374
 375         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 376                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 377         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 378                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 379         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 380                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 381         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 382                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 383         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 384                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 385         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 386                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 387         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 388                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 389                        AMDGPU_GEM_DOMAIN_VRAM);
 390
 391         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 392         if (!smu_table->metrics_table)
 393                 goto err0_out;
 394         smu_table->metrics_time = 0;
 395
 396         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 397         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 398         if (!smu_table->gpu_metrics_table)
 399                 goto err1_out;
 400
 401         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 402         if (!smu_table->watermarks_table)
 403                 goto err2_out;
 404
 405         return 0;
 406
 407 err2_out:
 408         kfree(smu_table->gpu_metrics_table);
 409 err1_out:
 410         kfree(smu_table->metrics_table);
 411 err0_out:
 412         return -ENOMEM;
 413 }
 414
 415 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 416                                                MetricsMember_t member,
 417                                                uint32_t *value)
 418 {
 419         struct smu_table_context *smu_table= &smu->smu_table;
 420         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 421         int ret = 0;
 422
 423         mutex_lock(&smu->metrics_lock);
 424
 425         ret = smu_cmn_get_metrics_table_locked(smu,
 426                                                NULL,
 427                                                false);
 428         if (ret) {
 429                 mutex_unlock(&smu->metrics_lock);
 430                 return ret;
 431         }
 432
 433         switch (member) {
 434         case METRICS_CURR_GFXCLK:
 435                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 436                 break;
 437         case METRICS_CURR_SOCCLK:
 438                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 439                 break;
 440         case METRICS_CURR_UCLK:
 441                 *value = metrics->CurrClock[PPCLK_UCLK];
 442                 break;
 443         case METRICS_CURR_VCLK:
 444                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 445                 break;
 446         case METRICS_CURR_VCLK1:
 447                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 448                 break;
 449         case METRICS_CURR_DCLK:
 450                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 451                 break;
 452         case METRICS_CURR_DCLK1:
 453                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 454                 break;
 455         case METRICS_CURR_DCEFCLK:
 456                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 457                 break;
 458         case METRICS_CURR_FCLK:
 459                 *value = metrics->CurrClock[PPCLK_FCLK];
 460                 break;
 461         case METRICS_AVERAGE_GFXCLK:
 462                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 463                         *value = metrics->AverageGfxclkFrequencyPostDs;
 464                 else
 465                         *value = metrics->AverageGfxclkFrequencyPreDs;
 466                 break;
 467         case METRICS_AVERAGE_FCLK:
 468                 *value = metrics->AverageFclkFrequencyPostDs;
 469                 break;
 470         case METRICS_AVERAGE_UCLK:
 471                 *value = metrics->AverageUclkFrequencyPostDs;
 472                 break;
 473         case METRICS_AVERAGE_GFXACTIVITY:
 474                 *value = metrics->AverageGfxActivity;
 475                 break;
 476         case METRICS_AVERAGE_MEMACTIVITY:
 477                 *value = metrics->AverageUclkActivity;
 478                 break;
 479         case METRICS_AVERAGE_SOCKETPOWER:
 480                 *value = metrics->AverageSocketPower << 8;
 481                 break;
 482         case METRICS_TEMPERATURE_EDGE:
 483                 *value = metrics->TemperatureEdge *
 484                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 485                 break;
 486         case METRICS_TEMPERATURE_HOTSPOT:
 487                 *value = metrics->TemperatureHotspot *
 488                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 489                 break;
 490         case METRICS_TEMPERATURE_MEM:
 491                 *value = metrics->TemperatureMem *
 492                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 493                 break;
 494         case METRICS_TEMPERATURE_VRGFX:
 495                 *value = metrics->TemperatureVrGfx *
 496                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 497                 break;
 498         case METRICS_TEMPERATURE_VRSOC:
 499                 *value = metrics->TemperatureVrSoc *
 500                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 501                 break;
 502         case METRICS_THROTTLER_STATUS:
 503                 *value = metrics->ThrottlerStatus;
 504                 break;
 505         case METRICS_CURR_FANSPEED:
 506                 *value = metrics->CurrFanSpeed;
 507                 break;
 508         default:
 509                 *value = UINT_MAX;
 510                 break;
 511         }
 512
 513         mutex_unlock(&smu->metrics_lock);
 514
 515         return ret;
 516
 517 }
 518
 519 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 520 {
 521         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 522
 523         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 524                                        GFP_KERNEL);
 525         if (!smu_dpm->dpm_context)
 526                 return -ENOMEM;
 527
 528         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 529
 530         return 0;
 531 }
 532
 533 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 534 {
 535         int ret = 0;
 536
 537         ret = sienna_cichlid_tables_init(smu);
 538         if (ret)
 539                 return ret;
 540
 541         ret = sienna_cichlid_allocate_dpm_context(smu);
 542         if (ret)
 543                 return ret;
 544
 545         return smu_v11_0_init_smc_tables(smu);
 546 }
 547
 548 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 549 {
 550         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 551         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 552         struct smu_11_0_dpm_table *dpm_table;
 553         struct amdgpu_device *adev = smu->adev;
 554         int ret = 0;
 555
 556         /* socclk dpm table setup */
 557         dpm_table = &dpm_context->dpm_tables.soc_table;
 558         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 559                 ret = smu_v11_0_set_single_dpm_table(smu,
 560                                                      SMU_SOCCLK,
 561                                                      dpm_table);
 562                 if (ret)
 563                         return ret;
 564                 dpm_table->is_fine_grained =
 565                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 566         } else {
 567                 dpm_table->count = 1;
 568                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 569                 dpm_table->dpm_levels[0].enabled = true;
 570                 dpm_table->min = dpm_table->dpm_levels[0].value;
 571                 dpm_table->max = dpm_table->dpm_levels[0].value;
 572         }
 573
 574         /* gfxclk dpm table setup */
 575         dpm_table = &dpm_context->dpm_tables.gfx_table;
 576         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 577                 ret = smu_v11_0_set_single_dpm_table(smu,
 578                                                      SMU_GFXCLK,
 579                                                      dpm_table);
 580                 if (ret)
 581                         return ret;
 582                 dpm_table->is_fine_grained =
 583                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 584         } else {
 585                 dpm_table->count = 1;
 586                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 587                 dpm_table->dpm_levels[0].enabled = true;
 588                 dpm_table->min = dpm_table->dpm_levels[0].value;
 589                 dpm_table->max = dpm_table->dpm_levels[0].value;
 590         }
 591
 592         /* uclk dpm table setup */
 593         dpm_table = &dpm_context->dpm_tables.uclk_table;
 594         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 595                 ret = smu_v11_0_set_single_dpm_table(smu,
 596                                                      SMU_UCLK,
 597                                                      dpm_table);
 598                 if (ret)
 599                         return ret;
 600                 dpm_table->is_fine_grained =
 601                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 602         } else {
 603                 dpm_table->count = 1;
 604                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 605                 dpm_table->dpm_levels[0].enabled = true;
 606                 dpm_table->min = dpm_table->dpm_levels[0].value;
 607                 dpm_table->max = dpm_table->dpm_levels[0].value;
 608         }
 609
 610         /* fclk dpm table setup */
 611         dpm_table = &dpm_context->dpm_tables.fclk_table;
 612         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 613                 ret = smu_v11_0_set_single_dpm_table(smu,
 614                                                      SMU_FCLK,
 615                                                      dpm_table);
 616                 if (ret)
 617                         return ret;
 618                 dpm_table->is_fine_grained =
 619                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 620         } else {
 621                 dpm_table->count = 1;
 622                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 623                 dpm_table->dpm_levels[0].enabled = true;
 624                 dpm_table->min = dpm_table->dpm_levels[0].value;
 625                 dpm_table->max = dpm_table->dpm_levels[0].value;
 626         }
 627
 628         /* vclk0 dpm table setup */
 629         dpm_table = &dpm_context->dpm_tables.vclk_table;
 630         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 631                 ret = smu_v11_0_set_single_dpm_table(smu,
 632                                                      SMU_VCLK,
 633                                                      dpm_table);
 634                 if (ret)
 635                         return ret;
 636                 dpm_table->is_fine_grained =
 637                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 638         } else {
 639                 dpm_table->count = 1;
 640                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 641                 dpm_table->dpm_levels[0].enabled = true;
 642                 dpm_table->min = dpm_table->dpm_levels[0].value;
 643                 dpm_table->max = dpm_table->dpm_levels[0].value;
 644         }
 645
 646         /* vclk1 dpm table setup */
 647         if (adev->vcn.num_vcn_inst > 1) {
 648                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 649                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 650                         ret = smu_v11_0_set_single_dpm_table(smu,
 651                                                              SMU_VCLK1,
 652                                                              dpm_table);
 653                         if (ret)
 654                                 return ret;
 655                         dpm_table->is_fine_grained =
 656                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 657                 } else {
 658                         dpm_table->count = 1;
 659                         dpm_table->dpm_levels[0].value =
 660                                 smu->smu_table.boot_values.vclk / 100;
 661                         dpm_table->dpm_levels[0].enabled = true;
 662                         dpm_table->min = dpm_table->dpm_levels[0].value;
 663                         dpm_table->max = dpm_table->dpm_levels[0].value;
 664                 }
 665         }
 666
 667         /* dclk0 dpm table setup */
 668         dpm_table = &dpm_context->dpm_tables.dclk_table;
 669         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 670                 ret = smu_v11_0_set_single_dpm_table(smu,
 671                                                      SMU_DCLK,
 672                                                      dpm_table);
 673                 if (ret)
 674                         return ret;
 675                 dpm_table->is_fine_grained =
 676                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 677         } else {
 678                 dpm_table->count = 1;
 679                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 680                 dpm_table->dpm_levels[0].enabled = true;
 681                 dpm_table->min = dpm_table->dpm_levels[0].value;
 682                 dpm_table->max = dpm_table->dpm_levels[0].value;
 683         }
 684
 685         /* dclk1 dpm table setup */
 686         if (adev->vcn.num_vcn_inst > 1) {
 687                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 688                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 689                         ret = smu_v11_0_set_single_dpm_table(smu,
 690                                                              SMU_DCLK1,
 691                                                              dpm_table);
 692                         if (ret)
 693                                 return ret;
 694                         dpm_table->is_fine_grained =
 695                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 696                 } else {
 697                         dpm_table->count = 1;
 698                         dpm_table->dpm_levels[0].value =
 699                                 smu->smu_table.boot_values.dclk / 100;
 700                         dpm_table->dpm_levels[0].enabled = true;
 701                         dpm_table->min = dpm_table->dpm_levels[0].value;
 702                         dpm_table->max = dpm_table->dpm_levels[0].value;
 703                 }
 704         }
 705
 706         /* dcefclk dpm table setup */
 707         dpm_table = &dpm_context->dpm_tables.dcef_table;
 708         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 709                 ret = smu_v11_0_set_single_dpm_table(smu,
 710                                                      SMU_DCEFCLK,
 711                                                      dpm_table);
 712                 if (ret)
 713                         return ret;
 714                 dpm_table->is_fine_grained =
 715                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 716         } else {
 717                 dpm_table->count = 1;
 718                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 719                 dpm_table->dpm_levels[0].enabled = true;
 720                 dpm_table->min = dpm_table->dpm_levels[0].value;
 721                 dpm_table->max = dpm_table->dpm_levels[0].value;
 722         }
 723
 724         /* pixelclk dpm table setup */
 725         dpm_table = &dpm_context->dpm_tables.pixel_table;
 726         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 727                 ret = smu_v11_0_set_single_dpm_table(smu,
 728                                                      SMU_PIXCLK,
 729                                                      dpm_table);
 730                 if (ret)
 731                         return ret;
 732                 dpm_table->is_fine_grained =
 733                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 734         } else {
 735                 dpm_table->count = 1;
 736                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 737                 dpm_table->dpm_levels[0].enabled = true;
 738                 dpm_table->min = dpm_table->dpm_levels[0].value;
 739                 dpm_table->max = dpm_table->dpm_levels[0].value;
 740         }
 741
 742         /* displayclk dpm table setup */
 743         dpm_table = &dpm_context->dpm_tables.display_table;
 744         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 745                 ret = smu_v11_0_set_single_dpm_table(smu,
 746                                                      SMU_DISPCLK,
 747                                                      dpm_table);
 748                 if (ret)
 749                         return ret;
 750                 dpm_table->is_fine_grained =
 751                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 752         } else {
 753                 dpm_table->count = 1;
 754                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 755                 dpm_table->dpm_levels[0].enabled = true;
 756                 dpm_table->min = dpm_table->dpm_levels[0].value;
 757                 dpm_table->max = dpm_table->dpm_levels[0].value;
 758         }
 759
 760         /* phyclk dpm table setup */
 761         dpm_table = &dpm_context->dpm_tables.phy_table;
 762         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 763                 ret = smu_v11_0_set_single_dpm_table(smu,
 764                                                      SMU_PHYCLK,
 765                                                      dpm_table);
 766                 if (ret)
 767                         return ret;
 768                 dpm_table->is_fine_grained =
 769                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 770         } else {
 771                 dpm_table->count = 1;
 772                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 773                 dpm_table->dpm_levels[0].enabled = true;
 774                 dpm_table->min = dpm_table->dpm_levels[0].value;
 775                 dpm_table->max = dpm_table->dpm_levels[0].value;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 782 {
 783         struct amdgpu_device *adev = smu->adev;
 784         int ret = 0;
 785
 786         if (enable) {
 787                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 788                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 789                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 790                         if (ret)
 791                                 return ret;
 792                         if (adev->vcn.num_vcn_inst > 1) {
 793                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 794                                                                   0x10000, NULL);
 795                                 if (ret)
 796                                         return ret;
 797                         }
 798                 }
 799         } else {
 800                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 801                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 802                         if (ret)
 803                                 return ret;
 804                         if (adev->vcn.num_vcn_inst > 1) {
 805                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 806                                                                   0x10000, NULL);
 807                                 if (ret)
 808                                         return ret;
 809                         }
 810                 }
 811         }
 812
 813         return ret;
 814 }
 815
 816 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 817 {
 818         int ret = 0;
 819
 820         if (enable) {
 821                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 822                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 823                         if (ret)
 824                                 return ret;
 825                 }
 826         } else {
 827                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 828                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 829                         if (ret)
 830                                 return ret;
 831                 }
 832         }
 833
 834         return ret;
 835 }
 836
 837 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 838                                        enum smu_clk_type clk_type,
 839                                        uint32_t *value)
 840 {
 841         MetricsMember_t member_type;
 842         int clk_id = 0;
 843
 844         clk_id = smu_cmn_to_asic_specific_index(smu,
 845                                                 CMN2ASIC_MAPPING_CLK,
 846                                                 clk_type);
 847         if (clk_id < 0)
 848                 return clk_id;
 849
 850         switch (clk_id) {
 851         case PPCLK_GFXCLK:
 852                 member_type = METRICS_CURR_GFXCLK;
 853                 break;
 854         case PPCLK_UCLK:
 855                 member_type = METRICS_CURR_UCLK;
 856                 break;
 857         case PPCLK_SOCCLK:
 858                 member_type = METRICS_CURR_SOCCLK;
 859                 break;
 860         case PPCLK_FCLK:
 861                 member_type = METRICS_CURR_FCLK;
 862                 break;
 863         case PPCLK_VCLK_0:
 864                 member_type = METRICS_CURR_VCLK;
 865                 break;
 866         case PPCLK_VCLK_1:
 867                 member_type = METRICS_CURR_VCLK1;
 868                 break;
 869         case PPCLK_DCLK_0:
 870                 member_type = METRICS_CURR_DCLK;
 871                 break;
 872         case PPCLK_DCLK_1:
 873                 member_type = METRICS_CURR_DCLK1;
 874                 break;
 875         case PPCLK_DCEFCLK:
 876                 member_type = METRICS_CURR_DCEFCLK;
 877                 break;
 878         default:
 879                 return -EINVAL;
 880         }
 881
 882         return sienna_cichlid_get_smu_metrics_data(smu,
 883                                                    member_type,
 884                                                    value);
 885
 886 }
 887
 888 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 889 {
 890         PPTable_t *pptable = smu->smu_table.driver_pptable;
 891         DpmDescriptor_t *dpm_desc = NULL;
 892         uint32_t clk_index = 0;
 893
 894         clk_index = smu_cmn_to_asic_specific_index(smu,
 895                                                    CMN2ASIC_MAPPING_CLK,
 896                                                    clk_type);
 897         dpm_desc = &pptable->DpmDescriptor[clk_index];
 898
 899         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 900         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 901 }
 902
 903 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 904                         enum smu_clk_type clk_type, char *buf)
 905 {
 906         struct amdgpu_device *adev = smu->adev;
 907         struct smu_table_context *table_context = &smu->smu_table;
 908         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 909         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 910         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 911         int i, size = 0, ret = 0;
 912         uint32_t cur_value = 0, value = 0, count = 0;
 913         uint32_t freq_values[3] = {0};
 914         uint32_t mark_index = 0;
 915         uint32_t gen_speed, lane_width;
 916
 917         switch (clk_type) {
 918         case SMU_GFXCLK:
 919         case SMU_SCLK:
 920         case SMU_SOCCLK:
 921         case SMU_MCLK:
 922         case SMU_UCLK:
 923         case SMU_FCLK:
 924         case SMU_DCEFCLK:
 925                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 926                 if (ret)
 927                         goto print_clk_out;
 928
 929                 /* no need to disable gfxoff when retrieving the current gfxclk */
 930                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 931                         amdgpu_gfx_off_ctrl(adev, false);
 932
 933                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 934                 if (ret)
 935                         goto print_clk_out;
 936
 937                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 938                         for (i = 0; i < count; i++) {
 939                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 940                                 if (ret)
 941                                         goto print_clk_out;
 942
 943                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 944                                                 cur_value == value ? "*" : "");
 945                         }
 946                 } else {
 947                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 948                         if (ret)
 949                                 goto print_clk_out;
 950                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 951                         if (ret)
 952                                 goto print_clk_out;
 953
 954                         freq_values[1] = cur_value;
 955                         mark_index = cur_value == freq_values[0] ? 0 :
 956                                      cur_value == freq_values[2] ? 2 : 1;
 957
 958                         count = 3;
 959                         if (mark_index != 1) {
 960                                 count = 2;
 961                                 freq_values[1] = freq_values[2];
 962                         }
 963
 964                         for (i = 0; i < count; i++) {
 965                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 966                                                 cur_value  == freq_values[i] ? "*" : "");
 967                         }
 968
 969                 }
 970                 break;
 971         case SMU_PCIE:
 972                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 973                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 974                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 975                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 976                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 977                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 978                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 979                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 980                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 981                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 982                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 983                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 984                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 985                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 986                                         pptable->LclkFreq[i],
 987                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 988                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 989                                         "*" : "");
 990                 break;
 991         default:
 992                 break;
 993         }
 994
 995 print_clk_out:
 996         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 997                 amdgpu_gfx_off_ctrl(adev, true);
 998
 999         return size;
1000 }
1001
1002 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1003                                    enum smu_clk_type clk_type, uint32_t mask)
1004 {
1005         struct amdgpu_device *adev = smu->adev;
1006         int ret = 0, size = 0;
1007         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1008
1009         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1010         soft_max_level = mask ? (fls(mask) - 1) : 0;
1011
1012         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1013                 amdgpu_gfx_off_ctrl(adev, false);
1014
1015         switch (clk_type) {
1016         case SMU_GFXCLK:
1017         case SMU_SCLK:
1018         case SMU_SOCCLK:
1019         case SMU_MCLK:
1020         case SMU_UCLK:
1021         case SMU_DCEFCLK:
1022         case SMU_FCLK:
1023                 /* There is only 2 levels for fine grained DPM */
1024                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1025                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1026                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1027                 }
1028
1029                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1030                 if (ret)
1031                         goto forec_level_out;
1032
1033                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1034                 if (ret)
1035                         goto forec_level_out;
1036
1037                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1038                 if (ret)
1039                         goto forec_level_out;
1040                 break;
1041         default:
1042                 break;
1043         }
1044
1045 forec_level_out:
1046         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1047                 amdgpu_gfx_off_ctrl(adev, true);
1048
1049         return size;
1050 }
1051
1052 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1053 {
1054         struct smu_11_0_dpm_context *dpm_context =
1055                                 smu->smu_dpm.dpm_context;
1056         struct smu_11_0_dpm_table *gfx_table =
1057                                 &dpm_context->dpm_tables.gfx_table;
1058         struct smu_11_0_dpm_table *mem_table =
1059                                 &dpm_context->dpm_tables.uclk_table;
1060         struct smu_11_0_dpm_table *soc_table =
1061                                 &dpm_context->dpm_tables.soc_table;
1062         struct smu_umd_pstate_table *pstate_table =
1063                                 &smu->pstate_table;
1064
1065         pstate_table->gfxclk_pstate.min = gfx_table->min;
1066         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1067
1068         pstate_table->uclk_pstate.min = mem_table->min;
1069         pstate_table->uclk_pstate.peak = mem_table->max;
1070
1071         pstate_table->socclk_pstate.min = soc_table->min;
1072         pstate_table->socclk_pstate.peak = soc_table->max;
1073
1074         return 0;
1075 }
1076
1077 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1078 {
1079         int ret = 0;
1080         uint32_t max_freq = 0;
1081
1082         /* Sienna_Cichlid do not support to change display num currently */
1083         return 0;
1084 #if 0
1085         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1086         if (ret)
1087                 return ret;
1088 #endif
1089
1090         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1091                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1092                 if (ret)
1093                         return ret;
1094                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1095                 if (ret)
1096                         return ret;
1097         }
1098
1099         return ret;
1100 }
1101
1102 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1103 {
1104         int ret = 0;
1105
1106         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1107             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1108             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1109 #if 0
1110                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1111                                                   smu->display_config->num_display,
1112                                                   NULL);
1113 #endif
1114                 if (ret)
1115                         return ret;
1116         }
1117
1118         return ret;
1119 }
1120
1121 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1122 {
1123         if (!value)
1124                 return -EINVAL;
1125
1126         return sienna_cichlid_get_smu_metrics_data(smu,
1127                                                    METRICS_AVERAGE_SOCKETPOWER,
1128                                                    value);
1129 }
1130
1131 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1132                                                enum amd_pp_sensors sensor,
1133                                                uint32_t *value)
1134 {
1135         int ret = 0;
1136
1137         if (!value)
1138                 return -EINVAL;
1139
1140         switch (sensor) {
1141         case AMDGPU_PP_SENSOR_GPU_LOAD:
1142                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1143                                                           METRICS_AVERAGE_GFXACTIVITY,
1144                                                           value);
1145                 break;
1146         case AMDGPU_PP_SENSOR_MEM_LOAD:
1147                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1148                                                           METRICS_AVERAGE_MEMACTIVITY,
1149                                                           value);
1150                 break;
1151         default:
1152                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1153                 return -EINVAL;
1154         }
1155
1156         return ret;
1157 }
1158
1159 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1160 {
1161         int ret = 0;
1162         uint32_t feature_mask[2];
1163         uint64_t feature_enabled;
1164
1165         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1166         if (ret)
1167                 return false;
1168
1169         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1170
1171         return !!(feature_enabled & SMC_DPM_FEATURE);
1172 }
1173
1174 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1175                                     uint32_t *speed)
1176 {
1177         if (!speed)
1178                 return -EINVAL;
1179
1180         switch (smu_v11_0_get_fan_control_mode(smu)) {
1181         case AMD_FAN_CTRL_AUTO:
1182                 return sienna_cichlid_get_smu_metrics_data(smu,
1183                                                            METRICS_CURR_FANSPEED,
1184                                                            speed);
1185         default:
1186                 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1187         }
1188 }
1189
1190 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1191 {
1192         PPTable_t *pptable = smu->smu_table.driver_pptable;
1193
1194         smu->fan_max_rpm = pptable->FanMaximumRpm;
1195
1196         return 0;
1197 }
1198
1199 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1200 {
1201         DpmActivityMonitorCoeffInt_t activity_monitor;
1202         uint32_t i, size = 0;
1203         int16_t workload_type = 0;
1204         static const char *profile_name[] = {
1205                                         "BOOTUP_DEFAULT",
1206                                         "3D_FULL_SCREEN",
1207                                         "POWER_SAVING",
1208                                         "VIDEO",
1209                                         "VR",
1210                                         "COMPUTE",
1211                                         "CUSTOM"};
1212         static const char *title[] = {
1213                         "PROFILE_INDEX(NAME)",
1214                         "CLOCK_TYPE(NAME)",
1215                         "FPS",
1216                         "MinFreqType",
1217                         "MinActiveFreqType",
1218                         "MinActiveFreq",
1219                         "BoosterFreqType",
1220                         "BoosterFreq",
1221                         "PD_Data_limit_c",
1222                         "PD_Data_error_coeff",
1223                         "PD_Data_error_rate_coeff"};
1224         int result = 0;
1225
1226         if (!buf)
1227                 return -EINVAL;
1228
1229         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1230                         title[0], title[1], title[2], title[3], title[4], title[5],
1231                         title[6], title[7], title[8], title[9], title[10]);
1232
1233         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1234                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1235                 workload_type = smu_cmn_to_asic_specific_index(smu,
1236                                                                CMN2ASIC_MAPPING_WORKLOAD,
1237                                                                i);
1238                 if (workload_type < 0)
1239                         return -EINVAL;
1240
1241                 result = smu_cmn_update_table(smu,
1242                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1243                                           (void *)(&activity_monitor), false);
1244                 if (result) {
1245                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1246                         return result;
1247                 }
1248
1249                 size += sprintf(buf + size, "%2d %14s%s:\n",
1250                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1251
1252                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1253                         " ",
1254                         0,
1255                         "GFXCLK",
1256                         activity_monitor.Gfx_FPS,
1257                         activity_monitor.Gfx_MinFreqStep,
1258                         activity_monitor.Gfx_MinActiveFreqType,
1259                         activity_monitor.Gfx_MinActiveFreq,
1260                         activity_monitor.Gfx_BoosterFreqType,
1261                         activity_monitor.Gfx_BoosterFreq,
1262                         activity_monitor.Gfx_PD_Data_limit_c,
1263                         activity_monitor.Gfx_PD_Data_error_coeff,
1264                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1265
1266                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1267                         " ",
1268                         1,
1269                         "SOCCLK",
1270                         activity_monitor.Fclk_FPS,
1271                         activity_monitor.Fclk_MinFreqStep,
1272                         activity_monitor.Fclk_MinActiveFreqType,
1273                         activity_monitor.Fclk_MinActiveFreq,
1274                         activity_monitor.Fclk_BoosterFreqType,
1275                         activity_monitor.Fclk_BoosterFreq,
1276                         activity_monitor.Fclk_PD_Data_limit_c,
1277                         activity_monitor.Fclk_PD_Data_error_coeff,
1278                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1279
1280                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1281                         " ",
1282                         2,
1283                         "MEMLK",
1284                         activity_monitor.Mem_FPS,
1285                         activity_monitor.Mem_MinFreqStep,
1286                         activity_monitor.Mem_MinActiveFreqType,
1287                         activity_monitor.Mem_MinActiveFreq,
1288                         activity_monitor.Mem_BoosterFreqType,
1289                         activity_monitor.Mem_BoosterFreq,
1290                         activity_monitor.Mem_PD_Data_limit_c,
1291                         activity_monitor.Mem_PD_Data_error_coeff,
1292                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1293         }
1294
1295         return size;
1296 }
1297
1298 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1299 {
1300         DpmActivityMonitorCoeffInt_t activity_monitor;
1301         int workload_type, ret = 0;
1302
1303         smu->power_profile_mode = input[size];
1304
1305         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1306                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1307                 return -EINVAL;
1308         }
1309
1310         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1311
1312                 ret = smu_cmn_update_table(smu,
1313                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1314                                        (void *)(&activity_monitor), false);
1315                 if (ret) {
1316                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1317                         return ret;
1318                 }
1319
1320                 switch (input[0]) {
1321                 case 0: /* Gfxclk */
1322                         activity_monitor.Gfx_FPS = input[1];
1323                         activity_monitor.Gfx_MinFreqStep = input[2];
1324                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1325                         activity_monitor.Gfx_MinActiveFreq = input[4];
1326                         activity_monitor.Gfx_BoosterFreqType = input[5];
1327                         activity_monitor.Gfx_BoosterFreq = input[6];
1328                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1329                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1330                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1331                         break;
1332                 case 1: /* Socclk */
1333                         activity_monitor.Fclk_FPS = input[1];
1334                         activity_monitor.Fclk_MinFreqStep = input[2];
1335                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1336                         activity_monitor.Fclk_MinActiveFreq = input[4];
1337                         activity_monitor.Fclk_BoosterFreqType = input[5];
1338                         activity_monitor.Fclk_BoosterFreq = input[6];
1339                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1340                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1341                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1342                         break;
1343                 case 2: /* Memlk */
1344                         activity_monitor.Mem_FPS = input[1];
1345                         activity_monitor.Mem_MinFreqStep = input[2];
1346                         activity_monitor.Mem_MinActiveFreqType = input[3];
1347                         activity_monitor.Mem_MinActiveFreq = input[4];
1348                         activity_monitor.Mem_BoosterFreqType = input[5];
1349                         activity_monitor.Mem_BoosterFreq = input[6];
1350                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1351                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1352                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1353                         break;
1354                 }
1355
1356                 ret = smu_cmn_update_table(smu,
1357                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1358                                        (void *)(&activity_monitor), true);
1359                 if (ret) {
1360                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1361                         return ret;
1362                 }
1363         }
1364
1365         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1366         workload_type = smu_cmn_to_asic_specific_index(smu,
1367                                                        CMN2ASIC_MAPPING_WORKLOAD,
1368                                                        smu->power_profile_mode);
1369         if (workload_type < 0)
1370                 return -EINVAL;
1371         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1372                                     1 << workload_type, NULL);
1373
1374         return ret;
1375 }
1376
1377 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1378 {
1379         struct smu_clocks min_clocks = {0};
1380         struct pp_display_clock_request clock_req;
1381         int ret = 0;
1382
1383         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1384         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1385         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1386
1387         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1388                 clock_req.clock_type = amd_pp_dcef_clock;
1389                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1390
1391                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1392                 if (!ret) {
1393                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1394                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1395                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1396                                                                   min_clocks.dcef_clock_in_sr/100,
1397                                                                   NULL);
1398                                 if (ret) {
1399                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1400                                         return ret;
1401                                 }
1402                         }
1403                 } else {
1404                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1405                 }
1406         }
1407
1408         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1409                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1410                 if (ret) {
1411                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1412                         return ret;
1413                 }
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1420                                                struct pp_smu_wm_range_sets *clock_ranges)
1421 {
1422         Watermarks_t *table = smu->smu_table.watermarks_table;
1423         int ret = 0;
1424         int i;
1425
1426         if (clock_ranges) {
1427                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1428                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1429                         return -EINVAL;
1430
1431                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1432                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1433                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1434                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1435                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1436                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1437                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1438                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1439                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1440
1441                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1442                                 clock_ranges->reader_wm_sets[i].wm_inst;
1443                 }
1444
1445                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1446                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1447                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1448                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1449                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1450                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1451                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1452                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1453                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1454
1455                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1456                                 clock_ranges->writer_wm_sets[i].wm_inst;
1457                 }
1458
1459                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1460         }
1461
1462         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1463              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1464                 ret = smu_cmn_write_watermarks_table(smu);
1465                 if (ret) {
1466                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1467                         return ret;
1468                 }
1469                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1470         }
1471
1472         return 0;
1473 }
1474
1475 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1476                                              enum amd_pp_sensors sensor,
1477                                              uint32_t *value)
1478 {
1479         int ret = 0;
1480
1481         if (!value)
1482                 return -EINVAL;
1483
1484         switch (sensor) {
1485         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1486                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1487                                                           METRICS_TEMPERATURE_HOTSPOT,
1488                                                           value);
1489                 break;
1490         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1491                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1492                                                           METRICS_TEMPERATURE_EDGE,
1493                                                           value);
1494                 break;
1495         case AMDGPU_PP_SENSOR_MEM_TEMP:
1496                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1497                                                           METRICS_TEMPERATURE_MEM,
1498                                                           value);
1499                 break;
1500         default:
1501                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1502                 return -EINVAL;
1503         }
1504
1505         return ret;
1506 }
1507
1508 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1509                                  enum amd_pp_sensors sensor,
1510                                  void *data, uint32_t *size)
1511 {
1512         int ret = 0;
1513         struct smu_table_context *table_context = &smu->smu_table;
1514         PPTable_t *pptable = table_context->driver_pptable;
1515
1516         if(!data || !size)
1517                 return -EINVAL;
1518
1519         mutex_lock(&smu->sensor_lock);
1520         switch (sensor) {
1521         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1522                 *(uint32_t *)data = pptable->FanMaximumRpm;
1523                 *size = 4;
1524                 break;
1525         case AMDGPU_PP_SENSOR_MEM_LOAD:
1526         case AMDGPU_PP_SENSOR_GPU_LOAD:
1527                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1528                 *size = 4;
1529                 break;
1530         case AMDGPU_PP_SENSOR_GPU_POWER:
1531                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1532                 *size = 4;
1533                 break;
1534         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1535         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1536         case AMDGPU_PP_SENSOR_MEM_TEMP:
1537                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1538                 *size = 4;
1539                 break;
1540         case AMDGPU_PP_SENSOR_GFX_MCLK:
1541                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1542                 *(uint32_t *)data *= 100;
1543                 *size = 4;
1544                 break;
1545         case AMDGPU_PP_SENSOR_GFX_SCLK:
1546                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1547                 *(uint32_t *)data *= 100;
1548                 *size = 4;
1549                 break;
1550         case AMDGPU_PP_SENSOR_VDDGFX:
1551                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1552                 *size = 4;
1553                 break;
1554         default:
1555                 ret = -EOPNOTSUPP;
1556                 break;
1557         }
1558         mutex_unlock(&smu->sensor_lock);
1559
1560         return ret;
1561 }
1562
1563 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1564 {
1565         uint32_t num_discrete_levels = 0;
1566         uint16_t *dpm_levels = NULL;
1567         uint16_t i = 0;
1568         struct smu_table_context *table_context = &smu->smu_table;
1569         PPTable_t *driver_ppt = NULL;
1570
1571         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1572                 return -EINVAL;
1573
1574         driver_ppt = table_context->driver_pptable;
1575         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1576         dpm_levels = driver_ppt->FreqTableUclk;
1577
1578         if (num_discrete_levels == 0 || dpm_levels == NULL)
1579                 return -EINVAL;
1580
1581         *num_states = num_discrete_levels;
1582         for (i = 0; i < num_discrete_levels; i++) {
1583                 /* convert to khz */
1584                 *clocks_in_khz = (*dpm_levels) * 1000;
1585                 clocks_in_khz++;
1586                 dpm_levels++;
1587         }
1588
1589         return 0;
1590 }
1591
1592 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1593                                                 struct smu_temperature_range *range)
1594 {
1595         struct smu_table_context *table_context = &smu->smu_table;
1596         struct smu_11_0_7_powerplay_table *powerplay_table =
1597                                 table_context->power_play_table;
1598         PPTable_t *pptable = smu->smu_table.driver_pptable;
1599
1600         if (!range)
1601                 return -EINVAL;
1602
1603         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1604
1605         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1606                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1607         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1608                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1609         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1610                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1611         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1612                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1613         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1614                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1615         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1616                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1617         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1618
1619         return 0;
1620 }
1621
1622 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1623                                                 bool disable_memory_clock_switch)
1624 {
1625         int ret = 0;
1626         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1627                 (struct smu_11_0_max_sustainable_clocks *)
1628                         smu->smu_table.max_sustainable_clocks;
1629         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1630         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1631
1632         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1633                 return 0;
1634
1635         if(disable_memory_clock_switch)
1636                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1637         else
1638                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1639
1640         if(!ret)
1641                 smu->disable_uclk_switch = disable_memory_clock_switch;
1642
1643         return ret;
1644 }
1645
1646 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1647 {
1648         struct smu_11_0_7_powerplay_table *powerplay_table =
1649                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1650         PPTable_t *pptable = smu->smu_table.driver_pptable;
1651         uint32_t power_limit, od_percent;
1652
1653         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1654                 /* the last hope to figure out the ppt limit */
1655                 if (!pptable) {
1656                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1657                         return -EINVAL;
1658                 }
1659                 power_limit =
1660                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1661         }
1662         smu->current_power_limit = power_limit;
1663
1664         if (smu->od_enabled) {
1665                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1666
1667                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1668
1669                 power_limit *= (100 + od_percent);
1670                 power_limit /= 100;
1671         }
1672         smu->max_power_limit = power_limit;
1673
1674         return 0;
1675 }
1676
1677 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1678                                          uint32_t pcie_gen_cap,
1679                                          uint32_t pcie_width_cap)
1680 {
1681         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1682         PPTable_t *pptable = smu->smu_table.driver_pptable;
1683         uint32_t smu_pcie_arg;
1684         int ret, i;
1685
1686         /* lclk dpm table setup */
1687         for (i = 0; i < MAX_PCIE_CONF; i++) {
1688                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1689                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1690         }
1691
1692         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1693                 smu_pcie_arg = (i << 16) |
1694                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1695                                         (pptable->PcieGenSpeed[i] << 8) :
1696                                         (pcie_gen_cap << 8)) |
1697                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1698                                         pptable->PcieLaneCount[i] :
1699                                         pcie_width_cap);
1700
1701                 ret = smu_cmn_send_smc_msg_with_param(smu,
1702                                           SMU_MSG_OverridePcieParameters,
1703                                           smu_pcie_arg,
1704                                           NULL);
1705
1706                 if (ret)
1707                         return ret;
1708
1709                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1710                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1711                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1712                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1719                                 enum smu_clk_type clk_type,
1720                                 uint32_t *min, uint32_t *max)
1721 {
1722         struct amdgpu_device *adev = smu->adev;
1723         int ret;
1724
1725         if (clk_type == SMU_GFXCLK)
1726                 amdgpu_gfx_off_ctrl(adev, false);
1727         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1728         if (clk_type == SMU_GFXCLK)
1729                 amdgpu_gfx_off_ctrl(adev, true);
1730
1731         return ret;
1732 }
1733
1734 static int sienna_cichlid_run_btc(struct smu_context *smu)
1735 {
1736         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1737 }
1738
1739 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1740 {
1741         struct amdgpu_device *adev = smu->adev;
1742         uint32_t val;
1743
1744         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1745                 return false;
1746
1747         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1748         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1749 }
1750
1751 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1752 {
1753         struct amdgpu_device *adev = smu->adev;
1754         uint32_t val;
1755         u32 smu_version;
1756
1757         /**
1758          * SRIOV env will not support SMU mode1 reset
1759          * PM FW support mode1 reset from 58.26
1760          */
1761         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1762         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1763                 return false;
1764
1765         /**
1766          * mode1 reset relies on PSP, so we should check if
1767          * PSP is alive.
1768          */
1769         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1770         return val != 0x0;
1771 }
1772
1773 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1774 {
1775         struct smu_table_context *table_context = &smu->smu_table;
1776         PPTable_t *pptable = table_context->driver_pptable;
1777         int i;
1778
1779         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1780
1781         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1782         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1783         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1784
1785         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1786                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1787                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1788                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1789                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1790         }
1791
1792         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1793                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1794                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1795         }
1796
1797         for (i = 0; i < TEMP_COUNT; i++) {
1798                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1799         }
1800
1801         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1802         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1803         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1804         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1805         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1806
1807         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1808         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1809                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1810                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1811         }
1812         dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1813         dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1814         dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1815         dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1816
1817         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1818
1819         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1820
1821         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1822         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1823         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1824         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1825
1826         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1827         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1828
1829         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1830         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1831         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1832         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1833
1834         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1835         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1836         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1837         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1838
1839         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1840         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1841
1842         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1843         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1844         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1845         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1846         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1847         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1848         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1849         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1850
1851         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1852                         "  .VoltageMode          = 0x%02x\n"
1853                         "  .SnapToDiscrete       = 0x%02x\n"
1854                         "  .NumDiscreteLevels    = 0x%02x\n"
1855                         "  .padding              = 0x%02x\n"
1856                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1857                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1858                         "  .SsFmin               = 0x%04x\n"
1859                         "  .Padding_16           = 0x%04x\n",
1860                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1861                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1862                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1863                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1864                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1865                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1866                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1867                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1868                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1869                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1870                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1871
1872         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1873                         "  .VoltageMode          = 0x%02x\n"
1874                         "  .SnapToDiscrete       = 0x%02x\n"
1875                         "  .NumDiscreteLevels    = 0x%02x\n"
1876                         "  .padding              = 0x%02x\n"
1877                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1878                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1879                         "  .SsFmin               = 0x%04x\n"
1880                         "  .Padding_16           = 0x%04x\n",
1881                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1882                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1883                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1884                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1885                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1886                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1887                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1888                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1889                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1890                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1891                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1892
1893         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1894                         "  .VoltageMode          = 0x%02x\n"
1895                         "  .SnapToDiscrete       = 0x%02x\n"
1896                         "  .NumDiscreteLevels    = 0x%02x\n"
1897                         "  .padding              = 0x%02x\n"
1898                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1899                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1900                         "  .SsFmin               = 0x%04x\n"
1901                         "  .Padding_16           = 0x%04x\n",
1902                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1903                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1904                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1905                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1906                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1907                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1908                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1909                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1910                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1911                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1912                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1913
1914         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1915                         "  .VoltageMode          = 0x%02x\n"
1916                         "  .SnapToDiscrete       = 0x%02x\n"
1917                         "  .NumDiscreteLevels    = 0x%02x\n"
1918                         "  .padding              = 0x%02x\n"
1919                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1920                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1921                         "  .SsFmin               = 0x%04x\n"
1922                         "  .Padding_16           = 0x%04x\n",
1923                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1924                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1925                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1926                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1927                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1928                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1929                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1930                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1931                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1932                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1933                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1934
1935         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1936                         "  .VoltageMode          = 0x%02x\n"
1937                         "  .SnapToDiscrete       = 0x%02x\n"
1938                         "  .NumDiscreteLevels    = 0x%02x\n"
1939                         "  .padding              = 0x%02x\n"
1940                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1941                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1942                         "  .SsFmin               = 0x%04x\n"
1943                         "  .Padding_16           = 0x%04x\n",
1944                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1945                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1946                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1947                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1948                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1949                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1950                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1951                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1952                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1953                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1954                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1955
1956         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1957                         "  .VoltageMode          = 0x%02x\n"
1958                         "  .SnapToDiscrete       = 0x%02x\n"
1959                         "  .NumDiscreteLevels    = 0x%02x\n"
1960                         "  .padding              = 0x%02x\n"
1961                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1962                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1963                         "  .SsFmin               = 0x%04x\n"
1964                         "  .Padding_16           = 0x%04x\n",
1965                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1966                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1967                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1968                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1969                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1970                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1971                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1972                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1973                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1974                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1975                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1976
1977         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
1978                         "  .VoltageMode          = 0x%02x\n"
1979                         "  .SnapToDiscrete       = 0x%02x\n"
1980                         "  .NumDiscreteLevels    = 0x%02x\n"
1981                         "  .padding              = 0x%02x\n"
1982                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1983                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1984                         "  .SsFmin               = 0x%04x\n"
1985                         "  .Padding_16           = 0x%04x\n",
1986                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1987                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1988                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1989                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1990                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1991                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1992                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1993                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1994                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1995                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1996                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1997
1998         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
1999                         "  .VoltageMode          = 0x%02x\n"
2000                         "  .SnapToDiscrete       = 0x%02x\n"
2001                         "  .NumDiscreteLevels    = 0x%02x\n"
2002                         "  .padding              = 0x%02x\n"
2003                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2004                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2005                         "  .SsFmin               = 0x%04x\n"
2006                         "  .Padding_16           = 0x%04x\n",
2007                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2008                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2009                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2010                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2011                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2012                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2013                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2014                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2015                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2016                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2017                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2018
2019         dev_info(smu->adev->dev, "FreqTableGfx\n");
2020         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2021                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2022
2023         dev_info(smu->adev->dev, "FreqTableVclk\n");
2024         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2025                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2026
2027         dev_info(smu->adev->dev, "FreqTableDclk\n");
2028         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2029                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2030
2031         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2032         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2033                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2034
2035         dev_info(smu->adev->dev, "FreqTableUclk\n");
2036         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2037                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2038
2039         dev_info(smu->adev->dev, "FreqTableFclk\n");
2040         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2041                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2042
2043         dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
2044         dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
2045         dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
2046         dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
2047         dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
2048         dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
2049         dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
2050         dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
2051         dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
2052         dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
2053         dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2054         dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2055         dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2056         dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2057         dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2058         dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2059
2060         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2061         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2062         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2063         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2064         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2065         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2066         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2067         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2068         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2069
2070         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2071         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2072                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2073
2074         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2075         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2076
2077         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2078         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2079                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2080
2081         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2082         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2083                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2084
2085         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2086         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2087                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2088
2089         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2090         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2091                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2092
2093         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2094         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2095         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2096         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2097         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2098
2099         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2100
2101         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2102         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2103         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2104         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2105         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2106         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2107         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2108         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2109         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2110         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2111         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2112
2113         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2114         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2115         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2116         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2117         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2118         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2119
2120         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2121         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2122         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2123         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2124         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2125
2126         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2127         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2128                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2129
2130         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2131         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2132         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2133         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2134
2135         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2136         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2137                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2138
2139         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2140         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2141                 pptable->UclkDpmSrcFreqRange.Fmin);
2142         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2143                 pptable->UclkDpmSrcFreqRange.Fmax);
2144         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2145         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2146                 pptable->UclkDpmTargFreqRange.Fmin);
2147         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2148                 pptable->UclkDpmTargFreqRange.Fmax);
2149         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2150         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2151
2152         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2153         for (i = 0; i < NUM_LINK_LEVELS; i++)
2154                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2155
2156         dev_info(smu->adev->dev, "PcieLaneCount\n");
2157         for (i = 0; i < NUM_LINK_LEVELS; i++)
2158                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2159
2160         dev_info(smu->adev->dev, "LclkFreq\n");
2161         for (i = 0; i < NUM_LINK_LEVELS; i++)
2162                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2163
2164         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2165         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2166
2167         dev_info(smu->adev->dev, "FanGain\n");
2168         for (i = 0; i < TEMP_COUNT; i++)
2169                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2170
2171         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2172         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2173         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2174         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2175         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2176         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2177         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2178         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2179         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2180         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2181         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2182         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2183
2184         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2185         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2186         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2187         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2188
2189         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2190         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2191         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2192         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2193
2194         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2195                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2196                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2197                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2198         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2199                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2200                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2201                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2202         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2203                         pptable->dBtcGbGfxPll.a,
2204                         pptable->dBtcGbGfxPll.b,
2205                         pptable->dBtcGbGfxPll.c);
2206         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2207                         pptable->dBtcGbGfxDfll.a,
2208                         pptable->dBtcGbGfxDfll.b,
2209                         pptable->dBtcGbGfxDfll.c);
2210         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2211                         pptable->dBtcGbSoc.a,
2212                         pptable->dBtcGbSoc.b,
2213                         pptable->dBtcGbSoc.c);
2214         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2215                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2216                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2217         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2218                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2219                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2220
2221         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2222         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2223                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2224                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2225                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2226                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2227         }
2228
2229         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2230                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2231                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2232                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2233         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2234                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2235                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2236                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2237
2238         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2239         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2240
2241         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2242         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2243         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2244         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2245
2246         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2247         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2248         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2249         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2250
2251         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2252         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2253
2254         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2255         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2256                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2257         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2258         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2259
2260         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2261         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2262                         pptable->ReservedEquation0.a,
2263                         pptable->ReservedEquation0.b,
2264                         pptable->ReservedEquation0.c);
2265         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2266                         pptable->ReservedEquation1.a,
2267                         pptable->ReservedEquation1.b,
2268                         pptable->ReservedEquation1.c);
2269         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2270                         pptable->ReservedEquation2.a,
2271                         pptable->ReservedEquation2.b,
2272                         pptable->ReservedEquation2.c);
2273         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2274                         pptable->ReservedEquation3.a,
2275                         pptable->ReservedEquation3.b,
2276                         pptable->ReservedEquation3.c);
2277
2278         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2279         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2280         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2281         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2282         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2283         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2284         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2285         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2286         dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2287
2288         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2289         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2290         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2291         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2292         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2293         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2294
2295         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2296                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2297                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2298                                 pptable->I2cControllers[i].Enabled);
2299                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2300                                 pptable->I2cControllers[i].Speed);
2301                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2302                                 pptable->I2cControllers[i].SlaveAddress);
2303                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2304                                 pptable->I2cControllers[i].ControllerPort);
2305                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2306                                 pptable->I2cControllers[i].ControllerName);
2307                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2308                                 pptable->I2cControllers[i].ThermalThrotter);
2309                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2310                                 pptable->I2cControllers[i].I2cProtocol);
2311                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2312                                 pptable->I2cControllers[i].PaddingConfig);
2313         }
2314
2315         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2316         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2317         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2318         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2319
2320         dev_info(smu->adev->dev, "Board Parameters:\n");
2321         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2322         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2323         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2324         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2325         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2326         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2327         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2328         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2329
2330         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2331         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2332         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2333
2334         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2335         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2336         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2337
2338         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2339         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2340         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2341
2342         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2343         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2344         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2345
2346         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2347
2348         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2349         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2350         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2351         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2352         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2353         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2354         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2355         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2356         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2357         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2358         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2359         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2360         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2361         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2362         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2363         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2364
2365         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2366         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2367         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2368
2369         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2370         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2371         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2372
2373         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2374         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2375
2376         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2377         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2378         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2379
2380         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2381         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2382         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2383         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2384         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2385
2386         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2387         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2388
2389         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2390         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2391                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2392         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2393         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2394                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2395         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2396         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2397                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2398         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2399         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2400                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2401
2402         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2403         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2404         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2405         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2406
2407         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2408         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2409         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2410         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2411         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2412         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2413         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2414         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2415         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2416         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2417         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2418
2419         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2420         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2421         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2422         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2423         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2424         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2425         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2426         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2427 }
2428
2429 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2430                                   uint8_t address, uint32_t numbytes,
2431                                   uint8_t *data)
2432 {
2433         int i;
2434
2435         req->I2CcontrollerPort = 0;
2436         req->I2CSpeed = 2;
2437         req->SlaveAddress = address;
2438         req->NumCmds = numbytes;
2439
2440         for (i = 0; i < numbytes; i++) {
2441                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2442
2443                 /* First 2 bytes are always write for lower 2b EEPROM address */
2444                 if (i < 2)
2445                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2446                 else
2447                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2448
2449
2450                 /* Add RESTART for read  after address filled */
2451                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2452
2453                 /* Add STOP in the end */
2454                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2455
2456                 /* Fill with data regardless if read or write to simplify code */
2457                 cmd->ReadWriteData = data[i];
2458         }
2459 }
2460
2461 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2462                                                uint8_t address,
2463                                                uint8_t *data,
2464                                                uint32_t numbytes)
2465 {
2466         uint32_t  i, ret = 0;
2467         SwI2cRequest_t req;
2468         struct amdgpu_device *adev = to_amdgpu_device(control);
2469         struct smu_table_context *smu_table = &adev->smu.smu_table;
2470         struct smu_table *table = &smu_table->driver_table;
2471
2472         if (numbytes > MAX_SW_I2C_COMMANDS) {
2473                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2474                         numbytes, MAX_SW_I2C_COMMANDS);
2475                 return -EINVAL;
2476         }
2477
2478         memset(&req, 0, sizeof(req));
2479         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2480
2481         mutex_lock(&adev->smu.mutex);
2482         /* Now read data starting with that address */
2483         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2484                                         true);
2485         mutex_unlock(&adev->smu.mutex);
2486
2487         if (!ret) {
2488                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2489
2490                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2491                 for (i = 0; i < numbytes; i++)
2492                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2493
2494                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2495                                   (uint16_t)address, numbytes);
2496
2497                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2498                                8, 1, data, numbytes, false);
2499         } else
2500                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2501
2502         return ret;
2503 }
2504
2505 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2506                                                 uint8_t address,
2507                                                 uint8_t *data,
2508                                                 uint32_t numbytes)
2509 {
2510         uint32_t ret;
2511         SwI2cRequest_t req;
2512         struct amdgpu_device *adev = to_amdgpu_device(control);
2513
2514         if (numbytes > MAX_SW_I2C_COMMANDS) {
2515                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2516                         numbytes, MAX_SW_I2C_COMMANDS);
2517                 return -EINVAL;
2518         }
2519
2520         memset(&req, 0, sizeof(req));
2521         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2522
2523         mutex_lock(&adev->smu.mutex);
2524         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2525         mutex_unlock(&adev->smu.mutex);
2526
2527         if (!ret) {
2528                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2529                                          (uint16_t)address, numbytes);
2530
2531                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2532                                8, 1, data, numbytes, false);
2533                 /*
2534                  * According to EEPROM spec there is a MAX of 10 ms required for
2535                  * EEPROM to flush internal RX buffer after STOP was issued at the
2536                  * end of write transaction. During this time the EEPROM will not be
2537                  * responsive to any more commands - so wait a bit more.
2538                  */
2539                 msleep(10);
2540
2541         } else
2542                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2543
2544         return ret;
2545 }
2546
2547 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2548                               struct i2c_msg *msgs, int num)
2549 {
2550         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2551         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2552
2553         for (i = 0; i < num; i++) {
2554                 /*
2555                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2556                  * once and hence the data needs to be spliced into chunks and sent each
2557                  * chunk separately
2558                  */
2559                 data_size = msgs[i].len - 2;
2560                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2561                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2562                 data_ptr = msgs[i].buf + 2;
2563
2564                 for (j = 0; j < data_size / data_chunk_size; j++) {
2565                         /* Insert the EEPROM dest addess, bits 0-15 */
2566                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2567                         data_chunk[1] = (next_eeprom_addr & 0xff);
2568
2569                         if (msgs[i].flags & I2C_M_RD) {
2570                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2571                                                              (uint8_t)msgs[i].addr,
2572                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2573
2574                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2575                         } else {
2576
2577                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2578
2579                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2580                                                               (uint8_t)msgs[i].addr,
2581                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2582                         }
2583
2584                         if (ret) {
2585                                 num = -EIO;
2586                                 goto fail;
2587                         }
2588
2589                         next_eeprom_addr += data_chunk_size;
2590                         data_ptr += data_chunk_size;
2591                 }
2592
2593                 if (data_size % data_chunk_size) {
2594                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2595                         data_chunk[1] = (next_eeprom_addr & 0xff);
2596
2597                         if (msgs[i].flags & I2C_M_RD) {
2598                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2599                                                              (uint8_t)msgs[i].addr,
2600                                                              data_chunk, (data_size % data_chunk_size) + 2);
2601
2602                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2603                         } else {
2604                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2605
2606                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2607                                                               (uint8_t)msgs[i].addr,
2608                                                               data_chunk, (data_size % data_chunk_size) + 2);
2609                         }
2610
2611                         if (ret) {
2612                                 num = -EIO;
2613                                 goto fail;
2614                         }
2615                 }
2616         }
2617
2618 fail:
2619         return num;
2620 }
2621
2622 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2623 {
2624         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2625 }
2626
2627
2628 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2629         .master_xfer = sienna_cichlid_i2c_xfer,
2630         .functionality = sienna_cichlid_i2c_func,
2631 };
2632
2633 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2634 {
2635         struct amdgpu_device *adev = to_amdgpu_device(control);
2636         int res;
2637
2638         control->owner = THIS_MODULE;
2639         control->class = I2C_CLASS_SPD;
2640         control->dev.parent = &adev->pdev->dev;
2641         control->algo = &sienna_cichlid_i2c_algo;
2642         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2643
2644         res = i2c_add_adapter(control);
2645         if (res)
2646                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2647
2648         return res;
2649 }
2650
2651 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2652 {
2653         i2c_del_adapter(control);
2654 }
2655
2656 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2657                                               void **table)
2658 {
2659         struct smu_table_context *smu_table = &smu->smu_table;
2660         struct gpu_metrics_v1_0 *gpu_metrics =
2661                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2662         SmuMetrics_t metrics;
2663         int ret = 0;
2664
2665         ret = smu_cmn_get_metrics_table(smu,
2666                                         &metrics,
2667                                         true);
2668         if (ret)
2669                 return ret;
2670
2671         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2672
2673         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2674         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2675         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2676         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2677         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2678         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2679
2680         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2681         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2682         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2683
2684         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2685         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2686
2687         if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2688                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2689         else
2690                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2691         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2692         gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2693         gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2694         gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2695         gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2696
2697         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2698         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2699         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2700         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2701         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2702         gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2703         gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2704
2705         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2706
2707         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2708
2709         gpu_metrics->pcie_link_width =
2710                         smu_v11_0_get_current_pcie_link_width(smu);
2711         gpu_metrics->pcie_link_speed =
2712                         smu_v11_0_get_current_pcie_link_speed(smu);
2713
2714         *table = (void *)gpu_metrics;
2715
2716         return sizeof(struct gpu_metrics_v1_0);
2717 }
2718
2719 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2720 {
2721         return smu_cmn_send_smc_msg_with_param(smu,
2722                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2723                                                0,
2724                                                NULL);
2725 }
2726
2727 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2728         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2729         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2730         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2731         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2732         .i2c_init = sienna_cichlid_i2c_control_init,
2733         .i2c_fini = sienna_cichlid_i2c_control_fini,
2734         .print_clk_levels = sienna_cichlid_print_clk_levels,
2735         .force_clk_levels = sienna_cichlid_force_clk_levels,
2736         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2737         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2738         .display_config_changed = sienna_cichlid_display_config_changed,
2739         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2740         .is_dpm_running = sienna_cichlid_is_dpm_running,
2741         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2742         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2743         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2744         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2745         .read_sensor = sienna_cichlid_read_sensor,
2746         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2747         .set_performance_level = smu_v11_0_set_performance_level,
2748         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2749         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2750         .get_power_limit = sienna_cichlid_get_power_limit,
2751         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2752         .dump_pptable = sienna_cichlid_dump_pptable,
2753         .init_microcode = smu_v11_0_init_microcode,
2754         .load_microcode = smu_v11_0_load_microcode,
2755         .init_smc_tables = sienna_cichlid_init_smc_tables,
2756         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2757         .init_power = smu_v11_0_init_power,
2758         .fini_power = smu_v11_0_fini_power,
2759         .check_fw_status = smu_v11_0_check_fw_status,
2760         .setup_pptable = sienna_cichlid_setup_pptable,
2761         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2762         .check_fw_version = smu_v11_0_check_fw_version,
2763         .write_pptable = smu_cmn_write_pptable,
2764         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2765         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2766         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2767         .system_features_control = smu_v11_0_system_features_control,
2768         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2769         .send_smc_msg = smu_cmn_send_smc_msg,
2770         .init_display_count = NULL,
2771         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2772         .get_enabled_mask = smu_cmn_get_enabled_mask,
2773         .feature_is_enabled = smu_cmn_feature_is_enabled,
2774         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2775         .notify_display_change = NULL,
2776         .set_power_limit = smu_v11_0_set_power_limit,
2777         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2778         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2779         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2780         .set_min_dcef_deep_sleep = NULL,
2781         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2782         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2783         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2784         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2785         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2786         .gfx_off_control = smu_v11_0_gfx_off_control,
2787         .register_irq_handler = smu_v11_0_register_irq_handler,
2788         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2789         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2790         .baco_is_support= sienna_cichlid_is_baco_supported,
2791         .baco_get_state = smu_v11_0_baco_get_state,
2792         .baco_set_state = smu_v11_0_baco_set_state,
2793         .baco_enter = smu_v11_0_baco_enter,
2794         .baco_exit = smu_v11_0_baco_exit,
2795         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2796         .mode1_reset = smu_v11_0_mode1_reset,
2797         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2798         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2799         .run_btc = sienna_cichlid_run_btc,
2800         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2801         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2802         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2803         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2804         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2805         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2806         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2807         .interrupt_work = smu_v11_0_interrupt_work,
2808 };
2809
2810 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2811 {
2812         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2813         smu->message_map = sienna_cichlid_message_map;
2814         smu->clock_map = sienna_cichlid_clk_map;
2815         smu->feature_map = sienna_cichlid_feature_mask_map;
2816         smu->table_map = sienna_cichlid_table_map;
2817         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2818         smu->workload_map = sienna_cichlid_workload_map;
2819 }