drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  77         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  78         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  79         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  80         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  81         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  82         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  83         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  84         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  85         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  86         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  87         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  88         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  89         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  90         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  91         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  92         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  93         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  94         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  95         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  96         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  97         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  98         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  99         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 113         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 114         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 115         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 116         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 117         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 118         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 119         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 120         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 121         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 122         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 123         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 124         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 125         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 126         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 127         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 128         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 129         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 130         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 131         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 132 };
 133
 134 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 135         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 136         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 137         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 138         CLK_MAP(FCLK,           PPCLK_FCLK),
 139         CLK_MAP(UCLK,           PPCLK_UCLK),
 140         CLK_MAP(MCLK,           PPCLK_UCLK),
 141         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 142         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 143         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 144         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 145         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 146         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 147         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 148         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 149 };
 150
 151 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 152         FEA_MAP(DPM_PREFETCHER),
 153         FEA_MAP(DPM_GFXCLK),
 154         FEA_MAP(DPM_GFX_GPO),
 155         FEA_MAP(DPM_UCLK),
 156         FEA_MAP(DPM_FCLK),
 157         FEA_MAP(DPM_SOCCLK),
 158         FEA_MAP(DPM_MP0CLK),
 159         FEA_MAP(DPM_LINK),
 160         FEA_MAP(DPM_DCEFCLK),
 161         FEA_MAP(DPM_XGMI),
 162         FEA_MAP(MEM_VDDCI_SCALING),
 163         FEA_MAP(MEM_MVDD_SCALING),
 164         FEA_MAP(DS_GFXCLK),
 165         FEA_MAP(DS_SOCCLK),
 166         FEA_MAP(DS_FCLK),
 167         FEA_MAP(DS_LCLK),
 168         FEA_MAP(DS_DCEFCLK),
 169         FEA_MAP(DS_UCLK),
 170         FEA_MAP(GFX_ULV),
 171         FEA_MAP(FW_DSTATE),
 172         FEA_MAP(GFXOFF),
 173         FEA_MAP(BACO),
 174         FEA_MAP(MM_DPM_PG),
 175         FEA_MAP(RSMU_SMN_CG),
 176         FEA_MAP(PPT),
 177         FEA_MAP(TDC),
 178         FEA_MAP(APCC_PLUS),
 179         FEA_MAP(GTHR),
 180         FEA_MAP(ACDC),
 181         FEA_MAP(VR0HOT),
 182         FEA_MAP(VR1HOT),
 183         FEA_MAP(FW_CTF),
 184         FEA_MAP(FAN_CONTROL),
 185         FEA_MAP(THERMAL),
 186         FEA_MAP(GFX_DCS),
 187         FEA_MAP(RM),
 188         FEA_MAP(LED_DISPLAY),
 189         FEA_MAP(GFX_SS),
 190         FEA_MAP(OUT_OF_BAND_MONITOR),
 191         FEA_MAP(TEMP_DEPENDENT_VMIN),
 192         FEA_MAP(MMHUB_PG),
 193         FEA_MAP(ATHUB_PG),
 194         FEA_MAP(APCC_DFLL),
 195 };
 196
 197 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 198         TAB_MAP(PPTABLE),
 199         TAB_MAP(WATERMARKS),
 200         TAB_MAP(AVFS_PSM_DEBUG),
 201         TAB_MAP(AVFS_FUSE_OVERRIDE),
 202         TAB_MAP(PMSTATUSLOG),
 203         TAB_MAP(SMU_METRICS),
 204         TAB_MAP(DRIVER_SMU_CONFIG),
 205         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 206         TAB_MAP(OVERDRIVE),
 207         TAB_MAP(I2C_COMMANDS),
 208         TAB_MAP(PACE),
 209 };
 210
 211 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 212         PWR_MAP(AC),
 213         PWR_MAP(DC),
 214 };
 215
 216 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 224 };
 225
 226 static int
 227 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 228                                   uint32_t *feature_mask, uint32_t num)
 229 {
 230         struct amdgpu_device *adev = smu->adev;
 231
 232         if (num > 2)
 233                 return -EINVAL;
 234
 235         memset(feature_mask, 0, sizeof(uint32_t) * num);
 236
 237         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 238                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 239                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 240                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 241                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 242                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 243                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 244                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 245                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 246                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 247                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 248                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 249                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 250                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 251                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 252                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 253                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 254                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 255                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 256                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 257
 258         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 259                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 260                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 261         }
 262
 263         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 264                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 265                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 266                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 267
 268         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 269                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 270
 271         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 272                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 273
 274         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 275                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 276
 277         if (adev->pm.pp_feature & PP_ULV_MASK)
 278                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 279
 280         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 281                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 282
 283         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 284                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 285
 286         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 287                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 288
 289         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 290                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 291
 292         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 293             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 294                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 295
 296         return 0;
 297 }
 298
 299 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 300 {
 301         struct smu_table_context *table_context = &smu->smu_table;
 302         struct smu_11_0_7_powerplay_table *powerplay_table =
 303                 table_context->power_play_table;
 304         struct smu_baco_context *smu_baco = &smu->smu_baco;
 305
 306         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 307                 smu->dc_controlled_by_gpio = true;
 308
 309         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 310             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 311                 smu_baco->platform_support = true;
 312
 313         table_context->thermal_controller_type =
 314                 powerplay_table->thermal_controller_type;
 315
 316         return 0;
 317 }
 318
 319 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 320 {
 321         struct smu_table_context *table_context = &smu->smu_table;
 322         PPTable_t *smc_pptable = table_context->driver_pptable;
 323         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 324         int index, ret;
 325
 326         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 327                                             smc_dpm_info);
 328
 329         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 330                                       (uint8_t **)&smc_dpm_table);
 331         if (ret)
 332                 return ret;
 333
 334         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 335                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 336
 337         return 0;
 338 }
 339
 340 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 341 {
 342         struct smu_table_context *table_context = &smu->smu_table;
 343         struct smu_11_0_7_powerplay_table *powerplay_table =
 344                 table_context->power_play_table;
 345
 346         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 347                sizeof(PPTable_t));
 348
 349         return 0;
 350 }
 351
 352 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 353 {
 354         int ret = 0;
 355
 356         ret = smu_v11_0_setup_pptable(smu);
 357         if (ret)
 358                 return ret;
 359
 360         ret = sienna_cichlid_store_powerplay_table(smu);
 361         if (ret)
 362                 return ret;
 363
 364         ret = sienna_cichlid_append_powerplay_table(smu);
 365         if (ret)
 366                 return ret;
 367
 368         ret = sienna_cichlid_check_powerplay_table(smu);
 369         if (ret)
 370                 return ret;
 371
 372         return ret;
 373 }
 374
 375 static int sienna_cichlid_tables_init(struct smu_context *smu)
 376 {
 377         struct smu_table_context *smu_table = &smu->smu_table;
 378         struct smu_table *tables = smu_table->tables;
 379
 380         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 381                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 382         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 383                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 384         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 385                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 386         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 387                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 388         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 389                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 390         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 391                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 392         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 393                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 394                        AMDGPU_GEM_DOMAIN_VRAM);
 395
 396         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 397         if (!smu_table->metrics_table)
 398                 goto err0_out;
 399         smu_table->metrics_time = 0;
 400
 401         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 402         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 403         if (!smu_table->gpu_metrics_table)
 404                 goto err1_out;
 405
 406         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 407         if (!smu_table->watermarks_table)
 408                 goto err2_out;
 409
 410         return 0;
 411
 412 err2_out:
 413         kfree(smu_table->gpu_metrics_table);
 414 err1_out:
 415         kfree(smu_table->metrics_table);
 416 err0_out:
 417         return -ENOMEM;
 418 }
 419
 420 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 421                                                MetricsMember_t member,
 422                                                uint32_t *value)
 423 {
 424         struct smu_table_context *smu_table= &smu->smu_table;
 425         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 426         int ret = 0;
 427
 428         mutex_lock(&smu->metrics_lock);
 429
 430         ret = smu_cmn_get_metrics_table_locked(smu,
 431                                                NULL,
 432                                                false);
 433         if (ret) {
 434                 mutex_unlock(&smu->metrics_lock);
 435                 return ret;
 436         }
 437
 438         switch (member) {
 439         case METRICS_CURR_GFXCLK:
 440                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 441                 break;
 442         case METRICS_CURR_SOCCLK:
 443                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 444                 break;
 445         case METRICS_CURR_UCLK:
 446                 *value = metrics->CurrClock[PPCLK_UCLK];
 447                 break;
 448         case METRICS_CURR_VCLK:
 449                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 450                 break;
 451         case METRICS_CURR_VCLK1:
 452                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 453                 break;
 454         case METRICS_CURR_DCLK:
 455                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 456                 break;
 457         case METRICS_CURR_DCLK1:
 458                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 459                 break;
 460         case METRICS_CURR_DCEFCLK:
 461                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 462                 break;
 463         case METRICS_CURR_FCLK:
 464                 *value = metrics->CurrClock[PPCLK_FCLK];
 465                 break;
 466         case METRICS_AVERAGE_GFXCLK:
 467                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 468                         *value = metrics->AverageGfxclkFrequencyPostDs;
 469                 else
 470                         *value = metrics->AverageGfxclkFrequencyPreDs;
 471                 break;
 472         case METRICS_AVERAGE_FCLK:
 473                 *value = metrics->AverageFclkFrequencyPostDs;
 474                 break;
 475         case METRICS_AVERAGE_UCLK:
 476                 *value = metrics->AverageUclkFrequencyPostDs;
 477                 break;
 478         case METRICS_AVERAGE_GFXACTIVITY:
 479                 *value = metrics->AverageGfxActivity;
 480                 break;
 481         case METRICS_AVERAGE_MEMACTIVITY:
 482                 *value = metrics->AverageUclkActivity;
 483                 break;
 484         case METRICS_AVERAGE_SOCKETPOWER:
 485                 *value = metrics->AverageSocketPower << 8;
 486                 break;
 487         case METRICS_TEMPERATURE_EDGE:
 488                 *value = metrics->TemperatureEdge *
 489                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 490                 break;
 491         case METRICS_TEMPERATURE_HOTSPOT:
 492                 *value = metrics->TemperatureHotspot *
 493                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 494                 break;
 495         case METRICS_TEMPERATURE_MEM:
 496                 *value = metrics->TemperatureMem *
 497                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 498                 break;
 499         case METRICS_TEMPERATURE_VRGFX:
 500                 *value = metrics->TemperatureVrGfx *
 501                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 502                 break;
 503         case METRICS_TEMPERATURE_VRSOC:
 504                 *value = metrics->TemperatureVrSoc *
 505                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 506                 break;
 507         case METRICS_THROTTLER_STATUS:
 508                 *value = metrics->ThrottlerStatus;
 509                 break;
 510         case METRICS_CURR_FANSPEED:
 511                 *value = metrics->CurrFanSpeed;
 512                 break;
 513         default:
 514                 *value = UINT_MAX;
 515                 break;
 516         }
 517
 518         mutex_unlock(&smu->metrics_lock);
 519
 520         return ret;
 521
 522 }
 523
 524 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 525 {
 526         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 527
 528         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 529                                        GFP_KERNEL);
 530         if (!smu_dpm->dpm_context)
 531                 return -ENOMEM;
 532
 533         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 534
 535         return 0;
 536 }
 537
 538 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 539 {
 540         int ret = 0;
 541
 542         ret = sienna_cichlid_tables_init(smu);
 543         if (ret)
 544                 return ret;
 545
 546         ret = sienna_cichlid_allocate_dpm_context(smu);
 547         if (ret)
 548                 return ret;
 549
 550         return smu_v11_0_init_smc_tables(smu);
 551 }
 552
 553 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 554 {
 555         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 556         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 557         struct smu_11_0_dpm_table *dpm_table;
 558         struct amdgpu_device *adev = smu->adev;
 559         int ret = 0;
 560
 561         /* socclk dpm table setup */
 562         dpm_table = &dpm_context->dpm_tables.soc_table;
 563         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 564                 ret = smu_v11_0_set_single_dpm_table(smu,
 565                                                      SMU_SOCCLK,
 566                                                      dpm_table);
 567                 if (ret)
 568                         return ret;
 569                 dpm_table->is_fine_grained =
 570                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 571         } else {
 572                 dpm_table->count = 1;
 573                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 574                 dpm_table->dpm_levels[0].enabled = true;
 575                 dpm_table->min = dpm_table->dpm_levels[0].value;
 576                 dpm_table->max = dpm_table->dpm_levels[0].value;
 577         }
 578
 579         /* gfxclk dpm table setup */
 580         dpm_table = &dpm_context->dpm_tables.gfx_table;
 581         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 582                 ret = smu_v11_0_set_single_dpm_table(smu,
 583                                                      SMU_GFXCLK,
 584                                                      dpm_table);
 585                 if (ret)
 586                         return ret;
 587                 dpm_table->is_fine_grained =
 588                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 589         } else {
 590                 dpm_table->count = 1;
 591                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 592                 dpm_table->dpm_levels[0].enabled = true;
 593                 dpm_table->min = dpm_table->dpm_levels[0].value;
 594                 dpm_table->max = dpm_table->dpm_levels[0].value;
 595         }
 596
 597         /* uclk dpm table setup */
 598         dpm_table = &dpm_context->dpm_tables.uclk_table;
 599         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 600                 ret = smu_v11_0_set_single_dpm_table(smu,
 601                                                      SMU_UCLK,
 602                                                      dpm_table);
 603                 if (ret)
 604                         return ret;
 605                 dpm_table->is_fine_grained =
 606                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 607         } else {
 608                 dpm_table->count = 1;
 609                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 610                 dpm_table->dpm_levels[0].enabled = true;
 611                 dpm_table->min = dpm_table->dpm_levels[0].value;
 612                 dpm_table->max = dpm_table->dpm_levels[0].value;
 613         }
 614
 615         /* fclk dpm table setup */
 616         dpm_table = &dpm_context->dpm_tables.fclk_table;
 617         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 618                 ret = smu_v11_0_set_single_dpm_table(smu,
 619                                                      SMU_FCLK,
 620                                                      dpm_table);
 621                 if (ret)
 622                         return ret;
 623                 dpm_table->is_fine_grained =
 624                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 625         } else {
 626                 dpm_table->count = 1;
 627                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 628                 dpm_table->dpm_levels[0].enabled = true;
 629                 dpm_table->min = dpm_table->dpm_levels[0].value;
 630                 dpm_table->max = dpm_table->dpm_levels[0].value;
 631         }
 632
 633         /* vclk0 dpm table setup */
 634         dpm_table = &dpm_context->dpm_tables.vclk_table;
 635         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 636                 ret = smu_v11_0_set_single_dpm_table(smu,
 637                                                      SMU_VCLK,
 638                                                      dpm_table);
 639                 if (ret)
 640                         return ret;
 641                 dpm_table->is_fine_grained =
 642                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 643         } else {
 644                 dpm_table->count = 1;
 645                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 646                 dpm_table->dpm_levels[0].enabled = true;
 647                 dpm_table->min = dpm_table->dpm_levels[0].value;
 648                 dpm_table->max = dpm_table->dpm_levels[0].value;
 649         }
 650
 651         /* vclk1 dpm table setup */
 652         if (adev->vcn.num_vcn_inst > 1) {
 653                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 654                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 655                         ret = smu_v11_0_set_single_dpm_table(smu,
 656                                                              SMU_VCLK1,
 657                                                              dpm_table);
 658                         if (ret)
 659                                 return ret;
 660                         dpm_table->is_fine_grained =
 661                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 662                 } else {
 663                         dpm_table->count = 1;
 664                         dpm_table->dpm_levels[0].value =
 665                                 smu->smu_table.boot_values.vclk / 100;
 666                         dpm_table->dpm_levels[0].enabled = true;
 667                         dpm_table->min = dpm_table->dpm_levels[0].value;
 668                         dpm_table->max = dpm_table->dpm_levels[0].value;
 669                 }
 670         }
 671
 672         /* dclk0 dpm table setup */
 673         dpm_table = &dpm_context->dpm_tables.dclk_table;
 674         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 675                 ret = smu_v11_0_set_single_dpm_table(smu,
 676                                                      SMU_DCLK,
 677                                                      dpm_table);
 678                 if (ret)
 679                         return ret;
 680                 dpm_table->is_fine_grained =
 681                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 682         } else {
 683                 dpm_table->count = 1;
 684                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 685                 dpm_table->dpm_levels[0].enabled = true;
 686                 dpm_table->min = dpm_table->dpm_levels[0].value;
 687                 dpm_table->max = dpm_table->dpm_levels[0].value;
 688         }
 689
 690         /* dclk1 dpm table setup */
 691         if (adev->vcn.num_vcn_inst > 1) {
 692                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 693                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 694                         ret = smu_v11_0_set_single_dpm_table(smu,
 695                                                              SMU_DCLK1,
 696                                                              dpm_table);
 697                         if (ret)
 698                                 return ret;
 699                         dpm_table->is_fine_grained =
 700                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 701                 } else {
 702                         dpm_table->count = 1;
 703                         dpm_table->dpm_levels[0].value =
 704                                 smu->smu_table.boot_values.dclk / 100;
 705                         dpm_table->dpm_levels[0].enabled = true;
 706                         dpm_table->min = dpm_table->dpm_levels[0].value;
 707                         dpm_table->max = dpm_table->dpm_levels[0].value;
 708                 }
 709         }
 710
 711         /* dcefclk dpm table setup */
 712         dpm_table = &dpm_context->dpm_tables.dcef_table;
 713         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 714                 ret = smu_v11_0_set_single_dpm_table(smu,
 715                                                      SMU_DCEFCLK,
 716                                                      dpm_table);
 717                 if (ret)
 718                         return ret;
 719                 dpm_table->is_fine_grained =
 720                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 721         } else {
 722                 dpm_table->count = 1;
 723                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 724                 dpm_table->dpm_levels[0].enabled = true;
 725                 dpm_table->min = dpm_table->dpm_levels[0].value;
 726                 dpm_table->max = dpm_table->dpm_levels[0].value;
 727         }
 728
 729         /* pixelclk dpm table setup */
 730         dpm_table = &dpm_context->dpm_tables.pixel_table;
 731         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 732                 ret = smu_v11_0_set_single_dpm_table(smu,
 733                                                      SMU_PIXCLK,
 734                                                      dpm_table);
 735                 if (ret)
 736                         return ret;
 737                 dpm_table->is_fine_grained =
 738                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 739         } else {
 740                 dpm_table->count = 1;
 741                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 742                 dpm_table->dpm_levels[0].enabled = true;
 743                 dpm_table->min = dpm_table->dpm_levels[0].value;
 744                 dpm_table->max = dpm_table->dpm_levels[0].value;
 745         }
 746
 747         /* displayclk dpm table setup */
 748         dpm_table = &dpm_context->dpm_tables.display_table;
 749         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 750                 ret = smu_v11_0_set_single_dpm_table(smu,
 751                                                      SMU_DISPCLK,
 752                                                      dpm_table);
 753                 if (ret)
 754                         return ret;
 755                 dpm_table->is_fine_grained =
 756                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 757         } else {
 758                 dpm_table->count = 1;
 759                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 760                 dpm_table->dpm_levels[0].enabled = true;
 761                 dpm_table->min = dpm_table->dpm_levels[0].value;
 762                 dpm_table->max = dpm_table->dpm_levels[0].value;
 763         }
 764
 765         /* phyclk dpm table setup */
 766         dpm_table = &dpm_context->dpm_tables.phy_table;
 767         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 768                 ret = smu_v11_0_set_single_dpm_table(smu,
 769                                                      SMU_PHYCLK,
 770                                                      dpm_table);
 771                 if (ret)
 772                         return ret;
 773                 dpm_table->is_fine_grained =
 774                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 775         } else {
 776                 dpm_table->count = 1;
 777                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 778                 dpm_table->dpm_levels[0].enabled = true;
 779                 dpm_table->min = dpm_table->dpm_levels[0].value;
 780                 dpm_table->max = dpm_table->dpm_levels[0].value;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 787 {
 788         struct amdgpu_device *adev = smu->adev;
 789         int ret = 0;
 790
 791         if (enable) {
 792                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 793                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 794                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 795                         if (ret)
 796                                 return ret;
 797                         if (adev->vcn.num_vcn_inst > 1) {
 798                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 799                                                                   0x10000, NULL);
 800                                 if (ret)
 801                                         return ret;
 802                         }
 803                 }
 804         } else {
 805                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 806                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 807                         if (ret)
 808                                 return ret;
 809                         if (adev->vcn.num_vcn_inst > 1) {
 810                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 811                                                                   0x10000, NULL);
 812                                 if (ret)
 813                                         return ret;
 814                         }
 815                 }
 816         }
 817
 818         return ret;
 819 }
 820
 821 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 822 {
 823         int ret = 0;
 824
 825         if (enable) {
 826                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 827                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 828                         if (ret)
 829                                 return ret;
 830                 }
 831         } else {
 832                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 833                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 834                         if (ret)
 835                                 return ret;
 836                 }
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 843                                        enum smu_clk_type clk_type,
 844                                        uint32_t *value)
 845 {
 846         MetricsMember_t member_type;
 847         int clk_id = 0;
 848
 849         clk_id = smu_cmn_to_asic_specific_index(smu,
 850                                                 CMN2ASIC_MAPPING_CLK,
 851                                                 clk_type);
 852         if (clk_id < 0)
 853                 return clk_id;
 854
 855         switch (clk_id) {
 856         case PPCLK_GFXCLK:
 857                 member_type = METRICS_CURR_GFXCLK;
 858                 break;
 859         case PPCLK_UCLK:
 860                 member_type = METRICS_CURR_UCLK;
 861                 break;
 862         case PPCLK_SOCCLK:
 863                 member_type = METRICS_CURR_SOCCLK;
 864                 break;
 865         case PPCLK_FCLK:
 866                 member_type = METRICS_CURR_FCLK;
 867                 break;
 868         case PPCLK_VCLK_0:
 869                 member_type = METRICS_CURR_VCLK;
 870                 break;
 871         case PPCLK_VCLK_1:
 872                 member_type = METRICS_CURR_VCLK1;
 873                 break;
 874         case PPCLK_DCLK_0:
 875                 member_type = METRICS_CURR_DCLK;
 876                 break;
 877         case PPCLK_DCLK_1:
 878                 member_type = METRICS_CURR_DCLK1;
 879                 break;
 880         case PPCLK_DCEFCLK:
 881                 member_type = METRICS_CURR_DCEFCLK;
 882                 break;
 883         default:
 884                 return -EINVAL;
 885         }
 886
 887         return sienna_cichlid_get_smu_metrics_data(smu,
 888                                                    member_type,
 889                                                    value);
 890
 891 }
 892
 893 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 894 {
 895         PPTable_t *pptable = smu->smu_table.driver_pptable;
 896         DpmDescriptor_t *dpm_desc = NULL;
 897         uint32_t clk_index = 0;
 898
 899         clk_index = smu_cmn_to_asic_specific_index(smu,
 900                                                    CMN2ASIC_MAPPING_CLK,
 901                                                    clk_type);
 902         dpm_desc = &pptable->DpmDescriptor[clk_index];
 903
 904         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 905         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 906 }
 907
 908 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 909                         enum smu_clk_type clk_type, char *buf)
 910 {
 911         struct amdgpu_device *adev = smu->adev;
 912         struct smu_table_context *table_context = &smu->smu_table;
 913         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 914         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 915         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 916         int i, size = 0, ret = 0;
 917         uint32_t cur_value = 0, value = 0, count = 0;
 918         uint32_t freq_values[3] = {0};
 919         uint32_t mark_index = 0;
 920         uint32_t gen_speed, lane_width;
 921
 922         switch (clk_type) {
 923         case SMU_GFXCLK:
 924         case SMU_SCLK:
 925         case SMU_SOCCLK:
 926         case SMU_MCLK:
 927         case SMU_UCLK:
 928         case SMU_FCLK:
 929         case SMU_DCEFCLK:
 930                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 931                 if (ret)
 932                         goto print_clk_out;
 933
 934                 /* no need to disable gfxoff when retrieving the current gfxclk */
 935                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 936                         amdgpu_gfx_off_ctrl(adev, false);
 937
 938                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 939                 if (ret)
 940                         goto print_clk_out;
 941
 942                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 943                         for (i = 0; i < count; i++) {
 944                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 945                                 if (ret)
 946                                         goto print_clk_out;
 947
 948                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 949                                                 cur_value == value ? "*" : "");
 950                         }
 951                 } else {
 952                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 953                         if (ret)
 954                                 goto print_clk_out;
 955                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 956                         if (ret)
 957                                 goto print_clk_out;
 958
 959                         freq_values[1] = cur_value;
 960                         mark_index = cur_value == freq_values[0] ? 0 :
 961                                      cur_value == freq_values[2] ? 2 : 1;
 962
 963                         count = 3;
 964                         if (mark_index != 1) {
 965                                 count = 2;
 966                                 freq_values[1] = freq_values[2];
 967                         }
 968
 969                         for (i = 0; i < count; i++) {
 970                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 971                                                 cur_value  == freq_values[i] ? "*" : "");
 972                         }
 973
 974                 }
 975                 break;
 976         case SMU_PCIE:
 977                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 978                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 979                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 980                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 981                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 982                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 983                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 984                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 985                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 986                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 987                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 988                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 989                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 990                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 991                                         pptable->LclkFreq[i],
 992                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 993                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 994                                         "*" : "");
 995                 break;
 996         default:
 997                 break;
 998         }
 999
1000 print_clk_out:
1001         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1002                 amdgpu_gfx_off_ctrl(adev, true);
1003
1004         return size;
1005 }
1006
1007 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1008                                    enum smu_clk_type clk_type, uint32_t mask)
1009 {
1010         struct amdgpu_device *adev = smu->adev;
1011         int ret = 0, size = 0;
1012         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1013
1014         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1015         soft_max_level = mask ? (fls(mask) - 1) : 0;
1016
1017         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1018                 amdgpu_gfx_off_ctrl(adev, false);
1019
1020         switch (clk_type) {
1021         case SMU_GFXCLK:
1022         case SMU_SCLK:
1023         case SMU_SOCCLK:
1024         case SMU_MCLK:
1025         case SMU_UCLK:
1026         case SMU_DCEFCLK:
1027         case SMU_FCLK:
1028                 /* There is only 2 levels for fine grained DPM */
1029                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1030                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1031                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1032                 }
1033
1034                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1035                 if (ret)
1036                         goto forec_level_out;
1037
1038                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1039                 if (ret)
1040                         goto forec_level_out;
1041
1042                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1043                 if (ret)
1044                         goto forec_level_out;
1045                 break;
1046         default:
1047                 break;
1048         }
1049
1050 forec_level_out:
1051         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1052                 amdgpu_gfx_off_ctrl(adev, true);
1053
1054         return size;
1055 }
1056
1057 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1058 {
1059         struct smu_11_0_dpm_context *dpm_context =
1060                                 smu->smu_dpm.dpm_context;
1061         struct smu_11_0_dpm_table *gfx_table =
1062                                 &dpm_context->dpm_tables.gfx_table;
1063         struct smu_11_0_dpm_table *mem_table =
1064                                 &dpm_context->dpm_tables.uclk_table;
1065         struct smu_11_0_dpm_table *soc_table =
1066                                 &dpm_context->dpm_tables.soc_table;
1067         struct smu_umd_pstate_table *pstate_table =
1068                                 &smu->pstate_table;
1069
1070         pstate_table->gfxclk_pstate.min = gfx_table->min;
1071         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1072
1073         pstate_table->uclk_pstate.min = mem_table->min;
1074         pstate_table->uclk_pstate.peak = mem_table->max;
1075
1076         pstate_table->socclk_pstate.min = soc_table->min;
1077         pstate_table->socclk_pstate.peak = soc_table->max;
1078
1079         return 0;
1080 }
1081
1082 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1083 {
1084         int ret = 0;
1085         uint32_t max_freq = 0;
1086
1087         /* Sienna_Cichlid do not support to change display num currently */
1088         return 0;
1089 #if 0
1090         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1091         if (ret)
1092                 return ret;
1093 #endif
1094
1095         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1096                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1097                 if (ret)
1098                         return ret;
1099                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1100                 if (ret)
1101                         return ret;
1102         }
1103
1104         return ret;
1105 }
1106
1107 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1108 {
1109         int ret = 0;
1110
1111         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1112             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1113             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1114 #if 0
1115                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1116                                                   smu->display_config->num_display,
1117                                                   NULL);
1118 #endif
1119                 if (ret)
1120                         return ret;
1121         }
1122
1123         return ret;
1124 }
1125
1126 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1127 {
1128         int ret = 0;
1129         uint32_t feature_mask[2];
1130         uint64_t feature_enabled;
1131
1132         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1133         if (ret)
1134                 return false;
1135
1136         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1137
1138         return !!(feature_enabled & SMC_DPM_FEATURE);
1139 }
1140
1141 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1142                                     uint32_t *speed)
1143 {
1144         if (!speed)
1145                 return -EINVAL;
1146
1147         return sienna_cichlid_get_smu_metrics_data(smu,
1148                                                 METRICS_CURR_FANSPEED,
1149                                                 speed);
1150 }
1151
1152 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1153 {
1154         PPTable_t *pptable = smu->smu_table.driver_pptable;
1155
1156         smu->fan_max_rpm = pptable->FanMaximumRpm;
1157
1158         return 0;
1159 }
1160
1161 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1162 {
1163         DpmActivityMonitorCoeffInt_t activity_monitor;
1164         uint32_t i, size = 0;
1165         int16_t workload_type = 0;
1166         static const char *profile_name[] = {
1167                                         "BOOTUP_DEFAULT",
1168                                         "3D_FULL_SCREEN",
1169                                         "POWER_SAVING",
1170                                         "VIDEO",
1171                                         "VR",
1172                                         "COMPUTE",
1173                                         "CUSTOM"};
1174         static const char *title[] = {
1175                         "PROFILE_INDEX(NAME)",
1176                         "CLOCK_TYPE(NAME)",
1177                         "FPS",
1178                         "MinFreqType",
1179                         "MinActiveFreqType",
1180                         "MinActiveFreq",
1181                         "BoosterFreqType",
1182                         "BoosterFreq",
1183                         "PD_Data_limit_c",
1184                         "PD_Data_error_coeff",
1185                         "PD_Data_error_rate_coeff"};
1186         int result = 0;
1187
1188         if (!buf)
1189                 return -EINVAL;
1190
1191         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1192                         title[0], title[1], title[2], title[3], title[4], title[5],
1193                         title[6], title[7], title[8], title[9], title[10]);
1194
1195         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1196                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1197                 workload_type = smu_cmn_to_asic_specific_index(smu,
1198                                                                CMN2ASIC_MAPPING_WORKLOAD,
1199                                                                i);
1200                 if (workload_type < 0)
1201                         return -EINVAL;
1202
1203                 result = smu_cmn_update_table(smu,
1204                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1205                                           (void *)(&activity_monitor), false);
1206                 if (result) {
1207                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1208                         return result;
1209                 }
1210
1211                 size += sprintf(buf + size, "%2d %14s%s:\n",
1212                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1213
1214                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1215                         " ",
1216                         0,
1217                         "GFXCLK",
1218                         activity_monitor.Gfx_FPS,
1219                         activity_monitor.Gfx_MinFreqStep,
1220                         activity_monitor.Gfx_MinActiveFreqType,
1221                         activity_monitor.Gfx_MinActiveFreq,
1222                         activity_monitor.Gfx_BoosterFreqType,
1223                         activity_monitor.Gfx_BoosterFreq,
1224                         activity_monitor.Gfx_PD_Data_limit_c,
1225                         activity_monitor.Gfx_PD_Data_error_coeff,
1226                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1227
1228                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1229                         " ",
1230                         1,
1231                         "SOCCLK",
1232                         activity_monitor.Fclk_FPS,
1233                         activity_monitor.Fclk_MinFreqStep,
1234                         activity_monitor.Fclk_MinActiveFreqType,
1235                         activity_monitor.Fclk_MinActiveFreq,
1236                         activity_monitor.Fclk_BoosterFreqType,
1237                         activity_monitor.Fclk_BoosterFreq,
1238                         activity_monitor.Fclk_PD_Data_limit_c,
1239                         activity_monitor.Fclk_PD_Data_error_coeff,
1240                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1241
1242                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1243                         " ",
1244                         2,
1245                         "MEMLK",
1246                         activity_monitor.Mem_FPS,
1247                         activity_monitor.Mem_MinFreqStep,
1248                         activity_monitor.Mem_MinActiveFreqType,
1249                         activity_monitor.Mem_MinActiveFreq,
1250                         activity_monitor.Mem_BoosterFreqType,
1251                         activity_monitor.Mem_BoosterFreq,
1252                         activity_monitor.Mem_PD_Data_limit_c,
1253                         activity_monitor.Mem_PD_Data_error_coeff,
1254                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1255         }
1256
1257         return size;
1258 }
1259
1260 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1261 {
1262         DpmActivityMonitorCoeffInt_t activity_monitor;
1263         int workload_type, ret = 0;
1264
1265         smu->power_profile_mode = input[size];
1266
1267         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1268                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1269                 return -EINVAL;
1270         }
1271
1272         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1273
1274                 ret = smu_cmn_update_table(smu,
1275                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1276                                        (void *)(&activity_monitor), false);
1277                 if (ret) {
1278                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1279                         return ret;
1280                 }
1281
1282                 switch (input[0]) {
1283                 case 0: /* Gfxclk */
1284                         activity_monitor.Gfx_FPS = input[1];
1285                         activity_monitor.Gfx_MinFreqStep = input[2];
1286                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1287                         activity_monitor.Gfx_MinActiveFreq = input[4];
1288                         activity_monitor.Gfx_BoosterFreqType = input[5];
1289                         activity_monitor.Gfx_BoosterFreq = input[6];
1290                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1291                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1292                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1293                         break;
1294                 case 1: /* Socclk */
1295                         activity_monitor.Fclk_FPS = input[1];
1296                         activity_monitor.Fclk_MinFreqStep = input[2];
1297                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1298                         activity_monitor.Fclk_MinActiveFreq = input[4];
1299                         activity_monitor.Fclk_BoosterFreqType = input[5];
1300                         activity_monitor.Fclk_BoosterFreq = input[6];
1301                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1302                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1303                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1304                         break;
1305                 case 2: /* Memlk */
1306                         activity_monitor.Mem_FPS = input[1];
1307                         activity_monitor.Mem_MinFreqStep = input[2];
1308                         activity_monitor.Mem_MinActiveFreqType = input[3];
1309                         activity_monitor.Mem_MinActiveFreq = input[4];
1310                         activity_monitor.Mem_BoosterFreqType = input[5];
1311                         activity_monitor.Mem_BoosterFreq = input[6];
1312                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1313                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1314                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1315                         break;
1316                 }
1317
1318                 ret = smu_cmn_update_table(smu,
1319                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1320                                        (void *)(&activity_monitor), true);
1321                 if (ret) {
1322                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1323                         return ret;
1324                 }
1325         }
1326
1327         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1328         workload_type = smu_cmn_to_asic_specific_index(smu,
1329                                                        CMN2ASIC_MAPPING_WORKLOAD,
1330                                                        smu->power_profile_mode);
1331         if (workload_type < 0)
1332                 return -EINVAL;
1333         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1334                                     1 << workload_type, NULL);
1335
1336         return ret;
1337 }
1338
1339 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1340 {
1341         struct smu_clocks min_clocks = {0};
1342         struct pp_display_clock_request clock_req;
1343         int ret = 0;
1344
1345         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1346         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1347         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1348
1349         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1350                 clock_req.clock_type = amd_pp_dcef_clock;
1351                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1352
1353                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1354                 if (!ret) {
1355                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1356                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1357                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1358                                                                   min_clocks.dcef_clock_in_sr/100,
1359                                                                   NULL);
1360                                 if (ret) {
1361                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1362                                         return ret;
1363                                 }
1364                         }
1365                 } else {
1366                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1367                 }
1368         }
1369
1370         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1371                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1372                 if (ret) {
1373                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1374                         return ret;
1375                 }
1376         }
1377
1378         return 0;
1379 }
1380
1381 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1382                                                struct pp_smu_wm_range_sets *clock_ranges)
1383 {
1384         Watermarks_t *table = smu->smu_table.watermarks_table;
1385         int ret = 0;
1386         int i;
1387
1388         if (clock_ranges) {
1389                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1390                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1391                         return -EINVAL;
1392
1393                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1394                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1395                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1396                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1397                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1398                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1399                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1400                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1401                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1402
1403                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1404                                 clock_ranges->reader_wm_sets[i].wm_inst;
1405                 }
1406
1407                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1408                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1409                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1410                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1411                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1412                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1413                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1414                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1415                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1416
1417                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1418                                 clock_ranges->writer_wm_sets[i].wm_inst;
1419                 }
1420
1421                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1422         }
1423
1424         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1425              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1426                 ret = smu_cmn_write_watermarks_table(smu);
1427                 if (ret) {
1428                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1429                         return ret;
1430                 }
1431                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1432         }
1433
1434         return 0;
1435 }
1436
1437 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1438                                  enum amd_pp_sensors sensor,
1439                                  void *data, uint32_t *size)
1440 {
1441         int ret = 0;
1442         struct smu_table_context *table_context = &smu->smu_table;
1443         PPTable_t *pptable = table_context->driver_pptable;
1444
1445         if(!data || !size)
1446                 return -EINVAL;
1447
1448         mutex_lock(&smu->sensor_lock);
1449         switch (sensor) {
1450         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1451                 *(uint32_t *)data = pptable->FanMaximumRpm;
1452                 *size = 4;
1453                 break;
1454         case AMDGPU_PP_SENSOR_MEM_LOAD:
1455                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1456                                                           METRICS_AVERAGE_MEMACTIVITY,
1457                                                           (uint32_t *)data);
1458                 *size = 4;
1459                 break;
1460         case AMDGPU_PP_SENSOR_GPU_LOAD:
1461                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1462                                                           METRICS_AVERAGE_GFXACTIVITY,
1463                                                           (uint32_t *)data);
1464                 *size = 4;
1465                 break;
1466         case AMDGPU_PP_SENSOR_GPU_POWER:
1467                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1468                                                           METRICS_AVERAGE_SOCKETPOWER,
1469                                                           (uint32_t *)data);
1470                 *size = 4;
1471                 break;
1472         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1473                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1474                                                           METRICS_TEMPERATURE_HOTSPOT,
1475                                                           (uint32_t *)data);
1476                 *size = 4;
1477                 break;
1478         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1479                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1480                                                           METRICS_TEMPERATURE_EDGE,
1481                                                           (uint32_t *)data);
1482                 *size = 4;
1483                 break;
1484         case AMDGPU_PP_SENSOR_MEM_TEMP:
1485                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1486                                                           METRICS_TEMPERATURE_MEM,
1487                                                           (uint32_t *)data);
1488                 *size = 4;
1489                 break;
1490         case AMDGPU_PP_SENSOR_GFX_MCLK:
1491                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1492                 *(uint32_t *)data *= 100;
1493                 *size = 4;
1494                 break;
1495         case AMDGPU_PP_SENSOR_GFX_SCLK:
1496                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1497                 *(uint32_t *)data *= 100;
1498                 *size = 4;
1499                 break;
1500         case AMDGPU_PP_SENSOR_VDDGFX:
1501                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1502                 *size = 4;
1503                 break;
1504         default:
1505                 ret = -EOPNOTSUPP;
1506                 break;
1507         }
1508         mutex_unlock(&smu->sensor_lock);
1509
1510         return ret;
1511 }
1512
1513 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1514 {
1515         uint32_t num_discrete_levels = 0;
1516         uint16_t *dpm_levels = NULL;
1517         uint16_t i = 0;
1518         struct smu_table_context *table_context = &smu->smu_table;
1519         PPTable_t *driver_ppt = NULL;
1520
1521         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1522                 return -EINVAL;
1523
1524         driver_ppt = table_context->driver_pptable;
1525         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1526         dpm_levels = driver_ppt->FreqTableUclk;
1527
1528         if (num_discrete_levels == 0 || dpm_levels == NULL)
1529                 return -EINVAL;
1530
1531         *num_states = num_discrete_levels;
1532         for (i = 0; i < num_discrete_levels; i++) {
1533                 /* convert to khz */
1534                 *clocks_in_khz = (*dpm_levels) * 1000;
1535                 clocks_in_khz++;
1536                 dpm_levels++;
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1543                                                 struct smu_temperature_range *range)
1544 {
1545         struct smu_table_context *table_context = &smu->smu_table;
1546         struct smu_11_0_7_powerplay_table *powerplay_table =
1547                                 table_context->power_play_table;
1548         PPTable_t *pptable = smu->smu_table.driver_pptable;
1549
1550         if (!range)
1551                 return -EINVAL;
1552
1553         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1554
1555         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1556                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1557         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1558                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1559         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1560                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1561         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1562                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1563         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1564                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1565         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1566                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1567         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1568
1569         return 0;
1570 }
1571
1572 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1573                                                 bool disable_memory_clock_switch)
1574 {
1575         int ret = 0;
1576         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1577                 (struct smu_11_0_max_sustainable_clocks *)
1578                         smu->smu_table.max_sustainable_clocks;
1579         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1580         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1581
1582         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1583                 return 0;
1584
1585         if(disable_memory_clock_switch)
1586                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1587         else
1588                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1589
1590         if(!ret)
1591                 smu->disable_uclk_switch = disable_memory_clock_switch;
1592
1593         return ret;
1594 }
1595
1596 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1597 {
1598         struct smu_11_0_7_powerplay_table *powerplay_table =
1599                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1600         PPTable_t *pptable = smu->smu_table.driver_pptable;
1601         uint32_t power_limit, od_percent;
1602
1603         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1604                 /* the last hope to figure out the ppt limit */
1605                 if (!pptable) {
1606                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1607                         return -EINVAL;
1608                 }
1609                 power_limit =
1610                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1611         }
1612         smu->current_power_limit = power_limit;
1613
1614         if (smu->od_enabled) {
1615                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1616
1617                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1618
1619                 power_limit *= (100 + od_percent);
1620                 power_limit /= 100;
1621         }
1622         smu->max_power_limit = power_limit;
1623
1624         return 0;
1625 }
1626
1627 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1628                                          uint32_t pcie_gen_cap,
1629                                          uint32_t pcie_width_cap)
1630 {
1631         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1632         PPTable_t *pptable = smu->smu_table.driver_pptable;
1633         uint32_t smu_pcie_arg;
1634         int ret, i;
1635
1636         /* lclk dpm table setup */
1637         for (i = 0; i < MAX_PCIE_CONF; i++) {
1638                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1639                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1640         }
1641
1642         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1643                 smu_pcie_arg = (i << 16) |
1644                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1645                                         (pptable->PcieGenSpeed[i] << 8) :
1646                                         (pcie_gen_cap << 8)) |
1647                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1648                                         pptable->PcieLaneCount[i] :
1649                                         pcie_width_cap);
1650
1651                 ret = smu_cmn_send_smc_msg_with_param(smu,
1652                                           SMU_MSG_OverridePcieParameters,
1653                                           smu_pcie_arg,
1654                                           NULL);
1655
1656                 if (ret)
1657                         return ret;
1658
1659                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1660                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1661                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1662                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1663         }
1664
1665         return 0;
1666 }
1667
1668 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1669                                 enum smu_clk_type clk_type,
1670                                 uint32_t *min, uint32_t *max)
1671 {
1672         struct amdgpu_device *adev = smu->adev;
1673         int ret;
1674
1675         if (clk_type == SMU_GFXCLK)
1676                 amdgpu_gfx_off_ctrl(adev, false);
1677         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1678         if (clk_type == SMU_GFXCLK)
1679                 amdgpu_gfx_off_ctrl(adev, true);
1680
1681         return ret;
1682 }
1683
1684 static int sienna_cichlid_run_btc(struct smu_context *smu)
1685 {
1686         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1687 }
1688
1689 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1690 {
1691         struct amdgpu_device *adev = smu->adev;
1692         uint32_t val;
1693
1694         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1695                 return false;
1696
1697         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1698         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1699 }
1700
1701 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1702 {
1703         struct amdgpu_device *adev = smu->adev;
1704         uint32_t val;
1705         u32 smu_version;
1706
1707         /**
1708          * SRIOV env will not support SMU mode1 reset
1709          * PM FW support mode1 reset from 58.26
1710          */
1711         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1712         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1713                 return false;
1714
1715         /**
1716          * mode1 reset relies on PSP, so we should check if
1717          * PSP is alive.
1718          */
1719         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1720         return val != 0x0;
1721 }
1722
1723 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1724 {
1725         struct smu_table_context *table_context = &smu->smu_table;
1726         PPTable_t *pptable = table_context->driver_pptable;
1727         int i;
1728
1729         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1730
1731         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1732         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1733         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1734
1735         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1736                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1737                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1738                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1739                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1740         }
1741
1742         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1743                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1744                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1745         }
1746
1747         for (i = 0; i < TEMP_COUNT; i++) {
1748                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1749         }
1750
1751         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1752         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1753         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1754         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1755         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1756
1757         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1758         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1759                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1760                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1761         }
1762         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1763
1764         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1765
1766         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1767         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1768         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1769         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1770
1771         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1772         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1773
1774         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1775         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1776         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1777         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1778
1779         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1780         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1781         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1782         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1783
1784         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1785         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1786
1787         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1788         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1789         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1790         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1791         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1792         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1793         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1794         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1795
1796         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1797                         "  .VoltageMode          = 0x%02x\n"
1798                         "  .SnapToDiscrete       = 0x%02x\n"
1799                         "  .NumDiscreteLevels    = 0x%02x\n"
1800                         "  .padding              = 0x%02x\n"
1801                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1802                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1803                         "  .SsFmin               = 0x%04x\n"
1804                         "  .Padding_16           = 0x%04x\n",
1805                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1806                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1807                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1808                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1809                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1810                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1811                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1812                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1813                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1814                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1815                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1816
1817         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1818                         "  .VoltageMode          = 0x%02x\n"
1819                         "  .SnapToDiscrete       = 0x%02x\n"
1820                         "  .NumDiscreteLevels    = 0x%02x\n"
1821                         "  .padding              = 0x%02x\n"
1822                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1823                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1824                         "  .SsFmin               = 0x%04x\n"
1825                         "  .Padding_16           = 0x%04x\n",
1826                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1827                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1828                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1829                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1830                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1831                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1832                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1833                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1834                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1835                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1836                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1837
1838         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1839                         "  .VoltageMode          = 0x%02x\n"
1840                         "  .SnapToDiscrete       = 0x%02x\n"
1841                         "  .NumDiscreteLevels    = 0x%02x\n"
1842                         "  .padding              = 0x%02x\n"
1843                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1844                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1845                         "  .SsFmin               = 0x%04x\n"
1846                         "  .Padding_16           = 0x%04x\n",
1847                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1848                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1849                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1850                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1851                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1852                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1853                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1854                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1855                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1856                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1857                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1858
1859         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1860                         "  .VoltageMode          = 0x%02x\n"
1861                         "  .SnapToDiscrete       = 0x%02x\n"
1862                         "  .NumDiscreteLevels    = 0x%02x\n"
1863                         "  .padding              = 0x%02x\n"
1864                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1865                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1866                         "  .SsFmin               = 0x%04x\n"
1867                         "  .Padding_16           = 0x%04x\n",
1868                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1869                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1870                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1871                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1872                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1873                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1874                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1875                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1876                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1877                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1878                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1879
1880         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1881                         "  .VoltageMode          = 0x%02x\n"
1882                         "  .SnapToDiscrete       = 0x%02x\n"
1883                         "  .NumDiscreteLevels    = 0x%02x\n"
1884                         "  .padding              = 0x%02x\n"
1885                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1886                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1887                         "  .SsFmin               = 0x%04x\n"
1888                         "  .Padding_16           = 0x%04x\n",
1889                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1890                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1891                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1892                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1893                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1894                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1895                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1896                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1897                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1898                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1899                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1900
1901         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1902                         "  .VoltageMode          = 0x%02x\n"
1903                         "  .SnapToDiscrete       = 0x%02x\n"
1904                         "  .NumDiscreteLevels    = 0x%02x\n"
1905                         "  .padding              = 0x%02x\n"
1906                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1907                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1908                         "  .SsFmin               = 0x%04x\n"
1909                         "  .Padding_16           = 0x%04x\n",
1910                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1911                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1912                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1913                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1914                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1915                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1916                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1917                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1918                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1919                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1920                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1921
1922         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
1923                         "  .VoltageMode          = 0x%02x\n"
1924                         "  .SnapToDiscrete       = 0x%02x\n"
1925                         "  .NumDiscreteLevels    = 0x%02x\n"
1926                         "  .padding              = 0x%02x\n"
1927                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1928                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1929                         "  .SsFmin               = 0x%04x\n"
1930                         "  .Padding_16           = 0x%04x\n",
1931                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1932                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1933                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1934                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1935                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1936                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1937                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1938                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1939                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1940                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1941                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1942
1943         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
1944                         "  .VoltageMode          = 0x%02x\n"
1945                         "  .SnapToDiscrete       = 0x%02x\n"
1946                         "  .NumDiscreteLevels    = 0x%02x\n"
1947                         "  .padding              = 0x%02x\n"
1948                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1949                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1950                         "  .SsFmin               = 0x%04x\n"
1951                         "  .Padding_16           = 0x%04x\n",
1952                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1953                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1954                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1955                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1956                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1957                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1958                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1959                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1960                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1961                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1962                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1963
1964         dev_info(smu->adev->dev, "FreqTableGfx\n");
1965         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1966                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1967
1968         dev_info(smu->adev->dev, "FreqTableVclk\n");
1969         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1970                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1971
1972         dev_info(smu->adev->dev, "FreqTableDclk\n");
1973         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1974                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1975
1976         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1977         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1978                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1979
1980         dev_info(smu->adev->dev, "FreqTableUclk\n");
1981         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1982                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1983
1984         dev_info(smu->adev->dev, "FreqTableFclk\n");
1985         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1986                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1987
1988         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
1989         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1990         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1991         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1992         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1993         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1994         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1995         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1996         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1997
1998         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
1999         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2000                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2001
2002         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2003         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2004
2005         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2006         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2007                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2008
2009         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2010         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2011                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2012
2013         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2014         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2015                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2016
2017         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2018         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2019                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2020
2021         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2022         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2023         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2024         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2025         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2026
2027         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2028
2029         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2030         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2031         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2032         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2033         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2034         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2035         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2036         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2037         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2038         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2039         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2040
2041         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2042         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2043         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2044         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2045         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2046         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2047
2048         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2049         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2050         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2051         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2052         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2053
2054         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2055         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2056                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2057
2058         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2059         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2060         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2061         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2062
2063         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2064         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2065                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2066
2067         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2068         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2069                 pptable->UclkDpmSrcFreqRange.Fmin);
2070         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2071                 pptable->UclkDpmSrcFreqRange.Fmax);
2072         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2073         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2074                 pptable->UclkDpmTargFreqRange.Fmin);
2075         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2076                 pptable->UclkDpmTargFreqRange.Fmax);
2077         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2078         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2079
2080         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2081         for (i = 0; i < NUM_LINK_LEVELS; i++)
2082                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2083
2084         dev_info(smu->adev->dev, "PcieLaneCount\n");
2085         for (i = 0; i < NUM_LINK_LEVELS; i++)
2086                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2087
2088         dev_info(smu->adev->dev, "LclkFreq\n");
2089         for (i = 0; i < NUM_LINK_LEVELS; i++)
2090                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2091
2092         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2093         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2094
2095         dev_info(smu->adev->dev, "FanGain\n");
2096         for (i = 0; i < TEMP_COUNT; i++)
2097                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2098
2099         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2100         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2101         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2102         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2103         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2104         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2105         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2106         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2107         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2108         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2109         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2110         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2111
2112         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2113         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2114         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2115         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2116
2117         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2118         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2119         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2120         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2121
2122         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2123                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2124                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2125                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2126         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2127                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2128                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2129                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2130         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2131                         pptable->dBtcGbGfxPll.a,
2132                         pptable->dBtcGbGfxPll.b,
2133                         pptable->dBtcGbGfxPll.c);
2134         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2135                         pptable->dBtcGbGfxDfll.a,
2136                         pptable->dBtcGbGfxDfll.b,
2137                         pptable->dBtcGbGfxDfll.c);
2138         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2139                         pptable->dBtcGbSoc.a,
2140                         pptable->dBtcGbSoc.b,
2141                         pptable->dBtcGbSoc.c);
2142         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2143                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2144                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2145         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2146                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2147                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2148
2149         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2150         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2151                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2152                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2153                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2154                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2155         }
2156
2157         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2158                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2159                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2160                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2161         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2162                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2163                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2164                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2165
2166         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2167         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2168
2169         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2170         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2171         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2172         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2173
2174         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2175         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2176         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2177         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2178
2179         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2180         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2181
2182         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2183         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2184                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2185         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2186         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2187
2188         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2189         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2190                         pptable->ReservedEquation0.a,
2191                         pptable->ReservedEquation0.b,
2192                         pptable->ReservedEquation0.c);
2193         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2194                         pptable->ReservedEquation1.a,
2195                         pptable->ReservedEquation1.b,
2196                         pptable->ReservedEquation1.c);
2197         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2198                         pptable->ReservedEquation2.a,
2199                         pptable->ReservedEquation2.b,
2200                         pptable->ReservedEquation2.c);
2201         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2202                         pptable->ReservedEquation3.a,
2203                         pptable->ReservedEquation3.b,
2204                         pptable->ReservedEquation3.c);
2205
2206         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2207         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2208         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2209         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2210         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2211         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2212         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2213         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2214
2215         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2216         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2217         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2218         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2219         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2220         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2221
2222         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2223                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2224                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2225                                 pptable->I2cControllers[i].Enabled);
2226                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2227                                 pptable->I2cControllers[i].Speed);
2228                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2229                                 pptable->I2cControllers[i].SlaveAddress);
2230                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2231                                 pptable->I2cControllers[i].ControllerPort);
2232                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2233                                 pptable->I2cControllers[i].ControllerName);
2234                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2235                                 pptable->I2cControllers[i].ThermalThrotter);
2236                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2237                                 pptable->I2cControllers[i].I2cProtocol);
2238                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2239                                 pptable->I2cControllers[i].PaddingConfig);
2240         }
2241
2242         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2243         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2244         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2245         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2246
2247         dev_info(smu->adev->dev, "Board Parameters:\n");
2248         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2249         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2250         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2251         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2252         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2253         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2254         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2255         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2256
2257         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2258         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2259         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2260
2261         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2262         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2263         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2264
2265         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2266         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2267         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2268
2269         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2270         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2271         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2272
2273         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2274
2275         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2276         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2277         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2278         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2279         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2280         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2281         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2282         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2283         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2284         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2285         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2286         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2287         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2288         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2289         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2290         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2291
2292         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2293         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2294         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2295
2296         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2297         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2298         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2299
2300         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2301         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2302
2303         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2304         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2305         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2306
2307         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2308         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2309         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2310         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2311         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2312
2313         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2314         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2315
2316         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2317         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2318                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2319         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2320         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2321                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2322         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2323         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2324                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2325         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2326         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2327                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2328
2329         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2330         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2331         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2332         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2333
2334         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2335         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2336         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2337         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2338         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2339         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2340         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2341         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2342         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2343         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2344         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2345
2346         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2347         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2348         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2349         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2350         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2351         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2352         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2353         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2354 }
2355
2356 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2357                                   uint8_t address, uint32_t numbytes,
2358                                   uint8_t *data)
2359 {
2360         int i;
2361
2362         req->I2CcontrollerPort = 0;
2363         req->I2CSpeed = 2;
2364         req->SlaveAddress = address;
2365         req->NumCmds = numbytes;
2366
2367         for (i = 0; i < numbytes; i++) {
2368                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2369
2370                 /* First 2 bytes are always write for lower 2b EEPROM address */
2371                 if (i < 2)
2372                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2373                 else
2374                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2375
2376
2377                 /* Add RESTART for read  after address filled */
2378                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2379
2380                 /* Add STOP in the end */
2381                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2382
2383                 /* Fill with data regardless if read or write to simplify code */
2384                 cmd->ReadWriteData = data[i];
2385         }
2386 }
2387
2388 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2389                                                uint8_t address,
2390                                                uint8_t *data,
2391                                                uint32_t numbytes)
2392 {
2393         uint32_t  i, ret = 0;
2394         SwI2cRequest_t req;
2395         struct amdgpu_device *adev = to_amdgpu_device(control);
2396         struct smu_table_context *smu_table = &adev->smu.smu_table;
2397         struct smu_table *table = &smu_table->driver_table;
2398
2399         if (numbytes > MAX_SW_I2C_COMMANDS) {
2400                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2401                         numbytes, MAX_SW_I2C_COMMANDS);
2402                 return -EINVAL;
2403         }
2404
2405         memset(&req, 0, sizeof(req));
2406         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2407
2408         mutex_lock(&adev->smu.mutex);
2409         /* Now read data starting with that address */
2410         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2411                                         true);
2412         mutex_unlock(&adev->smu.mutex);
2413
2414         if (!ret) {
2415                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2416
2417                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2418                 for (i = 0; i < numbytes; i++)
2419                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2420
2421                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2422                                   (uint16_t)address, numbytes);
2423
2424                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2425                                8, 1, data, numbytes, false);
2426         } else
2427                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2428
2429         return ret;
2430 }
2431
2432 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2433                                                 uint8_t address,
2434                                                 uint8_t *data,
2435                                                 uint32_t numbytes)
2436 {
2437         uint32_t ret;
2438         SwI2cRequest_t req;
2439         struct amdgpu_device *adev = to_amdgpu_device(control);
2440
2441         if (numbytes > MAX_SW_I2C_COMMANDS) {
2442                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2443                         numbytes, MAX_SW_I2C_COMMANDS);
2444                 return -EINVAL;
2445         }
2446
2447         memset(&req, 0, sizeof(req));
2448         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2449
2450         mutex_lock(&adev->smu.mutex);
2451         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2452         mutex_unlock(&adev->smu.mutex);
2453
2454         if (!ret) {
2455                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2456                                          (uint16_t)address, numbytes);
2457
2458                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2459                                8, 1, data, numbytes, false);
2460                 /*
2461                  * According to EEPROM spec there is a MAX of 10 ms required for
2462                  * EEPROM to flush internal RX buffer after STOP was issued at the
2463                  * end of write transaction. During this time the EEPROM will not be
2464                  * responsive to any more commands - so wait a bit more.
2465                  */
2466                 msleep(10);
2467
2468         } else
2469                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2470
2471         return ret;
2472 }
2473
2474 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2475                               struct i2c_msg *msgs, int num)
2476 {
2477         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2478         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2479
2480         for (i = 0; i < num; i++) {
2481                 /*
2482                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2483                  * once and hence the data needs to be spliced into chunks and sent each
2484                  * chunk separately
2485                  */
2486                 data_size = msgs[i].len - 2;
2487                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2488                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2489                 data_ptr = msgs[i].buf + 2;
2490
2491                 for (j = 0; j < data_size / data_chunk_size; j++) {
2492                         /* Insert the EEPROM dest addess, bits 0-15 */
2493                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2494                         data_chunk[1] = (next_eeprom_addr & 0xff);
2495
2496                         if (msgs[i].flags & I2C_M_RD) {
2497                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2498                                                              (uint8_t)msgs[i].addr,
2499                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2500
2501                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2502                         } else {
2503
2504                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2505
2506                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2507                                                               (uint8_t)msgs[i].addr,
2508                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2509                         }
2510
2511                         if (ret) {
2512                                 num = -EIO;
2513                                 goto fail;
2514                         }
2515
2516                         next_eeprom_addr += data_chunk_size;
2517                         data_ptr += data_chunk_size;
2518                 }
2519
2520                 if (data_size % data_chunk_size) {
2521                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2522                         data_chunk[1] = (next_eeprom_addr & 0xff);
2523
2524                         if (msgs[i].flags & I2C_M_RD) {
2525                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2526                                                              (uint8_t)msgs[i].addr,
2527                                                              data_chunk, (data_size % data_chunk_size) + 2);
2528
2529                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2530                         } else {
2531                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2532
2533                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2534                                                               (uint8_t)msgs[i].addr,
2535                                                               data_chunk, (data_size % data_chunk_size) + 2);
2536                         }
2537
2538                         if (ret) {
2539                                 num = -EIO;
2540                                 goto fail;
2541                         }
2542                 }
2543         }
2544
2545 fail:
2546         return num;
2547 }
2548
2549 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2550 {
2551         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2552 }
2553
2554
2555 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2556         .master_xfer = sienna_cichlid_i2c_xfer,
2557         .functionality = sienna_cichlid_i2c_func,
2558 };
2559
2560 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2561 {
2562         struct amdgpu_device *adev = to_amdgpu_device(control);
2563         int res;
2564
2565         control->owner = THIS_MODULE;
2566         control->class = I2C_CLASS_SPD;
2567         control->dev.parent = &adev->pdev->dev;
2568         control->algo = &sienna_cichlid_i2c_algo;
2569         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2570
2571         res = i2c_add_adapter(control);
2572         if (res)
2573                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2574
2575         return res;
2576 }
2577
2578 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2579 {
2580         i2c_del_adapter(control);
2581 }
2582
2583 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2584                                               void **table)
2585 {
2586         struct smu_table_context *smu_table = &smu->smu_table;
2587         struct gpu_metrics_v1_0 *gpu_metrics =
2588                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2589         SmuMetrics_t metrics;
2590         int ret = 0;
2591
2592         ret = smu_cmn_get_metrics_table(smu,
2593                                         &metrics,
2594                                         true);
2595         if (ret)
2596                 return ret;
2597
2598         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2599
2600         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2601         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2602         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2603         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2604         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2605         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2606
2607         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2608         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2609         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2610
2611         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2612         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2613
2614         if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2615                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2616         else
2617                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2618         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2619         gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2620         gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2621         gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2622         gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2623
2624         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2625         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2626         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2627         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2628         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2629         gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2630         gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2631
2632         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2633
2634         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2635
2636         gpu_metrics->pcie_link_width =
2637                         smu_v11_0_get_current_pcie_link_width(smu);
2638         gpu_metrics->pcie_link_speed =
2639                         smu_v11_0_get_current_pcie_link_speed(smu);
2640
2641         *table = (void *)gpu_metrics;
2642
2643         return sizeof(struct gpu_metrics_v1_0);
2644 }
2645
2646 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2647 {
2648         return smu_cmn_send_smc_msg_with_param(smu,
2649                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2650                                                0,
2651                                                NULL);
2652 }
2653
2654 static int sienna_cichlid_gpo_control(struct smu_context *smu,
2655                                       bool enablement)
2656 {
2657         uint32_t smu_version;
2658         int ret = 0;
2659
2660
2661         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2662                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2663                 if (ret)
2664                         return ret;
2665
2666                 if (enablement) {
2667                         if (smu_version < 0x003a2500) {
2668                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2669                                                                       SMU_MSG_SetGpoFeaturePMask,
2670                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2671                                                                       NULL);
2672                         } else {
2673                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2674                                                                       SMU_MSG_DisallowGpo,
2675                                                                       0,
2676                                                                       NULL);
2677                         }
2678                 } else {
2679                         if (smu_version < 0x003a2500) {
2680                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2681                                                                       SMU_MSG_SetGpoFeaturePMask,
2682                                                                       0,
2683                                                                       NULL);
2684                         } else {
2685                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2686                                                                       SMU_MSG_DisallowGpo,
2687                                                                       1,
2688                                                                       NULL);
2689                         }
2690                 }
2691         }
2692
2693         return ret;
2694 }
2695 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2696         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2697         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2698         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2699         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2700         .i2c_init = sienna_cichlid_i2c_control_init,
2701         .i2c_fini = sienna_cichlid_i2c_control_fini,
2702         .print_clk_levels = sienna_cichlid_print_clk_levels,
2703         .force_clk_levels = sienna_cichlid_force_clk_levels,
2704         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2705         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2706         .display_config_changed = sienna_cichlid_display_config_changed,
2707         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2708         .is_dpm_running = sienna_cichlid_is_dpm_running,
2709         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2710         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2711         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2712         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2713         .read_sensor = sienna_cichlid_read_sensor,
2714         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2715         .set_performance_level = smu_v11_0_set_performance_level,
2716         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2717         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2718         .get_power_limit = sienna_cichlid_get_power_limit,
2719         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2720         .dump_pptable = sienna_cichlid_dump_pptable,
2721         .init_microcode = smu_v11_0_init_microcode,
2722         .load_microcode = smu_v11_0_load_microcode,
2723         .init_smc_tables = sienna_cichlid_init_smc_tables,
2724         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2725         .init_power = smu_v11_0_init_power,
2726         .fini_power = smu_v11_0_fini_power,
2727         .check_fw_status = smu_v11_0_check_fw_status,
2728         .setup_pptable = sienna_cichlid_setup_pptable,
2729         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2730         .check_fw_version = smu_v11_0_check_fw_version,
2731         .write_pptable = smu_cmn_write_pptable,
2732         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2733         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2734         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2735         .system_features_control = smu_v11_0_system_features_control,
2736         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2737         .send_smc_msg = smu_cmn_send_smc_msg,
2738         .init_display_count = NULL,
2739         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2740         .get_enabled_mask = smu_cmn_get_enabled_mask,
2741         .feature_is_enabled = smu_cmn_feature_is_enabled,
2742         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2743         .notify_display_change = NULL,
2744         .set_power_limit = smu_v11_0_set_power_limit,
2745         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2746         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2747         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2748         .set_min_dcef_deep_sleep = NULL,
2749         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2750         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2751         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2752         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2753         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2754         .gfx_off_control = smu_v11_0_gfx_off_control,
2755         .register_irq_handler = smu_v11_0_register_irq_handler,
2756         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2757         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2758         .baco_is_support= sienna_cichlid_is_baco_supported,
2759         .baco_get_state = smu_v11_0_baco_get_state,
2760         .baco_set_state = smu_v11_0_baco_set_state,
2761         .baco_enter = smu_v11_0_baco_enter,
2762         .baco_exit = smu_v11_0_baco_exit,
2763         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2764         .mode1_reset = smu_v11_0_mode1_reset,
2765         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2766         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2767         .run_btc = sienna_cichlid_run_btc,
2768         .set_power_source = smu_v11_0_set_power_source,
2769         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2770         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2771         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2772         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2773         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2774         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2775         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2776         .interrupt_work = smu_v11_0_interrupt_work,
2777         .gpo_control = sienna_cichlid_gpo_control,
2778 };
2779
2780 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2781 {
2782         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2783         smu->message_map = sienna_cichlid_message_map;
2784         smu->clock_map = sienna_cichlid_clk_map;
2785         smu->feature_map = sienna_cichlid_feature_mask_map;
2786         smu->table_map = sienna_cichlid_table_map;
2787         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2788         smu->workload_map = sienna_cichlid_workload_map;
2789 }