drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  77         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  78         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  79         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  80         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  81         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  82         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  83         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  84         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  85         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  86         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  87         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  88         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  89         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  90         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  91         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  92         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  93         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  94         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  95         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  96         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  97         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  98         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  99         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 113         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 114         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 115         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 116         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 117         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 118         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 119         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 120         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 121         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 122         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 123         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 124         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 125         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 126         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 127         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 128         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 129         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 130         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 131 };
 132
 133 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 134         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 135         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 136         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 137         CLK_MAP(FCLK,           PPCLK_FCLK),
 138         CLK_MAP(UCLK,           PPCLK_UCLK),
 139         CLK_MAP(MCLK,           PPCLK_UCLK),
 140         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 141         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 142         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 143         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 144         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 145         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 146         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 147         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 148 };
 149
 150 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 151         FEA_MAP(DPM_PREFETCHER),
 152         FEA_MAP(DPM_GFXCLK),
 153         FEA_MAP(DPM_GFX_GPO),
 154         FEA_MAP(DPM_UCLK),
 155         FEA_MAP(DPM_FCLK),
 156         FEA_MAP(DPM_SOCCLK),
 157         FEA_MAP(DPM_MP0CLK),
 158         FEA_MAP(DPM_LINK),
 159         FEA_MAP(DPM_DCEFCLK),
 160         FEA_MAP(DPM_XGMI),
 161         FEA_MAP(MEM_VDDCI_SCALING),
 162         FEA_MAP(MEM_MVDD_SCALING),
 163         FEA_MAP(DS_GFXCLK),
 164         FEA_MAP(DS_SOCCLK),
 165         FEA_MAP(DS_FCLK),
 166         FEA_MAP(DS_LCLK),
 167         FEA_MAP(DS_DCEFCLK),
 168         FEA_MAP(DS_UCLK),
 169         FEA_MAP(GFX_ULV),
 170         FEA_MAP(FW_DSTATE),
 171         FEA_MAP(GFXOFF),
 172         FEA_MAP(BACO),
 173         FEA_MAP(MM_DPM_PG),
 174         FEA_MAP(RSMU_SMN_CG),
 175         FEA_MAP(PPT),
 176         FEA_MAP(TDC),
 177         FEA_MAP(APCC_PLUS),
 178         FEA_MAP(GTHR),
 179         FEA_MAP(ACDC),
 180         FEA_MAP(VR0HOT),
 181         FEA_MAP(VR1HOT),
 182         FEA_MAP(FW_CTF),
 183         FEA_MAP(FAN_CONTROL),
 184         FEA_MAP(THERMAL),
 185         FEA_MAP(GFX_DCS),
 186         FEA_MAP(RM),
 187         FEA_MAP(LED_DISPLAY),
 188         FEA_MAP(GFX_SS),
 189         FEA_MAP(OUT_OF_BAND_MONITOR),
 190         FEA_MAP(TEMP_DEPENDENT_VMIN),
 191         FEA_MAP(MMHUB_PG),
 192         FEA_MAP(ATHUB_PG),
 193         FEA_MAP(APCC_DFLL),
 194 };
 195
 196 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 197         TAB_MAP(PPTABLE),
 198         TAB_MAP(WATERMARKS),
 199         TAB_MAP(AVFS_PSM_DEBUG),
 200         TAB_MAP(AVFS_FUSE_OVERRIDE),
 201         TAB_MAP(PMSTATUSLOG),
 202         TAB_MAP(SMU_METRICS),
 203         TAB_MAP(DRIVER_SMU_CONFIG),
 204         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 205         TAB_MAP(OVERDRIVE),
 206         TAB_MAP(I2C_COMMANDS),
 207         TAB_MAP(PACE),
 208 };
 209
 210 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 211         PWR_MAP(AC),
 212         PWR_MAP(DC),
 213 };
 214
 215 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 223 };
 224
 225 static int
 226 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 227                                   uint32_t *feature_mask, uint32_t num)
 228 {
 229         struct amdgpu_device *adev = smu->adev;
 230
 231         if (num > 2)
 232                 return -EINVAL;
 233
 234         memset(feature_mask, 0, sizeof(uint32_t) * num);
 235
 236         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 237                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 238                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 239                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 240                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 241                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 242                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 243                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 244                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 245                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 246                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 247                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 248                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 249                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 250                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 251                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 252                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 253                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 254                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 255                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 256
 257         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 258                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 259                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 260         }
 261
 262         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 263                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 264                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 265                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 266
 267         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 268                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 269
 270         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 271                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 272
 273         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 274                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 275
 276         if (adev->pm.pp_feature & PP_ULV_MASK)
 277                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 278
 279         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 280                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 281
 282         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 283                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 284
 285         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 286                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 287
 288         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 289                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 290
 291         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 292             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 293                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 294
 295         return 0;
 296 }
 297
 298 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 299 {
 300         struct smu_table_context *table_context = &smu->smu_table;
 301         struct smu_11_0_7_powerplay_table *powerplay_table =
 302                 table_context->power_play_table;
 303         struct smu_baco_context *smu_baco = &smu->smu_baco;
 304
 305         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 306             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 307                 smu_baco->platform_support = true;
 308
 309         table_context->thermal_controller_type =
 310                 powerplay_table->thermal_controller_type;
 311
 312         return 0;
 313 }
 314
 315 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 316 {
 317         struct smu_table_context *table_context = &smu->smu_table;
 318         PPTable_t *smc_pptable = table_context->driver_pptable;
 319         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 320         int index, ret;
 321
 322         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 323                                             smc_dpm_info);
 324
 325         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 326                                       (uint8_t **)&smc_dpm_table);
 327         if (ret)
 328                 return ret;
 329
 330         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 331                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 332
 333         return 0;
 334 }
 335
 336 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 337 {
 338         struct smu_table_context *table_context = &smu->smu_table;
 339         struct smu_11_0_7_powerplay_table *powerplay_table =
 340                 table_context->power_play_table;
 341
 342         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 343                sizeof(PPTable_t));
 344
 345         return 0;
 346 }
 347
 348 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 349 {
 350         int ret = 0;
 351
 352         ret = smu_v11_0_setup_pptable(smu);
 353         if (ret)
 354                 return ret;
 355
 356         ret = sienna_cichlid_store_powerplay_table(smu);
 357         if (ret)
 358                 return ret;
 359
 360         ret = sienna_cichlid_append_powerplay_table(smu);
 361         if (ret)
 362                 return ret;
 363
 364         ret = sienna_cichlid_check_powerplay_table(smu);
 365         if (ret)
 366                 return ret;
 367
 368         return ret;
 369 }
 370
 371 static int sienna_cichlid_tables_init(struct smu_context *smu)
 372 {
 373         struct smu_table_context *smu_table = &smu->smu_table;
 374         struct smu_table *tables = smu_table->tables;
 375
 376         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 377                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 378         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 379                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 380         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 381                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 382         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 383                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 384         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 385                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 386         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 387                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 388         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 389                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 390                        AMDGPU_GEM_DOMAIN_VRAM);
 391
 392         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 393         if (!smu_table->metrics_table)
 394                 goto err0_out;
 395         smu_table->metrics_time = 0;
 396
 397         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 398         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 399         if (!smu_table->gpu_metrics_table)
 400                 goto err1_out;
 401
 402         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 403         if (!smu_table->watermarks_table)
 404                 goto err2_out;
 405
 406         return 0;
 407
 408 err2_out:
 409         kfree(smu_table->gpu_metrics_table);
 410 err1_out:
 411         kfree(smu_table->metrics_table);
 412 err0_out:
 413         return -ENOMEM;
 414 }
 415
 416 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 417                                                MetricsMember_t member,
 418                                                uint32_t *value)
 419 {
 420         struct smu_table_context *smu_table= &smu->smu_table;
 421         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 422         int ret = 0;
 423
 424         mutex_lock(&smu->metrics_lock);
 425
 426         ret = smu_cmn_get_metrics_table_locked(smu,
 427                                                NULL,
 428                                                false);
 429         if (ret) {
 430                 mutex_unlock(&smu->metrics_lock);
 431                 return ret;
 432         }
 433
 434         switch (member) {
 435         case METRICS_CURR_GFXCLK:
 436                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 437                 break;
 438         case METRICS_CURR_SOCCLK:
 439                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 440                 break;
 441         case METRICS_CURR_UCLK:
 442                 *value = metrics->CurrClock[PPCLK_UCLK];
 443                 break;
 444         case METRICS_CURR_VCLK:
 445                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 446                 break;
 447         case METRICS_CURR_VCLK1:
 448                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 449                 break;
 450         case METRICS_CURR_DCLK:
 451                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 452                 break;
 453         case METRICS_CURR_DCLK1:
 454                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 455                 break;
 456         case METRICS_CURR_DCEFCLK:
 457                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 458                 break;
 459         case METRICS_CURR_FCLK:
 460                 *value = metrics->CurrClock[PPCLK_FCLK];
 461                 break;
 462         case METRICS_AVERAGE_GFXCLK:
 463                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 464                         *value = metrics->AverageGfxclkFrequencyPostDs;
 465                 else
 466                         *value = metrics->AverageGfxclkFrequencyPreDs;
 467                 break;
 468         case METRICS_AVERAGE_FCLK:
 469                 *value = metrics->AverageFclkFrequencyPostDs;
 470                 break;
 471         case METRICS_AVERAGE_UCLK:
 472                 *value = metrics->AverageUclkFrequencyPostDs;
 473                 break;
 474         case METRICS_AVERAGE_GFXACTIVITY:
 475                 *value = metrics->AverageGfxActivity;
 476                 break;
 477         case METRICS_AVERAGE_MEMACTIVITY:
 478                 *value = metrics->AverageUclkActivity;
 479                 break;
 480         case METRICS_AVERAGE_SOCKETPOWER:
 481                 *value = metrics->AverageSocketPower << 8;
 482                 break;
 483         case METRICS_TEMPERATURE_EDGE:
 484                 *value = metrics->TemperatureEdge *
 485                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 486                 break;
 487         case METRICS_TEMPERATURE_HOTSPOT:
 488                 *value = metrics->TemperatureHotspot *
 489                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 490                 break;
 491         case METRICS_TEMPERATURE_MEM:
 492                 *value = metrics->TemperatureMem *
 493                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 494                 break;
 495         case METRICS_TEMPERATURE_VRGFX:
 496                 *value = metrics->TemperatureVrGfx *
 497                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 498                 break;
 499         case METRICS_TEMPERATURE_VRSOC:
 500                 *value = metrics->TemperatureVrSoc *
 501                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 502                 break;
 503         case METRICS_THROTTLER_STATUS:
 504                 *value = metrics->ThrottlerStatus;
 505                 break;
 506         case METRICS_CURR_FANSPEED:
 507                 *value = metrics->CurrFanSpeed;
 508                 break;
 509         default:
 510                 *value = UINT_MAX;
 511                 break;
 512         }
 513
 514         mutex_unlock(&smu->metrics_lock);
 515
 516         return ret;
 517
 518 }
 519
 520 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 521 {
 522         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 523
 524         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 525                                        GFP_KERNEL);
 526         if (!smu_dpm->dpm_context)
 527                 return -ENOMEM;
 528
 529         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 530
 531         return 0;
 532 }
 533
 534 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 535 {
 536         int ret = 0;
 537
 538         ret = sienna_cichlid_tables_init(smu);
 539         if (ret)
 540                 return ret;
 541
 542         ret = sienna_cichlid_allocate_dpm_context(smu);
 543         if (ret)
 544                 return ret;
 545
 546         return smu_v11_0_init_smc_tables(smu);
 547 }
 548
 549 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 550 {
 551         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 552         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 553         struct smu_11_0_dpm_table *dpm_table;
 554         struct amdgpu_device *adev = smu->adev;
 555         int ret = 0;
 556
 557         /* socclk dpm table setup */
 558         dpm_table = &dpm_context->dpm_tables.soc_table;
 559         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 560                 ret = smu_v11_0_set_single_dpm_table(smu,
 561                                                      SMU_SOCCLK,
 562                                                      dpm_table);
 563                 if (ret)
 564                         return ret;
 565                 dpm_table->is_fine_grained =
 566                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 567         } else {
 568                 dpm_table->count = 1;
 569                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 570                 dpm_table->dpm_levels[0].enabled = true;
 571                 dpm_table->min = dpm_table->dpm_levels[0].value;
 572                 dpm_table->max = dpm_table->dpm_levels[0].value;
 573         }
 574
 575         /* gfxclk dpm table setup */
 576         dpm_table = &dpm_context->dpm_tables.gfx_table;
 577         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 578                 ret = smu_v11_0_set_single_dpm_table(smu,
 579                                                      SMU_GFXCLK,
 580                                                      dpm_table);
 581                 if (ret)
 582                         return ret;
 583                 dpm_table->is_fine_grained =
 584                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 585         } else {
 586                 dpm_table->count = 1;
 587                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 588                 dpm_table->dpm_levels[0].enabled = true;
 589                 dpm_table->min = dpm_table->dpm_levels[0].value;
 590                 dpm_table->max = dpm_table->dpm_levels[0].value;
 591         }
 592
 593         /* uclk dpm table setup */
 594         dpm_table = &dpm_context->dpm_tables.uclk_table;
 595         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 596                 ret = smu_v11_0_set_single_dpm_table(smu,
 597                                                      SMU_UCLK,
 598                                                      dpm_table);
 599                 if (ret)
 600                         return ret;
 601                 dpm_table->is_fine_grained =
 602                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 603         } else {
 604                 dpm_table->count = 1;
 605                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 606                 dpm_table->dpm_levels[0].enabled = true;
 607                 dpm_table->min = dpm_table->dpm_levels[0].value;
 608                 dpm_table->max = dpm_table->dpm_levels[0].value;
 609         }
 610
 611         /* fclk dpm table setup */
 612         dpm_table = &dpm_context->dpm_tables.fclk_table;
 613         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 614                 ret = smu_v11_0_set_single_dpm_table(smu,
 615                                                      SMU_FCLK,
 616                                                      dpm_table);
 617                 if (ret)
 618                         return ret;
 619                 dpm_table->is_fine_grained =
 620                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 621         } else {
 622                 dpm_table->count = 1;
 623                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 624                 dpm_table->dpm_levels[0].enabled = true;
 625                 dpm_table->min = dpm_table->dpm_levels[0].value;
 626                 dpm_table->max = dpm_table->dpm_levels[0].value;
 627         }
 628
 629         /* vclk0 dpm table setup */
 630         dpm_table = &dpm_context->dpm_tables.vclk_table;
 631         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 632                 ret = smu_v11_0_set_single_dpm_table(smu,
 633                                                      SMU_VCLK,
 634                                                      dpm_table);
 635                 if (ret)
 636                         return ret;
 637                 dpm_table->is_fine_grained =
 638                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 639         } else {
 640                 dpm_table->count = 1;
 641                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 642                 dpm_table->dpm_levels[0].enabled = true;
 643                 dpm_table->min = dpm_table->dpm_levels[0].value;
 644                 dpm_table->max = dpm_table->dpm_levels[0].value;
 645         }
 646
 647         /* vclk1 dpm table setup */
 648         if (adev->vcn.num_vcn_inst > 1) {
 649                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 650                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 651                         ret = smu_v11_0_set_single_dpm_table(smu,
 652                                                              SMU_VCLK1,
 653                                                              dpm_table);
 654                         if (ret)
 655                                 return ret;
 656                         dpm_table->is_fine_grained =
 657                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 658                 } else {
 659                         dpm_table->count = 1;
 660                         dpm_table->dpm_levels[0].value =
 661                                 smu->smu_table.boot_values.vclk / 100;
 662                         dpm_table->dpm_levels[0].enabled = true;
 663                         dpm_table->min = dpm_table->dpm_levels[0].value;
 664                         dpm_table->max = dpm_table->dpm_levels[0].value;
 665                 }
 666         }
 667
 668         /* dclk0 dpm table setup */
 669         dpm_table = &dpm_context->dpm_tables.dclk_table;
 670         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 671                 ret = smu_v11_0_set_single_dpm_table(smu,
 672                                                      SMU_DCLK,
 673                                                      dpm_table);
 674                 if (ret)
 675                         return ret;
 676                 dpm_table->is_fine_grained =
 677                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 678         } else {
 679                 dpm_table->count = 1;
 680                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 681                 dpm_table->dpm_levels[0].enabled = true;
 682                 dpm_table->min = dpm_table->dpm_levels[0].value;
 683                 dpm_table->max = dpm_table->dpm_levels[0].value;
 684         }
 685
 686         /* dclk1 dpm table setup */
 687         if (adev->vcn.num_vcn_inst > 1) {
 688                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 689                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 690                         ret = smu_v11_0_set_single_dpm_table(smu,
 691                                                              SMU_DCLK1,
 692                                                              dpm_table);
 693                         if (ret)
 694                                 return ret;
 695                         dpm_table->is_fine_grained =
 696                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 697                 } else {
 698                         dpm_table->count = 1;
 699                         dpm_table->dpm_levels[0].value =
 700                                 smu->smu_table.boot_values.dclk / 100;
 701                         dpm_table->dpm_levels[0].enabled = true;
 702                         dpm_table->min = dpm_table->dpm_levels[0].value;
 703                         dpm_table->max = dpm_table->dpm_levels[0].value;
 704                 }
 705         }
 706
 707         /* dcefclk dpm table setup */
 708         dpm_table = &dpm_context->dpm_tables.dcef_table;
 709         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 710                 ret = smu_v11_0_set_single_dpm_table(smu,
 711                                                      SMU_DCEFCLK,
 712                                                      dpm_table);
 713                 if (ret)
 714                         return ret;
 715                 dpm_table->is_fine_grained =
 716                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 717         } else {
 718                 dpm_table->count = 1;
 719                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 720                 dpm_table->dpm_levels[0].enabled = true;
 721                 dpm_table->min = dpm_table->dpm_levels[0].value;
 722                 dpm_table->max = dpm_table->dpm_levels[0].value;
 723         }
 724
 725         /* pixelclk dpm table setup */
 726         dpm_table = &dpm_context->dpm_tables.pixel_table;
 727         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 728                 ret = smu_v11_0_set_single_dpm_table(smu,
 729                                                      SMU_PIXCLK,
 730                                                      dpm_table);
 731                 if (ret)
 732                         return ret;
 733                 dpm_table->is_fine_grained =
 734                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 735         } else {
 736                 dpm_table->count = 1;
 737                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 738                 dpm_table->dpm_levels[0].enabled = true;
 739                 dpm_table->min = dpm_table->dpm_levels[0].value;
 740                 dpm_table->max = dpm_table->dpm_levels[0].value;
 741         }
 742
 743         /* displayclk dpm table setup */
 744         dpm_table = &dpm_context->dpm_tables.display_table;
 745         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 746                 ret = smu_v11_0_set_single_dpm_table(smu,
 747                                                      SMU_DISPCLK,
 748                                                      dpm_table);
 749                 if (ret)
 750                         return ret;
 751                 dpm_table->is_fine_grained =
 752                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 753         } else {
 754                 dpm_table->count = 1;
 755                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 756                 dpm_table->dpm_levels[0].enabled = true;
 757                 dpm_table->min = dpm_table->dpm_levels[0].value;
 758                 dpm_table->max = dpm_table->dpm_levels[0].value;
 759         }
 760
 761         /* phyclk dpm table setup */
 762         dpm_table = &dpm_context->dpm_tables.phy_table;
 763         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 764                 ret = smu_v11_0_set_single_dpm_table(smu,
 765                                                      SMU_PHYCLK,
 766                                                      dpm_table);
 767                 if (ret)
 768                         return ret;
 769                 dpm_table->is_fine_grained =
 770                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 771         } else {
 772                 dpm_table->count = 1;
 773                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 774                 dpm_table->dpm_levels[0].enabled = true;
 775                 dpm_table->min = dpm_table->dpm_levels[0].value;
 776                 dpm_table->max = dpm_table->dpm_levels[0].value;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 783 {
 784         struct amdgpu_device *adev = smu->adev;
 785         int ret = 0;
 786
 787         if (enable) {
 788                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 789                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 790                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 791                         if (ret)
 792                                 return ret;
 793                         if (adev->vcn.num_vcn_inst > 1) {
 794                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 795                                                                   0x10000, NULL);
 796                                 if (ret)
 797                                         return ret;
 798                         }
 799                 }
 800         } else {
 801                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 802                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 803                         if (ret)
 804                                 return ret;
 805                         if (adev->vcn.num_vcn_inst > 1) {
 806                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 807                                                                   0x10000, NULL);
 808                                 if (ret)
 809                                         return ret;
 810                         }
 811                 }
 812         }
 813
 814         return ret;
 815 }
 816
 817 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 818 {
 819         int ret = 0;
 820
 821         if (enable) {
 822                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 823                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 824                         if (ret)
 825                                 return ret;
 826                 }
 827         } else {
 828                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 829                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 830                         if (ret)
 831                                 return ret;
 832                 }
 833         }
 834
 835         return ret;
 836 }
 837
 838 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 839                                        enum smu_clk_type clk_type,
 840                                        uint32_t *value)
 841 {
 842         MetricsMember_t member_type;
 843         int clk_id = 0;
 844
 845         clk_id = smu_cmn_to_asic_specific_index(smu,
 846                                                 CMN2ASIC_MAPPING_CLK,
 847                                                 clk_type);
 848         if (clk_id < 0)
 849                 return clk_id;
 850
 851         switch (clk_id) {
 852         case PPCLK_GFXCLK:
 853                 member_type = METRICS_CURR_GFXCLK;
 854                 break;
 855         case PPCLK_UCLK:
 856                 member_type = METRICS_CURR_UCLK;
 857                 break;
 858         case PPCLK_SOCCLK:
 859                 member_type = METRICS_CURR_SOCCLK;
 860                 break;
 861         case PPCLK_FCLK:
 862                 member_type = METRICS_CURR_FCLK;
 863                 break;
 864         case PPCLK_VCLK_0:
 865                 member_type = METRICS_CURR_VCLK;
 866                 break;
 867         case PPCLK_VCLK_1:
 868                 member_type = METRICS_CURR_VCLK1;
 869                 break;
 870         case PPCLK_DCLK_0:
 871                 member_type = METRICS_CURR_DCLK;
 872                 break;
 873         case PPCLK_DCLK_1:
 874                 member_type = METRICS_CURR_DCLK1;
 875                 break;
 876         case PPCLK_DCEFCLK:
 877                 member_type = METRICS_CURR_DCEFCLK;
 878                 break;
 879         default:
 880                 return -EINVAL;
 881         }
 882
 883         return sienna_cichlid_get_smu_metrics_data(smu,
 884                                                    member_type,
 885                                                    value);
 886
 887 }
 888
 889 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 890 {
 891         PPTable_t *pptable = smu->smu_table.driver_pptable;
 892         DpmDescriptor_t *dpm_desc = NULL;
 893         uint32_t clk_index = 0;
 894
 895         clk_index = smu_cmn_to_asic_specific_index(smu,
 896                                                    CMN2ASIC_MAPPING_CLK,
 897                                                    clk_type);
 898         dpm_desc = &pptable->DpmDescriptor[clk_index];
 899
 900         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 901         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 902 }
 903
 904 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 905                         enum smu_clk_type clk_type, char *buf)
 906 {
 907         struct amdgpu_device *adev = smu->adev;
 908         struct smu_table_context *table_context = &smu->smu_table;
 909         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 910         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 911         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 912         int i, size = 0, ret = 0;
 913         uint32_t cur_value = 0, value = 0, count = 0;
 914         uint32_t freq_values[3] = {0};
 915         uint32_t mark_index = 0;
 916         uint32_t gen_speed, lane_width;
 917
 918         switch (clk_type) {
 919         case SMU_GFXCLK:
 920         case SMU_SCLK:
 921         case SMU_SOCCLK:
 922         case SMU_MCLK:
 923         case SMU_UCLK:
 924         case SMU_FCLK:
 925         case SMU_DCEFCLK:
 926                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 927                 if (ret)
 928                         goto print_clk_out;
 929
 930                 /* no need to disable gfxoff when retrieving the current gfxclk */
 931                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 932                         amdgpu_gfx_off_ctrl(adev, false);
 933
 934                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 935                 if (ret)
 936                         goto print_clk_out;
 937
 938                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 939                         for (i = 0; i < count; i++) {
 940                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 941                                 if (ret)
 942                                         goto print_clk_out;
 943
 944                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 945                                                 cur_value == value ? "*" : "");
 946                         }
 947                 } else {
 948                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 949                         if (ret)
 950                                 goto print_clk_out;
 951                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 952                         if (ret)
 953                                 goto print_clk_out;
 954
 955                         freq_values[1] = cur_value;
 956                         mark_index = cur_value == freq_values[0] ? 0 :
 957                                      cur_value == freq_values[2] ? 2 : 1;
 958
 959                         count = 3;
 960                         if (mark_index != 1) {
 961                                 count = 2;
 962                                 freq_values[1] = freq_values[2];
 963                         }
 964
 965                         for (i = 0; i < count; i++) {
 966                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 967                                                 cur_value  == freq_values[i] ? "*" : "");
 968                         }
 969
 970                 }
 971                 break;
 972         case SMU_PCIE:
 973                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 974                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 975                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 976                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 977                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 978                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 979                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 980                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 981                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 982                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 983                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 984                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 985                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 986                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 987                                         pptable->LclkFreq[i],
 988                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 989                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 990                                         "*" : "");
 991                 break;
 992         default:
 993                 break;
 994         }
 995
 996 print_clk_out:
 997         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 998                 amdgpu_gfx_off_ctrl(adev, true);
 999
1000         return size;
1001 }
1002
1003 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1004                                    enum smu_clk_type clk_type, uint32_t mask)
1005 {
1006         struct amdgpu_device *adev = smu->adev;
1007         int ret = 0, size = 0;
1008         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1009
1010         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1011         soft_max_level = mask ? (fls(mask) - 1) : 0;
1012
1013         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1014                 amdgpu_gfx_off_ctrl(adev, false);
1015
1016         switch (clk_type) {
1017         case SMU_GFXCLK:
1018         case SMU_SCLK:
1019         case SMU_SOCCLK:
1020         case SMU_MCLK:
1021         case SMU_UCLK:
1022         case SMU_DCEFCLK:
1023         case SMU_FCLK:
1024                 /* There is only 2 levels for fine grained DPM */
1025                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1026                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1027                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1028                 }
1029
1030                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1031                 if (ret)
1032                         goto forec_level_out;
1033
1034                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1035                 if (ret)
1036                         goto forec_level_out;
1037
1038                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1039                 if (ret)
1040                         goto forec_level_out;
1041                 break;
1042         default:
1043                 break;
1044         }
1045
1046 forec_level_out:
1047         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1048                 amdgpu_gfx_off_ctrl(adev, true);
1049
1050         return size;
1051 }
1052
1053 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1054 {
1055         struct smu_11_0_dpm_context *dpm_context =
1056                                 smu->smu_dpm.dpm_context;
1057         struct smu_11_0_dpm_table *gfx_table =
1058                                 &dpm_context->dpm_tables.gfx_table;
1059         struct smu_11_0_dpm_table *mem_table =
1060                                 &dpm_context->dpm_tables.uclk_table;
1061         struct smu_11_0_dpm_table *soc_table =
1062                                 &dpm_context->dpm_tables.soc_table;
1063         struct smu_umd_pstate_table *pstate_table =
1064                                 &smu->pstate_table;
1065
1066         pstate_table->gfxclk_pstate.min = gfx_table->min;
1067         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1068
1069         pstate_table->uclk_pstate.min = mem_table->min;
1070         pstate_table->uclk_pstate.peak = mem_table->max;
1071
1072         pstate_table->socclk_pstate.min = soc_table->min;
1073         pstate_table->socclk_pstate.peak = soc_table->max;
1074
1075         return 0;
1076 }
1077
1078 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1079 {
1080         int ret = 0;
1081         uint32_t max_freq = 0;
1082
1083         /* Sienna_Cichlid do not support to change display num currently */
1084         return 0;
1085 #if 0
1086         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1087         if (ret)
1088                 return ret;
1089 #endif
1090
1091         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1092                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1093                 if (ret)
1094                         return ret;
1095                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1096                 if (ret)
1097                         return ret;
1098         }
1099
1100         return ret;
1101 }
1102
1103 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1104 {
1105         int ret = 0;
1106
1107         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1108             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1109             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1110 #if 0
1111                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1112                                                   smu->display_config->num_display,
1113                                                   NULL);
1114 #endif
1115                 if (ret)
1116                         return ret;
1117         }
1118
1119         return ret;
1120 }
1121
1122 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1123 {
1124         if (!value)
1125                 return -EINVAL;
1126
1127         return sienna_cichlid_get_smu_metrics_data(smu,
1128                                                    METRICS_AVERAGE_SOCKETPOWER,
1129                                                    value);
1130 }
1131
1132 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1133                                                enum amd_pp_sensors sensor,
1134                                                uint32_t *value)
1135 {
1136         int ret = 0;
1137
1138         if (!value)
1139                 return -EINVAL;
1140
1141         switch (sensor) {
1142         case AMDGPU_PP_SENSOR_GPU_LOAD:
1143                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1144                                                           METRICS_AVERAGE_GFXACTIVITY,
1145                                                           value);
1146                 break;
1147         case AMDGPU_PP_SENSOR_MEM_LOAD:
1148                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1149                                                           METRICS_AVERAGE_MEMACTIVITY,
1150                                                           value);
1151                 break;
1152         default:
1153                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1154                 return -EINVAL;
1155         }
1156
1157         return ret;
1158 }
1159
1160 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1161 {
1162         int ret = 0;
1163         uint32_t feature_mask[2];
1164         uint64_t feature_enabled;
1165
1166         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1167         if (ret)
1168                 return false;
1169
1170         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1171
1172         return !!(feature_enabled & SMC_DPM_FEATURE);
1173 }
1174
1175 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1176                                     uint32_t *speed)
1177 {
1178         if (!speed)
1179                 return -EINVAL;
1180
1181         return sienna_cichlid_get_smu_metrics_data(smu,
1182                                                 METRICS_CURR_FANSPEED,
1183                                                 speed);
1184 }
1185
1186 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1187 {
1188         PPTable_t *pptable = smu->smu_table.driver_pptable;
1189
1190         smu->fan_max_rpm = pptable->FanMaximumRpm;
1191
1192         return 0;
1193 }
1194
1195 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1196 {
1197         DpmActivityMonitorCoeffInt_t activity_monitor;
1198         uint32_t i, size = 0;
1199         int16_t workload_type = 0;
1200         static const char *profile_name[] = {
1201                                         "BOOTUP_DEFAULT",
1202                                         "3D_FULL_SCREEN",
1203                                         "POWER_SAVING",
1204                                         "VIDEO",
1205                                         "VR",
1206                                         "COMPUTE",
1207                                         "CUSTOM"};
1208         static const char *title[] = {
1209                         "PROFILE_INDEX(NAME)",
1210                         "CLOCK_TYPE(NAME)",
1211                         "FPS",
1212                         "MinFreqType",
1213                         "MinActiveFreqType",
1214                         "MinActiveFreq",
1215                         "BoosterFreqType",
1216                         "BoosterFreq",
1217                         "PD_Data_limit_c",
1218                         "PD_Data_error_coeff",
1219                         "PD_Data_error_rate_coeff"};
1220         int result = 0;
1221
1222         if (!buf)
1223                 return -EINVAL;
1224
1225         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1226                         title[0], title[1], title[2], title[3], title[4], title[5],
1227                         title[6], title[7], title[8], title[9], title[10]);
1228
1229         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1230                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1231                 workload_type = smu_cmn_to_asic_specific_index(smu,
1232                                                                CMN2ASIC_MAPPING_WORKLOAD,
1233                                                                i);
1234                 if (workload_type < 0)
1235                         return -EINVAL;
1236
1237                 result = smu_cmn_update_table(smu,
1238                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1239                                           (void *)(&activity_monitor), false);
1240                 if (result) {
1241                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1242                         return result;
1243                 }
1244
1245                 size += sprintf(buf + size, "%2d %14s%s:\n",
1246                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1247
1248                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1249                         " ",
1250                         0,
1251                         "GFXCLK",
1252                         activity_monitor.Gfx_FPS,
1253                         activity_monitor.Gfx_MinFreqStep,
1254                         activity_monitor.Gfx_MinActiveFreqType,
1255                         activity_monitor.Gfx_MinActiveFreq,
1256                         activity_monitor.Gfx_BoosterFreqType,
1257                         activity_monitor.Gfx_BoosterFreq,
1258                         activity_monitor.Gfx_PD_Data_limit_c,
1259                         activity_monitor.Gfx_PD_Data_error_coeff,
1260                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1261
1262                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1263                         " ",
1264                         1,
1265                         "SOCCLK",
1266                         activity_monitor.Fclk_FPS,
1267                         activity_monitor.Fclk_MinFreqStep,
1268                         activity_monitor.Fclk_MinActiveFreqType,
1269                         activity_monitor.Fclk_MinActiveFreq,
1270                         activity_monitor.Fclk_BoosterFreqType,
1271                         activity_monitor.Fclk_BoosterFreq,
1272                         activity_monitor.Fclk_PD_Data_limit_c,
1273                         activity_monitor.Fclk_PD_Data_error_coeff,
1274                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1275
1276                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1277                         " ",
1278                         2,
1279                         "MEMLK",
1280                         activity_monitor.Mem_FPS,
1281                         activity_monitor.Mem_MinFreqStep,
1282                         activity_monitor.Mem_MinActiveFreqType,
1283                         activity_monitor.Mem_MinActiveFreq,
1284                         activity_monitor.Mem_BoosterFreqType,
1285                         activity_monitor.Mem_BoosterFreq,
1286                         activity_monitor.Mem_PD_Data_limit_c,
1287                         activity_monitor.Mem_PD_Data_error_coeff,
1288                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1289         }
1290
1291         return size;
1292 }
1293
1294 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1295 {
1296         DpmActivityMonitorCoeffInt_t activity_monitor;
1297         int workload_type, ret = 0;
1298
1299         smu->power_profile_mode = input[size];
1300
1301         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1302                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1303                 return -EINVAL;
1304         }
1305
1306         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1307
1308                 ret = smu_cmn_update_table(smu,
1309                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1310                                        (void *)(&activity_monitor), false);
1311                 if (ret) {
1312                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1313                         return ret;
1314                 }
1315
1316                 switch (input[0]) {
1317                 case 0: /* Gfxclk */
1318                         activity_monitor.Gfx_FPS = input[1];
1319                         activity_monitor.Gfx_MinFreqStep = input[2];
1320                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1321                         activity_monitor.Gfx_MinActiveFreq = input[4];
1322                         activity_monitor.Gfx_BoosterFreqType = input[5];
1323                         activity_monitor.Gfx_BoosterFreq = input[6];
1324                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1325                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1326                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1327                         break;
1328                 case 1: /* Socclk */
1329                         activity_monitor.Fclk_FPS = input[1];
1330                         activity_monitor.Fclk_MinFreqStep = input[2];
1331                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1332                         activity_monitor.Fclk_MinActiveFreq = input[4];
1333                         activity_monitor.Fclk_BoosterFreqType = input[5];
1334                         activity_monitor.Fclk_BoosterFreq = input[6];
1335                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1336                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1337                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1338                         break;
1339                 case 2: /* Memlk */
1340                         activity_monitor.Mem_FPS = input[1];
1341                         activity_monitor.Mem_MinFreqStep = input[2];
1342                         activity_monitor.Mem_MinActiveFreqType = input[3];
1343                         activity_monitor.Mem_MinActiveFreq = input[4];
1344                         activity_monitor.Mem_BoosterFreqType = input[5];
1345                         activity_monitor.Mem_BoosterFreq = input[6];
1346                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1347                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1348                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1349                         break;
1350                 }
1351
1352                 ret = smu_cmn_update_table(smu,
1353                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1354                                        (void *)(&activity_monitor), true);
1355                 if (ret) {
1356                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1357                         return ret;
1358                 }
1359         }
1360
1361         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1362         workload_type = smu_cmn_to_asic_specific_index(smu,
1363                                                        CMN2ASIC_MAPPING_WORKLOAD,
1364                                                        smu->power_profile_mode);
1365         if (workload_type < 0)
1366                 return -EINVAL;
1367         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1368                                     1 << workload_type, NULL);
1369
1370         return ret;
1371 }
1372
1373 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1374 {
1375         struct smu_clocks min_clocks = {0};
1376         struct pp_display_clock_request clock_req;
1377         int ret = 0;
1378
1379         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1380         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1381         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1382
1383         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1384                 clock_req.clock_type = amd_pp_dcef_clock;
1385                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1386
1387                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1388                 if (!ret) {
1389                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1390                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1391                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1392                                                                   min_clocks.dcef_clock_in_sr/100,
1393                                                                   NULL);
1394                                 if (ret) {
1395                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1396                                         return ret;
1397                                 }
1398                         }
1399                 } else {
1400                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1401                 }
1402         }
1403
1404         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1405                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1406                 if (ret) {
1407                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1408                         return ret;
1409                 }
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1416                                                struct pp_smu_wm_range_sets *clock_ranges)
1417 {
1418         Watermarks_t *table = smu->smu_table.watermarks_table;
1419         int ret = 0;
1420         int i;
1421
1422         if (clock_ranges) {
1423                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1424                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1425                         return -EINVAL;
1426
1427                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1428                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1429                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1430                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1431                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1432                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1433                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1434                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1435                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1436
1437                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1438                                 clock_ranges->reader_wm_sets[i].wm_inst;
1439                 }
1440
1441                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1442                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1443                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1444                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1445                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1446                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1447                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1448                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1449                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1450
1451                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1452                                 clock_ranges->writer_wm_sets[i].wm_inst;
1453                 }
1454
1455                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1456         }
1457
1458         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1459              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1460                 ret = smu_cmn_write_watermarks_table(smu);
1461                 if (ret) {
1462                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1463                         return ret;
1464                 }
1465                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1472                                              enum amd_pp_sensors sensor,
1473                                              uint32_t *value)
1474 {
1475         int ret = 0;
1476
1477         if (!value)
1478                 return -EINVAL;
1479
1480         switch (sensor) {
1481         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1482                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1483                                                           METRICS_TEMPERATURE_HOTSPOT,
1484                                                           value);
1485                 break;
1486         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1487                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1488                                                           METRICS_TEMPERATURE_EDGE,
1489                                                           value);
1490                 break;
1491         case AMDGPU_PP_SENSOR_MEM_TEMP:
1492                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1493                                                           METRICS_TEMPERATURE_MEM,
1494                                                           value);
1495                 break;
1496         default:
1497                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1498                 return -EINVAL;
1499         }
1500
1501         return ret;
1502 }
1503
1504 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1505                                  enum amd_pp_sensors sensor,
1506                                  void *data, uint32_t *size)
1507 {
1508         int ret = 0;
1509         struct smu_table_context *table_context = &smu->smu_table;
1510         PPTable_t *pptable = table_context->driver_pptable;
1511
1512         if(!data || !size)
1513                 return -EINVAL;
1514
1515         mutex_lock(&smu->sensor_lock);
1516         switch (sensor) {
1517         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1518                 *(uint32_t *)data = pptable->FanMaximumRpm;
1519                 *size = 4;
1520                 break;
1521         case AMDGPU_PP_SENSOR_MEM_LOAD:
1522         case AMDGPU_PP_SENSOR_GPU_LOAD:
1523                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1524                 *size = 4;
1525                 break;
1526         case AMDGPU_PP_SENSOR_GPU_POWER:
1527                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1528                 *size = 4;
1529                 break;
1530         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1531         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1532         case AMDGPU_PP_SENSOR_MEM_TEMP:
1533                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1534                 *size = 4;
1535                 break;
1536         case AMDGPU_PP_SENSOR_GFX_MCLK:
1537                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1538                 *(uint32_t *)data *= 100;
1539                 *size = 4;
1540                 break;
1541         case AMDGPU_PP_SENSOR_GFX_SCLK:
1542                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1543                 *(uint32_t *)data *= 100;
1544                 *size = 4;
1545                 break;
1546         case AMDGPU_PP_SENSOR_VDDGFX:
1547                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1548                 *size = 4;
1549                 break;
1550         default:
1551                 ret = -EOPNOTSUPP;
1552                 break;
1553         }
1554         mutex_unlock(&smu->sensor_lock);
1555
1556         return ret;
1557 }
1558
1559 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1560 {
1561         uint32_t num_discrete_levels = 0;
1562         uint16_t *dpm_levels = NULL;
1563         uint16_t i = 0;
1564         struct smu_table_context *table_context = &smu->smu_table;
1565         PPTable_t *driver_ppt = NULL;
1566
1567         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1568                 return -EINVAL;
1569
1570         driver_ppt = table_context->driver_pptable;
1571         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1572         dpm_levels = driver_ppt->FreqTableUclk;
1573
1574         if (num_discrete_levels == 0 || dpm_levels == NULL)
1575                 return -EINVAL;
1576
1577         *num_states = num_discrete_levels;
1578         for (i = 0; i < num_discrete_levels; i++) {
1579                 /* convert to khz */
1580                 *clocks_in_khz = (*dpm_levels) * 1000;
1581                 clocks_in_khz++;
1582                 dpm_levels++;
1583         }
1584
1585         return 0;
1586 }
1587
1588 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1589                                                 struct smu_temperature_range *range)
1590 {
1591         struct smu_table_context *table_context = &smu->smu_table;
1592         struct smu_11_0_7_powerplay_table *powerplay_table =
1593                                 table_context->power_play_table;
1594         PPTable_t *pptable = smu->smu_table.driver_pptable;
1595
1596         if (!range)
1597                 return -EINVAL;
1598
1599         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1600
1601         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1602                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1603         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1604                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1605         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1606                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1607         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1608                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1609         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1610                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1611         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1612                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1613         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1614
1615         return 0;
1616 }
1617
1618 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1619                                                 bool disable_memory_clock_switch)
1620 {
1621         int ret = 0;
1622         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1623                 (struct smu_11_0_max_sustainable_clocks *)
1624                         smu->smu_table.max_sustainable_clocks;
1625         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1626         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1627
1628         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1629                 return 0;
1630
1631         if(disable_memory_clock_switch)
1632                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1633         else
1634                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1635
1636         if(!ret)
1637                 smu->disable_uclk_switch = disable_memory_clock_switch;
1638
1639         return ret;
1640 }
1641
1642 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1643 {
1644         struct smu_11_0_7_powerplay_table *powerplay_table =
1645                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1646         PPTable_t *pptable = smu->smu_table.driver_pptable;
1647         uint32_t power_limit, od_percent;
1648
1649         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1650                 /* the last hope to figure out the ppt limit */
1651                 if (!pptable) {
1652                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1653                         return -EINVAL;
1654                 }
1655                 power_limit =
1656                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1657         }
1658         smu->current_power_limit = power_limit;
1659
1660         if (smu->od_enabled) {
1661                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1662
1663                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1664
1665                 power_limit *= (100 + od_percent);
1666                 power_limit /= 100;
1667         }
1668         smu->max_power_limit = power_limit;
1669
1670         return 0;
1671 }
1672
1673 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1674                                          uint32_t pcie_gen_cap,
1675                                          uint32_t pcie_width_cap)
1676 {
1677         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1678         PPTable_t *pptable = smu->smu_table.driver_pptable;
1679         uint32_t smu_pcie_arg;
1680         int ret, i;
1681
1682         /* lclk dpm table setup */
1683         for (i = 0; i < MAX_PCIE_CONF; i++) {
1684                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1685                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1686         }
1687
1688         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1689                 smu_pcie_arg = (i << 16) |
1690                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1691                                         (pptable->PcieGenSpeed[i] << 8) :
1692                                         (pcie_gen_cap << 8)) |
1693                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1694                                         pptable->PcieLaneCount[i] :
1695                                         pcie_width_cap);
1696
1697                 ret = smu_cmn_send_smc_msg_with_param(smu,
1698                                           SMU_MSG_OverridePcieParameters,
1699                                           smu_pcie_arg,
1700                                           NULL);
1701
1702                 if (ret)
1703                         return ret;
1704
1705                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1706                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1707                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1708                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1715                                 enum smu_clk_type clk_type,
1716                                 uint32_t *min, uint32_t *max)
1717 {
1718         struct amdgpu_device *adev = smu->adev;
1719         int ret;
1720
1721         if (clk_type == SMU_GFXCLK)
1722                 amdgpu_gfx_off_ctrl(adev, false);
1723         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1724         if (clk_type == SMU_GFXCLK)
1725                 amdgpu_gfx_off_ctrl(adev, true);
1726
1727         return ret;
1728 }
1729
1730 static int sienna_cichlid_run_btc(struct smu_context *smu)
1731 {
1732         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1733 }
1734
1735 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1736 {
1737         struct amdgpu_device *adev = smu->adev;
1738         uint32_t val;
1739
1740         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1741                 return false;
1742
1743         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1744         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1745 }
1746
1747 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1748 {
1749         struct amdgpu_device *adev = smu->adev;
1750         uint32_t val;
1751         u32 smu_version;
1752
1753         /**
1754          * SRIOV env will not support SMU mode1 reset
1755          * PM FW support mode1 reset from 58.26
1756          */
1757         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1758         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1759                 return false;
1760
1761         /**
1762          * mode1 reset relies on PSP, so we should check if
1763          * PSP is alive.
1764          */
1765         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1766         return val != 0x0;
1767 }
1768
1769 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1770 {
1771         struct smu_table_context *table_context = &smu->smu_table;
1772         PPTable_t *pptable = table_context->driver_pptable;
1773         int i;
1774
1775         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1776
1777         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1778         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1779         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1780
1781         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1782                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1783                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1784                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1785                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1786         }
1787
1788         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1789                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1790                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1791         }
1792
1793         for (i = 0; i < TEMP_COUNT; i++) {
1794                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1795         }
1796
1797         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1798         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1799         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1800         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1801         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1802
1803         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1804         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1805                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1806                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1807         }
1808         dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1809         dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1810         dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1811         dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1812
1813         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1814
1815         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1816
1817         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1818         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1819         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1820         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1821
1822         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1823         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1824
1825         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1826         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1827         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1828         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1829
1830         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1831         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1832         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1833         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1834
1835         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1836         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1837
1838         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1839         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1840         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1841         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1842         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1843         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1844         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1845         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1846
1847         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1848                         "  .VoltageMode          = 0x%02x\n"
1849                         "  .SnapToDiscrete       = 0x%02x\n"
1850                         "  .NumDiscreteLevels    = 0x%02x\n"
1851                         "  .padding              = 0x%02x\n"
1852                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1853                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1854                         "  .SsFmin               = 0x%04x\n"
1855                         "  .Padding_16           = 0x%04x\n",
1856                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1857                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1858                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1859                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1860                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1861                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1862                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1863                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1864                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1865                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1866                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1867
1868         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1869                         "  .VoltageMode          = 0x%02x\n"
1870                         "  .SnapToDiscrete       = 0x%02x\n"
1871                         "  .NumDiscreteLevels    = 0x%02x\n"
1872                         "  .padding              = 0x%02x\n"
1873                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1874                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1875                         "  .SsFmin               = 0x%04x\n"
1876                         "  .Padding_16           = 0x%04x\n",
1877                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1878                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1879                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1880                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1881                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1882                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1883                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1884                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1885                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1886                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1887                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1888
1889         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1890                         "  .VoltageMode          = 0x%02x\n"
1891                         "  .SnapToDiscrete       = 0x%02x\n"
1892                         "  .NumDiscreteLevels    = 0x%02x\n"
1893                         "  .padding              = 0x%02x\n"
1894                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1895                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1896                         "  .SsFmin               = 0x%04x\n"
1897                         "  .Padding_16           = 0x%04x\n",
1898                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1899                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1900                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1901                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1902                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1903                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1904                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1905                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1906                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1907                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1908                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1909
1910         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1911                         "  .VoltageMode          = 0x%02x\n"
1912                         "  .SnapToDiscrete       = 0x%02x\n"
1913                         "  .NumDiscreteLevels    = 0x%02x\n"
1914                         "  .padding              = 0x%02x\n"
1915                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1916                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1917                         "  .SsFmin               = 0x%04x\n"
1918                         "  .Padding_16           = 0x%04x\n",
1919                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1920                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1921                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1922                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1923                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1924                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1925                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1926                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1927                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1928                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1929                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1930
1931         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1932                         "  .VoltageMode          = 0x%02x\n"
1933                         "  .SnapToDiscrete       = 0x%02x\n"
1934                         "  .NumDiscreteLevels    = 0x%02x\n"
1935                         "  .padding              = 0x%02x\n"
1936                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1937                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1938                         "  .SsFmin               = 0x%04x\n"
1939                         "  .Padding_16           = 0x%04x\n",
1940                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1941                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1942                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1943                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1944                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1945                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1946                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1947                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1948                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1949                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1950                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1951
1952         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1953                         "  .VoltageMode          = 0x%02x\n"
1954                         "  .SnapToDiscrete       = 0x%02x\n"
1955                         "  .NumDiscreteLevels    = 0x%02x\n"
1956                         "  .padding              = 0x%02x\n"
1957                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1958                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1959                         "  .SsFmin               = 0x%04x\n"
1960                         "  .Padding_16           = 0x%04x\n",
1961                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1962                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1963                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1964                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1965                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1966                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1967                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1968                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1969                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1970                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1971                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1972
1973         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
1974                         "  .VoltageMode          = 0x%02x\n"
1975                         "  .SnapToDiscrete       = 0x%02x\n"
1976                         "  .NumDiscreteLevels    = 0x%02x\n"
1977                         "  .padding              = 0x%02x\n"
1978                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1979                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1980                         "  .SsFmin               = 0x%04x\n"
1981                         "  .Padding_16           = 0x%04x\n",
1982                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1983                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1984                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1985                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1986                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1987                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1988                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1989                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1990                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1991                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1992                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1993
1994         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
1995                         "  .VoltageMode          = 0x%02x\n"
1996                         "  .SnapToDiscrete       = 0x%02x\n"
1997                         "  .NumDiscreteLevels    = 0x%02x\n"
1998                         "  .padding              = 0x%02x\n"
1999                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2000                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2001                         "  .SsFmin               = 0x%04x\n"
2002                         "  .Padding_16           = 0x%04x\n",
2003                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2004                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2005                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2006                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2007                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2008                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2009                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2010                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2011                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2012                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2013                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2014
2015         dev_info(smu->adev->dev, "FreqTableGfx\n");
2016         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2017                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2018
2019         dev_info(smu->adev->dev, "FreqTableVclk\n");
2020         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2021                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2022
2023         dev_info(smu->adev->dev, "FreqTableDclk\n");
2024         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2025                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2026
2027         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2028         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2029                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2030
2031         dev_info(smu->adev->dev, "FreqTableUclk\n");
2032         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2033                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2034
2035         dev_info(smu->adev->dev, "FreqTableFclk\n");
2036         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2037                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2038
2039         dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
2040         dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
2041         dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
2042         dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
2043         dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
2044         dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
2045         dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
2046         dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
2047         dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
2048         dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
2049         dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2050         dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2051         dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2052         dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2053         dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2054         dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2055
2056         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2057         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2058         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2059         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2060         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2061         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2062         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2063         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2064         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2065
2066         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2067         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2068                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2069
2070         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2071         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2072
2073         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2074         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2075                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2076
2077         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2078         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2079                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2080
2081         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2082         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2083                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2084
2085         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2086         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2087                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2088
2089         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2090         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2091         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2092         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2093         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2094
2095         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2096
2097         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2098         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2099         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2100         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2101         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2102         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2103         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2104         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2105         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2106         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2107         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2108
2109         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2110         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2111         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2112         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2113         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2114         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2115
2116         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2117         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2118         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2119         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2120         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2121
2122         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2123         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2124                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2125
2126         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2127         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2128         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2129         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2130
2131         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2132         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2133                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2134
2135         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2136         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2137                 pptable->UclkDpmSrcFreqRange.Fmin);
2138         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2139                 pptable->UclkDpmSrcFreqRange.Fmax);
2140         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2141         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2142                 pptable->UclkDpmTargFreqRange.Fmin);
2143         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2144                 pptable->UclkDpmTargFreqRange.Fmax);
2145         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2146         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2147
2148         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2149         for (i = 0; i < NUM_LINK_LEVELS; i++)
2150                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2151
2152         dev_info(smu->adev->dev, "PcieLaneCount\n");
2153         for (i = 0; i < NUM_LINK_LEVELS; i++)
2154                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2155
2156         dev_info(smu->adev->dev, "LclkFreq\n");
2157         for (i = 0; i < NUM_LINK_LEVELS; i++)
2158                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2159
2160         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2161         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2162
2163         dev_info(smu->adev->dev, "FanGain\n");
2164         for (i = 0; i < TEMP_COUNT; i++)
2165                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2166
2167         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2168         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2169         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2170         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2171         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2172         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2173         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2174         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2175         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2176         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2177         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2178         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2179
2180         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2181         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2182         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2183         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2184
2185         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2186         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2187         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2188         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2189
2190         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2191                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2192                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2193                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2194         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2195                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2196                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2197                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2198         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2199                         pptable->dBtcGbGfxPll.a,
2200                         pptable->dBtcGbGfxPll.b,
2201                         pptable->dBtcGbGfxPll.c);
2202         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2203                         pptable->dBtcGbGfxDfll.a,
2204                         pptable->dBtcGbGfxDfll.b,
2205                         pptable->dBtcGbGfxDfll.c);
2206         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2207                         pptable->dBtcGbSoc.a,
2208                         pptable->dBtcGbSoc.b,
2209                         pptable->dBtcGbSoc.c);
2210         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2211                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2212                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2213         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2214                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2215                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2216
2217         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2218         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2219                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2220                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2221                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2222                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2223         }
2224
2225         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2226                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2227                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2228                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2229         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2230                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2231                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2232                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2233
2234         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2235         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2236
2237         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2238         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2239         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2240         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2241
2242         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2243         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2244         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2245         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2246
2247         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2248         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2249
2250         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2251         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2252                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2253         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2254         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2255
2256         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2257         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2258                         pptable->ReservedEquation0.a,
2259                         pptable->ReservedEquation0.b,
2260                         pptable->ReservedEquation0.c);
2261         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2262                         pptable->ReservedEquation1.a,
2263                         pptable->ReservedEquation1.b,
2264                         pptable->ReservedEquation1.c);
2265         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2266                         pptable->ReservedEquation2.a,
2267                         pptable->ReservedEquation2.b,
2268                         pptable->ReservedEquation2.c);
2269         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2270                         pptable->ReservedEquation3.a,
2271                         pptable->ReservedEquation3.b,
2272                         pptable->ReservedEquation3.c);
2273
2274         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2275         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2276         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2277         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2278         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2279         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2280         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2281         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2282
2283         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2284         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2285         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2286         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2287         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2288         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2289
2290         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2291                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2292                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2293                                 pptable->I2cControllers[i].Enabled);
2294                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2295                                 pptable->I2cControllers[i].Speed);
2296                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2297                                 pptable->I2cControllers[i].SlaveAddress);
2298                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2299                                 pptable->I2cControllers[i].ControllerPort);
2300                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2301                                 pptable->I2cControllers[i].ControllerName);
2302                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2303                                 pptable->I2cControllers[i].ThermalThrotter);
2304                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2305                                 pptable->I2cControllers[i].I2cProtocol);
2306                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2307                                 pptable->I2cControllers[i].PaddingConfig);
2308         }
2309
2310         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2311         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2312         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2313         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2314
2315         dev_info(smu->adev->dev, "Board Parameters:\n");
2316         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2317         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2318         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2319         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2320         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2321         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2322         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2323         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2324
2325         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2326         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2327         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2328
2329         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2330         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2331         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2332
2333         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2334         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2335         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2336
2337         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2338         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2339         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2340
2341         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2342
2343         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2344         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2345         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2346         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2347         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2348         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2349         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2350         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2351         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2352         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2353         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2354         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2355         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2356         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2357         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2358         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2359
2360         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2361         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2362         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2363
2364         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2365         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2366         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2367
2368         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2369         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2370
2371         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2372         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2373         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2374
2375         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2376         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2377         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2378         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2379         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2380
2381         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2382         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2383
2384         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2385         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2386                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2387         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2388         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2389                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2390         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2391         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2392                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2393         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2394         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2395                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2396
2397         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2398         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2399         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2400         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2401
2402         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2403         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2404         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2405         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2406         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2407         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2408         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2409         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2410         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2411         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2412         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2413
2414         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2415         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2416         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2417         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2418         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2419         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2420         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2421         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2422 }
2423
2424 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2425                                   uint8_t address, uint32_t numbytes,
2426                                   uint8_t *data)
2427 {
2428         int i;
2429
2430         req->I2CcontrollerPort = 0;
2431         req->I2CSpeed = 2;
2432         req->SlaveAddress = address;
2433         req->NumCmds = numbytes;
2434
2435         for (i = 0; i < numbytes; i++) {
2436                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2437
2438                 /* First 2 bytes are always write for lower 2b EEPROM address */
2439                 if (i < 2)
2440                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2441                 else
2442                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2443
2444
2445                 /* Add RESTART for read  after address filled */
2446                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2447
2448                 /* Add STOP in the end */
2449                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2450
2451                 /* Fill with data regardless if read or write to simplify code */
2452                 cmd->ReadWriteData = data[i];
2453         }
2454 }
2455
2456 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2457                                                uint8_t address,
2458                                                uint8_t *data,
2459                                                uint32_t numbytes)
2460 {
2461         uint32_t  i, ret = 0;
2462         SwI2cRequest_t req;
2463         struct amdgpu_device *adev = to_amdgpu_device(control);
2464         struct smu_table_context *smu_table = &adev->smu.smu_table;
2465         struct smu_table *table = &smu_table->driver_table;
2466
2467         if (numbytes > MAX_SW_I2C_COMMANDS) {
2468                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2469                         numbytes, MAX_SW_I2C_COMMANDS);
2470                 return -EINVAL;
2471         }
2472
2473         memset(&req, 0, sizeof(req));
2474         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2475
2476         mutex_lock(&adev->smu.mutex);
2477         /* Now read data starting with that address */
2478         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2479                                         true);
2480         mutex_unlock(&adev->smu.mutex);
2481
2482         if (!ret) {
2483                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2484
2485                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2486                 for (i = 0; i < numbytes; i++)
2487                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2488
2489                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2490                                   (uint16_t)address, numbytes);
2491
2492                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2493                                8, 1, data, numbytes, false);
2494         } else
2495                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2496
2497         return ret;
2498 }
2499
2500 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2501                                                 uint8_t address,
2502                                                 uint8_t *data,
2503                                                 uint32_t numbytes)
2504 {
2505         uint32_t ret;
2506         SwI2cRequest_t req;
2507         struct amdgpu_device *adev = to_amdgpu_device(control);
2508
2509         if (numbytes > MAX_SW_I2C_COMMANDS) {
2510                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2511                         numbytes, MAX_SW_I2C_COMMANDS);
2512                 return -EINVAL;
2513         }
2514
2515         memset(&req, 0, sizeof(req));
2516         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2517
2518         mutex_lock(&adev->smu.mutex);
2519         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2520         mutex_unlock(&adev->smu.mutex);
2521
2522         if (!ret) {
2523                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2524                                          (uint16_t)address, numbytes);
2525
2526                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2527                                8, 1, data, numbytes, false);
2528                 /*
2529                  * According to EEPROM spec there is a MAX of 10 ms required for
2530                  * EEPROM to flush internal RX buffer after STOP was issued at the
2531                  * end of write transaction. During this time the EEPROM will not be
2532                  * responsive to any more commands - so wait a bit more.
2533                  */
2534                 msleep(10);
2535
2536         } else
2537                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2538
2539         return ret;
2540 }
2541
2542 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2543                               struct i2c_msg *msgs, int num)
2544 {
2545         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2546         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2547
2548         for (i = 0; i < num; i++) {
2549                 /*
2550                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2551                  * once and hence the data needs to be spliced into chunks and sent each
2552                  * chunk separately
2553                  */
2554                 data_size = msgs[i].len - 2;
2555                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2556                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2557                 data_ptr = msgs[i].buf + 2;
2558
2559                 for (j = 0; j < data_size / data_chunk_size; j++) {
2560                         /* Insert the EEPROM dest addess, bits 0-15 */
2561                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2562                         data_chunk[1] = (next_eeprom_addr & 0xff);
2563
2564                         if (msgs[i].flags & I2C_M_RD) {
2565                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2566                                                              (uint8_t)msgs[i].addr,
2567                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2568
2569                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2570                         } else {
2571
2572                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2573
2574                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2575                                                               (uint8_t)msgs[i].addr,
2576                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2577                         }
2578
2579                         if (ret) {
2580                                 num = -EIO;
2581                                 goto fail;
2582                         }
2583
2584                         next_eeprom_addr += data_chunk_size;
2585                         data_ptr += data_chunk_size;
2586                 }
2587
2588                 if (data_size % data_chunk_size) {
2589                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2590                         data_chunk[1] = (next_eeprom_addr & 0xff);
2591
2592                         if (msgs[i].flags & I2C_M_RD) {
2593                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2594                                                              (uint8_t)msgs[i].addr,
2595                                                              data_chunk, (data_size % data_chunk_size) + 2);
2596
2597                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2598                         } else {
2599                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2600
2601                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2602                                                               (uint8_t)msgs[i].addr,
2603                                                               data_chunk, (data_size % data_chunk_size) + 2);
2604                         }
2605
2606                         if (ret) {
2607                                 num = -EIO;
2608                                 goto fail;
2609                         }
2610                 }
2611         }
2612
2613 fail:
2614         return num;
2615 }
2616
2617 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2618 {
2619         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2620 }
2621
2622
2623 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2624         .master_xfer = sienna_cichlid_i2c_xfer,
2625         .functionality = sienna_cichlid_i2c_func,
2626 };
2627
2628 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2629 {
2630         struct amdgpu_device *adev = to_amdgpu_device(control);
2631         int res;
2632
2633         control->owner = THIS_MODULE;
2634         control->class = I2C_CLASS_SPD;
2635         control->dev.parent = &adev->pdev->dev;
2636         control->algo = &sienna_cichlid_i2c_algo;
2637         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2638
2639         res = i2c_add_adapter(control);
2640         if (res)
2641                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2642
2643         return res;
2644 }
2645
2646 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2647 {
2648         i2c_del_adapter(control);
2649 }
2650
2651 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2652                                               void **table)
2653 {
2654         struct smu_table_context *smu_table = &smu->smu_table;
2655         struct gpu_metrics_v1_0 *gpu_metrics =
2656                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2657         SmuMetrics_t metrics;
2658         int ret = 0;
2659
2660         ret = smu_cmn_get_metrics_table(smu,
2661                                         &metrics,
2662                                         true);
2663         if (ret)
2664                 return ret;
2665
2666         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2667
2668         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2669         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2670         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2671         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2672         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2673         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2674
2675         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2676         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2677         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2678
2679         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2680         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2681
2682         if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2683                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2684         else
2685                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2686         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2687         gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2688         gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2689         gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2690         gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2691
2692         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2693         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2694         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2695         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2696         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2697         gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2698         gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2699
2700         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2701
2702         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2703
2704         gpu_metrics->pcie_link_width =
2705                         smu_v11_0_get_current_pcie_link_width(smu);
2706         gpu_metrics->pcie_link_speed =
2707                         smu_v11_0_get_current_pcie_link_speed(smu);
2708
2709         *table = (void *)gpu_metrics;
2710
2711         return sizeof(struct gpu_metrics_v1_0);
2712 }
2713
2714 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2715 {
2716         return smu_cmn_send_smc_msg_with_param(smu,
2717                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2718                                                0,
2719                                                NULL);
2720 }
2721
2722 static int sienna_cichlid_gpo_control(struct smu_context *smu,
2723                                       bool enablement)
2724 {
2725         int ret = 0;
2726
2727         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2728                 if (enablement)
2729                         ret = smu_cmn_send_smc_msg_with_param(smu,
2730                                                         SMU_MSG_SetGpoFeaturePMask,
2731                                                         GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2732                                                         NULL);
2733                 else
2734                         ret = smu_cmn_send_smc_msg_with_param(smu,
2735                                                         SMU_MSG_SetGpoFeaturePMask,
2736                                                         0,
2737                                                         NULL);
2738         }
2739
2740         return ret;
2741 }
2742 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2743         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2744         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2745         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2746         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2747         .i2c_init = sienna_cichlid_i2c_control_init,
2748         .i2c_fini = sienna_cichlid_i2c_control_fini,
2749         .print_clk_levels = sienna_cichlid_print_clk_levels,
2750         .force_clk_levels = sienna_cichlid_force_clk_levels,
2751         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2752         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2753         .display_config_changed = sienna_cichlid_display_config_changed,
2754         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2755         .is_dpm_running = sienna_cichlid_is_dpm_running,
2756         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2757         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2758         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2759         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2760         .read_sensor = sienna_cichlid_read_sensor,
2761         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2762         .set_performance_level = smu_v11_0_set_performance_level,
2763         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2764         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2765         .get_power_limit = sienna_cichlid_get_power_limit,
2766         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2767         .dump_pptable = sienna_cichlid_dump_pptable,
2768         .init_microcode = smu_v11_0_init_microcode,
2769         .load_microcode = smu_v11_0_load_microcode,
2770         .init_smc_tables = sienna_cichlid_init_smc_tables,
2771         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2772         .init_power = smu_v11_0_init_power,
2773         .fini_power = smu_v11_0_fini_power,
2774         .check_fw_status = smu_v11_0_check_fw_status,
2775         .setup_pptable = sienna_cichlid_setup_pptable,
2776         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2777         .check_fw_version = smu_v11_0_check_fw_version,
2778         .write_pptable = smu_cmn_write_pptable,
2779         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2780         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2781         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2782         .system_features_control = smu_v11_0_system_features_control,
2783         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2784         .send_smc_msg = smu_cmn_send_smc_msg,
2785         .init_display_count = NULL,
2786         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2787         .get_enabled_mask = smu_cmn_get_enabled_mask,
2788         .feature_is_enabled = smu_cmn_feature_is_enabled,
2789         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2790         .notify_display_change = NULL,
2791         .set_power_limit = smu_v11_0_set_power_limit,
2792         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2793         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2794         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2795         .set_min_dcef_deep_sleep = NULL,
2796         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2797         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2798         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2799         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2800         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2801         .gfx_off_control = smu_v11_0_gfx_off_control,
2802         .register_irq_handler = smu_v11_0_register_irq_handler,
2803         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2804         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2805         .baco_is_support= sienna_cichlid_is_baco_supported,
2806         .baco_get_state = smu_v11_0_baco_get_state,
2807         .baco_set_state = smu_v11_0_baco_set_state,
2808         .baco_enter = smu_v11_0_baco_enter,
2809         .baco_exit = smu_v11_0_baco_exit,
2810         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2811         .mode1_reset = smu_v11_0_mode1_reset,
2812         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2813         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2814         .run_btc = sienna_cichlid_run_btc,
2815         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2816         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2817         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2818         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2819         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2820         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2821         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2822         .interrupt_work = smu_v11_0_interrupt_work,
2823         .gpo_control = sienna_cichlid_gpo_control,
2824 };
2825
2826 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2827 {
2828         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2829         smu->message_map = sienna_cichlid_message_map;
2830         smu->clock_map = sienna_cichlid_clk_map;
2831         smu->feature_map = sienna_cichlid_feature_mask_map;
2832         smu->table_map = sienna_cichlid_table_map;
2833         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2834         smu->workload_map = sienna_cichlid_workload_map;
2835 }