drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  77         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  78         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  79         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  80         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  81         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  82         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  83         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  84         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  85         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  86         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  87         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  88         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  89         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  90         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  91         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  92         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  93         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  94         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  95         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  96         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  97         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  98         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  99         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 113         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 114         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 115         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 116         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 117         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 118         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 119         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 120         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 121         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 122         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 123         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 124         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 125         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 126         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 127         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 128         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 129         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 130         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 131         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 132         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 133 };
 134
 135 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 136         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 137         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 138         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 139         CLK_MAP(FCLK,           PPCLK_FCLK),
 140         CLK_MAP(UCLK,           PPCLK_UCLK),
 141         CLK_MAP(MCLK,           PPCLK_UCLK),
 142         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 143         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 144         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 145         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 146         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 147         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 148         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 149         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 150 };
 151
 152 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 153         FEA_MAP(DPM_PREFETCHER),
 154         FEA_MAP(DPM_GFXCLK),
 155         FEA_MAP(DPM_GFX_GPO),
 156         FEA_MAP(DPM_UCLK),
 157         FEA_MAP(DPM_FCLK),
 158         FEA_MAP(DPM_SOCCLK),
 159         FEA_MAP(DPM_MP0CLK),
 160         FEA_MAP(DPM_LINK),
 161         FEA_MAP(DPM_DCEFCLK),
 162         FEA_MAP(DPM_XGMI),
 163         FEA_MAP(MEM_VDDCI_SCALING),
 164         FEA_MAP(MEM_MVDD_SCALING),
 165         FEA_MAP(DS_GFXCLK),
 166         FEA_MAP(DS_SOCCLK),
 167         FEA_MAP(DS_FCLK),
 168         FEA_MAP(DS_LCLK),
 169         FEA_MAP(DS_DCEFCLK),
 170         FEA_MAP(DS_UCLK),
 171         FEA_MAP(GFX_ULV),
 172         FEA_MAP(FW_DSTATE),
 173         FEA_MAP(GFXOFF),
 174         FEA_MAP(BACO),
 175         FEA_MAP(MM_DPM_PG),
 176         FEA_MAP(RSMU_SMN_CG),
 177         FEA_MAP(PPT),
 178         FEA_MAP(TDC),
 179         FEA_MAP(APCC_PLUS),
 180         FEA_MAP(GTHR),
 181         FEA_MAP(ACDC),
 182         FEA_MAP(VR0HOT),
 183         FEA_MAP(VR1HOT),
 184         FEA_MAP(FW_CTF),
 185         FEA_MAP(FAN_CONTROL),
 186         FEA_MAP(THERMAL),
 187         FEA_MAP(GFX_DCS),
 188         FEA_MAP(RM),
 189         FEA_MAP(LED_DISPLAY),
 190         FEA_MAP(GFX_SS),
 191         FEA_MAP(OUT_OF_BAND_MONITOR),
 192         FEA_MAP(TEMP_DEPENDENT_VMIN),
 193         FEA_MAP(MMHUB_PG),
 194         FEA_MAP(ATHUB_PG),
 195         FEA_MAP(APCC_DFLL),
 196 };
 197
 198 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 199         TAB_MAP(PPTABLE),
 200         TAB_MAP(WATERMARKS),
 201         TAB_MAP(AVFS_PSM_DEBUG),
 202         TAB_MAP(AVFS_FUSE_OVERRIDE),
 203         TAB_MAP(PMSTATUSLOG),
 204         TAB_MAP(SMU_METRICS),
 205         TAB_MAP(DRIVER_SMU_CONFIG),
 206         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 207         TAB_MAP(OVERDRIVE),
 208         TAB_MAP(I2C_COMMANDS),
 209         TAB_MAP(PACE),
 210 };
 211
 212 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 213         PWR_MAP(AC),
 214         PWR_MAP(DC),
 215 };
 216
 217 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 224         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 225 };
 226
 227 static int
 228 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 229                                   uint32_t *feature_mask, uint32_t num)
 230 {
 231         struct amdgpu_device *adev = smu->adev;
 232
 233         if (num > 2)
 234                 return -EINVAL;
 235
 236         memset(feature_mask, 0, sizeof(uint32_t) * num);
 237
 238         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 239                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 240                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 241                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 242                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 243                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 244                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 245                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 246                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 247                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 248                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 249                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 250                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 251                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 252                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 253                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 254                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 255                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 256                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 257                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 258
 259         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 260                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 261                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 262         }
 263
 264         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 265                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 266                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 267                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 268
 269         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 270                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 271
 272         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 273                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 274
 275         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 276                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 277
 278         if (adev->pm.pp_feature & PP_ULV_MASK)
 279                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 280
 281         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 282                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 283
 284         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 285                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 286
 287         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 288                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 289
 290         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 291                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 292
 293         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 294             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 295                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 296
 297         return 0;
 298 }
 299
 300 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 301 {
 302         struct smu_table_context *table_context = &smu->smu_table;
 303         struct smu_11_0_7_powerplay_table *powerplay_table =
 304                 table_context->power_play_table;
 305         struct smu_baco_context *smu_baco = &smu->smu_baco;
 306
 307         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 308                 smu->dc_controlled_by_gpio = true;
 309
 310         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 311             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 312                 smu_baco->platform_support = true;
 313
 314         table_context->thermal_controller_type =
 315                 powerplay_table->thermal_controller_type;
 316
 317         /*
 318          * Instead of having its own buffer space and get overdrive_table copied,
 319          * smu->od_settings just points to the actual overdrive_table
 320          */
 321         smu->od_settings = &powerplay_table->overdrive_table;
 322
 323         return 0;
 324 }
 325
 326 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 327 {
 328         struct smu_table_context *table_context = &smu->smu_table;
 329         PPTable_t *smc_pptable = table_context->driver_pptable;
 330         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 331         int index, ret;
 332
 333         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 334                                             smc_dpm_info);
 335
 336         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 337                                       (uint8_t **)&smc_dpm_table);
 338         if (ret)
 339                 return ret;
 340
 341         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 342                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 343
 344         return 0;
 345 }
 346
 347 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 348 {
 349         struct smu_table_context *table_context = &smu->smu_table;
 350         struct smu_11_0_7_powerplay_table *powerplay_table =
 351                 table_context->power_play_table;
 352
 353         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 354                sizeof(PPTable_t));
 355
 356         return 0;
 357 }
 358
 359 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 360 {
 361         int ret = 0;
 362
 363         ret = smu_v11_0_setup_pptable(smu);
 364         if (ret)
 365                 return ret;
 366
 367         ret = sienna_cichlid_store_powerplay_table(smu);
 368         if (ret)
 369                 return ret;
 370
 371         ret = sienna_cichlid_append_powerplay_table(smu);
 372         if (ret)
 373                 return ret;
 374
 375         ret = sienna_cichlid_check_powerplay_table(smu);
 376         if (ret)
 377                 return ret;
 378
 379         return ret;
 380 }
 381
 382 static int sienna_cichlid_tables_init(struct smu_context *smu)
 383 {
 384         struct smu_table_context *smu_table = &smu->smu_table;
 385         struct smu_table *tables = smu_table->tables;
 386
 387         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 388                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 389         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 390                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 391         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 392                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 393         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 394                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 395         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 396                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 397         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 398                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 399         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 400                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 401                        AMDGPU_GEM_DOMAIN_VRAM);
 402
 403         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 404         if (!smu_table->metrics_table)
 405                 goto err0_out;
 406         smu_table->metrics_time = 0;
 407
 408         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 409         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 410         if (!smu_table->gpu_metrics_table)
 411                 goto err1_out;
 412
 413         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 414         if (!smu_table->watermarks_table)
 415                 goto err2_out;
 416
 417         return 0;
 418
 419 err2_out:
 420         kfree(smu_table->gpu_metrics_table);
 421 err1_out:
 422         kfree(smu_table->metrics_table);
 423 err0_out:
 424         return -ENOMEM;
 425 }
 426
 427 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 428                                                MetricsMember_t member,
 429                                                uint32_t *value)
 430 {
 431         struct smu_table_context *smu_table= &smu->smu_table;
 432         SmuMetrics_t *metrics =
 433                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 434         int ret = 0;
 435
 436         mutex_lock(&smu->metrics_lock);
 437
 438         ret = smu_cmn_get_metrics_table_locked(smu,
 439                                                NULL,
 440                                                false);
 441         if (ret) {
 442                 mutex_unlock(&smu->metrics_lock);
 443                 return ret;
 444         }
 445
 446         switch (member) {
 447         case METRICS_CURR_GFXCLK:
 448                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 449                 break;
 450         case METRICS_CURR_SOCCLK:
 451                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 452                 break;
 453         case METRICS_CURR_UCLK:
 454                 *value = metrics->CurrClock[PPCLK_UCLK];
 455                 break;
 456         case METRICS_CURR_VCLK:
 457                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 458                 break;
 459         case METRICS_CURR_VCLK1:
 460                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 461                 break;
 462         case METRICS_CURR_DCLK:
 463                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 464                 break;
 465         case METRICS_CURR_DCLK1:
 466                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 467                 break;
 468         case METRICS_CURR_DCEFCLK:
 469                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 470                 break;
 471         case METRICS_CURR_FCLK:
 472                 *value = metrics->CurrClock[PPCLK_FCLK];
 473                 break;
 474         case METRICS_AVERAGE_GFXCLK:
 475                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 476                         *value = metrics->AverageGfxclkFrequencyPostDs;
 477                 else
 478                         *value = metrics->AverageGfxclkFrequencyPreDs;
 479                 break;
 480         case METRICS_AVERAGE_FCLK:
 481                 *value = metrics->AverageFclkFrequencyPostDs;
 482                 break;
 483         case METRICS_AVERAGE_UCLK:
 484                 *value = metrics->AverageUclkFrequencyPostDs;
 485                 break;
 486         case METRICS_AVERAGE_GFXACTIVITY:
 487                 *value = metrics->AverageGfxActivity;
 488                 break;
 489         case METRICS_AVERAGE_MEMACTIVITY:
 490                 *value = metrics->AverageUclkActivity;
 491                 break;
 492         case METRICS_AVERAGE_SOCKETPOWER:
 493                 *value = metrics->AverageSocketPower << 8;
 494                 break;
 495         case METRICS_TEMPERATURE_EDGE:
 496                 *value = metrics->TemperatureEdge *
 497                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 498                 break;
 499         case METRICS_TEMPERATURE_HOTSPOT:
 500                 *value = metrics->TemperatureHotspot *
 501                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 502                 break;
 503         case METRICS_TEMPERATURE_MEM:
 504                 *value = metrics->TemperatureMem *
 505                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 506                 break;
 507         case METRICS_TEMPERATURE_VRGFX:
 508                 *value = metrics->TemperatureVrGfx *
 509                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 510                 break;
 511         case METRICS_TEMPERATURE_VRSOC:
 512                 *value = metrics->TemperatureVrSoc *
 513                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 514                 break;
 515         case METRICS_THROTTLER_STATUS:
 516                 *value = metrics->ThrottlerStatus;
 517                 break;
 518         case METRICS_CURR_FANSPEED:
 519                 *value = metrics->CurrFanSpeed;
 520                 break;
 521         default:
 522                 *value = UINT_MAX;
 523                 break;
 524         }
 525
 526         mutex_unlock(&smu->metrics_lock);
 527
 528         return ret;
 529
 530 }
 531
 532 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 533 {
 534         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 535
 536         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 537                                        GFP_KERNEL);
 538         if (!smu_dpm->dpm_context)
 539                 return -ENOMEM;
 540
 541         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 542
 543         return 0;
 544 }
 545
 546 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 547 {
 548         int ret = 0;
 549
 550         ret = sienna_cichlid_tables_init(smu);
 551         if (ret)
 552                 return ret;
 553
 554         ret = sienna_cichlid_allocate_dpm_context(smu);
 555         if (ret)
 556                 return ret;
 557
 558         return smu_v11_0_init_smc_tables(smu);
 559 }
 560
 561 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 562 {
 563         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 564         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 565         struct smu_11_0_dpm_table *dpm_table;
 566         struct amdgpu_device *adev = smu->adev;
 567         int ret = 0;
 568
 569         /* socclk dpm table setup */
 570         dpm_table = &dpm_context->dpm_tables.soc_table;
 571         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 572                 ret = smu_v11_0_set_single_dpm_table(smu,
 573                                                      SMU_SOCCLK,
 574                                                      dpm_table);
 575                 if (ret)
 576                         return ret;
 577                 dpm_table->is_fine_grained =
 578                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 579         } else {
 580                 dpm_table->count = 1;
 581                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 582                 dpm_table->dpm_levels[0].enabled = true;
 583                 dpm_table->min = dpm_table->dpm_levels[0].value;
 584                 dpm_table->max = dpm_table->dpm_levels[0].value;
 585         }
 586
 587         /* gfxclk dpm table setup */
 588         dpm_table = &dpm_context->dpm_tables.gfx_table;
 589         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 590                 ret = smu_v11_0_set_single_dpm_table(smu,
 591                                                      SMU_GFXCLK,
 592                                                      dpm_table);
 593                 if (ret)
 594                         return ret;
 595                 dpm_table->is_fine_grained =
 596                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 597         } else {
 598                 dpm_table->count = 1;
 599                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 600                 dpm_table->dpm_levels[0].enabled = true;
 601                 dpm_table->min = dpm_table->dpm_levels[0].value;
 602                 dpm_table->max = dpm_table->dpm_levels[0].value;
 603         }
 604
 605         /* uclk dpm table setup */
 606         dpm_table = &dpm_context->dpm_tables.uclk_table;
 607         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 608                 ret = smu_v11_0_set_single_dpm_table(smu,
 609                                                      SMU_UCLK,
 610                                                      dpm_table);
 611                 if (ret)
 612                         return ret;
 613                 dpm_table->is_fine_grained =
 614                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 615         } else {
 616                 dpm_table->count = 1;
 617                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 618                 dpm_table->dpm_levels[0].enabled = true;
 619                 dpm_table->min = dpm_table->dpm_levels[0].value;
 620                 dpm_table->max = dpm_table->dpm_levels[0].value;
 621         }
 622
 623         /* fclk dpm table setup */
 624         dpm_table = &dpm_context->dpm_tables.fclk_table;
 625         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 626                 ret = smu_v11_0_set_single_dpm_table(smu,
 627                                                      SMU_FCLK,
 628                                                      dpm_table);
 629                 if (ret)
 630                         return ret;
 631                 dpm_table->is_fine_grained =
 632                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 633         } else {
 634                 dpm_table->count = 1;
 635                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 636                 dpm_table->dpm_levels[0].enabled = true;
 637                 dpm_table->min = dpm_table->dpm_levels[0].value;
 638                 dpm_table->max = dpm_table->dpm_levels[0].value;
 639         }
 640
 641         /* vclk0 dpm table setup */
 642         dpm_table = &dpm_context->dpm_tables.vclk_table;
 643         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 644                 ret = smu_v11_0_set_single_dpm_table(smu,
 645                                                      SMU_VCLK,
 646                                                      dpm_table);
 647                 if (ret)
 648                         return ret;
 649                 dpm_table->is_fine_grained =
 650                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 651         } else {
 652                 dpm_table->count = 1;
 653                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 654                 dpm_table->dpm_levels[0].enabled = true;
 655                 dpm_table->min = dpm_table->dpm_levels[0].value;
 656                 dpm_table->max = dpm_table->dpm_levels[0].value;
 657         }
 658
 659         /* vclk1 dpm table setup */
 660         if (adev->vcn.num_vcn_inst > 1) {
 661                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 662                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 663                         ret = smu_v11_0_set_single_dpm_table(smu,
 664                                                              SMU_VCLK1,
 665                                                              dpm_table);
 666                         if (ret)
 667                                 return ret;
 668                         dpm_table->is_fine_grained =
 669                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 670                 } else {
 671                         dpm_table->count = 1;
 672                         dpm_table->dpm_levels[0].value =
 673                                 smu->smu_table.boot_values.vclk / 100;
 674                         dpm_table->dpm_levels[0].enabled = true;
 675                         dpm_table->min = dpm_table->dpm_levels[0].value;
 676                         dpm_table->max = dpm_table->dpm_levels[0].value;
 677                 }
 678         }
 679
 680         /* dclk0 dpm table setup */
 681         dpm_table = &dpm_context->dpm_tables.dclk_table;
 682         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 683                 ret = smu_v11_0_set_single_dpm_table(smu,
 684                                                      SMU_DCLK,
 685                                                      dpm_table);
 686                 if (ret)
 687                         return ret;
 688                 dpm_table->is_fine_grained =
 689                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 690         } else {
 691                 dpm_table->count = 1;
 692                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 693                 dpm_table->dpm_levels[0].enabled = true;
 694                 dpm_table->min = dpm_table->dpm_levels[0].value;
 695                 dpm_table->max = dpm_table->dpm_levels[0].value;
 696         }
 697
 698         /* dclk1 dpm table setup */
 699         if (adev->vcn.num_vcn_inst > 1) {
 700                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 701                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 702                         ret = smu_v11_0_set_single_dpm_table(smu,
 703                                                              SMU_DCLK1,
 704                                                              dpm_table);
 705                         if (ret)
 706                                 return ret;
 707                         dpm_table->is_fine_grained =
 708                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 709                 } else {
 710                         dpm_table->count = 1;
 711                         dpm_table->dpm_levels[0].value =
 712                                 smu->smu_table.boot_values.dclk / 100;
 713                         dpm_table->dpm_levels[0].enabled = true;
 714                         dpm_table->min = dpm_table->dpm_levels[0].value;
 715                         dpm_table->max = dpm_table->dpm_levels[0].value;
 716                 }
 717         }
 718
 719         /* dcefclk dpm table setup */
 720         dpm_table = &dpm_context->dpm_tables.dcef_table;
 721         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 722                 ret = smu_v11_0_set_single_dpm_table(smu,
 723                                                      SMU_DCEFCLK,
 724                                                      dpm_table);
 725                 if (ret)
 726                         return ret;
 727                 dpm_table->is_fine_grained =
 728                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 729         } else {
 730                 dpm_table->count = 1;
 731                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 732                 dpm_table->dpm_levels[0].enabled = true;
 733                 dpm_table->min = dpm_table->dpm_levels[0].value;
 734                 dpm_table->max = dpm_table->dpm_levels[0].value;
 735         }
 736
 737         /* pixelclk dpm table setup */
 738         dpm_table = &dpm_context->dpm_tables.pixel_table;
 739         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 740                 ret = smu_v11_0_set_single_dpm_table(smu,
 741                                                      SMU_PIXCLK,
 742                                                      dpm_table);
 743                 if (ret)
 744                         return ret;
 745                 dpm_table->is_fine_grained =
 746                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 747         } else {
 748                 dpm_table->count = 1;
 749                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 750                 dpm_table->dpm_levels[0].enabled = true;
 751                 dpm_table->min = dpm_table->dpm_levels[0].value;
 752                 dpm_table->max = dpm_table->dpm_levels[0].value;
 753         }
 754
 755         /* displayclk dpm table setup */
 756         dpm_table = &dpm_context->dpm_tables.display_table;
 757         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 758                 ret = smu_v11_0_set_single_dpm_table(smu,
 759                                                      SMU_DISPCLK,
 760                                                      dpm_table);
 761                 if (ret)
 762                         return ret;
 763                 dpm_table->is_fine_grained =
 764                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 765         } else {
 766                 dpm_table->count = 1;
 767                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 768                 dpm_table->dpm_levels[0].enabled = true;
 769                 dpm_table->min = dpm_table->dpm_levels[0].value;
 770                 dpm_table->max = dpm_table->dpm_levels[0].value;
 771         }
 772
 773         /* phyclk dpm table setup */
 774         dpm_table = &dpm_context->dpm_tables.phy_table;
 775         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 776                 ret = smu_v11_0_set_single_dpm_table(smu,
 777                                                      SMU_PHYCLK,
 778                                                      dpm_table);
 779                 if (ret)
 780                         return ret;
 781                 dpm_table->is_fine_grained =
 782                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 783         } else {
 784                 dpm_table->count = 1;
 785                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 786                 dpm_table->dpm_levels[0].enabled = true;
 787                 dpm_table->min = dpm_table->dpm_levels[0].value;
 788                 dpm_table->max = dpm_table->dpm_levels[0].value;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 795 {
 796         struct amdgpu_device *adev = smu->adev;
 797         int ret = 0;
 798
 799         if (enable) {
 800                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 801                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 802                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 803                         if (ret)
 804                                 return ret;
 805                         if (adev->vcn.num_vcn_inst > 1) {
 806                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 807                                                                   0x10000, NULL);
 808                                 if (ret)
 809                                         return ret;
 810                         }
 811                 }
 812         } else {
 813                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 814                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 815                         if (ret)
 816                                 return ret;
 817                         if (adev->vcn.num_vcn_inst > 1) {
 818                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 819                                                                   0x10000, NULL);
 820                                 if (ret)
 821                                         return ret;
 822                         }
 823                 }
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 830 {
 831         int ret = 0;
 832
 833         if (enable) {
 834                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 835                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 836                         if (ret)
 837                                 return ret;
 838                 }
 839         } else {
 840                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 841                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 842                         if (ret)
 843                                 return ret;
 844                 }
 845         }
 846
 847         return ret;
 848 }
 849
 850 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 851                                        enum smu_clk_type clk_type,
 852                                        uint32_t *value)
 853 {
 854         MetricsMember_t member_type;
 855         int clk_id = 0;
 856
 857         clk_id = smu_cmn_to_asic_specific_index(smu,
 858                                                 CMN2ASIC_MAPPING_CLK,
 859                                                 clk_type);
 860         if (clk_id < 0)
 861                 return clk_id;
 862
 863         switch (clk_id) {
 864         case PPCLK_GFXCLK:
 865                 member_type = METRICS_CURR_GFXCLK;
 866                 break;
 867         case PPCLK_UCLK:
 868                 member_type = METRICS_CURR_UCLK;
 869                 break;
 870         case PPCLK_SOCCLK:
 871                 member_type = METRICS_CURR_SOCCLK;
 872                 break;
 873         case PPCLK_FCLK:
 874                 member_type = METRICS_CURR_FCLK;
 875                 break;
 876         case PPCLK_VCLK_0:
 877                 member_type = METRICS_CURR_VCLK;
 878                 break;
 879         case PPCLK_VCLK_1:
 880                 member_type = METRICS_CURR_VCLK1;
 881                 break;
 882         case PPCLK_DCLK_0:
 883                 member_type = METRICS_CURR_DCLK;
 884                 break;
 885         case PPCLK_DCLK_1:
 886                 member_type = METRICS_CURR_DCLK1;
 887                 break;
 888         case PPCLK_DCEFCLK:
 889                 member_type = METRICS_CURR_DCEFCLK;
 890                 break;
 891         default:
 892                 return -EINVAL;
 893         }
 894
 895         return sienna_cichlid_get_smu_metrics_data(smu,
 896                                                    member_type,
 897                                                    value);
 898
 899 }
 900
 901 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 902 {
 903         PPTable_t *pptable = smu->smu_table.driver_pptable;
 904         DpmDescriptor_t *dpm_desc = NULL;
 905         uint32_t clk_index = 0;
 906
 907         clk_index = smu_cmn_to_asic_specific_index(smu,
 908                                                    CMN2ASIC_MAPPING_CLK,
 909                                                    clk_type);
 910         dpm_desc = &pptable->DpmDescriptor[clk_index];
 911
 912         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 913         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 914 }
 915
 916 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
 917                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
 918 {
 919         return od_table->cap[cap];
 920 }
 921
 922 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
 923                                                 enum SMU_11_0_7_ODSETTING_ID setting,
 924                                                 uint32_t *min, uint32_t *max)
 925 {
 926         if (min)
 927                 *min = od_table->min[setting];
 928         if (max)
 929                 *max = od_table->max[setting];
 930 }
 931
 932 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 933                         enum smu_clk_type clk_type, char *buf)
 934 {
 935         struct amdgpu_device *adev = smu->adev;
 936         struct smu_table_context *table_context = &smu->smu_table;
 937         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 938         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 939         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 940         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
 941         OverDriveTable_t *od_table =
 942                 (OverDriveTable_t *)table_context->overdrive_table;
 943         int i, size = 0, ret = 0;
 944         uint32_t cur_value = 0, value = 0, count = 0;
 945         uint32_t freq_values[3] = {0};
 946         uint32_t mark_index = 0;
 947         uint32_t gen_speed, lane_width;
 948         uint32_t min_value, max_value;
 949
 950         switch (clk_type) {
 951         case SMU_GFXCLK:
 952         case SMU_SCLK:
 953         case SMU_SOCCLK:
 954         case SMU_MCLK:
 955         case SMU_UCLK:
 956         case SMU_FCLK:
 957         case SMU_DCEFCLK:
 958                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 959                 if (ret)
 960                         goto print_clk_out;
 961
 962                 /* no need to disable gfxoff when retrieving the current gfxclk */
 963                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 964                         amdgpu_gfx_off_ctrl(adev, false);
 965
 966                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 967                 if (ret)
 968                         goto print_clk_out;
 969
 970                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 971                         for (i = 0; i < count; i++) {
 972                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 973                                 if (ret)
 974                                         goto print_clk_out;
 975
 976                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 977                                                 cur_value == value ? "*" : "");
 978                         }
 979                 } else {
 980                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 981                         if (ret)
 982                                 goto print_clk_out;
 983                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 984                         if (ret)
 985                                 goto print_clk_out;
 986
 987                         freq_values[1] = cur_value;
 988                         mark_index = cur_value == freq_values[0] ? 0 :
 989                                      cur_value == freq_values[2] ? 2 : 1;
 990
 991                         count = 3;
 992                         if (mark_index != 1) {
 993                                 count = 2;
 994                                 freq_values[1] = freq_values[2];
 995                         }
 996
 997                         for (i = 0; i < count; i++) {
 998                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 999                                                 cur_value  == freq_values[i] ? "*" : "");
1000                         }
1001
1002                 }
1003                 break;
1004         case SMU_PCIE:
1005                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1006                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1007                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1008                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1009                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1010                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1011                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1012                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1013                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1014                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1015                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1016                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1017                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1018                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1019                                         pptable->LclkFreq[i],
1020                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1021                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1022                                         "*" : "");
1023                 break;
1024         case SMU_OD_SCLK:
1025                 if (!smu->od_enabled || !od_table || !od_settings)
1026                         break;
1027
1028                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1029                         break;
1030
1031                 size += sprintf(buf + size, "OD_SCLK:\n");
1032                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1033                 break;
1034
1035         case SMU_OD_MCLK:
1036                 if (!smu->od_enabled || !od_table || !od_settings)
1037                         break;
1038
1039                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1040                         break;
1041
1042                 size += sprintf(buf + size, "OD_MCLK:\n");
1043                 size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1044                 break;
1045
1046         case SMU_OD_RANGE:
1047                 if (!smu->od_enabled || !od_table || !od_settings)
1048                         break;
1049
1050                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1051
1052                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1053                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1054                                                             &min_value, NULL);
1055                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1056                                                             NULL, &max_value);
1057                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1058                                         min_value, max_value);
1059                 }
1060
1061                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1062                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1063                                                             &min_value, NULL);
1064                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1065                                                             NULL, &max_value);
1066                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1067                                         min_value, max_value);
1068                 }
1069                 break;
1070
1071         default:
1072                 break;
1073         }
1074
1075 print_clk_out:
1076         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1077                 amdgpu_gfx_off_ctrl(adev, true);
1078
1079         return size;
1080 }
1081
1082 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1083                                    enum smu_clk_type clk_type, uint32_t mask)
1084 {
1085         struct amdgpu_device *adev = smu->adev;
1086         int ret = 0, size = 0;
1087         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1088
1089         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1090         soft_max_level = mask ? (fls(mask) - 1) : 0;
1091
1092         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1093                 amdgpu_gfx_off_ctrl(adev, false);
1094
1095         switch (clk_type) {
1096         case SMU_GFXCLK:
1097         case SMU_SCLK:
1098         case SMU_SOCCLK:
1099         case SMU_MCLK:
1100         case SMU_UCLK:
1101         case SMU_DCEFCLK:
1102         case SMU_FCLK:
1103                 /* There is only 2 levels for fine grained DPM */
1104                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1105                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1106                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1107                 }
1108
1109                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1110                 if (ret)
1111                         goto forec_level_out;
1112
1113                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1114                 if (ret)
1115                         goto forec_level_out;
1116
1117                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1118                 if (ret)
1119                         goto forec_level_out;
1120                 break;
1121         default:
1122                 break;
1123         }
1124
1125 forec_level_out:
1126         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1127                 amdgpu_gfx_off_ctrl(adev, true);
1128
1129         return size;
1130 }
1131
1132 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1133 {
1134         struct smu_11_0_dpm_context *dpm_context =
1135                                 smu->smu_dpm.dpm_context;
1136         struct smu_11_0_dpm_table *gfx_table =
1137                                 &dpm_context->dpm_tables.gfx_table;
1138         struct smu_11_0_dpm_table *mem_table =
1139                                 &dpm_context->dpm_tables.uclk_table;
1140         struct smu_11_0_dpm_table *soc_table =
1141                                 &dpm_context->dpm_tables.soc_table;
1142         struct smu_umd_pstate_table *pstate_table =
1143                                 &smu->pstate_table;
1144
1145         pstate_table->gfxclk_pstate.min = gfx_table->min;
1146         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1147         if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1148                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1149
1150         pstate_table->uclk_pstate.min = mem_table->min;
1151         pstate_table->uclk_pstate.peak = mem_table->max;
1152         if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1153                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1154
1155         pstate_table->socclk_pstate.min = soc_table->min;
1156         pstate_table->socclk_pstate.peak = soc_table->max;
1157         if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1158                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1159
1160         return 0;
1161 }
1162
1163 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1164 {
1165         int ret = 0;
1166         uint32_t max_freq = 0;
1167
1168         /* Sienna_Cichlid do not support to change display num currently */
1169         return 0;
1170 #if 0
1171         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1172         if (ret)
1173                 return ret;
1174 #endif
1175
1176         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1177                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1178                 if (ret)
1179                         return ret;
1180                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1181                 if (ret)
1182                         return ret;
1183         }
1184
1185         return ret;
1186 }
1187
1188 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1189 {
1190         int ret = 0;
1191
1192         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1193             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1194             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1195 #if 0
1196                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1197                                                   smu->display_config->num_display,
1198                                                   NULL);
1199 #endif
1200                 if (ret)
1201                         return ret;
1202         }
1203
1204         return ret;
1205 }
1206
1207 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1208 {
1209         int ret = 0;
1210         uint32_t feature_mask[2];
1211         uint64_t feature_enabled;
1212
1213         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1214         if (ret)
1215                 return false;
1216
1217         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1218
1219         return !!(feature_enabled & SMC_DPM_FEATURE);
1220 }
1221
1222 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1223                                     uint32_t *speed)
1224 {
1225         if (!speed)
1226                 return -EINVAL;
1227
1228         return sienna_cichlid_get_smu_metrics_data(smu,
1229                                                 METRICS_CURR_FANSPEED,
1230                                                 speed);
1231 }
1232
1233 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1234 {
1235         PPTable_t *pptable = smu->smu_table.driver_pptable;
1236
1237         smu->fan_max_rpm = pptable->FanMaximumRpm;
1238
1239         return 0;
1240 }
1241
1242 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1243 {
1244         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1245         DpmActivityMonitorCoeffInt_t *activity_monitor =
1246                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1247         uint32_t i, size = 0;
1248         int16_t workload_type = 0;
1249         static const char *profile_name[] = {
1250                                         "BOOTUP_DEFAULT",
1251                                         "3D_FULL_SCREEN",
1252                                         "POWER_SAVING",
1253                                         "VIDEO",
1254                                         "VR",
1255                                         "COMPUTE",
1256                                         "CUSTOM"};
1257         static const char *title[] = {
1258                         "PROFILE_INDEX(NAME)",
1259                         "CLOCK_TYPE(NAME)",
1260                         "FPS",
1261                         "MinFreqType",
1262                         "MinActiveFreqType",
1263                         "MinActiveFreq",
1264                         "BoosterFreqType",
1265                         "BoosterFreq",
1266                         "PD_Data_limit_c",
1267                         "PD_Data_error_coeff",
1268                         "PD_Data_error_rate_coeff"};
1269         int result = 0;
1270
1271         if (!buf)
1272                 return -EINVAL;
1273
1274         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1275                         title[0], title[1], title[2], title[3], title[4], title[5],
1276                         title[6], title[7], title[8], title[9], title[10]);
1277
1278         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1279                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1280                 workload_type = smu_cmn_to_asic_specific_index(smu,
1281                                                                CMN2ASIC_MAPPING_WORKLOAD,
1282                                                                i);
1283                 if (workload_type < 0)
1284                         return -EINVAL;
1285
1286                 result = smu_cmn_update_table(smu,
1287                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1288                                           (void *)(&activity_monitor_external), false);
1289                 if (result) {
1290                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1291                         return result;
1292                 }
1293
1294                 size += sprintf(buf + size, "%2d %14s%s:\n",
1295                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1296
1297                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1298                         " ",
1299                         0,
1300                         "GFXCLK",
1301                         activity_monitor->Gfx_FPS,
1302                         activity_monitor->Gfx_MinFreqStep,
1303                         activity_monitor->Gfx_MinActiveFreqType,
1304                         activity_monitor->Gfx_MinActiveFreq,
1305                         activity_monitor->Gfx_BoosterFreqType,
1306                         activity_monitor->Gfx_BoosterFreq,
1307                         activity_monitor->Gfx_PD_Data_limit_c,
1308                         activity_monitor->Gfx_PD_Data_error_coeff,
1309                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1310
1311                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1312                         " ",
1313                         1,
1314                         "SOCCLK",
1315                         activity_monitor->Fclk_FPS,
1316                         activity_monitor->Fclk_MinFreqStep,
1317                         activity_monitor->Fclk_MinActiveFreqType,
1318                         activity_monitor->Fclk_MinActiveFreq,
1319                         activity_monitor->Fclk_BoosterFreqType,
1320                         activity_monitor->Fclk_BoosterFreq,
1321                         activity_monitor->Fclk_PD_Data_limit_c,
1322                         activity_monitor->Fclk_PD_Data_error_coeff,
1323                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1324
1325                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1326                         " ",
1327                         2,
1328                         "MEMLK",
1329                         activity_monitor->Mem_FPS,
1330                         activity_monitor->Mem_MinFreqStep,
1331                         activity_monitor->Mem_MinActiveFreqType,
1332                         activity_monitor->Mem_MinActiveFreq,
1333                         activity_monitor->Mem_BoosterFreqType,
1334                         activity_monitor->Mem_BoosterFreq,
1335                         activity_monitor->Mem_PD_Data_limit_c,
1336                         activity_monitor->Mem_PD_Data_error_coeff,
1337                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1338         }
1339
1340         return size;
1341 }
1342
1343 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1344 {
1345
1346         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1347         DpmActivityMonitorCoeffInt_t *activity_monitor =
1348                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1349         int workload_type, ret = 0;
1350
1351         smu->power_profile_mode = input[size];
1352
1353         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1354                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1355                 return -EINVAL;
1356         }
1357
1358         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1359
1360                 ret = smu_cmn_update_table(smu,
1361                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1362                                        (void *)(&activity_monitor_external), false);
1363                 if (ret) {
1364                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1365                         return ret;
1366                 }
1367
1368                 switch (input[0]) {
1369                 case 0: /* Gfxclk */
1370                         activity_monitor->Gfx_FPS = input[1];
1371                         activity_monitor->Gfx_MinFreqStep = input[2];
1372                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1373                         activity_monitor->Gfx_MinActiveFreq = input[4];
1374                         activity_monitor->Gfx_BoosterFreqType = input[5];
1375                         activity_monitor->Gfx_BoosterFreq = input[6];
1376                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1377                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1378                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1379                         break;
1380                 case 1: /* Socclk */
1381                         activity_monitor->Fclk_FPS = input[1];
1382                         activity_monitor->Fclk_MinFreqStep = input[2];
1383                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1384                         activity_monitor->Fclk_MinActiveFreq = input[4];
1385                         activity_monitor->Fclk_BoosterFreqType = input[5];
1386                         activity_monitor->Fclk_BoosterFreq = input[6];
1387                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1388                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1389                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1390                         break;
1391                 case 2: /* Memlk */
1392                         activity_monitor->Mem_FPS = input[1];
1393                         activity_monitor->Mem_MinFreqStep = input[2];
1394                         activity_monitor->Mem_MinActiveFreqType = input[3];
1395                         activity_monitor->Mem_MinActiveFreq = input[4];
1396                         activity_monitor->Mem_BoosterFreqType = input[5];
1397                         activity_monitor->Mem_BoosterFreq = input[6];
1398                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1399                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1400                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1401                         break;
1402                 }
1403
1404                 ret = smu_cmn_update_table(smu,
1405                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1406                                        (void *)(&activity_monitor_external), true);
1407                 if (ret) {
1408                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1409                         return ret;
1410                 }
1411         }
1412
1413         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1414         workload_type = smu_cmn_to_asic_specific_index(smu,
1415                                                        CMN2ASIC_MAPPING_WORKLOAD,
1416                                                        smu->power_profile_mode);
1417         if (workload_type < 0)
1418                 return -EINVAL;
1419         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1420                                     1 << workload_type, NULL);
1421
1422         return ret;
1423 }
1424
1425 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1426 {
1427         struct smu_clocks min_clocks = {0};
1428         struct pp_display_clock_request clock_req;
1429         int ret = 0;
1430
1431         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1432         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1433         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1434
1435         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1436                 clock_req.clock_type = amd_pp_dcef_clock;
1437                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1438
1439                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1440                 if (!ret) {
1441                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1442                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1443                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1444                                                                   min_clocks.dcef_clock_in_sr/100,
1445                                                                   NULL);
1446                                 if (ret) {
1447                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1448                                         return ret;
1449                                 }
1450                         }
1451                 } else {
1452                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1453                 }
1454         }
1455
1456         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1457                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1458                 if (ret) {
1459                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1460                         return ret;
1461                 }
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1468                                                struct pp_smu_wm_range_sets *clock_ranges)
1469 {
1470         Watermarks_t *table = smu->smu_table.watermarks_table;
1471         int ret = 0;
1472         int i;
1473
1474         if (clock_ranges) {
1475                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1476                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1477                         return -EINVAL;
1478
1479                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1480                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1481                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1482                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1483                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1484                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1485                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1486                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1487                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1488
1489                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1490                                 clock_ranges->reader_wm_sets[i].wm_inst;
1491                 }
1492
1493                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1494                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1495                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1496                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1497                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1498                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1499                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1500                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1501                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1502
1503                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1504                                 clock_ranges->writer_wm_sets[i].wm_inst;
1505                 }
1506
1507                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1508         }
1509
1510         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1511              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1512                 ret = smu_cmn_write_watermarks_table(smu);
1513                 if (ret) {
1514                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1515                         return ret;
1516                 }
1517                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1518         }
1519
1520         return 0;
1521 }
1522
1523 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1524                                  enum amd_pp_sensors sensor,
1525                                  void *data, uint32_t *size)
1526 {
1527         int ret = 0;
1528         struct smu_table_context *table_context = &smu->smu_table;
1529         PPTable_t *pptable = table_context->driver_pptable;
1530
1531         if(!data || !size)
1532                 return -EINVAL;
1533
1534         mutex_lock(&smu->sensor_lock);
1535         switch (sensor) {
1536         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1537                 *(uint32_t *)data = pptable->FanMaximumRpm;
1538                 *size = 4;
1539                 break;
1540         case AMDGPU_PP_SENSOR_MEM_LOAD:
1541                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1542                                                           METRICS_AVERAGE_MEMACTIVITY,
1543                                                           (uint32_t *)data);
1544                 *size = 4;
1545                 break;
1546         case AMDGPU_PP_SENSOR_GPU_LOAD:
1547                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1548                                                           METRICS_AVERAGE_GFXACTIVITY,
1549                                                           (uint32_t *)data);
1550                 *size = 4;
1551                 break;
1552         case AMDGPU_PP_SENSOR_GPU_POWER:
1553                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1554                                                           METRICS_AVERAGE_SOCKETPOWER,
1555                                                           (uint32_t *)data);
1556                 *size = 4;
1557                 break;
1558         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1559                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1560                                                           METRICS_TEMPERATURE_HOTSPOT,
1561                                                           (uint32_t *)data);
1562                 *size = 4;
1563                 break;
1564         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1565                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1566                                                           METRICS_TEMPERATURE_EDGE,
1567                                                           (uint32_t *)data);
1568                 *size = 4;
1569                 break;
1570         case AMDGPU_PP_SENSOR_MEM_TEMP:
1571                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1572                                                           METRICS_TEMPERATURE_MEM,
1573                                                           (uint32_t *)data);
1574                 *size = 4;
1575                 break;
1576         case AMDGPU_PP_SENSOR_GFX_MCLK:
1577                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1578                 *(uint32_t *)data *= 100;
1579                 *size = 4;
1580                 break;
1581         case AMDGPU_PP_SENSOR_GFX_SCLK:
1582                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1583                 *(uint32_t *)data *= 100;
1584                 *size = 4;
1585                 break;
1586         case AMDGPU_PP_SENSOR_VDDGFX:
1587                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1588                 *size = 4;
1589                 break;
1590         default:
1591                 ret = -EOPNOTSUPP;
1592                 break;
1593         }
1594         mutex_unlock(&smu->sensor_lock);
1595
1596         return ret;
1597 }
1598
1599 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1600 {
1601         uint32_t num_discrete_levels = 0;
1602         uint16_t *dpm_levels = NULL;
1603         uint16_t i = 0;
1604         struct smu_table_context *table_context = &smu->smu_table;
1605         PPTable_t *driver_ppt = NULL;
1606
1607         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1608                 return -EINVAL;
1609
1610         driver_ppt = table_context->driver_pptable;
1611         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1612         dpm_levels = driver_ppt->FreqTableUclk;
1613
1614         if (num_discrete_levels == 0 || dpm_levels == NULL)
1615                 return -EINVAL;
1616
1617         *num_states = num_discrete_levels;
1618         for (i = 0; i < num_discrete_levels; i++) {
1619                 /* convert to khz */
1620                 *clocks_in_khz = (*dpm_levels) * 1000;
1621                 clocks_in_khz++;
1622                 dpm_levels++;
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1629                                                 struct smu_temperature_range *range)
1630 {
1631         struct smu_table_context *table_context = &smu->smu_table;
1632         struct smu_11_0_7_powerplay_table *powerplay_table =
1633                                 table_context->power_play_table;
1634         PPTable_t *pptable = smu->smu_table.driver_pptable;
1635
1636         if (!range)
1637                 return -EINVAL;
1638
1639         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1640
1641         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1642                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1643         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1644                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1645         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1646                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1647         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1648                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1649         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1650                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1651         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1652                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1653         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1654
1655         return 0;
1656 }
1657
1658 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1659                                                 bool disable_memory_clock_switch)
1660 {
1661         int ret = 0;
1662         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1663                 (struct smu_11_0_max_sustainable_clocks *)
1664                         smu->smu_table.max_sustainable_clocks;
1665         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1666         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1667
1668         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1669                 return 0;
1670
1671         if(disable_memory_clock_switch)
1672                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1673         else
1674                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1675
1676         if(!ret)
1677                 smu->disable_uclk_switch = disable_memory_clock_switch;
1678
1679         return ret;
1680 }
1681
1682 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1683 {
1684         struct smu_11_0_7_powerplay_table *powerplay_table =
1685                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1686         PPTable_t *pptable = smu->smu_table.driver_pptable;
1687         uint32_t power_limit, od_percent;
1688
1689         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1690                 /* the last hope to figure out the ppt limit */
1691                 if (!pptable) {
1692                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1693                         return -EINVAL;
1694                 }
1695                 power_limit =
1696                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1697         }
1698         smu->current_power_limit = power_limit;
1699
1700         if (smu->od_enabled) {
1701                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1702
1703                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1704
1705                 power_limit *= (100 + od_percent);
1706                 power_limit /= 100;
1707         }
1708         smu->max_power_limit = power_limit;
1709
1710         return 0;
1711 }
1712
1713 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1714                                          uint32_t pcie_gen_cap,
1715                                          uint32_t pcie_width_cap)
1716 {
1717         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1718         PPTable_t *pptable = smu->smu_table.driver_pptable;
1719         uint32_t smu_pcie_arg;
1720         int ret, i;
1721
1722         /* lclk dpm table setup */
1723         for (i = 0; i < MAX_PCIE_CONF; i++) {
1724                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1725                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1726         }
1727
1728         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1729                 smu_pcie_arg = (i << 16) |
1730                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1731                                         (pptable->PcieGenSpeed[i] << 8) :
1732                                         (pcie_gen_cap << 8)) |
1733                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1734                                         pptable->PcieLaneCount[i] :
1735                                         pcie_width_cap);
1736
1737                 ret = smu_cmn_send_smc_msg_with_param(smu,
1738                                           SMU_MSG_OverridePcieParameters,
1739                                           smu_pcie_arg,
1740                                           NULL);
1741
1742                 if (ret)
1743                         return ret;
1744
1745                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1746                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1747                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1748                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1749         }
1750
1751         return 0;
1752 }
1753
1754 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1755                                 enum smu_clk_type clk_type,
1756                                 uint32_t *min, uint32_t *max)
1757 {
1758         struct amdgpu_device *adev = smu->adev;
1759         int ret;
1760
1761         if (clk_type == SMU_GFXCLK)
1762                 amdgpu_gfx_off_ctrl(adev, false);
1763         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1764         if (clk_type == SMU_GFXCLK)
1765                 amdgpu_gfx_off_ctrl(adev, true);
1766
1767         return ret;
1768 }
1769
1770 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1771                                          OverDriveTable_t *od_table)
1772 {
1773         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1774                                                           od_table->GfxclkFmax);
1775         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1776                                                         od_table->UclkFmax);
1777 }
1778
1779 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1780 {
1781         OverDriveTable_t *od_table =
1782                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1783         OverDriveTable_t *boot_od_table =
1784                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1785         int ret = 0;
1786
1787         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1788                                    0, (void *)od_table, false);
1789         if (ret) {
1790                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1791                 return ret;
1792         }
1793
1794         memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
1795
1796         sienna_cichlid_dump_od_table(smu, od_table);
1797
1798         return 0;
1799 }
1800
1801 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1802                                                  struct smu_11_0_7_overdrive_table *od_table,
1803                                                  enum SMU_11_0_7_ODSETTING_ID setting,
1804                                                  uint32_t value)
1805 {
1806         if (value < od_table->min[setting]) {
1807                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1808                                           setting, value, od_table->min[setting]);
1809                 return -EINVAL;
1810         }
1811         if (value > od_table->max[setting]) {
1812                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1813                                           setting, value, od_table->max[setting]);
1814                 return -EINVAL;
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1821                                             enum PP_OD_DPM_TABLE_COMMAND type,
1822                                             long input[], uint32_t size)
1823 {
1824         struct smu_table_context *table_context = &smu->smu_table;
1825         OverDriveTable_t *od_table =
1826                 (OverDriveTable_t *)table_context->overdrive_table;
1827         struct smu_11_0_7_overdrive_table *od_settings =
1828                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
1829         enum SMU_11_0_7_ODSETTING_ID freq_setting;
1830         uint16_t *freq_ptr;
1831         int i, ret = 0;
1832
1833         if (!smu->od_enabled) {
1834                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1835                 return -EINVAL;
1836         }
1837
1838         if (!smu->od_settings) {
1839                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
1840                 return -ENOENT;
1841         }
1842
1843         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1844                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1845                 return -EINVAL;
1846         }
1847
1848         switch (type) {
1849         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1850                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
1851                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1852                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1853                         return -ENOTSUPP;
1854                 }
1855
1856                 for (i = 0; i < size; i += 2) {
1857                         if (i + 2 > size) {
1858                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1859                                 return -EINVAL;
1860                         }
1861
1862                         switch (input[i]) {
1863                         case 0:
1864                                 if (input[i + 1] > od_table->GfxclkFmax) {
1865                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1866                                                 input[i + 1], od_table->GfxclkFmax);
1867                                         return -EINVAL;
1868                                 }
1869
1870                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
1871                                 freq_ptr = &od_table->GfxclkFmin;
1872                                 break;
1873
1874                         case 1:
1875                                 if (input[i + 1] < od_table->GfxclkFmin) {
1876                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1877                                                 input[i + 1], od_table->GfxclkFmin);
1878                                         return -EINVAL;
1879                                 }
1880
1881                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
1882                                 freq_ptr = &od_table->GfxclkFmax;
1883                                 break;
1884
1885                         default:
1886                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1887                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
1888                                 return -EINVAL;
1889                         }
1890
1891                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
1892                                                                     freq_setting, input[i + 1]);
1893                         if (ret)
1894                                 return ret;
1895
1896                         *freq_ptr = (uint16_t)input[i + 1];
1897                 }
1898                 break;
1899
1900         case PP_OD_EDIT_MCLK_VDDC_TABLE:
1901                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1902                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
1903                         return -ENOTSUPP;
1904                 }
1905
1906                 for (i = 0; i < size; i += 2) {
1907                         if (i + 2 > size) {
1908                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1909                                 return -EINVAL;
1910                         }
1911
1912                         switch (input[i]) {
1913                         case 0:
1914                                 if (input[i + 1] > od_table->UclkFmax) {
1915                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
1916                                                 input[i + 1], od_table->UclkFmax);
1917                                         return -EINVAL;
1918                                 }
1919
1920                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
1921                                 freq_ptr = &od_table->UclkFmin;
1922                                 break;
1923
1924                         case 1:
1925                                 if (input[i + 1] < od_table->UclkFmin) {
1926                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
1927                                                 input[i + 1], od_table->UclkFmin);
1928                                         return -EINVAL;
1929                                 }
1930
1931                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
1932                                 freq_ptr = &od_table->UclkFmax;
1933                                 break;
1934
1935                         default:
1936                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1937                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
1938                                 return -EINVAL;
1939                         }
1940
1941                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
1942                                                                     freq_setting, input[i + 1]);
1943                         if (ret)
1944                                 return ret;
1945
1946                         *freq_ptr = (uint16_t)input[i + 1];
1947                 }
1948                 break;
1949
1950         case PP_OD_RESTORE_DEFAULT_TABLE:
1951                 memcpy(table_context->overdrive_table,
1952                                 table_context->boot_overdrive_table,
1953                                 sizeof(OverDriveTable_t));
1954                 fallthrough;
1955
1956         case PP_OD_COMMIT_DPM_TABLE:
1957                 sienna_cichlid_dump_od_table(smu, od_table);
1958
1959                 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1960                                            0, (void *)od_table, true);
1961                 if (ret) {
1962                         dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
1963                         return ret;
1964                 }
1965                 break;
1966
1967         default:
1968                 return -ENOSYS;
1969         }
1970
1971         return ret;
1972 }
1973
1974 static int sienna_cichlid_run_btc(struct smu_context *smu)
1975 {
1976         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1977 }
1978
1979 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1980 {
1981         struct amdgpu_device *adev = smu->adev;
1982         uint32_t val;
1983
1984         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1985                 return false;
1986
1987         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1988         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1989 }
1990
1991 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1992 {
1993         struct amdgpu_device *adev = smu->adev;
1994         uint32_t val;
1995         u32 smu_version;
1996
1997         /**
1998          * SRIOV env will not support SMU mode1 reset
1999          * PM FW support mode1 reset from 58.26
2000          */
2001         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2002         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2003                 return false;
2004
2005         /**
2006          * mode1 reset relies on PSP, so we should check if
2007          * PSP is alive.
2008          */
2009         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2010         return val != 0x0;
2011 }
2012
2013 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2014 {
2015         struct smu_table_context *table_context = &smu->smu_table;
2016         PPTable_t *pptable = table_context->driver_pptable;
2017         int i;
2018
2019         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2020
2021         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2022         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2023         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2024
2025         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2026                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2027                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2028                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2029                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2030         }
2031
2032         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2033                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2034                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2035         }
2036
2037         for (i = 0; i < TEMP_COUNT; i++) {
2038                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2039         }
2040
2041         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2042         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2043         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2044         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2045         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2046
2047         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2048         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2049                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2050                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2051         }
2052         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2053
2054         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2055
2056         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2057         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2058         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2059         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2060
2061         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2062         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2063
2064         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2065         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2066         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2067         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2068
2069         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2070         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2071         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2072         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2073
2074         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2075         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2076
2077         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2078         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2079         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2080         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2081         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2082         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2083         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2084         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2085
2086         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2087                         "  .VoltageMode          = 0x%02x\n"
2088                         "  .SnapToDiscrete       = 0x%02x\n"
2089                         "  .NumDiscreteLevels    = 0x%02x\n"
2090                         "  .padding              = 0x%02x\n"
2091                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2092                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2093                         "  .SsFmin               = 0x%04x\n"
2094                         "  .Padding_16           = 0x%04x\n",
2095                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2096                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2097                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2098                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2099                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2100                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2101                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2102                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2103                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2104                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2105                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2106
2107         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2108                         "  .VoltageMode          = 0x%02x\n"
2109                         "  .SnapToDiscrete       = 0x%02x\n"
2110                         "  .NumDiscreteLevels    = 0x%02x\n"
2111                         "  .padding              = 0x%02x\n"
2112                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2113                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2114                         "  .SsFmin               = 0x%04x\n"
2115                         "  .Padding_16           = 0x%04x\n",
2116                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2117                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2118                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2119                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2120                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2121                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2122                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2123                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2124                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2125                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2126                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2127
2128         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2129                         "  .VoltageMode          = 0x%02x\n"
2130                         "  .SnapToDiscrete       = 0x%02x\n"
2131                         "  .NumDiscreteLevels    = 0x%02x\n"
2132                         "  .padding              = 0x%02x\n"
2133                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2134                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2135                         "  .SsFmin               = 0x%04x\n"
2136                         "  .Padding_16           = 0x%04x\n",
2137                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2138                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2139                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2140                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2141                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2142                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2143                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2144                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2145                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2146                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2147                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2148
2149         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2150                         "  .VoltageMode          = 0x%02x\n"
2151                         "  .SnapToDiscrete       = 0x%02x\n"
2152                         "  .NumDiscreteLevels    = 0x%02x\n"
2153                         "  .padding              = 0x%02x\n"
2154                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2155                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2156                         "  .SsFmin               = 0x%04x\n"
2157                         "  .Padding_16           = 0x%04x\n",
2158                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2159                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2160                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2161                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2162                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2163                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2164                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2165                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2166                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2167                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2168                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2169
2170         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2171                         "  .VoltageMode          = 0x%02x\n"
2172                         "  .SnapToDiscrete       = 0x%02x\n"
2173                         "  .NumDiscreteLevels    = 0x%02x\n"
2174                         "  .padding              = 0x%02x\n"
2175                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2176                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2177                         "  .SsFmin               = 0x%04x\n"
2178                         "  .Padding_16           = 0x%04x\n",
2179                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2180                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2181                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2182                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2183                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2184                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2185                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2186                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2187                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2188                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2189                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2190
2191         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2192                         "  .VoltageMode          = 0x%02x\n"
2193                         "  .SnapToDiscrete       = 0x%02x\n"
2194                         "  .NumDiscreteLevels    = 0x%02x\n"
2195                         "  .padding              = 0x%02x\n"
2196                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2197                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2198                         "  .SsFmin               = 0x%04x\n"
2199                         "  .Padding_16           = 0x%04x\n",
2200                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2201                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2202                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2203                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2204                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2205                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2206                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2207                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2208                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2209                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2210                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2211
2212         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2213                         "  .VoltageMode          = 0x%02x\n"
2214                         "  .SnapToDiscrete       = 0x%02x\n"
2215                         "  .NumDiscreteLevels    = 0x%02x\n"
2216                         "  .padding              = 0x%02x\n"
2217                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2218                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2219                         "  .SsFmin               = 0x%04x\n"
2220                         "  .Padding_16           = 0x%04x\n",
2221                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2222                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2223                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2224                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2225                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2226                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2227                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2228                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2229                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2230                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2231                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2232
2233         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2234                         "  .VoltageMode          = 0x%02x\n"
2235                         "  .SnapToDiscrete       = 0x%02x\n"
2236                         "  .NumDiscreteLevels    = 0x%02x\n"
2237                         "  .padding              = 0x%02x\n"
2238                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2239                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2240                         "  .SsFmin               = 0x%04x\n"
2241                         "  .Padding_16           = 0x%04x\n",
2242                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2243                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2244                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2245                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2246                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2247                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2248                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2249                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2250                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2251                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2252                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2253
2254         dev_info(smu->adev->dev, "FreqTableGfx\n");
2255         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2256                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2257
2258         dev_info(smu->adev->dev, "FreqTableVclk\n");
2259         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2260                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2261
2262         dev_info(smu->adev->dev, "FreqTableDclk\n");
2263         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2264                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2265
2266         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2267         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2268                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2269
2270         dev_info(smu->adev->dev, "FreqTableUclk\n");
2271         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2272                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2273
2274         dev_info(smu->adev->dev, "FreqTableFclk\n");
2275         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2276                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2277
2278         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2279         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2280         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2281         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2282         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2283         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2284         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2285         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2286         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2287
2288         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2289         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2290                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2291
2292         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2293         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2294
2295         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2296         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2297                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2298
2299         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2300         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2301                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2302
2303         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2304         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2305                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2306
2307         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2308         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2309                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2310
2311         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2312         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2313         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2314         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2315         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2316
2317         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2318
2319         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2320         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2321         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2322         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2323         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2324         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2325         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2326         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2327         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2328         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2329         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2330
2331         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2332         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2333         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2334         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2335         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2336         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2337
2338         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2339         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2340         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2341         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2342         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2343
2344         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2345         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2346                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2347
2348         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2349         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2350         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2351         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2352
2353         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2354         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2355                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2356
2357         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2358         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2359                 pptable->UclkDpmSrcFreqRange.Fmin);
2360         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2361                 pptable->UclkDpmSrcFreqRange.Fmax);
2362         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2363         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2364                 pptable->UclkDpmTargFreqRange.Fmin);
2365         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2366                 pptable->UclkDpmTargFreqRange.Fmax);
2367         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2368         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2369
2370         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2371         for (i = 0; i < NUM_LINK_LEVELS; i++)
2372                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2373
2374         dev_info(smu->adev->dev, "PcieLaneCount\n");
2375         for (i = 0; i < NUM_LINK_LEVELS; i++)
2376                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2377
2378         dev_info(smu->adev->dev, "LclkFreq\n");
2379         for (i = 0; i < NUM_LINK_LEVELS; i++)
2380                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2381
2382         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2383         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2384
2385         dev_info(smu->adev->dev, "FanGain\n");
2386         for (i = 0; i < TEMP_COUNT; i++)
2387                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2388
2389         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2390         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2391         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2392         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2393         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2394         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2395         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2396         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2397         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2398         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2399         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2400         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2401
2402         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2403         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2404         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2405         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2406
2407         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2408         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2409         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2410         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2411
2412         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2413                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2414                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2415                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2416         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2417                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2418                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2419                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2420         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2421                         pptable->dBtcGbGfxPll.a,
2422                         pptable->dBtcGbGfxPll.b,
2423                         pptable->dBtcGbGfxPll.c);
2424         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2425                         pptable->dBtcGbGfxDfll.a,
2426                         pptable->dBtcGbGfxDfll.b,
2427                         pptable->dBtcGbGfxDfll.c);
2428         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2429                         pptable->dBtcGbSoc.a,
2430                         pptable->dBtcGbSoc.b,
2431                         pptable->dBtcGbSoc.c);
2432         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2433                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2434                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2435         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2436                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2437                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2438
2439         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2440         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2441                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2442                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2443                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2444                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2445         }
2446
2447         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2448                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2449                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2450                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2451         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2452                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2453                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2454                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2455
2456         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2457         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2458
2459         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2460         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2461         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2462         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2463
2464         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2465         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2466         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2467         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2468
2469         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2470         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2471
2472         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2473         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2474                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2475         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2476         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2477
2478         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2479         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2480                         pptable->ReservedEquation0.a,
2481                         pptable->ReservedEquation0.b,
2482                         pptable->ReservedEquation0.c);
2483         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2484                         pptable->ReservedEquation1.a,
2485                         pptable->ReservedEquation1.b,
2486                         pptable->ReservedEquation1.c);
2487         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2488                         pptable->ReservedEquation2.a,
2489                         pptable->ReservedEquation2.b,
2490                         pptable->ReservedEquation2.c);
2491         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2492                         pptable->ReservedEquation3.a,
2493                         pptable->ReservedEquation3.b,
2494                         pptable->ReservedEquation3.c);
2495
2496         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2497         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2498         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2499         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2500         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2501         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2502         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2503         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2504
2505         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2506         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2507         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2508         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2509         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2510         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2511
2512         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2513                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2514                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2515                                 pptable->I2cControllers[i].Enabled);
2516                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2517                                 pptable->I2cControllers[i].Speed);
2518                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2519                                 pptable->I2cControllers[i].SlaveAddress);
2520                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2521                                 pptable->I2cControllers[i].ControllerPort);
2522                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2523                                 pptable->I2cControllers[i].ControllerName);
2524                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2525                                 pptable->I2cControllers[i].ThermalThrotter);
2526                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2527                                 pptable->I2cControllers[i].I2cProtocol);
2528                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2529                                 pptable->I2cControllers[i].PaddingConfig);
2530         }
2531
2532         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2533         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2534         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2535         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2536
2537         dev_info(smu->adev->dev, "Board Parameters:\n");
2538         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2539         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2540         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2541         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2542         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2543         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2544         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2545         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2546
2547         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2548         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2549         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2550
2551         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2552         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2553         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2554
2555         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2556         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2557         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2558
2559         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2560         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2561         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2562
2563         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2564
2565         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2566         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2567         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2568         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2569         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2570         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2571         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2572         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2573         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2574         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2575         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2576         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2577         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2578         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2579         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2580         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2581
2582         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2583         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2584         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2585
2586         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2587         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2588         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2589
2590         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2591         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2592
2593         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2594         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2595         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2596
2597         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2598         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2599         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2600         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2601         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2602
2603         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2604         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2605
2606         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2607         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2608                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2609         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2610         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2611                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2612         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2613         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2614                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2615         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2616         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2617                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2618
2619         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2620         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2621         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2622         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2623
2624         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2625         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2626         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2627         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2628         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2629         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2630         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2631         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2632         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2633         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2634         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2635
2636         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2637         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2638         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2639         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2640         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2641         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2642         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2643         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2644 }
2645
2646 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2647                                   uint8_t address, uint32_t numbytes,
2648                                   uint8_t *data)
2649 {
2650         int i;
2651
2652         req->I2CcontrollerPort = 0;
2653         req->I2CSpeed = 2;
2654         req->SlaveAddress = address;
2655         req->NumCmds = numbytes;
2656
2657         for (i = 0; i < numbytes; i++) {
2658                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2659
2660                 /* First 2 bytes are always write for lower 2b EEPROM address */
2661                 if (i < 2)
2662                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2663                 else
2664                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2665
2666
2667                 /* Add RESTART for read  after address filled */
2668                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2669
2670                 /* Add STOP in the end */
2671                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2672
2673                 /* Fill with data regardless if read or write to simplify code */
2674                 cmd->ReadWriteData = data[i];
2675         }
2676 }
2677
2678 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2679                                                uint8_t address,
2680                                                uint8_t *data,
2681                                                uint32_t numbytes)
2682 {
2683         uint32_t  i, ret = 0;
2684         SwI2cRequest_t req;
2685         struct amdgpu_device *adev = to_amdgpu_device(control);
2686         struct smu_table_context *smu_table = &adev->smu.smu_table;
2687         struct smu_table *table = &smu_table->driver_table;
2688
2689         if (numbytes > MAX_SW_I2C_COMMANDS) {
2690                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2691                         numbytes, MAX_SW_I2C_COMMANDS);
2692                 return -EINVAL;
2693         }
2694
2695         memset(&req, 0, sizeof(req));
2696         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2697
2698         mutex_lock(&adev->smu.mutex);
2699         /* Now read data starting with that address */
2700         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2701                                         true);
2702         mutex_unlock(&adev->smu.mutex);
2703
2704         if (!ret) {
2705                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2706
2707                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2708                 for (i = 0; i < numbytes; i++)
2709                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2710
2711                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2712                                   (uint16_t)address, numbytes);
2713
2714                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2715                                8, 1, data, numbytes, false);
2716         } else
2717                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2718
2719         return ret;
2720 }
2721
2722 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2723                                                 uint8_t address,
2724                                                 uint8_t *data,
2725                                                 uint32_t numbytes)
2726 {
2727         uint32_t ret;
2728         SwI2cRequest_t req;
2729         struct amdgpu_device *adev = to_amdgpu_device(control);
2730
2731         if (numbytes > MAX_SW_I2C_COMMANDS) {
2732                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2733                         numbytes, MAX_SW_I2C_COMMANDS);
2734                 return -EINVAL;
2735         }
2736
2737         memset(&req, 0, sizeof(req));
2738         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2739
2740         mutex_lock(&adev->smu.mutex);
2741         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2742         mutex_unlock(&adev->smu.mutex);
2743
2744         if (!ret) {
2745                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2746                                          (uint16_t)address, numbytes);
2747
2748                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2749                                8, 1, data, numbytes, false);
2750                 /*
2751                  * According to EEPROM spec there is a MAX of 10 ms required for
2752                  * EEPROM to flush internal RX buffer after STOP was issued at the
2753                  * end of write transaction. During this time the EEPROM will not be
2754                  * responsive to any more commands - so wait a bit more.
2755                  */
2756                 msleep(10);
2757
2758         } else
2759                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2760
2761         return ret;
2762 }
2763
2764 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2765                               struct i2c_msg *msgs, int num)
2766 {
2767         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2768         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2769
2770         for (i = 0; i < num; i++) {
2771                 /*
2772                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2773                  * once and hence the data needs to be spliced into chunks and sent each
2774                  * chunk separately
2775                  */
2776                 data_size = msgs[i].len - 2;
2777                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2778                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2779                 data_ptr = msgs[i].buf + 2;
2780
2781                 for (j = 0; j < data_size / data_chunk_size; j++) {
2782                         /* Insert the EEPROM dest addess, bits 0-15 */
2783                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2784                         data_chunk[1] = (next_eeprom_addr & 0xff);
2785
2786                         if (msgs[i].flags & I2C_M_RD) {
2787                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2788                                                              (uint8_t)msgs[i].addr,
2789                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2790
2791                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2792                         } else {
2793
2794                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2795
2796                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2797                                                               (uint8_t)msgs[i].addr,
2798                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2799                         }
2800
2801                         if (ret) {
2802                                 num = -EIO;
2803                                 goto fail;
2804                         }
2805
2806                         next_eeprom_addr += data_chunk_size;
2807                         data_ptr += data_chunk_size;
2808                 }
2809
2810                 if (data_size % data_chunk_size) {
2811                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2812                         data_chunk[1] = (next_eeprom_addr & 0xff);
2813
2814                         if (msgs[i].flags & I2C_M_RD) {
2815                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2816                                                              (uint8_t)msgs[i].addr,
2817                                                              data_chunk, (data_size % data_chunk_size) + 2);
2818
2819                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2820                         } else {
2821                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2822
2823                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2824                                                               (uint8_t)msgs[i].addr,
2825                                                               data_chunk, (data_size % data_chunk_size) + 2);
2826                         }
2827
2828                         if (ret) {
2829                                 num = -EIO;
2830                                 goto fail;
2831                         }
2832                 }
2833         }
2834
2835 fail:
2836         return num;
2837 }
2838
2839 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2840 {
2841         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2842 }
2843
2844
2845 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2846         .master_xfer = sienna_cichlid_i2c_xfer,
2847         .functionality = sienna_cichlid_i2c_func,
2848 };
2849
2850 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2851 {
2852         struct amdgpu_device *adev = to_amdgpu_device(control);
2853         int res;
2854
2855         control->owner = THIS_MODULE;
2856         control->class = I2C_CLASS_SPD;
2857         control->dev.parent = &adev->pdev->dev;
2858         control->algo = &sienna_cichlid_i2c_algo;
2859         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2860
2861         res = i2c_add_adapter(control);
2862         if (res)
2863                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2864
2865         return res;
2866 }
2867
2868 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2869 {
2870         i2c_del_adapter(control);
2871 }
2872
2873 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2874                                               void **table)
2875 {
2876         struct smu_table_context *smu_table = &smu->smu_table;
2877         struct gpu_metrics_v1_0 *gpu_metrics =
2878                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2879         SmuMetricsExternal_t metrics_external;
2880         SmuMetrics_t *metrics =
2881                 &(metrics_external.SmuMetrics);
2882         int ret = 0;
2883
2884         ret = smu_cmn_get_metrics_table(smu,
2885                                         &metrics_external,
2886                                         true);
2887         if (ret)
2888                 return ret;
2889
2890         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2891
2892         gpu_metrics->temperature_edge = metrics->TemperatureEdge;
2893         gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
2894         gpu_metrics->temperature_mem = metrics->TemperatureMem;
2895         gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx;
2896         gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc;
2897         gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0;
2898
2899         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2900         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2901         gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage;
2902
2903         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2904         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2905
2906         if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2907                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2908         else
2909                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2910         gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs;
2911         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2912         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2913         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2914         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2915
2916         gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2917         gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2918         gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2919         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2920         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2921         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2922         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2923
2924         gpu_metrics->throttle_status = metrics->ThrottlerStatus;
2925
2926         gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
2927
2928         gpu_metrics->pcie_link_width =
2929                         smu_v11_0_get_current_pcie_link_width(smu);
2930         gpu_metrics->pcie_link_speed =
2931                         smu_v11_0_get_current_pcie_link_speed(smu);
2932
2933         *table = (void *)gpu_metrics;
2934
2935         return sizeof(struct gpu_metrics_v1_0);
2936 }
2937
2938 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2939 {
2940         return smu_cmn_send_smc_msg_with_param(smu,
2941                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2942                                                0,
2943                                                NULL);
2944 }
2945
2946 static int sienna_cichlid_gpo_control(struct smu_context *smu,
2947                                       bool enablement)
2948 {
2949         uint32_t smu_version;
2950         int ret = 0;
2951
2952
2953         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2954                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2955                 if (ret)
2956                         return ret;
2957
2958                 if (enablement) {
2959                         if (smu_version < 0x003a2500) {
2960                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2961                                                                       SMU_MSG_SetGpoFeaturePMask,
2962                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2963                                                                       NULL);
2964                         } else {
2965                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2966                                                                       SMU_MSG_DisallowGpo,
2967                                                                       0,
2968                                                                       NULL);
2969                         }
2970                 } else {
2971                         if (smu_version < 0x003a2500) {
2972                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2973                                                                       SMU_MSG_SetGpoFeaturePMask,
2974                                                                       0,
2975                                                                       NULL);
2976                         } else {
2977                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2978                                                                       SMU_MSG_DisallowGpo,
2979                                                                       1,
2980                                                                       NULL);
2981                         }
2982                 }
2983         }
2984
2985         return ret;
2986 }
2987
2988 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
2989 {
2990         uint32_t smu_version;
2991         int ret = 0;
2992
2993         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2994         if (ret)
2995                 return ret;
2996
2997         /*
2998          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
2999          * onwards PMFWs.
3000          */
3001         if (smu_version < 0x003A2D00)
3002                 return 0;
3003
3004         return smu_cmn_send_smc_msg_with_param(smu,
3005                                                SMU_MSG_Enable2ndUSB20Port,
3006                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3007                                                1 : 0,
3008                                                NULL);
3009 }
3010
3011 static int sienna_cichlid_system_features_control(struct smu_context *smu,
3012                                                   bool en)
3013 {
3014         int ret = 0;
3015
3016         if (en) {
3017                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3018                 if (ret)
3019                         return ret;
3020         }
3021
3022         return smu_v11_0_system_features_control(smu, en);
3023 }
3024
3025 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3026         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3027         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3028         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3029         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3030         .i2c_init = sienna_cichlid_i2c_control_init,
3031         .i2c_fini = sienna_cichlid_i2c_control_fini,
3032         .print_clk_levels = sienna_cichlid_print_clk_levels,
3033         .force_clk_levels = sienna_cichlid_force_clk_levels,
3034         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3035         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3036         .display_config_changed = sienna_cichlid_display_config_changed,
3037         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3038         .is_dpm_running = sienna_cichlid_is_dpm_running,
3039         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
3040         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3041         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
3042         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3043         .read_sensor = sienna_cichlid_read_sensor,
3044         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
3045         .set_performance_level = smu_v11_0_set_performance_level,
3046         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3047         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3048         .get_power_limit = sienna_cichlid_get_power_limit,
3049         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
3050         .dump_pptable = sienna_cichlid_dump_pptable,
3051         .init_microcode = smu_v11_0_init_microcode,
3052         .load_microcode = smu_v11_0_load_microcode,
3053         .init_smc_tables = sienna_cichlid_init_smc_tables,
3054         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3055         .init_power = smu_v11_0_init_power,
3056         .fini_power = smu_v11_0_fini_power,
3057         .check_fw_status = smu_v11_0_check_fw_status,
3058         .setup_pptable = sienna_cichlid_setup_pptable,
3059         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3060         .check_fw_version = smu_v11_0_check_fw_version,
3061         .write_pptable = smu_cmn_write_pptable,
3062         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3063         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3064         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3065         .system_features_control = sienna_cichlid_system_features_control,
3066         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3067         .send_smc_msg = smu_cmn_send_smc_msg,
3068         .init_display_count = NULL,
3069         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3070         .get_enabled_mask = smu_cmn_get_enabled_mask,
3071         .feature_is_enabled = smu_cmn_feature_is_enabled,
3072         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3073         .notify_display_change = NULL,
3074         .set_power_limit = smu_v11_0_set_power_limit,
3075         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3076         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3077         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3078         .set_min_dcef_deep_sleep = NULL,
3079         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3080         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3081         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3082         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3083         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3084         .gfx_off_control = smu_v11_0_gfx_off_control,
3085         .register_irq_handler = smu_v11_0_register_irq_handler,
3086         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3087         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3088         .baco_is_support= sienna_cichlid_is_baco_supported,
3089         .baco_get_state = smu_v11_0_baco_get_state,
3090         .baco_set_state = smu_v11_0_baco_set_state,
3091         .baco_enter = smu_v11_0_baco_enter,
3092         .baco_exit = smu_v11_0_baco_exit,
3093         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3094         .mode1_reset = smu_v11_0_mode1_reset,
3095         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
3096         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3097         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
3098         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
3099         .run_btc = sienna_cichlid_run_btc,
3100         .set_power_source = smu_v11_0_set_power_source,
3101         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3102         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3103         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
3104         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
3105         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3106         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3107         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
3108         .interrupt_work = smu_v11_0_interrupt_work,
3109         .gpo_control = sienna_cichlid_gpo_control,
3110 };
3111
3112 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3113 {
3114         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
3115         smu->message_map = sienna_cichlid_message_map;
3116         smu->clock_map = sienna_cichlid_clk_map;
3117         smu->feature_map = sienna_cichlid_feature_mask_map;
3118         smu->table_map = sienna_cichlid_table_map;
3119         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3120         smu->workload_map = sienna_cichlid_workload_map;
3121 }