drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  77         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  78         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  79         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  80         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  81         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  82         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  83         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  84         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  85         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  86         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  87         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  88         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  89         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  90         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  91         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  92         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  93         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  94         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  95         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  96         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  97         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  98         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  99         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 108         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 109         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 110         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 111         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 112         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 113         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 114         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 115         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 116         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 117         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 118         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 119         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 120         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 121         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 122         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 123         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 124         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 125         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 126         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 127         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 128         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 129         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 130         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 131         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 132         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 133 };
 134
 135 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 136         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 137         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 138         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 139         CLK_MAP(FCLK,           PPCLK_FCLK),
 140         CLK_MAP(UCLK,           PPCLK_UCLK),
 141         CLK_MAP(MCLK,           PPCLK_UCLK),
 142         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 143         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 144         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 145         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 146         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 147         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 148         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 149         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 150 };
 151
 152 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 153         FEA_MAP(DPM_PREFETCHER),
 154         FEA_MAP(DPM_GFXCLK),
 155         FEA_MAP(DPM_GFX_GPO),
 156         FEA_MAP(DPM_UCLK),
 157         FEA_MAP(DPM_FCLK),
 158         FEA_MAP(DPM_SOCCLK),
 159         FEA_MAP(DPM_MP0CLK),
 160         FEA_MAP(DPM_LINK),
 161         FEA_MAP(DPM_DCEFCLK),
 162         FEA_MAP(DPM_XGMI),
 163         FEA_MAP(MEM_VDDCI_SCALING),
 164         FEA_MAP(MEM_MVDD_SCALING),
 165         FEA_MAP(DS_GFXCLK),
 166         FEA_MAP(DS_SOCCLK),
 167         FEA_MAP(DS_FCLK),
 168         FEA_MAP(DS_LCLK),
 169         FEA_MAP(DS_DCEFCLK),
 170         FEA_MAP(DS_UCLK),
 171         FEA_MAP(GFX_ULV),
 172         FEA_MAP(FW_DSTATE),
 173         FEA_MAP(GFXOFF),
 174         FEA_MAP(BACO),
 175         FEA_MAP(MM_DPM_PG),
 176         FEA_MAP(RSMU_SMN_CG),
 177         FEA_MAP(PPT),
 178         FEA_MAP(TDC),
 179         FEA_MAP(APCC_PLUS),
 180         FEA_MAP(GTHR),
 181         FEA_MAP(ACDC),
 182         FEA_MAP(VR0HOT),
 183         FEA_MAP(VR1HOT),
 184         FEA_MAP(FW_CTF),
 185         FEA_MAP(FAN_CONTROL),
 186         FEA_MAP(THERMAL),
 187         FEA_MAP(GFX_DCS),
 188         FEA_MAP(RM),
 189         FEA_MAP(LED_DISPLAY),
 190         FEA_MAP(GFX_SS),
 191         FEA_MAP(OUT_OF_BAND_MONITOR),
 192         FEA_MAP(TEMP_DEPENDENT_VMIN),
 193         FEA_MAP(MMHUB_PG),
 194         FEA_MAP(ATHUB_PG),
 195         FEA_MAP(APCC_DFLL),
 196 };
 197
 198 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 199         TAB_MAP(PPTABLE),
 200         TAB_MAP(WATERMARKS),
 201         TAB_MAP(AVFS_PSM_DEBUG),
 202         TAB_MAP(AVFS_FUSE_OVERRIDE),
 203         TAB_MAP(PMSTATUSLOG),
 204         TAB_MAP(SMU_METRICS),
 205         TAB_MAP(DRIVER_SMU_CONFIG),
 206         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 207         TAB_MAP(OVERDRIVE),
 208         TAB_MAP(I2C_COMMANDS),
 209         TAB_MAP(PACE),
 210 };
 211
 212 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 213         PWR_MAP(AC),
 214         PWR_MAP(DC),
 215 };
 216
 217 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 224         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 225 };
 226
 227 static int
 228 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 229                                   uint32_t *feature_mask, uint32_t num)
 230 {
 231         struct amdgpu_device *adev = smu->adev;
 232
 233         if (num > 2)
 234                 return -EINVAL;
 235
 236         memset(feature_mask, 0, sizeof(uint32_t) * num);
 237
 238         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 239                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 240                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 241                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 242                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 243                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 244                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 245                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 246                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 247                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 248                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 249                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 250                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 251                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 252                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 253                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 254                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 255                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 256                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 257                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 258
 259         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 260                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 261                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 262         }
 263
 264         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 265                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 266                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 267                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 268
 269         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 270                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 271
 272         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 273                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 274
 275         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 276                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 277
 278         if (adev->pm.pp_feature & PP_ULV_MASK)
 279                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 280
 281         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 282                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 283
 284         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 285                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 286
 287         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 288                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 289
 290         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 291                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 292
 293         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 294             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 295                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 296
 297         return 0;
 298 }
 299
 300 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 301 {
 302         struct smu_table_context *table_context = &smu->smu_table;
 303         struct smu_11_0_7_powerplay_table *powerplay_table =
 304                 table_context->power_play_table;
 305         struct smu_baco_context *smu_baco = &smu->smu_baco;
 306
 307         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 308                 smu->dc_controlled_by_gpio = true;
 309
 310         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 311             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 312                 smu_baco->platform_support = true;
 313
 314         table_context->thermal_controller_type =
 315                 powerplay_table->thermal_controller_type;
 316
 317         return 0;
 318 }
 319
 320 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 321 {
 322         struct smu_table_context *table_context = &smu->smu_table;
 323         PPTable_t *smc_pptable = table_context->driver_pptable;
 324         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 325         int index, ret;
 326
 327         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 328                                             smc_dpm_info);
 329
 330         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 331                                       (uint8_t **)&smc_dpm_table);
 332         if (ret)
 333                 return ret;
 334
 335         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 336                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 337
 338         return 0;
 339 }
 340
 341 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 342 {
 343         struct smu_table_context *table_context = &smu->smu_table;
 344         struct smu_11_0_7_powerplay_table *powerplay_table =
 345                 table_context->power_play_table;
 346
 347         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 348                sizeof(PPTable_t));
 349
 350         return 0;
 351 }
 352
 353 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 354 {
 355         int ret = 0;
 356
 357         ret = smu_v11_0_setup_pptable(smu);
 358         if (ret)
 359                 return ret;
 360
 361         ret = sienna_cichlid_store_powerplay_table(smu);
 362         if (ret)
 363                 return ret;
 364
 365         ret = sienna_cichlid_append_powerplay_table(smu);
 366         if (ret)
 367                 return ret;
 368
 369         ret = sienna_cichlid_check_powerplay_table(smu);
 370         if (ret)
 371                 return ret;
 372
 373         return ret;
 374 }
 375
 376 static int sienna_cichlid_tables_init(struct smu_context *smu)
 377 {
 378         struct smu_table_context *smu_table = &smu->smu_table;
 379         struct smu_table *tables = smu_table->tables;
 380
 381         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 382                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 383         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 384                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 385         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 386                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 387         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 388                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 389         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 390                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 391         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 392                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 393         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 394                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 395                        AMDGPU_GEM_DOMAIN_VRAM);
 396
 397         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 398         if (!smu_table->metrics_table)
 399                 goto err0_out;
 400         smu_table->metrics_time = 0;
 401
 402         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 403         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 404         if (!smu_table->gpu_metrics_table)
 405                 goto err1_out;
 406
 407         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 408         if (!smu_table->watermarks_table)
 409                 goto err2_out;
 410
 411         return 0;
 412
 413 err2_out:
 414         kfree(smu_table->gpu_metrics_table);
 415 err1_out:
 416         kfree(smu_table->metrics_table);
 417 err0_out:
 418         return -ENOMEM;
 419 }
 420
 421 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 422                                                MetricsMember_t member,
 423                                                uint32_t *value)
 424 {
 425         struct smu_table_context *smu_table= &smu->smu_table;
 426         SmuMetrics_t *metrics =
 427                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 428         int ret = 0;
 429
 430         mutex_lock(&smu->metrics_lock);
 431
 432         ret = smu_cmn_get_metrics_table_locked(smu,
 433                                                NULL,
 434                                                false);
 435         if (ret) {
 436                 mutex_unlock(&smu->metrics_lock);
 437                 return ret;
 438         }
 439
 440         switch (member) {
 441         case METRICS_CURR_GFXCLK:
 442                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 443                 break;
 444         case METRICS_CURR_SOCCLK:
 445                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 446                 break;
 447         case METRICS_CURR_UCLK:
 448                 *value = metrics->CurrClock[PPCLK_UCLK];
 449                 break;
 450         case METRICS_CURR_VCLK:
 451                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 452                 break;
 453         case METRICS_CURR_VCLK1:
 454                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 455                 break;
 456         case METRICS_CURR_DCLK:
 457                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 458                 break;
 459         case METRICS_CURR_DCLK1:
 460                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 461                 break;
 462         case METRICS_CURR_DCEFCLK:
 463                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 464                 break;
 465         case METRICS_CURR_FCLK:
 466                 *value = metrics->CurrClock[PPCLK_FCLK];
 467                 break;
 468         case METRICS_AVERAGE_GFXCLK:
 469                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 470                         *value = metrics->AverageGfxclkFrequencyPostDs;
 471                 else
 472                         *value = metrics->AverageGfxclkFrequencyPreDs;
 473                 break;
 474         case METRICS_AVERAGE_FCLK:
 475                 *value = metrics->AverageFclkFrequencyPostDs;
 476                 break;
 477         case METRICS_AVERAGE_UCLK:
 478                 *value = metrics->AverageUclkFrequencyPostDs;
 479                 break;
 480         case METRICS_AVERAGE_GFXACTIVITY:
 481                 *value = metrics->AverageGfxActivity;
 482                 break;
 483         case METRICS_AVERAGE_MEMACTIVITY:
 484                 *value = metrics->AverageUclkActivity;
 485                 break;
 486         case METRICS_AVERAGE_SOCKETPOWER:
 487                 *value = metrics->AverageSocketPower << 8;
 488                 break;
 489         case METRICS_TEMPERATURE_EDGE:
 490                 *value = metrics->TemperatureEdge *
 491                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 492                 break;
 493         case METRICS_TEMPERATURE_HOTSPOT:
 494                 *value = metrics->TemperatureHotspot *
 495                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 496                 break;
 497         case METRICS_TEMPERATURE_MEM:
 498                 *value = metrics->TemperatureMem *
 499                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 500                 break;
 501         case METRICS_TEMPERATURE_VRGFX:
 502                 *value = metrics->TemperatureVrGfx *
 503                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 504                 break;
 505         case METRICS_TEMPERATURE_VRSOC:
 506                 *value = metrics->TemperatureVrSoc *
 507                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 508                 break;
 509         case METRICS_THROTTLER_STATUS:
 510                 *value = metrics->ThrottlerStatus;
 511                 break;
 512         case METRICS_CURR_FANSPEED:
 513                 *value = metrics->CurrFanSpeed;
 514                 break;
 515         default:
 516                 *value = UINT_MAX;
 517                 break;
 518         }
 519
 520         mutex_unlock(&smu->metrics_lock);
 521
 522         return ret;
 523
 524 }
 525
 526 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 527 {
 528         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 529
 530         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 531                                        GFP_KERNEL);
 532         if (!smu_dpm->dpm_context)
 533                 return -ENOMEM;
 534
 535         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 536
 537         return 0;
 538 }
 539
 540 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 541 {
 542         int ret = 0;
 543
 544         ret = sienna_cichlid_tables_init(smu);
 545         if (ret)
 546                 return ret;
 547
 548         ret = sienna_cichlid_allocate_dpm_context(smu);
 549         if (ret)
 550                 return ret;
 551
 552         return smu_v11_0_init_smc_tables(smu);
 553 }
 554
 555 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 556 {
 557         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 558         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 559         struct smu_11_0_dpm_table *dpm_table;
 560         struct amdgpu_device *adev = smu->adev;
 561         int ret = 0;
 562
 563         /* socclk dpm table setup */
 564         dpm_table = &dpm_context->dpm_tables.soc_table;
 565         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 566                 ret = smu_v11_0_set_single_dpm_table(smu,
 567                                                      SMU_SOCCLK,
 568                                                      dpm_table);
 569                 if (ret)
 570                         return ret;
 571                 dpm_table->is_fine_grained =
 572                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 573         } else {
 574                 dpm_table->count = 1;
 575                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 576                 dpm_table->dpm_levels[0].enabled = true;
 577                 dpm_table->min = dpm_table->dpm_levels[0].value;
 578                 dpm_table->max = dpm_table->dpm_levels[0].value;
 579         }
 580
 581         /* gfxclk dpm table setup */
 582         dpm_table = &dpm_context->dpm_tables.gfx_table;
 583         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 584                 ret = smu_v11_0_set_single_dpm_table(smu,
 585                                                      SMU_GFXCLK,
 586                                                      dpm_table);
 587                 if (ret)
 588                         return ret;
 589                 dpm_table->is_fine_grained =
 590                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 591         } else {
 592                 dpm_table->count = 1;
 593                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 594                 dpm_table->dpm_levels[0].enabled = true;
 595                 dpm_table->min = dpm_table->dpm_levels[0].value;
 596                 dpm_table->max = dpm_table->dpm_levels[0].value;
 597         }
 598
 599         /* uclk dpm table setup */
 600         dpm_table = &dpm_context->dpm_tables.uclk_table;
 601         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 602                 ret = smu_v11_0_set_single_dpm_table(smu,
 603                                                      SMU_UCLK,
 604                                                      dpm_table);
 605                 if (ret)
 606                         return ret;
 607                 dpm_table->is_fine_grained =
 608                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 609         } else {
 610                 dpm_table->count = 1;
 611                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 612                 dpm_table->dpm_levels[0].enabled = true;
 613                 dpm_table->min = dpm_table->dpm_levels[0].value;
 614                 dpm_table->max = dpm_table->dpm_levels[0].value;
 615         }
 616
 617         /* fclk dpm table setup */
 618         dpm_table = &dpm_context->dpm_tables.fclk_table;
 619         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 620                 ret = smu_v11_0_set_single_dpm_table(smu,
 621                                                      SMU_FCLK,
 622                                                      dpm_table);
 623                 if (ret)
 624                         return ret;
 625                 dpm_table->is_fine_grained =
 626                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 627         } else {
 628                 dpm_table->count = 1;
 629                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 630                 dpm_table->dpm_levels[0].enabled = true;
 631                 dpm_table->min = dpm_table->dpm_levels[0].value;
 632                 dpm_table->max = dpm_table->dpm_levels[0].value;
 633         }
 634
 635         /* vclk0 dpm table setup */
 636         dpm_table = &dpm_context->dpm_tables.vclk_table;
 637         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 638                 ret = smu_v11_0_set_single_dpm_table(smu,
 639                                                      SMU_VCLK,
 640                                                      dpm_table);
 641                 if (ret)
 642                         return ret;
 643                 dpm_table->is_fine_grained =
 644                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 645         } else {
 646                 dpm_table->count = 1;
 647                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 648                 dpm_table->dpm_levels[0].enabled = true;
 649                 dpm_table->min = dpm_table->dpm_levels[0].value;
 650                 dpm_table->max = dpm_table->dpm_levels[0].value;
 651         }
 652
 653         /* vclk1 dpm table setup */
 654         if (adev->vcn.num_vcn_inst > 1) {
 655                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 656                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 657                         ret = smu_v11_0_set_single_dpm_table(smu,
 658                                                              SMU_VCLK1,
 659                                                              dpm_table);
 660                         if (ret)
 661                                 return ret;
 662                         dpm_table->is_fine_grained =
 663                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 664                 } else {
 665                         dpm_table->count = 1;
 666                         dpm_table->dpm_levels[0].value =
 667                                 smu->smu_table.boot_values.vclk / 100;
 668                         dpm_table->dpm_levels[0].enabled = true;
 669                         dpm_table->min = dpm_table->dpm_levels[0].value;
 670                         dpm_table->max = dpm_table->dpm_levels[0].value;
 671                 }
 672         }
 673
 674         /* dclk0 dpm table setup */
 675         dpm_table = &dpm_context->dpm_tables.dclk_table;
 676         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 677                 ret = smu_v11_0_set_single_dpm_table(smu,
 678                                                      SMU_DCLK,
 679                                                      dpm_table);
 680                 if (ret)
 681                         return ret;
 682                 dpm_table->is_fine_grained =
 683                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 684         } else {
 685                 dpm_table->count = 1;
 686                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 687                 dpm_table->dpm_levels[0].enabled = true;
 688                 dpm_table->min = dpm_table->dpm_levels[0].value;
 689                 dpm_table->max = dpm_table->dpm_levels[0].value;
 690         }
 691
 692         /* dclk1 dpm table setup */
 693         if (adev->vcn.num_vcn_inst > 1) {
 694                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 695                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 696                         ret = smu_v11_0_set_single_dpm_table(smu,
 697                                                              SMU_DCLK1,
 698                                                              dpm_table);
 699                         if (ret)
 700                                 return ret;
 701                         dpm_table->is_fine_grained =
 702                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 703                 } else {
 704                         dpm_table->count = 1;
 705                         dpm_table->dpm_levels[0].value =
 706                                 smu->smu_table.boot_values.dclk / 100;
 707                         dpm_table->dpm_levels[0].enabled = true;
 708                         dpm_table->min = dpm_table->dpm_levels[0].value;
 709                         dpm_table->max = dpm_table->dpm_levels[0].value;
 710                 }
 711         }
 712
 713         /* dcefclk dpm table setup */
 714         dpm_table = &dpm_context->dpm_tables.dcef_table;
 715         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 716                 ret = smu_v11_0_set_single_dpm_table(smu,
 717                                                      SMU_DCEFCLK,
 718                                                      dpm_table);
 719                 if (ret)
 720                         return ret;
 721                 dpm_table->is_fine_grained =
 722                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 723         } else {
 724                 dpm_table->count = 1;
 725                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 726                 dpm_table->dpm_levels[0].enabled = true;
 727                 dpm_table->min = dpm_table->dpm_levels[0].value;
 728                 dpm_table->max = dpm_table->dpm_levels[0].value;
 729         }
 730
 731         /* pixelclk dpm table setup */
 732         dpm_table = &dpm_context->dpm_tables.pixel_table;
 733         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 734                 ret = smu_v11_0_set_single_dpm_table(smu,
 735                                                      SMU_PIXCLK,
 736                                                      dpm_table);
 737                 if (ret)
 738                         return ret;
 739                 dpm_table->is_fine_grained =
 740                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 741         } else {
 742                 dpm_table->count = 1;
 743                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 744                 dpm_table->dpm_levels[0].enabled = true;
 745                 dpm_table->min = dpm_table->dpm_levels[0].value;
 746                 dpm_table->max = dpm_table->dpm_levels[0].value;
 747         }
 748
 749         /* displayclk dpm table setup */
 750         dpm_table = &dpm_context->dpm_tables.display_table;
 751         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 752                 ret = smu_v11_0_set_single_dpm_table(smu,
 753                                                      SMU_DISPCLK,
 754                                                      dpm_table);
 755                 if (ret)
 756                         return ret;
 757                 dpm_table->is_fine_grained =
 758                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 759         } else {
 760                 dpm_table->count = 1;
 761                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 762                 dpm_table->dpm_levels[0].enabled = true;
 763                 dpm_table->min = dpm_table->dpm_levels[0].value;
 764                 dpm_table->max = dpm_table->dpm_levels[0].value;
 765         }
 766
 767         /* phyclk dpm table setup */
 768         dpm_table = &dpm_context->dpm_tables.phy_table;
 769         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 770                 ret = smu_v11_0_set_single_dpm_table(smu,
 771                                                      SMU_PHYCLK,
 772                                                      dpm_table);
 773                 if (ret)
 774                         return ret;
 775                 dpm_table->is_fine_grained =
 776                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 777         } else {
 778                 dpm_table->count = 1;
 779                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 780                 dpm_table->dpm_levels[0].enabled = true;
 781                 dpm_table->min = dpm_table->dpm_levels[0].value;
 782                 dpm_table->max = dpm_table->dpm_levels[0].value;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 789 {
 790         struct amdgpu_device *adev = smu->adev;
 791         int ret = 0;
 792
 793         if (enable) {
 794                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 795                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 796                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 797                         if (ret)
 798                                 return ret;
 799                         if (adev->vcn.num_vcn_inst > 1) {
 800                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 801                                                                   0x10000, NULL);
 802                                 if (ret)
 803                                         return ret;
 804                         }
 805                 }
 806         } else {
 807                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 808                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 809                         if (ret)
 810                                 return ret;
 811                         if (adev->vcn.num_vcn_inst > 1) {
 812                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 813                                                                   0x10000, NULL);
 814                                 if (ret)
 815                                         return ret;
 816                         }
 817                 }
 818         }
 819
 820         return ret;
 821 }
 822
 823 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 824 {
 825         int ret = 0;
 826
 827         if (enable) {
 828                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 829                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 830                         if (ret)
 831                                 return ret;
 832                 }
 833         } else {
 834                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 835                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 836                         if (ret)
 837                                 return ret;
 838                 }
 839         }
 840
 841         return ret;
 842 }
 843
 844 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 845                                        enum smu_clk_type clk_type,
 846                                        uint32_t *value)
 847 {
 848         MetricsMember_t member_type;
 849         int clk_id = 0;
 850
 851         clk_id = smu_cmn_to_asic_specific_index(smu,
 852                                                 CMN2ASIC_MAPPING_CLK,
 853                                                 clk_type);
 854         if (clk_id < 0)
 855                 return clk_id;
 856
 857         switch (clk_id) {
 858         case PPCLK_GFXCLK:
 859                 member_type = METRICS_CURR_GFXCLK;
 860                 break;
 861         case PPCLK_UCLK:
 862                 member_type = METRICS_CURR_UCLK;
 863                 break;
 864         case PPCLK_SOCCLK:
 865                 member_type = METRICS_CURR_SOCCLK;
 866                 break;
 867         case PPCLK_FCLK:
 868                 member_type = METRICS_CURR_FCLK;
 869                 break;
 870         case PPCLK_VCLK_0:
 871                 member_type = METRICS_CURR_VCLK;
 872                 break;
 873         case PPCLK_VCLK_1:
 874                 member_type = METRICS_CURR_VCLK1;
 875                 break;
 876         case PPCLK_DCLK_0:
 877                 member_type = METRICS_CURR_DCLK;
 878                 break;
 879         case PPCLK_DCLK_1:
 880                 member_type = METRICS_CURR_DCLK1;
 881                 break;
 882         case PPCLK_DCEFCLK:
 883                 member_type = METRICS_CURR_DCEFCLK;
 884                 break;
 885         default:
 886                 return -EINVAL;
 887         }
 888
 889         return sienna_cichlid_get_smu_metrics_data(smu,
 890                                                    member_type,
 891                                                    value);
 892
 893 }
 894
 895 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 896 {
 897         PPTable_t *pptable = smu->smu_table.driver_pptable;
 898         DpmDescriptor_t *dpm_desc = NULL;
 899         uint32_t clk_index = 0;
 900
 901         clk_index = smu_cmn_to_asic_specific_index(smu,
 902                                                    CMN2ASIC_MAPPING_CLK,
 903                                                    clk_type);
 904         dpm_desc = &pptable->DpmDescriptor[clk_index];
 905
 906         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 907         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 908 }
 909
 910 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 911                         enum smu_clk_type clk_type, char *buf)
 912 {
 913         struct amdgpu_device *adev = smu->adev;
 914         struct smu_table_context *table_context = &smu->smu_table;
 915         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 916         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 917         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 918         int i, size = 0, ret = 0;
 919         uint32_t cur_value = 0, value = 0, count = 0;
 920         uint32_t freq_values[3] = {0};
 921         uint32_t mark_index = 0;
 922         uint32_t gen_speed, lane_width;
 923
 924         switch (clk_type) {
 925         case SMU_GFXCLK:
 926         case SMU_SCLK:
 927         case SMU_SOCCLK:
 928         case SMU_MCLK:
 929         case SMU_UCLK:
 930         case SMU_FCLK:
 931         case SMU_DCEFCLK:
 932                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 933                 if (ret)
 934                         goto print_clk_out;
 935
 936                 /* no need to disable gfxoff when retrieving the current gfxclk */
 937                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 938                         amdgpu_gfx_off_ctrl(adev, false);
 939
 940                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 941                 if (ret)
 942                         goto print_clk_out;
 943
 944                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 945                         for (i = 0; i < count; i++) {
 946                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 947                                 if (ret)
 948                                         goto print_clk_out;
 949
 950                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 951                                                 cur_value == value ? "*" : "");
 952                         }
 953                 } else {
 954                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 955                         if (ret)
 956                                 goto print_clk_out;
 957                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 958                         if (ret)
 959                                 goto print_clk_out;
 960
 961                         freq_values[1] = cur_value;
 962                         mark_index = cur_value == freq_values[0] ? 0 :
 963                                      cur_value == freq_values[2] ? 2 : 1;
 964
 965                         count = 3;
 966                         if (mark_index != 1) {
 967                                 count = 2;
 968                                 freq_values[1] = freq_values[2];
 969                         }
 970
 971                         for (i = 0; i < count; i++) {
 972                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 973                                                 cur_value  == freq_values[i] ? "*" : "");
 974                         }
 975
 976                 }
 977                 break;
 978         case SMU_PCIE:
 979                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 980                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 981                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 982                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 983                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 984                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 985                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 986                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 987                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 988                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 989                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 990                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 991                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 992                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 993                                         pptable->LclkFreq[i],
 994                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 995                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 996                                         "*" : "");
 997                 break;
 998         default:
 999                 break;
1000         }
1001
1002 print_clk_out:
1003         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1004                 amdgpu_gfx_off_ctrl(adev, true);
1005
1006         return size;
1007 }
1008
1009 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1010                                    enum smu_clk_type clk_type, uint32_t mask)
1011 {
1012         struct amdgpu_device *adev = smu->adev;
1013         int ret = 0, size = 0;
1014         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1015
1016         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1017         soft_max_level = mask ? (fls(mask) - 1) : 0;
1018
1019         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1020                 amdgpu_gfx_off_ctrl(adev, false);
1021
1022         switch (clk_type) {
1023         case SMU_GFXCLK:
1024         case SMU_SCLK:
1025         case SMU_SOCCLK:
1026         case SMU_MCLK:
1027         case SMU_UCLK:
1028         case SMU_DCEFCLK:
1029         case SMU_FCLK:
1030                 /* There is only 2 levels for fine grained DPM */
1031                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1032                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1033                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1034                 }
1035
1036                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1037                 if (ret)
1038                         goto forec_level_out;
1039
1040                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1041                 if (ret)
1042                         goto forec_level_out;
1043
1044                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1045                 if (ret)
1046                         goto forec_level_out;
1047                 break;
1048         default:
1049                 break;
1050         }
1051
1052 forec_level_out:
1053         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1054                 amdgpu_gfx_off_ctrl(adev, true);
1055
1056         return size;
1057 }
1058
1059 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1060 {
1061         struct smu_11_0_dpm_context *dpm_context =
1062                                 smu->smu_dpm.dpm_context;
1063         struct smu_11_0_dpm_table *gfx_table =
1064                                 &dpm_context->dpm_tables.gfx_table;
1065         struct smu_11_0_dpm_table *mem_table =
1066                                 &dpm_context->dpm_tables.uclk_table;
1067         struct smu_11_0_dpm_table *soc_table =
1068                                 &dpm_context->dpm_tables.soc_table;
1069         struct smu_umd_pstate_table *pstate_table =
1070                                 &smu->pstate_table;
1071
1072         pstate_table->gfxclk_pstate.min = gfx_table->min;
1073         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1074         if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1075                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1076
1077         pstate_table->uclk_pstate.min = mem_table->min;
1078         pstate_table->uclk_pstate.peak = mem_table->max;
1079         if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1080                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1081
1082         pstate_table->socclk_pstate.min = soc_table->min;
1083         pstate_table->socclk_pstate.peak = soc_table->max;
1084         if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1085                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1086
1087         return 0;
1088 }
1089
1090 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1091 {
1092         int ret = 0;
1093         uint32_t max_freq = 0;
1094
1095         /* Sienna_Cichlid do not support to change display num currently */
1096         return 0;
1097 #if 0
1098         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1099         if (ret)
1100                 return ret;
1101 #endif
1102
1103         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1104                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1105                 if (ret)
1106                         return ret;
1107                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1108                 if (ret)
1109                         return ret;
1110         }
1111
1112         return ret;
1113 }
1114
1115 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1116 {
1117         int ret = 0;
1118
1119         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1120             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1121             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1122 #if 0
1123                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1124                                                   smu->display_config->num_display,
1125                                                   NULL);
1126 #endif
1127                 if (ret)
1128                         return ret;
1129         }
1130
1131         return ret;
1132 }
1133
1134 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1135 {
1136         int ret = 0;
1137         uint32_t feature_mask[2];
1138         uint64_t feature_enabled;
1139
1140         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1141         if (ret)
1142                 return false;
1143
1144         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1145
1146         return !!(feature_enabled & SMC_DPM_FEATURE);
1147 }
1148
1149 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1150                                     uint32_t *speed)
1151 {
1152         if (!speed)
1153                 return -EINVAL;
1154
1155         return sienna_cichlid_get_smu_metrics_data(smu,
1156                                                 METRICS_CURR_FANSPEED,
1157                                                 speed);
1158 }
1159
1160 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1161 {
1162         PPTable_t *pptable = smu->smu_table.driver_pptable;
1163
1164         smu->fan_max_rpm = pptable->FanMaximumRpm;
1165
1166         return 0;
1167 }
1168
1169 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1170 {
1171         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1172         DpmActivityMonitorCoeffInt_t *activity_monitor =
1173                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1174         uint32_t i, size = 0;
1175         int16_t workload_type = 0;
1176         static const char *profile_name[] = {
1177                                         "BOOTUP_DEFAULT",
1178                                         "3D_FULL_SCREEN",
1179                                         "POWER_SAVING",
1180                                         "VIDEO",
1181                                         "VR",
1182                                         "COMPUTE",
1183                                         "CUSTOM"};
1184         static const char *title[] = {
1185                         "PROFILE_INDEX(NAME)",
1186                         "CLOCK_TYPE(NAME)",
1187                         "FPS",
1188                         "MinFreqType",
1189                         "MinActiveFreqType",
1190                         "MinActiveFreq",
1191                         "BoosterFreqType",
1192                         "BoosterFreq",
1193                         "PD_Data_limit_c",
1194                         "PD_Data_error_coeff",
1195                         "PD_Data_error_rate_coeff"};
1196         int result = 0;
1197
1198         if (!buf)
1199                 return -EINVAL;
1200
1201         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1202                         title[0], title[1], title[2], title[3], title[4], title[5],
1203                         title[6], title[7], title[8], title[9], title[10]);
1204
1205         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1206                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1207                 workload_type = smu_cmn_to_asic_specific_index(smu,
1208                                                                CMN2ASIC_MAPPING_WORKLOAD,
1209                                                                i);
1210                 if (workload_type < 0)
1211                         return -EINVAL;
1212
1213                 result = smu_cmn_update_table(smu,
1214                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1215                                           (void *)(&activity_monitor_external), false);
1216                 if (result) {
1217                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1218                         return result;
1219                 }
1220
1221                 size += sprintf(buf + size, "%2d %14s%s:\n",
1222                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1223
1224                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1225                         " ",
1226                         0,
1227                         "GFXCLK",
1228                         activity_monitor->Gfx_FPS,
1229                         activity_monitor->Gfx_MinFreqStep,
1230                         activity_monitor->Gfx_MinActiveFreqType,
1231                         activity_monitor->Gfx_MinActiveFreq,
1232                         activity_monitor->Gfx_BoosterFreqType,
1233                         activity_monitor->Gfx_BoosterFreq,
1234                         activity_monitor->Gfx_PD_Data_limit_c,
1235                         activity_monitor->Gfx_PD_Data_error_coeff,
1236                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1237
1238                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1239                         " ",
1240                         1,
1241                         "SOCCLK",
1242                         activity_monitor->Fclk_FPS,
1243                         activity_monitor->Fclk_MinFreqStep,
1244                         activity_monitor->Fclk_MinActiveFreqType,
1245                         activity_monitor->Fclk_MinActiveFreq,
1246                         activity_monitor->Fclk_BoosterFreqType,
1247                         activity_monitor->Fclk_BoosterFreq,
1248                         activity_monitor->Fclk_PD_Data_limit_c,
1249                         activity_monitor->Fclk_PD_Data_error_coeff,
1250                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1251
1252                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1253                         " ",
1254                         2,
1255                         "MEMLK",
1256                         activity_monitor->Mem_FPS,
1257                         activity_monitor->Mem_MinFreqStep,
1258                         activity_monitor->Mem_MinActiveFreqType,
1259                         activity_monitor->Mem_MinActiveFreq,
1260                         activity_monitor->Mem_BoosterFreqType,
1261                         activity_monitor->Mem_BoosterFreq,
1262                         activity_monitor->Mem_PD_Data_limit_c,
1263                         activity_monitor->Mem_PD_Data_error_coeff,
1264                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1265         }
1266
1267         return size;
1268 }
1269
1270 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1271 {
1272
1273         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1274         DpmActivityMonitorCoeffInt_t *activity_monitor =
1275                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1276         int workload_type, ret = 0;
1277
1278         smu->power_profile_mode = input[size];
1279
1280         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1281                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1282                 return -EINVAL;
1283         }
1284
1285         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1286
1287                 ret = smu_cmn_update_table(smu,
1288                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1289                                        (void *)(&activity_monitor_external), false);
1290                 if (ret) {
1291                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1292                         return ret;
1293                 }
1294
1295                 switch (input[0]) {
1296                 case 0: /* Gfxclk */
1297                         activity_monitor->Gfx_FPS = input[1];
1298                         activity_monitor->Gfx_MinFreqStep = input[2];
1299                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1300                         activity_monitor->Gfx_MinActiveFreq = input[4];
1301                         activity_monitor->Gfx_BoosterFreqType = input[5];
1302                         activity_monitor->Gfx_BoosterFreq = input[6];
1303                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1304                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1305                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1306                         break;
1307                 case 1: /* Socclk */
1308                         activity_monitor->Fclk_FPS = input[1];
1309                         activity_monitor->Fclk_MinFreqStep = input[2];
1310                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1311                         activity_monitor->Fclk_MinActiveFreq = input[4];
1312                         activity_monitor->Fclk_BoosterFreqType = input[5];
1313                         activity_monitor->Fclk_BoosterFreq = input[6];
1314                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1315                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1316                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1317                         break;
1318                 case 2: /* Memlk */
1319                         activity_monitor->Mem_FPS = input[1];
1320                         activity_monitor->Mem_MinFreqStep = input[2];
1321                         activity_monitor->Mem_MinActiveFreqType = input[3];
1322                         activity_monitor->Mem_MinActiveFreq = input[4];
1323                         activity_monitor->Mem_BoosterFreqType = input[5];
1324                         activity_monitor->Mem_BoosterFreq = input[6];
1325                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1326                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1327                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1328                         break;
1329                 }
1330
1331                 ret = smu_cmn_update_table(smu,
1332                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1333                                        (void *)(&activity_monitor_external), true);
1334                 if (ret) {
1335                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1336                         return ret;
1337                 }
1338         }
1339
1340         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1341         workload_type = smu_cmn_to_asic_specific_index(smu,
1342                                                        CMN2ASIC_MAPPING_WORKLOAD,
1343                                                        smu->power_profile_mode);
1344         if (workload_type < 0)
1345                 return -EINVAL;
1346         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1347                                     1 << workload_type, NULL);
1348
1349         return ret;
1350 }
1351
1352 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1353 {
1354         struct smu_clocks min_clocks = {0};
1355         struct pp_display_clock_request clock_req;
1356         int ret = 0;
1357
1358         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1359         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1360         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1361
1362         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1363                 clock_req.clock_type = amd_pp_dcef_clock;
1364                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1365
1366                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1367                 if (!ret) {
1368                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1369                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1370                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1371                                                                   min_clocks.dcef_clock_in_sr/100,
1372                                                                   NULL);
1373                                 if (ret) {
1374                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1375                                         return ret;
1376                                 }
1377                         }
1378                 } else {
1379                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1380                 }
1381         }
1382
1383         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1384                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1385                 if (ret) {
1386                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1387                         return ret;
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1395                                                struct pp_smu_wm_range_sets *clock_ranges)
1396 {
1397         Watermarks_t *table = smu->smu_table.watermarks_table;
1398         int ret = 0;
1399         int i;
1400
1401         if (clock_ranges) {
1402                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1403                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1404                         return -EINVAL;
1405
1406                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1407                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1408                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1409                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1410                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1411                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1412                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1413                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1414                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1415
1416                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1417                                 clock_ranges->reader_wm_sets[i].wm_inst;
1418                 }
1419
1420                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1421                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1422                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1423                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1424                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1425                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1426                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1427                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1428                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1429
1430                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1431                                 clock_ranges->writer_wm_sets[i].wm_inst;
1432                 }
1433
1434                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1435         }
1436
1437         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1438              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1439                 ret = smu_cmn_write_watermarks_table(smu);
1440                 if (ret) {
1441                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1442                         return ret;
1443                 }
1444                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1445         }
1446
1447         return 0;
1448 }
1449
1450 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1451                                  enum amd_pp_sensors sensor,
1452                                  void *data, uint32_t *size)
1453 {
1454         int ret = 0;
1455         struct smu_table_context *table_context = &smu->smu_table;
1456         PPTable_t *pptable = table_context->driver_pptable;
1457
1458         if(!data || !size)
1459                 return -EINVAL;
1460
1461         mutex_lock(&smu->sensor_lock);
1462         switch (sensor) {
1463         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1464                 *(uint32_t *)data = pptable->FanMaximumRpm;
1465                 *size = 4;
1466                 break;
1467         case AMDGPU_PP_SENSOR_MEM_LOAD:
1468                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1469                                                           METRICS_AVERAGE_MEMACTIVITY,
1470                                                           (uint32_t *)data);
1471                 *size = 4;
1472                 break;
1473         case AMDGPU_PP_SENSOR_GPU_LOAD:
1474                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1475                                                           METRICS_AVERAGE_GFXACTIVITY,
1476                                                           (uint32_t *)data);
1477                 *size = 4;
1478                 break;
1479         case AMDGPU_PP_SENSOR_GPU_POWER:
1480                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1481                                                           METRICS_AVERAGE_SOCKETPOWER,
1482                                                           (uint32_t *)data);
1483                 *size = 4;
1484                 break;
1485         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1486                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1487                                                           METRICS_TEMPERATURE_HOTSPOT,
1488                                                           (uint32_t *)data);
1489                 *size = 4;
1490                 break;
1491         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1492                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1493                                                           METRICS_TEMPERATURE_EDGE,
1494                                                           (uint32_t *)data);
1495                 *size = 4;
1496                 break;
1497         case AMDGPU_PP_SENSOR_MEM_TEMP:
1498                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1499                                                           METRICS_TEMPERATURE_MEM,
1500                                                           (uint32_t *)data);
1501                 *size = 4;
1502                 break;
1503         case AMDGPU_PP_SENSOR_GFX_MCLK:
1504                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1505                 *(uint32_t *)data *= 100;
1506                 *size = 4;
1507                 break;
1508         case AMDGPU_PP_SENSOR_GFX_SCLK:
1509                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1510                 *(uint32_t *)data *= 100;
1511                 *size = 4;
1512                 break;
1513         case AMDGPU_PP_SENSOR_VDDGFX:
1514                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1515                 *size = 4;
1516                 break;
1517         default:
1518                 ret = -EOPNOTSUPP;
1519                 break;
1520         }
1521         mutex_unlock(&smu->sensor_lock);
1522
1523         return ret;
1524 }
1525
1526 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1527 {
1528         uint32_t num_discrete_levels = 0;
1529         uint16_t *dpm_levels = NULL;
1530         uint16_t i = 0;
1531         struct smu_table_context *table_context = &smu->smu_table;
1532         PPTable_t *driver_ppt = NULL;
1533
1534         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1535                 return -EINVAL;
1536
1537         driver_ppt = table_context->driver_pptable;
1538         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1539         dpm_levels = driver_ppt->FreqTableUclk;
1540
1541         if (num_discrete_levels == 0 || dpm_levels == NULL)
1542                 return -EINVAL;
1543
1544         *num_states = num_discrete_levels;
1545         for (i = 0; i < num_discrete_levels; i++) {
1546                 /* convert to khz */
1547                 *clocks_in_khz = (*dpm_levels) * 1000;
1548                 clocks_in_khz++;
1549                 dpm_levels++;
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1556                                                 struct smu_temperature_range *range)
1557 {
1558         struct smu_table_context *table_context = &smu->smu_table;
1559         struct smu_11_0_7_powerplay_table *powerplay_table =
1560                                 table_context->power_play_table;
1561         PPTable_t *pptable = smu->smu_table.driver_pptable;
1562
1563         if (!range)
1564                 return -EINVAL;
1565
1566         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1567
1568         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1569                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1570         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1571                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1572         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1573                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1574         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1575                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1576         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1577                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1578         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1579                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1580         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1581
1582         return 0;
1583 }
1584
1585 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1586                                                 bool disable_memory_clock_switch)
1587 {
1588         int ret = 0;
1589         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1590                 (struct smu_11_0_max_sustainable_clocks *)
1591                         smu->smu_table.max_sustainable_clocks;
1592         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1593         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1594
1595         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1596                 return 0;
1597
1598         if(disable_memory_clock_switch)
1599                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1600         else
1601                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1602
1603         if(!ret)
1604                 smu->disable_uclk_switch = disable_memory_clock_switch;
1605
1606         return ret;
1607 }
1608
1609 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1610 {
1611         struct smu_11_0_7_powerplay_table *powerplay_table =
1612                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1613         PPTable_t *pptable = smu->smu_table.driver_pptable;
1614         uint32_t power_limit, od_percent;
1615
1616         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1617                 /* the last hope to figure out the ppt limit */
1618                 if (!pptable) {
1619                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1620                         return -EINVAL;
1621                 }
1622                 power_limit =
1623                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1624         }
1625         smu->current_power_limit = power_limit;
1626
1627         if (smu->od_enabled) {
1628                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1629
1630                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1631
1632                 power_limit *= (100 + od_percent);
1633                 power_limit /= 100;
1634         }
1635         smu->max_power_limit = power_limit;
1636
1637         return 0;
1638 }
1639
1640 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1641                                          uint32_t pcie_gen_cap,
1642                                          uint32_t pcie_width_cap)
1643 {
1644         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1645         PPTable_t *pptable = smu->smu_table.driver_pptable;
1646         uint32_t smu_pcie_arg;
1647         int ret, i;
1648
1649         /* lclk dpm table setup */
1650         for (i = 0; i < MAX_PCIE_CONF; i++) {
1651                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1652                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1653         }
1654
1655         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1656                 smu_pcie_arg = (i << 16) |
1657                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1658                                         (pptable->PcieGenSpeed[i] << 8) :
1659                                         (pcie_gen_cap << 8)) |
1660                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1661                                         pptable->PcieLaneCount[i] :
1662                                         pcie_width_cap);
1663
1664                 ret = smu_cmn_send_smc_msg_with_param(smu,
1665                                           SMU_MSG_OverridePcieParameters,
1666                                           smu_pcie_arg,
1667                                           NULL);
1668
1669                 if (ret)
1670                         return ret;
1671
1672                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1673                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1674                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1675                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1682                                 enum smu_clk_type clk_type,
1683                                 uint32_t *min, uint32_t *max)
1684 {
1685         struct amdgpu_device *adev = smu->adev;
1686         int ret;
1687
1688         if (clk_type == SMU_GFXCLK)
1689                 amdgpu_gfx_off_ctrl(adev, false);
1690         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1691         if (clk_type == SMU_GFXCLK)
1692                 amdgpu_gfx_off_ctrl(adev, true);
1693
1694         return ret;
1695 }
1696
1697 static int sienna_cichlid_run_btc(struct smu_context *smu)
1698 {
1699         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1700 }
1701
1702 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1703 {
1704         struct amdgpu_device *adev = smu->adev;
1705         uint32_t val;
1706
1707         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1708                 return false;
1709
1710         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1711         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1712 }
1713
1714 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1715 {
1716         struct amdgpu_device *adev = smu->adev;
1717         uint32_t val;
1718         u32 smu_version;
1719
1720         /**
1721          * SRIOV env will not support SMU mode1 reset
1722          * PM FW support mode1 reset from 58.26
1723          */
1724         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1725         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1726                 return false;
1727
1728         /**
1729          * mode1 reset relies on PSP, so we should check if
1730          * PSP is alive.
1731          */
1732         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1733         return val != 0x0;
1734 }
1735
1736 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1737 {
1738         struct smu_table_context *table_context = &smu->smu_table;
1739         PPTable_t *pptable = table_context->driver_pptable;
1740         int i;
1741
1742         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1743
1744         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1745         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1746         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1747
1748         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1749                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1750                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1751                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1752                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1753         }
1754
1755         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1756                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1757                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1758         }
1759
1760         for (i = 0; i < TEMP_COUNT; i++) {
1761                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1762         }
1763
1764         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1765         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1766         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1767         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1768         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1769
1770         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1771         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1772                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1773                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1774         }
1775         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1776
1777         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1778
1779         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1780         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1781         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1782         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1783
1784         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1785         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1786
1787         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1788         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1789         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1790         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1791
1792         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1793         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1794         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1795         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1796
1797         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1798         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1799
1800         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1801         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1802         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1803         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1804         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1805         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1806         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1807         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1808
1809         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1810                         "  .VoltageMode          = 0x%02x\n"
1811                         "  .SnapToDiscrete       = 0x%02x\n"
1812                         "  .NumDiscreteLevels    = 0x%02x\n"
1813                         "  .padding              = 0x%02x\n"
1814                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1815                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1816                         "  .SsFmin               = 0x%04x\n"
1817                         "  .Padding_16           = 0x%04x\n",
1818                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1819                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1820                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1821                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1822                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1823                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1824                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1825                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1826                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1827                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1828                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1829
1830         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1831                         "  .VoltageMode          = 0x%02x\n"
1832                         "  .SnapToDiscrete       = 0x%02x\n"
1833                         "  .NumDiscreteLevels    = 0x%02x\n"
1834                         "  .padding              = 0x%02x\n"
1835                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1836                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1837                         "  .SsFmin               = 0x%04x\n"
1838                         "  .Padding_16           = 0x%04x\n",
1839                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1840                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1841                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1842                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1843                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1844                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1845                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1846                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1847                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1848                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1849                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1850
1851         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1852                         "  .VoltageMode          = 0x%02x\n"
1853                         "  .SnapToDiscrete       = 0x%02x\n"
1854                         "  .NumDiscreteLevels    = 0x%02x\n"
1855                         "  .padding              = 0x%02x\n"
1856                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1857                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1858                         "  .SsFmin               = 0x%04x\n"
1859                         "  .Padding_16           = 0x%04x\n",
1860                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1861                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1862                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1863                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1864                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1865                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1866                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1867                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1868                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1869                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1870                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1871
1872         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1873                         "  .VoltageMode          = 0x%02x\n"
1874                         "  .SnapToDiscrete       = 0x%02x\n"
1875                         "  .NumDiscreteLevels    = 0x%02x\n"
1876                         "  .padding              = 0x%02x\n"
1877                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1878                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1879                         "  .SsFmin               = 0x%04x\n"
1880                         "  .Padding_16           = 0x%04x\n",
1881                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1882                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1883                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1884                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1885                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1886                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1887                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1888                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1889                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1890                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1891                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1892
1893         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1894                         "  .VoltageMode          = 0x%02x\n"
1895                         "  .SnapToDiscrete       = 0x%02x\n"
1896                         "  .NumDiscreteLevels    = 0x%02x\n"
1897                         "  .padding              = 0x%02x\n"
1898                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1899                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1900                         "  .SsFmin               = 0x%04x\n"
1901                         "  .Padding_16           = 0x%04x\n",
1902                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1903                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1904                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1905                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1906                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1907                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1908                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1909                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1910                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1911                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1912                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1913
1914         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1915                         "  .VoltageMode          = 0x%02x\n"
1916                         "  .SnapToDiscrete       = 0x%02x\n"
1917                         "  .NumDiscreteLevels    = 0x%02x\n"
1918                         "  .padding              = 0x%02x\n"
1919                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1920                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1921                         "  .SsFmin               = 0x%04x\n"
1922                         "  .Padding_16           = 0x%04x\n",
1923                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1924                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1925                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1926                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1927                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1928                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1929                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1930                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1931                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1932                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1933                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1934
1935         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
1936                         "  .VoltageMode          = 0x%02x\n"
1937                         "  .SnapToDiscrete       = 0x%02x\n"
1938                         "  .NumDiscreteLevels    = 0x%02x\n"
1939                         "  .padding              = 0x%02x\n"
1940                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1941                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1942                         "  .SsFmin               = 0x%04x\n"
1943                         "  .Padding_16           = 0x%04x\n",
1944                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1945                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1946                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1947                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1948                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1949                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1950                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1951                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1952                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1953                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1954                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1955
1956         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
1957                         "  .VoltageMode          = 0x%02x\n"
1958                         "  .SnapToDiscrete       = 0x%02x\n"
1959                         "  .NumDiscreteLevels    = 0x%02x\n"
1960                         "  .padding              = 0x%02x\n"
1961                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1962                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1963                         "  .SsFmin               = 0x%04x\n"
1964                         "  .Padding_16           = 0x%04x\n",
1965                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1966                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1967                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1968                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1969                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1970                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1971                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1972                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1973                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1974                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1975                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1976
1977         dev_info(smu->adev->dev, "FreqTableGfx\n");
1978         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1979                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1980
1981         dev_info(smu->adev->dev, "FreqTableVclk\n");
1982         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1983                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1984
1985         dev_info(smu->adev->dev, "FreqTableDclk\n");
1986         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1987                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1988
1989         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1990         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1991                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1992
1993         dev_info(smu->adev->dev, "FreqTableUclk\n");
1994         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1995                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1996
1997         dev_info(smu->adev->dev, "FreqTableFclk\n");
1998         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1999                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2000
2001         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2002         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2003         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2004         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2005         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2006         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2007         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2008         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2009         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2010
2011         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2012         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2013                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2014
2015         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2016         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2017
2018         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2019         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2020                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2021
2022         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2023         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2024                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2025
2026         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2027         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2028                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2029
2030         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2031         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2032                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2033
2034         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2035         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2036         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2037         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2038         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2039
2040         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2041
2042         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2043         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2044         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2045         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2046         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2047         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2048         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2049         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2050         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2051         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2052         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2053
2054         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2055         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2056         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2057         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2058         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2059         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2060
2061         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2062         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2063         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2064         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2065         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2066
2067         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2068         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2069                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2070
2071         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2072         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2073         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2074         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2075
2076         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2077         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2078                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2079
2080         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2081         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2082                 pptable->UclkDpmSrcFreqRange.Fmin);
2083         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2084                 pptable->UclkDpmSrcFreqRange.Fmax);
2085         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2086         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2087                 pptable->UclkDpmTargFreqRange.Fmin);
2088         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2089                 pptable->UclkDpmTargFreqRange.Fmax);
2090         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2091         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2092
2093         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2094         for (i = 0; i < NUM_LINK_LEVELS; i++)
2095                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2096
2097         dev_info(smu->adev->dev, "PcieLaneCount\n");
2098         for (i = 0; i < NUM_LINK_LEVELS; i++)
2099                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2100
2101         dev_info(smu->adev->dev, "LclkFreq\n");
2102         for (i = 0; i < NUM_LINK_LEVELS; i++)
2103                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2104
2105         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2106         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2107
2108         dev_info(smu->adev->dev, "FanGain\n");
2109         for (i = 0; i < TEMP_COUNT; i++)
2110                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2111
2112         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2113         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2114         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2115         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2116         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2117         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2118         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2119         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2120         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2121         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2122         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2123         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2124
2125         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2126         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2127         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2128         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2129
2130         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2131         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2132         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2133         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2134
2135         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2136                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2137                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2138                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2139         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2140                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2141                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2142                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2143         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2144                         pptable->dBtcGbGfxPll.a,
2145                         pptable->dBtcGbGfxPll.b,
2146                         pptable->dBtcGbGfxPll.c);
2147         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2148                         pptable->dBtcGbGfxDfll.a,
2149                         pptable->dBtcGbGfxDfll.b,
2150                         pptable->dBtcGbGfxDfll.c);
2151         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2152                         pptable->dBtcGbSoc.a,
2153                         pptable->dBtcGbSoc.b,
2154                         pptable->dBtcGbSoc.c);
2155         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2156                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2157                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2158         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2159                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2160                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2161
2162         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2163         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2164                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2165                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2166                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2167                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2168         }
2169
2170         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2171                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2172                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2173                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2174         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2175                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2176                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2177                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2178
2179         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2180         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2181
2182         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2183         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2184         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2185         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2186
2187         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2188         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2189         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2190         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2191
2192         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2193         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2194
2195         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2196         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2197                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2198         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2199         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2200
2201         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2202         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2203                         pptable->ReservedEquation0.a,
2204                         pptable->ReservedEquation0.b,
2205                         pptable->ReservedEquation0.c);
2206         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2207                         pptable->ReservedEquation1.a,
2208                         pptable->ReservedEquation1.b,
2209                         pptable->ReservedEquation1.c);
2210         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2211                         pptable->ReservedEquation2.a,
2212                         pptable->ReservedEquation2.b,
2213                         pptable->ReservedEquation2.c);
2214         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2215                         pptable->ReservedEquation3.a,
2216                         pptable->ReservedEquation3.b,
2217                         pptable->ReservedEquation3.c);
2218
2219         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2220         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2221         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2222         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2223         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2224         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2225         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2226         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2227
2228         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2229         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2230         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2231         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2232         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2233         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2234
2235         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2236                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2237                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2238                                 pptable->I2cControllers[i].Enabled);
2239                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2240                                 pptable->I2cControllers[i].Speed);
2241                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2242                                 pptable->I2cControllers[i].SlaveAddress);
2243                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2244                                 pptable->I2cControllers[i].ControllerPort);
2245                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2246                                 pptable->I2cControllers[i].ControllerName);
2247                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2248                                 pptable->I2cControllers[i].ThermalThrotter);
2249                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2250                                 pptable->I2cControllers[i].I2cProtocol);
2251                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2252                                 pptable->I2cControllers[i].PaddingConfig);
2253         }
2254
2255         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2256         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2257         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2258         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2259
2260         dev_info(smu->adev->dev, "Board Parameters:\n");
2261         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2262         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2263         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2264         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2265         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2266         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2267         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2268         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2269
2270         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2271         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2272         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2273
2274         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2275         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2276         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2277
2278         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2279         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2280         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2281
2282         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2283         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2284         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2285
2286         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2287
2288         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2289         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2290         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2291         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2292         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2293         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2294         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2295         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2296         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2297         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2298         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2299         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2300         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2301         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2302         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2303         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2304
2305         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2306         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2307         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2308
2309         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2310         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2311         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2312
2313         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2314         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2315
2316         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2317         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2318         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2319
2320         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2321         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2322         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2323         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2324         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2325
2326         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2327         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2328
2329         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2330         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2331                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2332         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2333         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2334                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2335         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2336         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2337                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2338         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2339         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2340                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2341
2342         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2343         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2344         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2345         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2346
2347         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2348         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2349         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2350         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2351         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2352         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2353         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2354         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2355         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2356         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2357         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2358
2359         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2360         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2361         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2362         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2363         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2364         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2365         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2366         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2367 }
2368
2369 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2370                                   uint8_t address, uint32_t numbytes,
2371                                   uint8_t *data)
2372 {
2373         int i;
2374
2375         req->I2CcontrollerPort = 0;
2376         req->I2CSpeed = 2;
2377         req->SlaveAddress = address;
2378         req->NumCmds = numbytes;
2379
2380         for (i = 0; i < numbytes; i++) {
2381                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2382
2383                 /* First 2 bytes are always write for lower 2b EEPROM address */
2384                 if (i < 2)
2385                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2386                 else
2387                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2388
2389
2390                 /* Add RESTART for read  after address filled */
2391                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2392
2393                 /* Add STOP in the end */
2394                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2395
2396                 /* Fill with data regardless if read or write to simplify code */
2397                 cmd->ReadWriteData = data[i];
2398         }
2399 }
2400
2401 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2402                                                uint8_t address,
2403                                                uint8_t *data,
2404                                                uint32_t numbytes)
2405 {
2406         uint32_t  i, ret = 0;
2407         SwI2cRequest_t req;
2408         struct amdgpu_device *adev = to_amdgpu_device(control);
2409         struct smu_table_context *smu_table = &adev->smu.smu_table;
2410         struct smu_table *table = &smu_table->driver_table;
2411
2412         if (numbytes > MAX_SW_I2C_COMMANDS) {
2413                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2414                         numbytes, MAX_SW_I2C_COMMANDS);
2415                 return -EINVAL;
2416         }
2417
2418         memset(&req, 0, sizeof(req));
2419         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2420
2421         mutex_lock(&adev->smu.mutex);
2422         /* Now read data starting with that address */
2423         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2424                                         true);
2425         mutex_unlock(&adev->smu.mutex);
2426
2427         if (!ret) {
2428                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2429
2430                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2431                 for (i = 0; i < numbytes; i++)
2432                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2433
2434                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2435                                   (uint16_t)address, numbytes);
2436
2437                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2438                                8, 1, data, numbytes, false);
2439         } else
2440                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2441
2442         return ret;
2443 }
2444
2445 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2446                                                 uint8_t address,
2447                                                 uint8_t *data,
2448                                                 uint32_t numbytes)
2449 {
2450         uint32_t ret;
2451         SwI2cRequest_t req;
2452         struct amdgpu_device *adev = to_amdgpu_device(control);
2453
2454         if (numbytes > MAX_SW_I2C_COMMANDS) {
2455                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2456                         numbytes, MAX_SW_I2C_COMMANDS);
2457                 return -EINVAL;
2458         }
2459
2460         memset(&req, 0, sizeof(req));
2461         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2462
2463         mutex_lock(&adev->smu.mutex);
2464         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2465         mutex_unlock(&adev->smu.mutex);
2466
2467         if (!ret) {
2468                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2469                                          (uint16_t)address, numbytes);
2470
2471                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2472                                8, 1, data, numbytes, false);
2473                 /*
2474                  * According to EEPROM spec there is a MAX of 10 ms required for
2475                  * EEPROM to flush internal RX buffer after STOP was issued at the
2476                  * end of write transaction. During this time the EEPROM will not be
2477                  * responsive to any more commands - so wait a bit more.
2478                  */
2479                 msleep(10);
2480
2481         } else
2482                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2483
2484         return ret;
2485 }
2486
2487 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2488                               struct i2c_msg *msgs, int num)
2489 {
2490         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2491         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2492
2493         for (i = 0; i < num; i++) {
2494                 /*
2495                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2496                  * once and hence the data needs to be spliced into chunks and sent each
2497                  * chunk separately
2498                  */
2499                 data_size = msgs[i].len - 2;
2500                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2501                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2502                 data_ptr = msgs[i].buf + 2;
2503
2504                 for (j = 0; j < data_size / data_chunk_size; j++) {
2505                         /* Insert the EEPROM dest addess, bits 0-15 */
2506                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2507                         data_chunk[1] = (next_eeprom_addr & 0xff);
2508
2509                         if (msgs[i].flags & I2C_M_RD) {
2510                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2511                                                              (uint8_t)msgs[i].addr,
2512                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2513
2514                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2515                         } else {
2516
2517                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2518
2519                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2520                                                               (uint8_t)msgs[i].addr,
2521                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2522                         }
2523
2524                         if (ret) {
2525                                 num = -EIO;
2526                                 goto fail;
2527                         }
2528
2529                         next_eeprom_addr += data_chunk_size;
2530                         data_ptr += data_chunk_size;
2531                 }
2532
2533                 if (data_size % data_chunk_size) {
2534                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2535                         data_chunk[1] = (next_eeprom_addr & 0xff);
2536
2537                         if (msgs[i].flags & I2C_M_RD) {
2538                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2539                                                              (uint8_t)msgs[i].addr,
2540                                                              data_chunk, (data_size % data_chunk_size) + 2);
2541
2542                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2543                         } else {
2544                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2545
2546                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2547                                                               (uint8_t)msgs[i].addr,
2548                                                               data_chunk, (data_size % data_chunk_size) + 2);
2549                         }
2550
2551                         if (ret) {
2552                                 num = -EIO;
2553                                 goto fail;
2554                         }
2555                 }
2556         }
2557
2558 fail:
2559         return num;
2560 }
2561
2562 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2563 {
2564         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2565 }
2566
2567
2568 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2569         .master_xfer = sienna_cichlid_i2c_xfer,
2570         .functionality = sienna_cichlid_i2c_func,
2571 };
2572
2573 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2574 {
2575         struct amdgpu_device *adev = to_amdgpu_device(control);
2576         int res;
2577
2578         control->owner = THIS_MODULE;
2579         control->class = I2C_CLASS_SPD;
2580         control->dev.parent = &adev->pdev->dev;
2581         control->algo = &sienna_cichlid_i2c_algo;
2582         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2583
2584         res = i2c_add_adapter(control);
2585         if (res)
2586                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2587
2588         return res;
2589 }
2590
2591 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2592 {
2593         i2c_del_adapter(control);
2594 }
2595
2596 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2597                                               void **table)
2598 {
2599         struct smu_table_context *smu_table = &smu->smu_table;
2600         struct gpu_metrics_v1_0 *gpu_metrics =
2601                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2602         SmuMetricsExternal_t metrics_external;
2603         SmuMetrics_t *metrics =
2604                 &(metrics_external.SmuMetrics);
2605         int ret = 0;
2606
2607         ret = smu_cmn_get_metrics_table(smu,
2608                                         &metrics_external,
2609                                         true);
2610         if (ret)
2611                 return ret;
2612
2613         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2614
2615         gpu_metrics->temperature_edge = metrics->TemperatureEdge;
2616         gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
2617         gpu_metrics->temperature_mem = metrics->TemperatureMem;
2618         gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx;
2619         gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc;
2620         gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0;
2621
2622         gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2623         gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2624         gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage;
2625
2626         gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2627         gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2628
2629         if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2630                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2631         else
2632                 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2633         gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs;
2634         gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2635         gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2636         gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2637         gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2638
2639         gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2640         gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2641         gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2642         gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2643         gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2644         gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2645         gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2646
2647         gpu_metrics->throttle_status = metrics->ThrottlerStatus;
2648
2649         gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
2650
2651         gpu_metrics->pcie_link_width =
2652                         smu_v11_0_get_current_pcie_link_width(smu);
2653         gpu_metrics->pcie_link_speed =
2654                         smu_v11_0_get_current_pcie_link_speed(smu);
2655
2656         *table = (void *)gpu_metrics;
2657
2658         return sizeof(struct gpu_metrics_v1_0);
2659 }
2660
2661 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2662 {
2663         return smu_cmn_send_smc_msg_with_param(smu,
2664                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2665                                                0,
2666                                                NULL);
2667 }
2668
2669 static int sienna_cichlid_gpo_control(struct smu_context *smu,
2670                                       bool enablement)
2671 {
2672         uint32_t smu_version;
2673         int ret = 0;
2674
2675
2676         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2677                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2678                 if (ret)
2679                         return ret;
2680
2681                 if (enablement) {
2682                         if (smu_version < 0x003a2500) {
2683                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2684                                                                       SMU_MSG_SetGpoFeaturePMask,
2685                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2686                                                                       NULL);
2687                         } else {
2688                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2689                                                                       SMU_MSG_DisallowGpo,
2690                                                                       0,
2691                                                                       NULL);
2692                         }
2693                 } else {
2694                         if (smu_version < 0x003a2500) {
2695                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2696                                                                       SMU_MSG_SetGpoFeaturePMask,
2697                                                                       0,
2698                                                                       NULL);
2699                         } else {
2700                                 ret = smu_cmn_send_smc_msg_with_param(smu,
2701                                                                       SMU_MSG_DisallowGpo,
2702                                                                       1,
2703                                                                       NULL);
2704                         }
2705                 }
2706         }
2707
2708         return ret;
2709 }
2710
2711 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
2712 {
2713         uint32_t smu_version;
2714         int ret = 0;
2715
2716         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2717         if (ret)
2718                 return ret;
2719
2720         /*
2721          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
2722          * onwards PMFWs.
2723          */
2724         if (smu_version < 0x003A2D00)
2725                 return 0;
2726
2727         return smu_cmn_send_smc_msg_with_param(smu,
2728                                                SMU_MSG_Enable2ndUSB20Port,
2729                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
2730                                                1 : 0,
2731                                                NULL);
2732 }
2733
2734 static int sienna_cichlid_system_features_control(struct smu_context *smu,
2735                                                   bool en)
2736 {
2737         int ret = 0;
2738
2739         if (en) {
2740                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
2741                 if (ret)
2742                         return ret;
2743         }
2744
2745         return smu_v11_0_system_features_control(smu, en);
2746 }
2747
2748 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2749         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2750         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2751         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2752         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2753         .i2c_init = sienna_cichlid_i2c_control_init,
2754         .i2c_fini = sienna_cichlid_i2c_control_fini,
2755         .print_clk_levels = sienna_cichlid_print_clk_levels,
2756         .force_clk_levels = sienna_cichlid_force_clk_levels,
2757         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2758         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2759         .display_config_changed = sienna_cichlid_display_config_changed,
2760         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2761         .is_dpm_running = sienna_cichlid_is_dpm_running,
2762         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2763         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2764         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2765         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2766         .read_sensor = sienna_cichlid_read_sensor,
2767         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2768         .set_performance_level = smu_v11_0_set_performance_level,
2769         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2770         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2771         .get_power_limit = sienna_cichlid_get_power_limit,
2772         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2773         .dump_pptable = sienna_cichlid_dump_pptable,
2774         .init_microcode = smu_v11_0_init_microcode,
2775         .load_microcode = smu_v11_0_load_microcode,
2776         .init_smc_tables = sienna_cichlid_init_smc_tables,
2777         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2778         .init_power = smu_v11_0_init_power,
2779         .fini_power = smu_v11_0_fini_power,
2780         .check_fw_status = smu_v11_0_check_fw_status,
2781         .setup_pptable = sienna_cichlid_setup_pptable,
2782         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2783         .check_fw_version = smu_v11_0_check_fw_version,
2784         .write_pptable = smu_cmn_write_pptable,
2785         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2786         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2787         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2788         .system_features_control = sienna_cichlid_system_features_control,
2789         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2790         .send_smc_msg = smu_cmn_send_smc_msg,
2791         .init_display_count = NULL,
2792         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2793         .get_enabled_mask = smu_cmn_get_enabled_mask,
2794         .feature_is_enabled = smu_cmn_feature_is_enabled,
2795         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2796         .notify_display_change = NULL,
2797         .set_power_limit = smu_v11_0_set_power_limit,
2798         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2799         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2800         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2801         .set_min_dcef_deep_sleep = NULL,
2802         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2803         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2804         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2805         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2806         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2807         .gfx_off_control = smu_v11_0_gfx_off_control,
2808         .register_irq_handler = smu_v11_0_register_irq_handler,
2809         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2810         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2811         .baco_is_support= sienna_cichlid_is_baco_supported,
2812         .baco_get_state = smu_v11_0_baco_get_state,
2813         .baco_set_state = smu_v11_0_baco_set_state,
2814         .baco_enter = smu_v11_0_baco_enter,
2815         .baco_exit = smu_v11_0_baco_exit,
2816         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2817         .mode1_reset = smu_v11_0_mode1_reset,
2818         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2819         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2820         .run_btc = sienna_cichlid_run_btc,
2821         .set_power_source = smu_v11_0_set_power_source,
2822         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2823         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2824         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2825         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2826         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2827         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2828         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2829         .interrupt_work = smu_v11_0_interrupt_work,
2830         .gpo_control = sienna_cichlid_gpo_control,
2831 };
2832
2833 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2834 {
2835         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2836         smu->message_map = sienna_cichlid_message_map;
2837         smu->clock_map = sienna_cichlid_clk_map;
2838         smu->feature_map = sienna_cichlid_feature_mask_map;
2839         smu->table_map = sienna_cichlid_table_map;
2840         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2841         smu->workload_map = sienna_cichlid_workload_map;
2842 }