drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member) do {\
  77         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
  78                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79         else\
  80                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81 } while(0)
  82
  83 /* STB FIFO depth is in 64bit units */
  84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
  85
  86 static int get_table_size(struct smu_context *smu)
  87 {
  88         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
  89                 return sizeof(PPTable_beige_goby_t);
  90         else
  91                 return sizeof(PPTable_t);
  92 }
  93
  94 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  95         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  96         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  97         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  98         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  99         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 100         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 101         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 102         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 103         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 104         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 105         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 106         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 107         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 108         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 109         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 110         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 111         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 112         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 113         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 114         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 115         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 116         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 117         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 118         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 119         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 120         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 121         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 122         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 123         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 124         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 125         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 126         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 127         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 128         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 129         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 130         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 131         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 132         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 133         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 134         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 135         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 136         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 137         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 138         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 139         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 140         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 141         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 142         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 143         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 144         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 145         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 146         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 147         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 148         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 149         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 150         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 151 };
 152
 153 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 154         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 155         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 156         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 157         CLK_MAP(FCLK,           PPCLK_FCLK),
 158         CLK_MAP(UCLK,           PPCLK_UCLK),
 159         CLK_MAP(MCLK,           PPCLK_UCLK),
 160         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 161         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 162         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 163         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 164         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 165         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 166         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 167         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 168 };
 169
 170 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 171         FEA_MAP(DPM_PREFETCHER),
 172         FEA_MAP(DPM_GFXCLK),
 173         FEA_MAP(DPM_GFX_GPO),
 174         FEA_MAP(DPM_UCLK),
 175         FEA_MAP(DPM_FCLK),
 176         FEA_MAP(DPM_SOCCLK),
 177         FEA_MAP(DPM_MP0CLK),
 178         FEA_MAP(DPM_LINK),
 179         FEA_MAP(DPM_DCEFCLK),
 180         FEA_MAP(DPM_XGMI),
 181         FEA_MAP(MEM_VDDCI_SCALING),
 182         FEA_MAP(MEM_MVDD_SCALING),
 183         FEA_MAP(DS_GFXCLK),
 184         FEA_MAP(DS_SOCCLK),
 185         FEA_MAP(DS_FCLK),
 186         FEA_MAP(DS_LCLK),
 187         FEA_MAP(DS_DCEFCLK),
 188         FEA_MAP(DS_UCLK),
 189         FEA_MAP(GFX_ULV),
 190         FEA_MAP(FW_DSTATE),
 191         FEA_MAP(GFXOFF),
 192         FEA_MAP(BACO),
 193         FEA_MAP(MM_DPM_PG),
 194         FEA_MAP(RSMU_SMN_CG),
 195         FEA_MAP(PPT),
 196         FEA_MAP(TDC),
 197         FEA_MAP(APCC_PLUS),
 198         FEA_MAP(GTHR),
 199         FEA_MAP(ACDC),
 200         FEA_MAP(VR0HOT),
 201         FEA_MAP(VR1HOT),
 202         FEA_MAP(FW_CTF),
 203         FEA_MAP(FAN_CONTROL),
 204         FEA_MAP(THERMAL),
 205         FEA_MAP(GFX_DCS),
 206         FEA_MAP(RM),
 207         FEA_MAP(LED_DISPLAY),
 208         FEA_MAP(GFX_SS),
 209         FEA_MAP(OUT_OF_BAND_MONITOR),
 210         FEA_MAP(TEMP_DEPENDENT_VMIN),
 211         FEA_MAP(MMHUB_PG),
 212         FEA_MAP(ATHUB_PG),
 213         FEA_MAP(APCC_DFLL),
 214 };
 215
 216 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 217         TAB_MAP(PPTABLE),
 218         TAB_MAP(WATERMARKS),
 219         TAB_MAP(AVFS_PSM_DEBUG),
 220         TAB_MAP(AVFS_FUSE_OVERRIDE),
 221         TAB_MAP(PMSTATUSLOG),
 222         TAB_MAP(SMU_METRICS),
 223         TAB_MAP(DRIVER_SMU_CONFIG),
 224         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 225         TAB_MAP(OVERDRIVE),
 226         TAB_MAP(I2C_COMMANDS),
 227         TAB_MAP(PACE),
 228 };
 229
 230 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 231         PWR_MAP(AC),
 232         PWR_MAP(DC),
 233 };
 234
 235 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 236         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 237         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 238         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 239         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 240         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 241         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 242         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 243 };
 244
 245 static const uint8_t sienna_cichlid_throttler_map[] = {
 246         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 247         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 248         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 249         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 250         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 251         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 252         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 253         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 254         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 255         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 256         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 257         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 258         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 259         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 260         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 261         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 262         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 263         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 264 };
 265
 266 static int
 267 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 268                                   uint32_t *feature_mask, uint32_t num)
 269 {
 270         struct amdgpu_device *adev = smu->adev;
 271
 272         if (num > 2)
 273                 return -EINVAL;
 274
 275         memset(feature_mask, 0, sizeof(uint32_t) * num);
 276
 277         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 278                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 279                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 280                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 281                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 282                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 283                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 284                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 285                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 286                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 287                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 288                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 289                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 290                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 291                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 292                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 293                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 294                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 295                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 296                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 297
 298         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 299                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 300                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 301         }
 302
 303         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 304             (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
 305             !(adev->flags & AMD_IS_APU))
 306                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 307
 308         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 309                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 310                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 311                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 312
 313         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 315
 316         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 318
 319         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 321
 322         if (adev->pm.pp_feature & PP_ULV_MASK)
 323                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 324
 325         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 327
 328         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 330
 331         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 333
 334         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 335                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 336
 337         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 338             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 339                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 340
 341         if (smu->dc_controlled_by_gpio)
 342        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 343
 344         if (amdgpu_aspm)
 345                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 346
 347         return 0;
 348 }
 349
 350 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 351 {
 352         struct smu_table_context *table_context = &smu->smu_table;
 353         struct smu_11_0_7_powerplay_table *powerplay_table =
 354                 table_context->power_play_table;
 355         struct smu_baco_context *smu_baco = &smu->smu_baco;
 356         struct amdgpu_device *adev = smu->adev;
 357         uint32_t val;
 358
 359         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 360                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 361                 smu_baco->platform_support =
 362                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 363                                                                         false;
 364         }
 365 }
 366
 367 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 368 {
 369         struct smu_table_context *table_context = &smu->smu_table;
 370         struct smu_11_0_7_powerplay_table *powerplay_table =
 371                 table_context->power_play_table;
 372
 373         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 374                 smu->dc_controlled_by_gpio = true;
 375
 376         sienna_cichlid_check_bxco_support(smu);
 377
 378         table_context->thermal_controller_type =
 379                 powerplay_table->thermal_controller_type;
 380
 381         /*
 382          * Instead of having its own buffer space and get overdrive_table copied,
 383          * smu->od_settings just points to the actual overdrive_table
 384          */
 385         smu->od_settings = &powerplay_table->overdrive_table;
 386
 387         return 0;
 388 }
 389
 390 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 391 {
 392         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 393         int index, ret;
 394         I2cControllerConfig_t *table_member;
 395
 396         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 397                                             smc_dpm_info);
 398
 399         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 400                                       (uint8_t **)&smc_dpm_table);
 401         if (ret)
 402                 return ret;
 403         GET_PPTABLE_MEMBER(I2cControllers, &table_member);
 404         memcpy(table_member, smc_dpm_table->I2cControllers,
 405                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 406
 407         return 0;
 408 }
 409
 410 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 411 {
 412         struct smu_table_context *table_context = &smu->smu_table;
 413         struct smu_11_0_7_powerplay_table *powerplay_table =
 414                 table_context->power_play_table;
 415         int table_size;
 416
 417         table_size = get_table_size(smu);
 418         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 419                table_size);
 420
 421         return 0;
 422 }
 423
 424 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 425 {
 426         int ret = 0;
 427
 428         ret = smu_v11_0_setup_pptable(smu);
 429         if (ret)
 430                 return ret;
 431
 432         ret = sienna_cichlid_store_powerplay_table(smu);
 433         if (ret)
 434                 return ret;
 435
 436         ret = sienna_cichlid_append_powerplay_table(smu);
 437         if (ret)
 438                 return ret;
 439
 440         ret = sienna_cichlid_check_powerplay_table(smu);
 441         if (ret)
 442                 return ret;
 443
 444         return ret;
 445 }
 446
 447 static int sienna_cichlid_tables_init(struct smu_context *smu)
 448 {
 449         struct smu_table_context *smu_table = &smu->smu_table;
 450         struct smu_table *tables = smu_table->tables;
 451         int table_size;
 452
 453         table_size = get_table_size(smu);
 454         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 455                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 456         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 457                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 458         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 459                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 460         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 461                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 462         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 463                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 464         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 465                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 466         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 467                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 468                        AMDGPU_GEM_DOMAIN_VRAM);
 469
 470         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 471         if (!smu_table->metrics_table)
 472                 goto err0_out;
 473         smu_table->metrics_time = 0;
 474
 475         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 476         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 477         if (!smu_table->gpu_metrics_table)
 478                 goto err1_out;
 479
 480         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 481         if (!smu_table->watermarks_table)
 482                 goto err2_out;
 483
 484         return 0;
 485
 486 err2_out:
 487         kfree(smu_table->gpu_metrics_table);
 488 err1_out:
 489         kfree(smu_table->metrics_table);
 490 err0_out:
 491         return -ENOMEM;
 492 }
 493
 494 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
 495 {
 496         struct smu_table_context *smu_table= &smu->smu_table;
 497         SmuMetricsExternal_t *metrics_ext =
 498                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 499         uint32_t throttler_status = 0;
 500         int i;
 501
 502         if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 503              (smu->smc_fw_version >= 0x3A4300)) {
 504                 for (i = 0; i < THROTTLER_COUNT; i++)
 505                         throttler_status |=
 506                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 507         } else {
 508                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 509         }
 510
 511         return throttler_status;
 512 }
 513
 514 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 515                                                MetricsMember_t member,
 516                                                uint32_t *value)
 517 {
 518         struct smu_table_context *smu_table= &smu->smu_table;
 519         SmuMetrics_t *metrics =
 520                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 521         SmuMetrics_V2_t *metrics_v2 =
 522                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 523         bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 524                 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
 525         uint16_t average_gfx_activity;
 526         int ret = 0;
 527
 528         mutex_lock(&smu->metrics_lock);
 529
 530         ret = smu_cmn_get_metrics_table_locked(smu,
 531                                                NULL,
 532                                                false);
 533         if (ret) {
 534                 mutex_unlock(&smu->metrics_lock);
 535                 return ret;
 536         }
 537
 538         switch (member) {
 539         case METRICS_CURR_GFXCLK:
 540                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 541                         metrics->CurrClock[PPCLK_GFXCLK];
 542                 break;
 543         case METRICS_CURR_SOCCLK:
 544                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 545                         metrics->CurrClock[PPCLK_SOCCLK];
 546                 break;
 547         case METRICS_CURR_UCLK:
 548                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 549                         metrics->CurrClock[PPCLK_UCLK];
 550                 break;
 551         case METRICS_CURR_VCLK:
 552                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 553                         metrics->CurrClock[PPCLK_VCLK_0];
 554                 break;
 555         case METRICS_CURR_VCLK1:
 556                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 557                         metrics->CurrClock[PPCLK_VCLK_1];
 558                 break;
 559         case METRICS_CURR_DCLK:
 560                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 561                         metrics->CurrClock[PPCLK_DCLK_0];
 562                 break;
 563         case METRICS_CURR_DCLK1:
 564                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 565                         metrics->CurrClock[PPCLK_DCLK_1];
 566                 break;
 567         case METRICS_CURR_DCEFCLK:
 568                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 569                         metrics->CurrClock[PPCLK_DCEFCLK];
 570                 break;
 571         case METRICS_CURR_FCLK:
 572                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 573                         metrics->CurrClock[PPCLK_FCLK];
 574                 break;
 575         case METRICS_AVERAGE_GFXCLK:
 576                 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 577                         metrics->AverageGfxActivity;
 578                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 579                         *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 580                                 metrics->AverageGfxclkFrequencyPostDs;
 581                 else
 582                         *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 583                                 metrics->AverageGfxclkFrequencyPreDs;
 584                 break;
 585         case METRICS_AVERAGE_FCLK:
 586                 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 587                         metrics->AverageFclkFrequencyPostDs;
 588                 break;
 589         case METRICS_AVERAGE_UCLK:
 590                 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 591                         metrics->AverageUclkFrequencyPostDs;
 592                 break;
 593         case METRICS_AVERAGE_GFXACTIVITY:
 594                 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 595                         metrics->AverageGfxActivity;
 596                 break;
 597         case METRICS_AVERAGE_MEMACTIVITY:
 598                 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 599                         metrics->AverageUclkActivity;
 600                 break;
 601         case METRICS_AVERAGE_SOCKETPOWER:
 602                 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 603                         metrics->AverageSocketPower << 8;
 604                 break;
 605         case METRICS_TEMPERATURE_EDGE:
 606                 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
 607                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 608                 break;
 609         case METRICS_TEMPERATURE_HOTSPOT:
 610                 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
 611                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 612                 break;
 613         case METRICS_TEMPERATURE_MEM:
 614                 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
 615                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 616                 break;
 617         case METRICS_TEMPERATURE_VRGFX:
 618                 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
 619                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 620                 break;
 621         case METRICS_TEMPERATURE_VRSOC:
 622                 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
 623                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 624                 break;
 625         case METRICS_THROTTLER_STATUS:
 626                 *value = sienna_cichlid_get_throttler_status_locked(smu);
 627                 break;
 628         case METRICS_CURR_FANSPEED:
 629                 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 630                 break;
 631         default:
 632                 *value = UINT_MAX;
 633                 break;
 634         }
 635
 636         mutex_unlock(&smu->metrics_lock);
 637
 638         return ret;
 639
 640 }
 641
 642 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 643 {
 644         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 645
 646         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 647                                        GFP_KERNEL);
 648         if (!smu_dpm->dpm_context)
 649                 return -ENOMEM;
 650
 651         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 652
 653         return 0;
 654 }
 655
 656 static void sienna_cichlid_stb_init(struct smu_context *smu);
 657
 658 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 659 {
 660         int ret = 0;
 661
 662         ret = sienna_cichlid_tables_init(smu);
 663         if (ret)
 664                 return ret;
 665
 666         ret = sienna_cichlid_allocate_dpm_context(smu);
 667         if (ret)
 668                 return ret;
 669
 670         sienna_cichlid_stb_init(smu);
 671
 672         return smu_v11_0_init_smc_tables(smu);
 673 }
 674
 675 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 676 {
 677         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 678         struct smu_11_0_dpm_table *dpm_table;
 679         struct amdgpu_device *adev = smu->adev;
 680         int i, ret = 0;
 681         DpmDescriptor_t *table_member;
 682
 683         /* socclk dpm table setup */
 684         dpm_table = &dpm_context->dpm_tables.soc_table;
 685         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 686         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 687                 ret = smu_v11_0_set_single_dpm_table(smu,
 688                                                      SMU_SOCCLK,
 689                                                      dpm_table);
 690                 if (ret)
 691                         return ret;
 692                 dpm_table->is_fine_grained =
 693                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 694         } else {
 695                 dpm_table->count = 1;
 696                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 697                 dpm_table->dpm_levels[0].enabled = true;
 698                 dpm_table->min = dpm_table->dpm_levels[0].value;
 699                 dpm_table->max = dpm_table->dpm_levels[0].value;
 700         }
 701
 702         /* gfxclk dpm table setup */
 703         dpm_table = &dpm_context->dpm_tables.gfx_table;
 704         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 705                 ret = smu_v11_0_set_single_dpm_table(smu,
 706                                                      SMU_GFXCLK,
 707                                                      dpm_table);
 708                 if (ret)
 709                         return ret;
 710                 dpm_table->is_fine_grained =
 711                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 712         } else {
 713                 dpm_table->count = 1;
 714                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 715                 dpm_table->dpm_levels[0].enabled = true;
 716                 dpm_table->min = dpm_table->dpm_levels[0].value;
 717                 dpm_table->max = dpm_table->dpm_levels[0].value;
 718         }
 719
 720         /* uclk dpm table setup */
 721         dpm_table = &dpm_context->dpm_tables.uclk_table;
 722         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 723                 ret = smu_v11_0_set_single_dpm_table(smu,
 724                                                      SMU_UCLK,
 725                                                      dpm_table);
 726                 if (ret)
 727                         return ret;
 728                 dpm_table->is_fine_grained =
 729                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 730         } else {
 731                 dpm_table->count = 1;
 732                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 733                 dpm_table->dpm_levels[0].enabled = true;
 734                 dpm_table->min = dpm_table->dpm_levels[0].value;
 735                 dpm_table->max = dpm_table->dpm_levels[0].value;
 736         }
 737
 738         /* fclk dpm table setup */
 739         dpm_table = &dpm_context->dpm_tables.fclk_table;
 740         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 741                 ret = smu_v11_0_set_single_dpm_table(smu,
 742                                                      SMU_FCLK,
 743                                                      dpm_table);
 744                 if (ret)
 745                         return ret;
 746                 dpm_table->is_fine_grained =
 747                         !table_member[PPCLK_FCLK].SnapToDiscrete;
 748         } else {
 749                 dpm_table->count = 1;
 750                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 751                 dpm_table->dpm_levels[0].enabled = true;
 752                 dpm_table->min = dpm_table->dpm_levels[0].value;
 753                 dpm_table->max = dpm_table->dpm_levels[0].value;
 754         }
 755
 756         /* vclk0/1 dpm table setup */
 757         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 758                 if (adev->vcn.harvest_config & (1 << i))
 759                         continue;
 760
 761                 dpm_table = &dpm_context->dpm_tables.vclk_table;
 762                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 763                         ret = smu_v11_0_set_single_dpm_table(smu,
 764                                                              i ? SMU_VCLK1 : SMU_VCLK,
 765                                                              dpm_table);
 766                         if (ret)
 767                                 return ret;
 768                         dpm_table->is_fine_grained =
 769                                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
 770                 } else {
 771                         dpm_table->count = 1;
 772                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 773                         dpm_table->dpm_levels[0].enabled = true;
 774                         dpm_table->min = dpm_table->dpm_levels[0].value;
 775                         dpm_table->max = dpm_table->dpm_levels[0].value;
 776                 }
 777         }
 778
 779         /* dclk0/1 dpm table setup */
 780         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 781                 if (adev->vcn.harvest_config & (1 << i))
 782                         continue;
 783                 dpm_table = &dpm_context->dpm_tables.dclk_table;
 784                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 785                         ret = smu_v11_0_set_single_dpm_table(smu,
 786                                                              i ? SMU_DCLK1 : SMU_DCLK,
 787                                                              dpm_table);
 788                         if (ret)
 789                                 return ret;
 790                         dpm_table->is_fine_grained =
 791                                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
 792                 } else {
 793                         dpm_table->count = 1;
 794                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 795                         dpm_table->dpm_levels[0].enabled = true;
 796                         dpm_table->min = dpm_table->dpm_levels[0].value;
 797                         dpm_table->max = dpm_table->dpm_levels[0].value;
 798                 }
 799         }
 800
 801         /* dcefclk dpm table setup */
 802         dpm_table = &dpm_context->dpm_tables.dcef_table;
 803         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 804                 ret = smu_v11_0_set_single_dpm_table(smu,
 805                                                      SMU_DCEFCLK,
 806                                                      dpm_table);
 807                 if (ret)
 808                         return ret;
 809                 dpm_table->is_fine_grained =
 810                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
 811         } else {
 812                 dpm_table->count = 1;
 813                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 814                 dpm_table->dpm_levels[0].enabled = true;
 815                 dpm_table->min = dpm_table->dpm_levels[0].value;
 816                 dpm_table->max = dpm_table->dpm_levels[0].value;
 817         }
 818
 819         /* pixelclk dpm table setup */
 820         dpm_table = &dpm_context->dpm_tables.pixel_table;
 821         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 822                 ret = smu_v11_0_set_single_dpm_table(smu,
 823                                                      SMU_PIXCLK,
 824                                                      dpm_table);
 825                 if (ret)
 826                         return ret;
 827                 dpm_table->is_fine_grained =
 828                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
 829         } else {
 830                 dpm_table->count = 1;
 831                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 832                 dpm_table->dpm_levels[0].enabled = true;
 833                 dpm_table->min = dpm_table->dpm_levels[0].value;
 834                 dpm_table->max = dpm_table->dpm_levels[0].value;
 835         }
 836
 837         /* displayclk dpm table setup */
 838         dpm_table = &dpm_context->dpm_tables.display_table;
 839         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 840                 ret = smu_v11_0_set_single_dpm_table(smu,
 841                                                      SMU_DISPCLK,
 842                                                      dpm_table);
 843                 if (ret)
 844                         return ret;
 845                 dpm_table->is_fine_grained =
 846                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
 847         } else {
 848                 dpm_table->count = 1;
 849                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 850                 dpm_table->dpm_levels[0].enabled = true;
 851                 dpm_table->min = dpm_table->dpm_levels[0].value;
 852                 dpm_table->max = dpm_table->dpm_levels[0].value;
 853         }
 854
 855         /* phyclk dpm table setup */
 856         dpm_table = &dpm_context->dpm_tables.phy_table;
 857         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 858                 ret = smu_v11_0_set_single_dpm_table(smu,
 859                                                      SMU_PHYCLK,
 860                                                      dpm_table);
 861                 if (ret)
 862                         return ret;
 863                 dpm_table->is_fine_grained =
 864                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
 865         } else {
 866                 dpm_table->count = 1;
 867                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 868                 dpm_table->dpm_levels[0].enabled = true;
 869                 dpm_table->min = dpm_table->dpm_levels[0].value;
 870                 dpm_table->max = dpm_table->dpm_levels[0].value;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 877 {
 878         struct amdgpu_device *adev = smu->adev;
 879         int i, ret = 0;
 880
 881         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 882                 if (adev->vcn.harvest_config & (1 << i))
 883                         continue;
 884                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 885                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 886                         ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
 887                                                               SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
 888                                                               0x10000 * i, NULL);
 889                         if (ret)
 890                                 return ret;
 891                 }
 892         }
 893
 894         return ret;
 895 }
 896
 897 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 898 {
 899         int ret = 0;
 900
 901         if (enable) {
 902                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 903                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 904                         if (ret)
 905                                 return ret;
 906                 }
 907         } else {
 908                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 909                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 910                         if (ret)
 911                                 return ret;
 912                 }
 913         }
 914
 915         return ret;
 916 }
 917
 918 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 919                                        enum smu_clk_type clk_type,
 920                                        uint32_t *value)
 921 {
 922         MetricsMember_t member_type;
 923         int clk_id = 0;
 924
 925         clk_id = smu_cmn_to_asic_specific_index(smu,
 926                                                 CMN2ASIC_MAPPING_CLK,
 927                                                 clk_type);
 928         if (clk_id < 0)
 929                 return clk_id;
 930
 931         switch (clk_id) {
 932         case PPCLK_GFXCLK:
 933                 member_type = METRICS_CURR_GFXCLK;
 934                 break;
 935         case PPCLK_UCLK:
 936                 member_type = METRICS_CURR_UCLK;
 937                 break;
 938         case PPCLK_SOCCLK:
 939                 member_type = METRICS_CURR_SOCCLK;
 940                 break;
 941         case PPCLK_FCLK:
 942                 member_type = METRICS_CURR_FCLK;
 943                 break;
 944         case PPCLK_VCLK_0:
 945                 member_type = METRICS_CURR_VCLK;
 946                 break;
 947         case PPCLK_VCLK_1:
 948                 member_type = METRICS_CURR_VCLK1;
 949                 break;
 950         case PPCLK_DCLK_0:
 951                 member_type = METRICS_CURR_DCLK;
 952                 break;
 953         case PPCLK_DCLK_1:
 954                 member_type = METRICS_CURR_DCLK1;
 955                 break;
 956         case PPCLK_DCEFCLK:
 957                 member_type = METRICS_CURR_DCEFCLK;
 958                 break;
 959         default:
 960                 return -EINVAL;
 961         }
 962
 963         return sienna_cichlid_get_smu_metrics_data(smu,
 964                                                    member_type,
 965                                                    value);
 966
 967 }
 968
 969 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 970 {
 971         DpmDescriptor_t *dpm_desc = NULL;
 972         DpmDescriptor_t *table_member;
 973         uint32_t clk_index = 0;
 974
 975         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 976         clk_index = smu_cmn_to_asic_specific_index(smu,
 977                                                    CMN2ASIC_MAPPING_CLK,
 978                                                    clk_type);
 979         dpm_desc = &table_member[clk_index];
 980
 981         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 982         return dpm_desc->SnapToDiscrete == 0;
 983 }
 984
 985 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
 986                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
 987 {
 988         return od_table->cap[cap];
 989 }
 990
 991 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
 992                                                 enum SMU_11_0_7_ODSETTING_ID setting,
 993                                                 uint32_t *min, uint32_t *max)
 994 {
 995         if (min)
 996                 *min = od_table->min[setting];
 997         if (max)
 998                 *max = od_table->max[setting];
 999 }
1000
1001 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1002                         enum smu_clk_type clk_type, char *buf)
1003 {
1004         struct amdgpu_device *adev = smu->adev;
1005         struct smu_table_context *table_context = &smu->smu_table;
1006         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1007         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1008         uint16_t *table_member;
1009
1010         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1011         OverDriveTable_t *od_table =
1012                 (OverDriveTable_t *)table_context->overdrive_table;
1013         int i, size = 0, ret = 0;
1014         uint32_t cur_value = 0, value = 0, count = 0;
1015         uint32_t freq_values[3] = {0};
1016         uint32_t mark_index = 0;
1017         uint32_t gen_speed, lane_width;
1018         uint32_t min_value, max_value;
1019         uint32_t smu_version;
1020
1021         smu_cmn_get_sysfs_buf(&buf, &size);
1022
1023         switch (clk_type) {
1024         case SMU_GFXCLK:
1025         case SMU_SCLK:
1026         case SMU_SOCCLK:
1027         case SMU_MCLK:
1028         case SMU_UCLK:
1029         case SMU_FCLK:
1030         case SMU_VCLK:
1031         case SMU_VCLK1:
1032         case SMU_DCLK:
1033         case SMU_DCLK1:
1034         case SMU_DCEFCLK:
1035                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1036                 if (ret)
1037                         goto print_clk_out;
1038
1039                 /* no need to disable gfxoff when retrieving the current gfxclk */
1040                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1041                         amdgpu_gfx_off_ctrl(adev, false);
1042
1043                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1044                 if (ret)
1045                         goto print_clk_out;
1046
1047                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1048                         for (i = 0; i < count; i++) {
1049                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1050                                 if (ret)
1051                                         goto print_clk_out;
1052
1053                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1054                                                 cur_value == value ? "*" : "");
1055                         }
1056                 } else {
1057                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1058                         if (ret)
1059                                 goto print_clk_out;
1060                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1061                         if (ret)
1062                                 goto print_clk_out;
1063
1064                         freq_values[1] = cur_value;
1065                         mark_index = cur_value == freq_values[0] ? 0 :
1066                                      cur_value == freq_values[2] ? 2 : 1;
1067
1068                         count = 3;
1069                         if (mark_index != 1) {
1070                                 count = 2;
1071                                 freq_values[1] = freq_values[2];
1072                         }
1073
1074                         for (i = 0; i < count; i++) {
1075                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1076                                                 cur_value  == freq_values[i] ? "*" : "");
1077                         }
1078
1079                 }
1080                 break;
1081         case SMU_PCIE:
1082                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1083                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1084                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1085                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1086                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1087                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1088                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1089                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1090                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1091                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1092                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1093                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1094                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1095                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1096                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1097                                         table_member[i],
1098                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1099                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1100                                         "*" : "");
1101                 break;
1102         case SMU_OD_SCLK:
1103                 if (!smu->od_enabled || !od_table || !od_settings)
1104                         break;
1105
1106                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1107                         break;
1108
1109                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1110                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1111                 break;
1112
1113         case SMU_OD_MCLK:
1114                 if (!smu->od_enabled || !od_table || !od_settings)
1115                         break;
1116
1117                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1118                         break;
1119
1120                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1121                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1122                 break;
1123
1124         case SMU_OD_VDDGFX_OFFSET:
1125                 if (!smu->od_enabled || !od_table || !od_settings)
1126                         break;
1127
1128                 /*
1129                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1130                  * and onwards SMU firmwares.
1131                  */
1132                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1133                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1134                      (smu_version < 0x003a2900))
1135                         break;
1136
1137                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1138                 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1139                 break;
1140
1141         case SMU_OD_RANGE:
1142                 if (!smu->od_enabled || !od_table || !od_settings)
1143                         break;
1144
1145                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1146
1147                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1148                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1149                                                             &min_value, NULL);
1150                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1151                                                             NULL, &max_value);
1152                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1153                                         min_value, max_value);
1154                 }
1155
1156                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1157                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1158                                                             &min_value, NULL);
1159                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1160                                                             NULL, &max_value);
1161                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1162                                         min_value, max_value);
1163                 }
1164                 break;
1165
1166         default:
1167                 break;
1168         }
1169
1170 print_clk_out:
1171         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1172                 amdgpu_gfx_off_ctrl(adev, true);
1173
1174         return size;
1175 }
1176
1177 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1178                                    enum smu_clk_type clk_type, uint32_t mask)
1179 {
1180         struct amdgpu_device *adev = smu->adev;
1181         int ret = 0;
1182         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1183
1184         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1185         soft_max_level = mask ? (fls(mask) - 1) : 0;
1186
1187         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1188                 amdgpu_gfx_off_ctrl(adev, false);
1189
1190         switch (clk_type) {
1191         case SMU_GFXCLK:
1192         case SMU_SCLK:
1193         case SMU_SOCCLK:
1194         case SMU_MCLK:
1195         case SMU_UCLK:
1196         case SMU_FCLK:
1197                 /* There is only 2 levels for fine grained DPM */
1198                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1199                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1200                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1201                 }
1202
1203                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1204                 if (ret)
1205                         goto forec_level_out;
1206
1207                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1208                 if (ret)
1209                         goto forec_level_out;
1210
1211                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1212                 if (ret)
1213                         goto forec_level_out;
1214                 break;
1215         case SMU_DCEFCLK:
1216                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1217                 break;
1218         default:
1219                 break;
1220         }
1221
1222 forec_level_out:
1223         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1224                 amdgpu_gfx_off_ctrl(adev, true);
1225
1226         return 0;
1227 }
1228
1229 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1230 {
1231         struct smu_11_0_dpm_context *dpm_context =
1232                                 smu->smu_dpm.dpm_context;
1233         struct smu_11_0_dpm_table *gfx_table =
1234                                 &dpm_context->dpm_tables.gfx_table;
1235         struct smu_11_0_dpm_table *mem_table =
1236                                 &dpm_context->dpm_tables.uclk_table;
1237         struct smu_11_0_dpm_table *soc_table =
1238                                 &dpm_context->dpm_tables.soc_table;
1239         struct smu_umd_pstate_table *pstate_table =
1240                                 &smu->pstate_table;
1241
1242         pstate_table->gfxclk_pstate.min = gfx_table->min;
1243         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1244         if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1245                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1246
1247         pstate_table->uclk_pstate.min = mem_table->min;
1248         pstate_table->uclk_pstate.peak = mem_table->max;
1249         if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1250                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1251
1252         pstate_table->socclk_pstate.min = soc_table->min;
1253         pstate_table->socclk_pstate.peak = soc_table->max;
1254         if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1255                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1256
1257         return 0;
1258 }
1259
1260 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1261 {
1262         int ret = 0;
1263         uint32_t max_freq = 0;
1264
1265         /* Sienna_Cichlid do not support to change display num currently */
1266         return 0;
1267 #if 0
1268         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1269         if (ret)
1270                 return ret;
1271 #endif
1272
1273         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1274                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1275                 if (ret)
1276                         return ret;
1277                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1278                 if (ret)
1279                         return ret;
1280         }
1281
1282         return ret;
1283 }
1284
1285 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1286 {
1287         int ret = 0;
1288
1289         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1290             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1291             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1292 #if 0
1293                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1294                                                   smu->display_config->num_display,
1295                                                   NULL);
1296 #endif
1297                 if (ret)
1298                         return ret;
1299         }
1300
1301         return ret;
1302 }
1303
1304 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1305 {
1306         int ret = 0;
1307         uint32_t feature_mask[2];
1308         uint64_t feature_enabled;
1309
1310         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1311         if (ret)
1312                 return false;
1313
1314         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1315
1316         return !!(feature_enabled & SMC_DPM_FEATURE);
1317 }
1318
1319 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1320                                             uint32_t *speed)
1321 {
1322         if (!speed)
1323                 return -EINVAL;
1324
1325         /*
1326          * For Sienna_Cichlid and later, the fan speed(rpm) reported
1327          * by pmfw is always trustable(even when the fan control feature
1328          * disabled or 0 RPM kicked in).
1329          */
1330         return sienna_cichlid_get_smu_metrics_data(smu,
1331                                                    METRICS_CURR_FANSPEED,
1332                                                    speed);
1333 }
1334
1335 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1336 {
1337         uint16_t *table_member;
1338
1339         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1340         smu->fan_max_rpm = *table_member;
1341
1342         return 0;
1343 }
1344
1345 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1346 {
1347         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1348         DpmActivityMonitorCoeffInt_t *activity_monitor =
1349                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1350         uint32_t i, size = 0;
1351         int16_t workload_type = 0;
1352         static const char *title[] = {
1353                         "PROFILE_INDEX(NAME)",
1354                         "CLOCK_TYPE(NAME)",
1355                         "FPS",
1356                         "MinFreqType",
1357                         "MinActiveFreqType",
1358                         "MinActiveFreq",
1359                         "BoosterFreqType",
1360                         "BoosterFreq",
1361                         "PD_Data_limit_c",
1362                         "PD_Data_error_coeff",
1363                         "PD_Data_error_rate_coeff"};
1364         int result = 0;
1365
1366         if (!buf)
1367                 return -EINVAL;
1368
1369         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1370                         title[0], title[1], title[2], title[3], title[4], title[5],
1371                         title[6], title[7], title[8], title[9], title[10]);
1372
1373         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1374                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1375                 workload_type = smu_cmn_to_asic_specific_index(smu,
1376                                                                CMN2ASIC_MAPPING_WORKLOAD,
1377                                                                i);
1378                 if (workload_type < 0)
1379                         return -EINVAL;
1380
1381                 result = smu_cmn_update_table(smu,
1382                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1383                                           (void *)(&activity_monitor_external), false);
1384                 if (result) {
1385                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1386                         return result;
1387                 }
1388
1389                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1390                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1391
1392                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1393                         " ",
1394                         0,
1395                         "GFXCLK",
1396                         activity_monitor->Gfx_FPS,
1397                         activity_monitor->Gfx_MinFreqStep,
1398                         activity_monitor->Gfx_MinActiveFreqType,
1399                         activity_monitor->Gfx_MinActiveFreq,
1400                         activity_monitor->Gfx_BoosterFreqType,
1401                         activity_monitor->Gfx_BoosterFreq,
1402                         activity_monitor->Gfx_PD_Data_limit_c,
1403                         activity_monitor->Gfx_PD_Data_error_coeff,
1404                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1405
1406                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1407                         " ",
1408                         1,
1409                         "SOCCLK",
1410                         activity_monitor->Fclk_FPS,
1411                         activity_monitor->Fclk_MinFreqStep,
1412                         activity_monitor->Fclk_MinActiveFreqType,
1413                         activity_monitor->Fclk_MinActiveFreq,
1414                         activity_monitor->Fclk_BoosterFreqType,
1415                         activity_monitor->Fclk_BoosterFreq,
1416                         activity_monitor->Fclk_PD_Data_limit_c,
1417                         activity_monitor->Fclk_PD_Data_error_coeff,
1418                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1419
1420                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1421                         " ",
1422                         2,
1423                         "MEMLK",
1424                         activity_monitor->Mem_FPS,
1425                         activity_monitor->Mem_MinFreqStep,
1426                         activity_monitor->Mem_MinActiveFreqType,
1427                         activity_monitor->Mem_MinActiveFreq,
1428                         activity_monitor->Mem_BoosterFreqType,
1429                         activity_monitor->Mem_BoosterFreq,
1430                         activity_monitor->Mem_PD_Data_limit_c,
1431                         activity_monitor->Mem_PD_Data_error_coeff,
1432                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1433         }
1434
1435         return size;
1436 }
1437
1438 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1439 {
1440
1441         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1442         DpmActivityMonitorCoeffInt_t *activity_monitor =
1443                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1444         int workload_type, ret = 0;
1445
1446         smu->power_profile_mode = input[size];
1447
1448         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1449                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1450                 return -EINVAL;
1451         }
1452
1453         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1454
1455                 ret = smu_cmn_update_table(smu,
1456                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1457                                        (void *)(&activity_monitor_external), false);
1458                 if (ret) {
1459                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1460                         return ret;
1461                 }
1462
1463                 switch (input[0]) {
1464                 case 0: /* Gfxclk */
1465                         activity_monitor->Gfx_FPS = input[1];
1466                         activity_monitor->Gfx_MinFreqStep = input[2];
1467                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1468                         activity_monitor->Gfx_MinActiveFreq = input[4];
1469                         activity_monitor->Gfx_BoosterFreqType = input[5];
1470                         activity_monitor->Gfx_BoosterFreq = input[6];
1471                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1472                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1473                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1474                         break;
1475                 case 1: /* Socclk */
1476                         activity_monitor->Fclk_FPS = input[1];
1477                         activity_monitor->Fclk_MinFreqStep = input[2];
1478                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1479                         activity_monitor->Fclk_MinActiveFreq = input[4];
1480                         activity_monitor->Fclk_BoosterFreqType = input[5];
1481                         activity_monitor->Fclk_BoosterFreq = input[6];
1482                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1483                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1484                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1485                         break;
1486                 case 2: /* Memlk */
1487                         activity_monitor->Mem_FPS = input[1];
1488                         activity_monitor->Mem_MinFreqStep = input[2];
1489                         activity_monitor->Mem_MinActiveFreqType = input[3];
1490                         activity_monitor->Mem_MinActiveFreq = input[4];
1491                         activity_monitor->Mem_BoosterFreqType = input[5];
1492                         activity_monitor->Mem_BoosterFreq = input[6];
1493                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1494                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1495                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1496                         break;
1497                 }
1498
1499                 ret = smu_cmn_update_table(smu,
1500                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1501                                        (void *)(&activity_monitor_external), true);
1502                 if (ret) {
1503                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1504                         return ret;
1505                 }
1506         }
1507
1508         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1509         workload_type = smu_cmn_to_asic_specific_index(smu,
1510                                                        CMN2ASIC_MAPPING_WORKLOAD,
1511                                                        smu->power_profile_mode);
1512         if (workload_type < 0)
1513                 return -EINVAL;
1514         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1515                                     1 << workload_type, NULL);
1516
1517         return ret;
1518 }
1519
1520 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1521 {
1522         struct smu_clocks min_clocks = {0};
1523         struct pp_display_clock_request clock_req;
1524         int ret = 0;
1525
1526         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1527         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1528         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1529
1530         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1531                 clock_req.clock_type = amd_pp_dcef_clock;
1532                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1533
1534                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1535                 if (!ret) {
1536                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1537                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1538                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1539                                                                   min_clocks.dcef_clock_in_sr/100,
1540                                                                   NULL);
1541                                 if (ret) {
1542                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1543                                         return ret;
1544                                 }
1545                         }
1546                 } else {
1547                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1548                 }
1549         }
1550
1551         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1552                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1553                 if (ret) {
1554                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1555                         return ret;
1556                 }
1557         }
1558
1559         return 0;
1560 }
1561
1562 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1563                                                struct pp_smu_wm_range_sets *clock_ranges)
1564 {
1565         Watermarks_t *table = smu->smu_table.watermarks_table;
1566         int ret = 0;
1567         int i;
1568
1569         if (clock_ranges) {
1570                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1571                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1572                         return -EINVAL;
1573
1574                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1575                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1576                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1577                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1578                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1579                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1580                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1581                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1582                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1583
1584                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1585                                 clock_ranges->reader_wm_sets[i].wm_inst;
1586                 }
1587
1588                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1589                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1590                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1591                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1592                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1593                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1594                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1595                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1596                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1597
1598                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1599                                 clock_ranges->writer_wm_sets[i].wm_inst;
1600                 }
1601
1602                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1603         }
1604
1605         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1606              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1607                 ret = smu_cmn_write_watermarks_table(smu);
1608                 if (ret) {
1609                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1610                         return ret;
1611                 }
1612                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1613         }
1614
1615         return 0;
1616 }
1617
1618 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1619                                  enum amd_pp_sensors sensor,
1620                                  void *data, uint32_t *size)
1621 {
1622         int ret = 0;
1623         uint16_t *temp;
1624
1625         if(!data || !size)
1626                 return -EINVAL;
1627
1628         mutex_lock(&smu->sensor_lock);
1629         switch (sensor) {
1630         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1631                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1632                 *(uint16_t *)data = *temp;
1633                 *size = 4;
1634                 break;
1635         case AMDGPU_PP_SENSOR_MEM_LOAD:
1636                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1637                                                           METRICS_AVERAGE_MEMACTIVITY,
1638                                                           (uint32_t *)data);
1639                 *size = 4;
1640                 break;
1641         case AMDGPU_PP_SENSOR_GPU_LOAD:
1642                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1643                                                           METRICS_AVERAGE_GFXACTIVITY,
1644                                                           (uint32_t *)data);
1645                 *size = 4;
1646                 break;
1647         case AMDGPU_PP_SENSOR_GPU_POWER:
1648                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1649                                                           METRICS_AVERAGE_SOCKETPOWER,
1650                                                           (uint32_t *)data);
1651                 *size = 4;
1652                 break;
1653         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1654                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1655                                                           METRICS_TEMPERATURE_HOTSPOT,
1656                                                           (uint32_t *)data);
1657                 *size = 4;
1658                 break;
1659         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1660                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1661                                                           METRICS_TEMPERATURE_EDGE,
1662                                                           (uint32_t *)data);
1663                 *size = 4;
1664                 break;
1665         case AMDGPU_PP_SENSOR_MEM_TEMP:
1666                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1667                                                           METRICS_TEMPERATURE_MEM,
1668                                                           (uint32_t *)data);
1669                 *size = 4;
1670                 break;
1671         case AMDGPU_PP_SENSOR_GFX_MCLK:
1672                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1673                 *(uint32_t *)data *= 100;
1674                 *size = 4;
1675                 break;
1676         case AMDGPU_PP_SENSOR_GFX_SCLK:
1677                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1678                 *(uint32_t *)data *= 100;
1679                 *size = 4;
1680                 break;
1681         case AMDGPU_PP_SENSOR_VDDGFX:
1682                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1683                 *size = 4;
1684                 break;
1685         default:
1686                 ret = -EOPNOTSUPP;
1687                 break;
1688         }
1689         mutex_unlock(&smu->sensor_lock);
1690
1691         return ret;
1692 }
1693
1694 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1695 {
1696         uint32_t num_discrete_levels = 0;
1697         uint16_t *dpm_levels = NULL;
1698         uint16_t i = 0;
1699         struct smu_table_context *table_context = &smu->smu_table;
1700         DpmDescriptor_t *table_member1;
1701         uint16_t *table_member2;
1702
1703         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1704                 return -EINVAL;
1705
1706         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1707         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1708         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1709         dpm_levels = table_member2;
1710
1711         if (num_discrete_levels == 0 || dpm_levels == NULL)
1712                 return -EINVAL;
1713
1714         *num_states = num_discrete_levels;
1715         for (i = 0; i < num_discrete_levels; i++) {
1716                 /* convert to khz */
1717                 *clocks_in_khz = (*dpm_levels) * 1000;
1718                 clocks_in_khz++;
1719                 dpm_levels++;
1720         }
1721
1722         return 0;
1723 }
1724
1725 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1726                                                 struct smu_temperature_range *range)
1727 {
1728         struct smu_table_context *table_context = &smu->smu_table;
1729         struct smu_11_0_7_powerplay_table *powerplay_table =
1730                                 table_context->power_play_table;
1731         uint16_t *table_member;
1732         uint16_t temp_edge, temp_hotspot, temp_mem;
1733
1734         if (!range)
1735                 return -EINVAL;
1736
1737         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1738
1739         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1740         temp_edge = table_member[TEMP_EDGE];
1741         temp_hotspot = table_member[TEMP_HOTSPOT];
1742         temp_mem = table_member[TEMP_MEM];
1743
1744         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1745         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
1746                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1747         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1748         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
1749                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1750         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1751         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
1752                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1753
1754         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1755
1756         return 0;
1757 }
1758
1759 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1760                                                 bool disable_memory_clock_switch)
1761 {
1762         int ret = 0;
1763         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1764                 (struct smu_11_0_max_sustainable_clocks *)
1765                         smu->smu_table.max_sustainable_clocks;
1766         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1767         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1768
1769         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1770                 return 0;
1771
1772         if(disable_memory_clock_switch)
1773                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1774         else
1775                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1776
1777         if(!ret)
1778                 smu->disable_uclk_switch = disable_memory_clock_switch;
1779
1780         return ret;
1781 }
1782
1783 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1784                                           uint32_t *current_power_limit,
1785                                           uint32_t *default_power_limit,
1786                                           uint32_t *max_power_limit)
1787 {
1788         struct smu_11_0_7_powerplay_table *powerplay_table =
1789                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1790         uint32_t power_limit, od_percent;
1791         uint16_t *table_member;
1792
1793         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1794
1795         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1796                 power_limit =
1797                         table_member[PPT_THROTTLER_PPT0];
1798         }
1799
1800         if (current_power_limit)
1801                 *current_power_limit = power_limit;
1802         if (default_power_limit)
1803                 *default_power_limit = power_limit;
1804
1805         if (max_power_limit) {
1806                 if (smu->od_enabled) {
1807                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1808
1809                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1810
1811                         power_limit *= (100 + od_percent);
1812                         power_limit /= 100;
1813                 }
1814                 *max_power_limit = power_limit;
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1821                                          uint32_t pcie_gen_cap,
1822                                          uint32_t pcie_width_cap)
1823 {
1824         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1825
1826         uint32_t smu_pcie_arg;
1827         uint8_t *table_member1, *table_member2;
1828         int ret, i;
1829
1830         GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1831         GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1832
1833         /* lclk dpm table setup */
1834         for (i = 0; i < MAX_PCIE_CONF; i++) {
1835                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1836                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
1837         }
1838
1839         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1840                 smu_pcie_arg = (i << 16) |
1841                         ((table_member1[i] <= pcie_gen_cap) ?
1842                          (table_member1[i] << 8) :
1843                          (pcie_gen_cap << 8)) |
1844                         ((table_member2[i] <= pcie_width_cap) ?
1845                          table_member2[i] :
1846                          pcie_width_cap);
1847
1848                 ret = smu_cmn_send_smc_msg_with_param(smu,
1849                                 SMU_MSG_OverridePcieParameters,
1850                                 smu_pcie_arg,
1851                                 NULL);
1852                 if (ret)
1853                         return ret;
1854
1855                 if (table_member1[i] > pcie_gen_cap)
1856                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1857                 if (table_member2[i] > pcie_width_cap)
1858                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1859         }
1860
1861         return 0;
1862 }
1863
1864 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1865                                 enum smu_clk_type clk_type,
1866                                 uint32_t *min, uint32_t *max)
1867 {
1868         struct amdgpu_device *adev = smu->adev;
1869         int ret;
1870
1871         if (clk_type == SMU_GFXCLK)
1872                 amdgpu_gfx_off_ctrl(adev, false);
1873         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1874         if (clk_type == SMU_GFXCLK)
1875                 amdgpu_gfx_off_ctrl(adev, true);
1876
1877         return ret;
1878 }
1879
1880 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1881                                          OverDriveTable_t *od_table)
1882 {
1883         struct amdgpu_device *adev = smu->adev;
1884         uint32_t smu_version;
1885
1886         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1887                                                           od_table->GfxclkFmax);
1888         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1889                                                         od_table->UclkFmax);
1890
1891         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1892         if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1893                (smu_version < 0x003a2900)))
1894                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
1895 }
1896
1897 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1898 {
1899         OverDriveTable_t *od_table =
1900                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1901         OverDriveTable_t *boot_od_table =
1902                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1903         OverDriveTable_t *user_od_table =
1904                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
1905         int ret = 0;
1906
1907         /*
1908          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1909          *   - either they already have the default OD settings got during cold bootup
1910          *   - or they have some user customized OD settings which cannot be overwritten
1911          */
1912         if (smu->adev->in_suspend)
1913                 return 0;
1914
1915         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1916                                    0, (void *)boot_od_table, false);
1917         if (ret) {
1918                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1919                 return ret;
1920         }
1921
1922         sienna_cichlid_dump_od_table(smu, boot_od_table);
1923
1924         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1925         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
1926
1927         return 0;
1928 }
1929
1930 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1931                                                  struct smu_11_0_7_overdrive_table *od_table,
1932                                                  enum SMU_11_0_7_ODSETTING_ID setting,
1933                                                  uint32_t value)
1934 {
1935         if (value < od_table->min[setting]) {
1936                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1937                                           setting, value, od_table->min[setting]);
1938                 return -EINVAL;
1939         }
1940         if (value > od_table->max[setting]) {
1941                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1942                                           setting, value, od_table->max[setting]);
1943                 return -EINVAL;
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1950                                             enum PP_OD_DPM_TABLE_COMMAND type,
1951                                             long input[], uint32_t size)
1952 {
1953         struct smu_table_context *table_context = &smu->smu_table;
1954         OverDriveTable_t *od_table =
1955                 (OverDriveTable_t *)table_context->overdrive_table;
1956         struct smu_11_0_7_overdrive_table *od_settings =
1957                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
1958         struct amdgpu_device *adev = smu->adev;
1959         enum SMU_11_0_7_ODSETTING_ID freq_setting;
1960         uint16_t *freq_ptr;
1961         int i, ret = 0;
1962         uint32_t smu_version;
1963
1964         if (!smu->od_enabled) {
1965                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1966                 return -EINVAL;
1967         }
1968
1969         if (!smu->od_settings) {
1970                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
1971                 return -ENOENT;
1972         }
1973
1974         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1975                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1976                 return -EINVAL;
1977         }
1978
1979         switch (type) {
1980         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1981                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
1982                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1983                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1984                         return -ENOTSUPP;
1985                 }
1986
1987                 for (i = 0; i < size; i += 2) {
1988                         if (i + 2 > size) {
1989                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1990                                 return -EINVAL;
1991                         }
1992
1993                         switch (input[i]) {
1994                         case 0:
1995                                 if (input[i + 1] > od_table->GfxclkFmax) {
1996                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1997                                                 input[i + 1], od_table->GfxclkFmax);
1998                                         return -EINVAL;
1999                                 }
2000
2001                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2002                                 freq_ptr = &od_table->GfxclkFmin;
2003                                 break;
2004
2005                         case 1:
2006                                 if (input[i + 1] < od_table->GfxclkFmin) {
2007                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2008                                                 input[i + 1], od_table->GfxclkFmin);
2009                                         return -EINVAL;
2010                                 }
2011
2012                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2013                                 freq_ptr = &od_table->GfxclkFmax;
2014                                 break;
2015
2016                         default:
2017                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2018                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2019                                 return -EINVAL;
2020                         }
2021
2022                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2023                                                                     freq_setting, input[i + 1]);
2024                         if (ret)
2025                                 return ret;
2026
2027                         *freq_ptr = (uint16_t)input[i + 1];
2028                 }
2029                 break;
2030
2031         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2032                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2033                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2034                         return -ENOTSUPP;
2035                 }
2036
2037                 for (i = 0; i < size; i += 2) {
2038                         if (i + 2 > size) {
2039                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2040                                 return -EINVAL;
2041                         }
2042
2043                         switch (input[i]) {
2044                         case 0:
2045                                 if (input[i + 1] > od_table->UclkFmax) {
2046                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2047                                                 input[i + 1], od_table->UclkFmax);
2048                                         return -EINVAL;
2049                                 }
2050
2051                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2052                                 freq_ptr = &od_table->UclkFmin;
2053                                 break;
2054
2055                         case 1:
2056                                 if (input[i + 1] < od_table->UclkFmin) {
2057                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2058                                                 input[i + 1], od_table->UclkFmin);
2059                                         return -EINVAL;
2060                                 }
2061
2062                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2063                                 freq_ptr = &od_table->UclkFmax;
2064                                 break;
2065
2066                         default:
2067                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2068                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2069                                 return -EINVAL;
2070                         }
2071
2072                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2073                                                                     freq_setting, input[i + 1]);
2074                         if (ret)
2075                                 return ret;
2076
2077                         *freq_ptr = (uint16_t)input[i + 1];
2078                 }
2079                 break;
2080
2081         case PP_OD_RESTORE_DEFAULT_TABLE:
2082                 memcpy(table_context->overdrive_table,
2083                                 table_context->boot_overdrive_table,
2084                                 sizeof(OverDriveTable_t));
2085                 fallthrough;
2086
2087         case PP_OD_COMMIT_DPM_TABLE:
2088                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2089                         sienna_cichlid_dump_od_table(smu, od_table);
2090                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2091                         if (ret) {
2092                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2093                                 return ret;
2094                         }
2095                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2096                         smu->user_dpm_profile.user_od = true;
2097
2098                         if (!memcmp(table_context->user_overdrive_table,
2099                                     table_context->boot_overdrive_table,
2100                                     sizeof(OverDriveTable_t)))
2101                                 smu->user_dpm_profile.user_od = false;
2102                 }
2103                 break;
2104
2105         case PP_OD_EDIT_VDDGFX_OFFSET:
2106                 if (size != 1) {
2107                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2108                         return -EINVAL;
2109                 }
2110
2111                 /*
2112                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2113                  * and onwards SMU firmwares.
2114                  */
2115                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2116                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2117                      (smu_version < 0x003a2900)) {
2118                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2119                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2120                         return -EOPNOTSUPP;
2121                 }
2122
2123                 od_table->VddGfxOffset = (int16_t)input[0];
2124
2125                 sienna_cichlid_dump_od_table(smu, od_table);
2126                 break;
2127
2128         default:
2129                 return -ENOSYS;
2130         }
2131
2132         return ret;
2133 }
2134
2135 static int sienna_cichlid_run_btc(struct smu_context *smu)
2136 {
2137         int res;
2138
2139         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2140         if (res)
2141                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2142
2143         return res;
2144 }
2145
2146 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2147 {
2148         struct amdgpu_device *adev = smu->adev;
2149
2150         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2151                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2152         else
2153                 return smu_v11_0_baco_enter(smu);
2154 }
2155
2156 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2157 {
2158         struct amdgpu_device *adev = smu->adev;
2159
2160         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2161                 /* Wait for PMFW handling for the Dstate change */
2162                 msleep(10);
2163                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2164         } else {
2165                 return smu_v11_0_baco_exit(smu);
2166         }
2167 }
2168
2169 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2170 {
2171         struct amdgpu_device *adev = smu->adev;
2172         uint32_t val;
2173         u32 smu_version;
2174
2175         /**
2176          * SRIOV env will not support SMU mode1 reset
2177          * PM FW support mode1 reset from 58.26
2178          */
2179         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2180         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2181                 return false;
2182
2183         /**
2184          * mode1 reset relies on PSP, so we should check if
2185          * PSP is alive.
2186          */
2187         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2188         return val != 0x0;
2189 }
2190
2191 static void beige_goby_dump_pptable(struct smu_context *smu)
2192 {
2193         struct smu_table_context *table_context = &smu->smu_table;
2194         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2195         int i;
2196
2197         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2198
2199         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2200         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2201         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2202
2203         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2204                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2205                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2206                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2207                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2208         }
2209
2210         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2211                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2212                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2213         }
2214
2215         for (i = 0; i < TEMP_COUNT; i++) {
2216                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2217         }
2218
2219         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2220         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2221         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2222         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2223         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2224
2225         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2226         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2227                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2228                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2229         }
2230         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2231
2232         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2233
2234         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2235         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2236         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2237         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2238
2239         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2240
2241         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2242
2243         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2244         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2245         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2246         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2247
2248         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2249         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2250
2251         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2252         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2253         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2254         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2255         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2256         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2257         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2258         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2259
2260         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2261                         "  .VoltageMode          = 0x%02x\n"
2262                         "  .SnapToDiscrete       = 0x%02x\n"
2263                         "  .NumDiscreteLevels    = 0x%02x\n"
2264                         "  .padding              = 0x%02x\n"
2265                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2266                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2267                         "  .SsFmin               = 0x%04x\n"
2268                         "  .Padding_16           = 0x%04x\n",
2269                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2270                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2271                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2272                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2273                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2274                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2275                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2276                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2277                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2278                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2279                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2280
2281         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2282                         "  .VoltageMode          = 0x%02x\n"
2283                         "  .SnapToDiscrete       = 0x%02x\n"
2284                         "  .NumDiscreteLevels    = 0x%02x\n"
2285                         "  .padding              = 0x%02x\n"
2286                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2287                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2288                         "  .SsFmin               = 0x%04x\n"
2289                         "  .Padding_16           = 0x%04x\n",
2290                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2291                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2292                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2293                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2294                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2295                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2296                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2297                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2298                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2299                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2300                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2301
2302         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2303                         "  .VoltageMode          = 0x%02x\n"
2304                         "  .SnapToDiscrete       = 0x%02x\n"
2305                         "  .NumDiscreteLevels    = 0x%02x\n"
2306                         "  .padding              = 0x%02x\n"
2307                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2308                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2309                         "  .SsFmin               = 0x%04x\n"
2310                         "  .Padding_16           = 0x%04x\n",
2311                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2312                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2313                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2314                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2315                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2316                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2317                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2318                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2319                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2320                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2321                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2322
2323         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2324                         "  .VoltageMode          = 0x%02x\n"
2325                         "  .SnapToDiscrete       = 0x%02x\n"
2326                         "  .NumDiscreteLevels    = 0x%02x\n"
2327                         "  .padding              = 0x%02x\n"
2328                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2329                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2330                         "  .SsFmin               = 0x%04x\n"
2331                         "  .Padding_16           = 0x%04x\n",
2332                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2333                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2334                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2335                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2336                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2337                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2338                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2339                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2340                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2341                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2342                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2343
2344         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2345                         "  .VoltageMode          = 0x%02x\n"
2346                         "  .SnapToDiscrete       = 0x%02x\n"
2347                         "  .NumDiscreteLevels    = 0x%02x\n"
2348                         "  .padding              = 0x%02x\n"
2349                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2350                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2351                         "  .SsFmin               = 0x%04x\n"
2352                         "  .Padding_16           = 0x%04x\n",
2353                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2354                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2355                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2356                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2357                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2358                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2359                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2360                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2361                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2362                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2363                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2364
2365         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2366                         "  .VoltageMode          = 0x%02x\n"
2367                         "  .SnapToDiscrete       = 0x%02x\n"
2368                         "  .NumDiscreteLevels    = 0x%02x\n"
2369                         "  .padding              = 0x%02x\n"
2370                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2371                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2372                         "  .SsFmin               = 0x%04x\n"
2373                         "  .Padding_16           = 0x%04x\n",
2374                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2375                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2376                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2377                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2378                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2379                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2380                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2381                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2382                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2383                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2384                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2385
2386         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2387                         "  .VoltageMode          = 0x%02x\n"
2388                         "  .SnapToDiscrete       = 0x%02x\n"
2389                         "  .NumDiscreteLevels    = 0x%02x\n"
2390                         "  .padding              = 0x%02x\n"
2391                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2392                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2393                         "  .SsFmin               = 0x%04x\n"
2394                         "  .Padding_16           = 0x%04x\n",
2395                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2396                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2397                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2398                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2399                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2400                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2401                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2402                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2403                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2404                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2405                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2406
2407         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2408                         "  .VoltageMode          = 0x%02x\n"
2409                         "  .SnapToDiscrete       = 0x%02x\n"
2410                         "  .NumDiscreteLevels    = 0x%02x\n"
2411                         "  .padding              = 0x%02x\n"
2412                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2413                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2414                         "  .SsFmin               = 0x%04x\n"
2415                         "  .Padding_16           = 0x%04x\n",
2416                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2417                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2418                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2419                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2420                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2421                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2422                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2423                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2424                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2425                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2426                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2427
2428         dev_info(smu->adev->dev, "FreqTableGfx\n");
2429         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2430                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2431
2432         dev_info(smu->adev->dev, "FreqTableVclk\n");
2433         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2434                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2435
2436         dev_info(smu->adev->dev, "FreqTableDclk\n");
2437         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2438                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2439
2440         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2441         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2442                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2443
2444         dev_info(smu->adev->dev, "FreqTableUclk\n");
2445         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2446                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2447
2448         dev_info(smu->adev->dev, "FreqTableFclk\n");
2449         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2450                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2451
2452         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2453         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2454         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2455         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2456         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2457         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2458         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2459         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2460         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2461
2462         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2463         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2464                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2465
2466         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2467         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2468
2469         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2470         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2471                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2472
2473         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2474         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2475                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2476
2477         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2478         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2479                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2480
2481         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2482         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2483                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2484
2485         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2486         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2487         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2488         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2489         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2490
2491         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2492
2493         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2494         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2495         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2496         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2497         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2498         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2499         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2500         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2501         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2502         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2503         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2504
2505         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2506         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2507         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2508         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2509         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2510         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2511
2512         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2513         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2514         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2515         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2516         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2517
2518         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2519         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2520                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2521
2522         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2523         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2524         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2525         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2526
2527         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2528         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2529                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2530
2531         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2532         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2533                 pptable->UclkDpmSrcFreqRange.Fmin);
2534         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2535                 pptable->UclkDpmSrcFreqRange.Fmax);
2536         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2537         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2538                 pptable->UclkDpmTargFreqRange.Fmin);
2539         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2540                 pptable->UclkDpmTargFreqRange.Fmax);
2541         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2542         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2543
2544         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2545         for (i = 0; i < NUM_LINK_LEVELS; i++)
2546                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2547
2548         dev_info(smu->adev->dev, "PcieLaneCount\n");
2549         for (i = 0; i < NUM_LINK_LEVELS; i++)
2550                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2551
2552         dev_info(smu->adev->dev, "LclkFreq\n");
2553         for (i = 0; i < NUM_LINK_LEVELS; i++)
2554                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2555
2556         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2557         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2558
2559         dev_info(smu->adev->dev, "FanGain\n");
2560         for (i = 0; i < TEMP_COUNT; i++)
2561                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2562
2563         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2564         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2565         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2566         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2567         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2568         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2569         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2570         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2571         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2572         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2573         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2574         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2575
2576         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2577         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2578         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2579         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2580
2581         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2582         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2583         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2584         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2585
2586         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2587                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2588                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2589                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2590         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2591                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2592                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2593                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2594         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2595                         pptable->dBtcGbGfxPll.a,
2596                         pptable->dBtcGbGfxPll.b,
2597                         pptable->dBtcGbGfxPll.c);
2598         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2599                         pptable->dBtcGbGfxDfll.a,
2600                         pptable->dBtcGbGfxDfll.b,
2601                         pptable->dBtcGbGfxDfll.c);
2602         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2603                         pptable->dBtcGbSoc.a,
2604                         pptable->dBtcGbSoc.b,
2605                         pptable->dBtcGbSoc.c);
2606         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2607                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2608                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2609         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2610                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2611                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2612
2613         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2614         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2615                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2616                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2617                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2618                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2619         }
2620
2621         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2622                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2623                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2624                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2625         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2626                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2627                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2628                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2629
2630         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2631         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2632
2633         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2634         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2635         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2636         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2637
2638         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2639         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2640         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2641         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2642
2643         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2644         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2645
2646         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2647         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2648                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2649         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2650         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2651
2652         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2653         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2654                         pptable->ReservedEquation0.a,
2655                         pptable->ReservedEquation0.b,
2656                         pptable->ReservedEquation0.c);
2657         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2658                         pptable->ReservedEquation1.a,
2659                         pptable->ReservedEquation1.b,
2660                         pptable->ReservedEquation1.c);
2661         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2662                         pptable->ReservedEquation2.a,
2663                         pptable->ReservedEquation2.b,
2664                         pptable->ReservedEquation2.c);
2665         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2666                         pptable->ReservedEquation3.a,
2667                         pptable->ReservedEquation3.b,
2668                         pptable->ReservedEquation3.c);
2669
2670         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2671         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2672         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2673         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2674         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2675         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2676         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2677         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2678
2679         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2680         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2681         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2682         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2683         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2684         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2685
2686         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2687                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2688                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2689                                 pptable->I2cControllers[i].Enabled);
2690                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2691                                 pptable->I2cControllers[i].Speed);
2692                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2693                                 pptable->I2cControllers[i].SlaveAddress);
2694                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2695                                 pptable->I2cControllers[i].ControllerPort);
2696                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2697                                 pptable->I2cControllers[i].ControllerName);
2698                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2699                                 pptable->I2cControllers[i].ThermalThrotter);
2700                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2701                                 pptable->I2cControllers[i].I2cProtocol);
2702                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2703                                 pptable->I2cControllers[i].PaddingConfig);
2704         }
2705
2706         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2707         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2708         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2709         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2710
2711         dev_info(smu->adev->dev, "Board Parameters:\n");
2712         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2713         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2714         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2715         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2716         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2717         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2718         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2719         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2720
2721         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2722         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2723         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2724
2725         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2726         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2727         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2728
2729         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2730         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2731         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2732
2733         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2734         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2735         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2736
2737         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2738
2739         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2740         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2741         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2742         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2743         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2744         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2745         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2746         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2747         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2748         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2749         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2750         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2751         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2752         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2753         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2754         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2755
2756         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2757         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2758         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2759
2760         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2761         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2762         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2763
2764         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2765         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2766
2767         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2768         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2769         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2770
2771         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2772         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2773         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2774         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2775         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2776
2777         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2778         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2779
2780         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2781         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2782                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2783         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2784         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2785                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2786         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2787         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2788                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2789         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2790         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2791                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2792
2793         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2794         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2795         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2796         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2797
2798         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2799         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2800         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2801         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2802         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2803         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2804         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2805         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2806         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2807         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2808         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2809
2810         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2811         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2812         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2813         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2814         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2815         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2816         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2817         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2818 }
2819
2820 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2821 {
2822         struct smu_table_context *table_context = &smu->smu_table;
2823         PPTable_t *pptable = table_context->driver_pptable;
2824         int i;
2825
2826         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
2827                 beige_goby_dump_pptable(smu);
2828                 return;
2829         }
2830
2831         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2832
2833         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2834         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2835         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2836
2837         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2838                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2839                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2840                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2841                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2842         }
2843
2844         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2845                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2846                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2847         }
2848
2849         for (i = 0; i < TEMP_COUNT; i++) {
2850                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2851         }
2852
2853         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2854         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2855         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2856         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2857         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2858
2859         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2860         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2861                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2862                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2863         }
2864         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2865
2866         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2867
2868         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2869         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2870         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2871         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2872
2873         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2874         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2875
2876         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2877         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2878         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2879         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2880
2881         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2882         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2883         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2884         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2885
2886         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2887         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2888
2889         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2890         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2891         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2892         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2893         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2894         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2895         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2896         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2897
2898         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2899                         "  .VoltageMode          = 0x%02x\n"
2900                         "  .SnapToDiscrete       = 0x%02x\n"
2901                         "  .NumDiscreteLevels    = 0x%02x\n"
2902                         "  .padding              = 0x%02x\n"
2903                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2904                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2905                         "  .SsFmin               = 0x%04x\n"
2906                         "  .Padding_16           = 0x%04x\n",
2907                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2908                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2909                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2910                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2911                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2912                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2913                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2914                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2915                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2916                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2917                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2918
2919         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2920                         "  .VoltageMode          = 0x%02x\n"
2921                         "  .SnapToDiscrete       = 0x%02x\n"
2922                         "  .NumDiscreteLevels    = 0x%02x\n"
2923                         "  .padding              = 0x%02x\n"
2924                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2925                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2926                         "  .SsFmin               = 0x%04x\n"
2927                         "  .Padding_16           = 0x%04x\n",
2928                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2929                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2930                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2931                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2932                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2933                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2934                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2935                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2936                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2937                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2938                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2939
2940         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2941                         "  .VoltageMode          = 0x%02x\n"
2942                         "  .SnapToDiscrete       = 0x%02x\n"
2943                         "  .NumDiscreteLevels    = 0x%02x\n"
2944                         "  .padding              = 0x%02x\n"
2945                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2946                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2947                         "  .SsFmin               = 0x%04x\n"
2948                         "  .Padding_16           = 0x%04x\n",
2949                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2950                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2951                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2952                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2953                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2954                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2955                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2956                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2957                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2958                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2959                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2960
2961         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2962                         "  .VoltageMode          = 0x%02x\n"
2963                         "  .SnapToDiscrete       = 0x%02x\n"
2964                         "  .NumDiscreteLevels    = 0x%02x\n"
2965                         "  .padding              = 0x%02x\n"
2966                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2967                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2968                         "  .SsFmin               = 0x%04x\n"
2969                         "  .Padding_16           = 0x%04x\n",
2970                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2971                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2972                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2973                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2974                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2975                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2976                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2977                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2978                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2979                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2980                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2981
2982         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2983                         "  .VoltageMode          = 0x%02x\n"
2984                         "  .SnapToDiscrete       = 0x%02x\n"
2985                         "  .NumDiscreteLevels    = 0x%02x\n"
2986                         "  .padding              = 0x%02x\n"
2987                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2988                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2989                         "  .SsFmin               = 0x%04x\n"
2990                         "  .Padding_16           = 0x%04x\n",
2991                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2992                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2993                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2994                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2995                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2996                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2997                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2998                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2999                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3000                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3001                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3002
3003         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3004                         "  .VoltageMode          = 0x%02x\n"
3005                         "  .SnapToDiscrete       = 0x%02x\n"
3006                         "  .NumDiscreteLevels    = 0x%02x\n"
3007                         "  .padding              = 0x%02x\n"
3008                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3009                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3010                         "  .SsFmin               = 0x%04x\n"
3011                         "  .Padding_16           = 0x%04x\n",
3012                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3013                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3014                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3015                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3016                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3017                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3018                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3019                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3020                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3021                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3022                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3023
3024         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3025                         "  .VoltageMode          = 0x%02x\n"
3026                         "  .SnapToDiscrete       = 0x%02x\n"
3027                         "  .NumDiscreteLevels    = 0x%02x\n"
3028                         "  .padding              = 0x%02x\n"
3029                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3030                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3031                         "  .SsFmin               = 0x%04x\n"
3032                         "  .Padding_16           = 0x%04x\n",
3033                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3034                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3035                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3036                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3037                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3038                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3039                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3040                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3041                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3042                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3043                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3044
3045         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3046                         "  .VoltageMode          = 0x%02x\n"
3047                         "  .SnapToDiscrete       = 0x%02x\n"
3048                         "  .NumDiscreteLevels    = 0x%02x\n"
3049                         "  .padding              = 0x%02x\n"
3050                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3051                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3052                         "  .SsFmin               = 0x%04x\n"
3053                         "  .Padding_16           = 0x%04x\n",
3054                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3055                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3056                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3057                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3058                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3059                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3060                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3061                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3062                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3063                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3064                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3065
3066         dev_info(smu->adev->dev, "FreqTableGfx\n");
3067         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3068                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3069
3070         dev_info(smu->adev->dev, "FreqTableVclk\n");
3071         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3072                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3073
3074         dev_info(smu->adev->dev, "FreqTableDclk\n");
3075         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3076                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3077
3078         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3079         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3080                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3081
3082         dev_info(smu->adev->dev, "FreqTableUclk\n");
3083         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3084                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3085
3086         dev_info(smu->adev->dev, "FreqTableFclk\n");
3087         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3088                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3089
3090         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3091         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3092         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3093         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3094         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3095         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3096         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3097         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3098         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3099
3100         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3101         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3102                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3103
3104         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3105         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3106
3107         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3108         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3109                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3110
3111         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3112         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3113                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3114
3115         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3116         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3117                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3118
3119         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3120         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3121                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3122
3123         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3124         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3125         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3126         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3127         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3128
3129         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3130
3131         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3132         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3133         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3134         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3135         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3136         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3137         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3138         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3139         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3140         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3141         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3142
3143         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3144         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3145         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3146         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3147         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3148         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3149
3150         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3151         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3152         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3153         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3154         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3155
3156         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3157         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3158                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3159
3160         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3161         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3162         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3163         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3164
3165         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3166         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3167                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3168
3169         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3170         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3171                 pptable->UclkDpmSrcFreqRange.Fmin);
3172         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3173                 pptable->UclkDpmSrcFreqRange.Fmax);
3174         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3175         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3176                 pptable->UclkDpmTargFreqRange.Fmin);
3177         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3178                 pptable->UclkDpmTargFreqRange.Fmax);
3179         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3180         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3181
3182         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3183         for (i = 0; i < NUM_LINK_LEVELS; i++)
3184                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3185
3186         dev_info(smu->adev->dev, "PcieLaneCount\n");
3187         for (i = 0; i < NUM_LINK_LEVELS; i++)
3188                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3189
3190         dev_info(smu->adev->dev, "LclkFreq\n");
3191         for (i = 0; i < NUM_LINK_LEVELS; i++)
3192                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3193
3194         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3195         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3196
3197         dev_info(smu->adev->dev, "FanGain\n");
3198         for (i = 0; i < TEMP_COUNT; i++)
3199                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3200
3201         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3202         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3203         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3204         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3205         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3206         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3207         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3208         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3209         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3210         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3211         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3212         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3213
3214         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3215         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3216         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3217         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3218
3219         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3220         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3221         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3222         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3223
3224         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3225                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3226                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3227                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3228         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3229                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3230                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3231                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3232         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3233                         pptable->dBtcGbGfxPll.a,
3234                         pptable->dBtcGbGfxPll.b,
3235                         pptable->dBtcGbGfxPll.c);
3236         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3237                         pptable->dBtcGbGfxDfll.a,
3238                         pptable->dBtcGbGfxDfll.b,
3239                         pptable->dBtcGbGfxDfll.c);
3240         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3241                         pptable->dBtcGbSoc.a,
3242                         pptable->dBtcGbSoc.b,
3243                         pptable->dBtcGbSoc.c);
3244         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3245                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3246                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3247         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3248                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3249                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3250
3251         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3252         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3253                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3254                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3255                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3256                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3257         }
3258
3259         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3260                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3261                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3262                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3263         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3264                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3265                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3266                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3267
3268         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3269         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3270
3271         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3272         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3273         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3274         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3275
3276         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3277         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3278         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3279         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3280
3281         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3282         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3283
3284         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3285         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3286                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3287         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3288         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3289
3290         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3291         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3292                         pptable->ReservedEquation0.a,
3293                         pptable->ReservedEquation0.b,
3294                         pptable->ReservedEquation0.c);
3295         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3296                         pptable->ReservedEquation1.a,
3297                         pptable->ReservedEquation1.b,
3298                         pptable->ReservedEquation1.c);
3299         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3300                         pptable->ReservedEquation2.a,
3301                         pptable->ReservedEquation2.b,
3302                         pptable->ReservedEquation2.c);
3303         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3304                         pptable->ReservedEquation3.a,
3305                         pptable->ReservedEquation3.b,
3306                         pptable->ReservedEquation3.c);
3307
3308         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3309         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3310         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3311         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3312         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3313         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3314         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3315         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3316
3317         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3318         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3319         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3320         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3321         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3322         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3323
3324         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3325                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3326                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3327                                 pptable->I2cControllers[i].Enabled);
3328                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3329                                 pptable->I2cControllers[i].Speed);
3330                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3331                                 pptable->I2cControllers[i].SlaveAddress);
3332                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3333                                 pptable->I2cControllers[i].ControllerPort);
3334                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3335                                 pptable->I2cControllers[i].ControllerName);
3336                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3337                                 pptable->I2cControllers[i].ThermalThrotter);
3338                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3339                                 pptable->I2cControllers[i].I2cProtocol);
3340                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3341                                 pptable->I2cControllers[i].PaddingConfig);
3342         }
3343
3344         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3345         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3346         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3347         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3348
3349         dev_info(smu->adev->dev, "Board Parameters:\n");
3350         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3351         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3352         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3353         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3354         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3355         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3356         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3357         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3358
3359         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3360         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3361         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3362
3363         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3364         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3365         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3366
3367         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3368         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3369         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3370
3371         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3372         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3373         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3374
3375         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3376
3377         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3378         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3379         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3380         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3381         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3382         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3383         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3384         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3385         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3386         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3387         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3388         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3389         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3390         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3391         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3392         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3393
3394         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3395         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3396         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3397
3398         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3399         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3400         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3401
3402         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3403         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3404
3405         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3406         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3407         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3408
3409         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3410         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3411         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3412         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3413         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3414
3415         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3416         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3417
3418         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3419         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3420                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3421         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3422         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3423                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3424         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3425         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3426                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3427         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3428         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3429                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3430
3431         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3432         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3433         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3434         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3435
3436         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3437         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3438         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3439         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3440         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3441         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3442         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3443         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3444         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3445         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3446         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3447
3448         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3449         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3450         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3451         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3452         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3453         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3454         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3455         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3456 }
3457
3458 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3459                                    struct i2c_msg *msg, int num_msgs)
3460 {
3461         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
3462         struct smu_table_context *smu_table = &adev->smu.smu_table;
3463         struct smu_table *table = &smu_table->driver_table;
3464         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3465         int i, j, r, c;
3466         u16 dir;
3467
3468         req = kzalloc(sizeof(*req), GFP_KERNEL);
3469         if (!req)
3470                 return -ENOMEM;
3471
3472         req->I2CcontrollerPort = 1;
3473         req->I2CSpeed = I2C_SPEED_FAST_400K;
3474         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3475         dir = msg[0].flags & I2C_M_RD;
3476
3477         for (c = i = 0; i < num_msgs; i++) {
3478                 for (j = 0; j < msg[i].len; j++, c++) {
3479                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3480
3481                         if (!(msg[i].flags & I2C_M_RD)) {
3482                                 /* write */
3483                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3484                                 cmd->ReadWriteData = msg[i].buf[j];
3485                         }
3486
3487                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3488                                 /* The direction changes.
3489                                  */
3490                                 dir = msg[i].flags & I2C_M_RD;
3491                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3492                         }
3493
3494                         req->NumCmds++;
3495
3496                         /*
3497                          * Insert STOP if we are at the last byte of either last
3498                          * message for the transaction or the client explicitly
3499                          * requires a STOP at this particular message.
3500                          */
3501                         if ((j == msg[i].len - 1) &&
3502                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3503                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3504                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3505                         }
3506                 }
3507         }
3508         mutex_lock(&adev->smu.mutex);
3509         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3510         mutex_unlock(&adev->smu.mutex);
3511         if (r)
3512                 goto fail;
3513
3514         for (c = i = 0; i < num_msgs; i++) {
3515                 if (!(msg[i].flags & I2C_M_RD)) {
3516                         c += msg[i].len;
3517                         continue;
3518                 }
3519                 for (j = 0; j < msg[i].len; j++, c++) {
3520                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3521
3522                         msg[i].buf[j] = cmd->ReadWriteData;
3523                 }
3524         }
3525         r = num_msgs;
3526 fail:
3527         kfree(req);
3528         return r;
3529 }
3530
3531 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3532 {
3533         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3534 }
3535
3536
3537 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3538         .master_xfer = sienna_cichlid_i2c_xfer,
3539         .functionality = sienna_cichlid_i2c_func,
3540 };
3541
3542 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3543         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3544         .max_read_len  = MAX_SW_I2C_COMMANDS,
3545         .max_write_len = MAX_SW_I2C_COMMANDS,
3546         .max_comb_1st_msg_len = 2,
3547         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3548 };
3549
3550 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3551 {
3552         struct amdgpu_device *adev = to_amdgpu_device(control);
3553         int res;
3554
3555         control->owner = THIS_MODULE;
3556         control->class = I2C_CLASS_HWMON;
3557         control->dev.parent = &adev->pdev->dev;
3558         control->algo = &sienna_cichlid_i2c_algo;
3559         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
3560         control->quirks = &sienna_cichlid_i2c_control_quirks;
3561
3562         res = i2c_add_adapter(control);
3563         if (res)
3564                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3565
3566         return res;
3567 }
3568
3569 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3570 {
3571         i2c_del_adapter(control);
3572 }
3573
3574 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3575                                               void **table)
3576 {
3577         struct smu_table_context *smu_table = &smu->smu_table;
3578         struct gpu_metrics_v1_3 *gpu_metrics =
3579                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3580         SmuMetricsExternal_t metrics_external;
3581         SmuMetrics_t *metrics =
3582                 &(metrics_external.SmuMetrics);
3583         SmuMetrics_V2_t *metrics_v2 =
3584                 &(metrics_external.SmuMetrics_V2);
3585         struct amdgpu_device *adev = smu->adev;
3586         bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
3587                 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3588         uint16_t average_gfx_activity;
3589         int ret = 0;
3590
3591         mutex_lock(&smu->metrics_lock);
3592         ret = smu_cmn_get_metrics_table_locked(smu,
3593                                                &metrics_external,
3594                                                true);
3595         if (ret) {
3596                 mutex_unlock(&smu->metrics_lock);
3597                 return ret;
3598         }
3599
3600         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3601
3602         gpu_metrics->temperature_edge =
3603                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3604         gpu_metrics->temperature_hotspot =
3605                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3606         gpu_metrics->temperature_mem =
3607                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3608         gpu_metrics->temperature_vrgfx =
3609                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3610         gpu_metrics->temperature_vrsoc =
3611                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3612         gpu_metrics->temperature_vrmem =
3613                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3614
3615         gpu_metrics->average_gfx_activity =
3616                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3617         gpu_metrics->average_umc_activity =
3618                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3619         gpu_metrics->average_mm_activity =
3620                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3621
3622         gpu_metrics->average_socket_power =
3623                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3624         gpu_metrics->energy_accumulator =
3625                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3626
3627         if (metrics->CurrGfxVoltageOffset)
3628                 gpu_metrics->voltage_gfx =
3629                         (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3630         if (metrics->CurrMemVidOffset)
3631                 gpu_metrics->voltage_mem =
3632                         (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3633         if (metrics->CurrSocVoltageOffset)
3634                 gpu_metrics->voltage_soc =
3635                         (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3636
3637         average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3638         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3639                 gpu_metrics->average_gfxclk_frequency =
3640                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
3641         else
3642                 gpu_metrics->average_gfxclk_frequency =
3643                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3644         gpu_metrics->average_uclk_frequency =
3645                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3646         gpu_metrics->average_vclk0_frequency =
3647                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3648         gpu_metrics->average_dclk0_frequency =
3649                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3650         gpu_metrics->average_vclk1_frequency =
3651                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3652         gpu_metrics->average_dclk1_frequency =
3653                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3654
3655         gpu_metrics->current_gfxclk =
3656                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3657         gpu_metrics->current_socclk =
3658                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3659         gpu_metrics->current_uclk =
3660                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3661         gpu_metrics->current_vclk0 =
3662                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3663         gpu_metrics->current_dclk0 =
3664                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3665         gpu_metrics->current_vclk1 =
3666                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3667         gpu_metrics->current_dclk1 =
3668                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3669
3670         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3671         gpu_metrics->indep_throttle_status =
3672                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3673                                                            sienna_cichlid_throttler_map);
3674
3675         gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3676
3677         if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3678               ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
3679                 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3680                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3681         } else {
3682                 gpu_metrics->pcie_link_width =
3683                                 smu_v11_0_get_current_pcie_link_width(smu);
3684                 gpu_metrics->pcie_link_speed =
3685                                 smu_v11_0_get_current_pcie_link_speed(smu);
3686         }
3687
3688         mutex_unlock(&smu->metrics_lock);
3689
3690         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3691
3692         *table = (void *)gpu_metrics;
3693
3694         return sizeof(struct gpu_metrics_v1_3);
3695 }
3696
3697 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3698 {
3699         struct smu_table_context *table_context = &smu->smu_table;
3700         PPTable_t *smc_pptable = table_context->driver_pptable;
3701
3702         /*
3703          * Skip the MGpuFanBoost setting for those ASICs
3704          * which do not support it
3705          */
3706         if (!smc_pptable->MGpuFanBoostLimitRpm)
3707                 return 0;
3708
3709         return smu_cmn_send_smc_msg_with_param(smu,
3710                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
3711                                                0,
3712                                                NULL);
3713 }
3714
3715 static int sienna_cichlid_gpo_control(struct smu_context *smu,
3716                                       bool enablement)
3717 {
3718         uint32_t smu_version;
3719         int ret = 0;
3720
3721
3722         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
3723                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3724                 if (ret)
3725                         return ret;
3726
3727                 if (enablement) {
3728                         if (smu_version < 0x003a2500) {
3729                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3730                                                                       SMU_MSG_SetGpoFeaturePMask,
3731                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3732                                                                       NULL);
3733                         } else {
3734                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3735                                                                       SMU_MSG_DisallowGpo,
3736                                                                       0,
3737                                                                       NULL);
3738                         }
3739                 } else {
3740                         if (smu_version < 0x003a2500) {
3741                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3742                                                                       SMU_MSG_SetGpoFeaturePMask,
3743                                                                       0,
3744                                                                       NULL);
3745                         } else {
3746                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3747                                                                       SMU_MSG_DisallowGpo,
3748                                                                       1,
3749                                                                       NULL);
3750                         }
3751                 }
3752         }
3753
3754         return ret;
3755 }
3756
3757 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3758 {
3759         uint32_t smu_version;
3760         int ret = 0;
3761
3762         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3763         if (ret)
3764                 return ret;
3765
3766         /*
3767          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3768          * onwards PMFWs.
3769          */
3770         if (smu_version < 0x003A2D00)
3771                 return 0;
3772
3773         return smu_cmn_send_smc_msg_with_param(smu,
3774                                                SMU_MSG_Enable2ndUSB20Port,
3775                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3776                                                1 : 0,
3777                                                NULL);
3778 }
3779
3780 static int sienna_cichlid_system_features_control(struct smu_context *smu,
3781                                                   bool en)
3782 {
3783         int ret = 0;
3784
3785         if (en) {
3786                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3787                 if (ret)
3788                         return ret;
3789         }
3790
3791         return smu_v11_0_system_features_control(smu, en);
3792 }
3793
3794 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3795                                         enum pp_mp1_state mp1_state)
3796 {
3797         int ret;
3798
3799         switch (mp1_state) {
3800         case PP_MP1_STATE_UNLOAD:
3801                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3802                 break;
3803         default:
3804                 /* Ignore others */
3805                 ret = 0;
3806         }
3807
3808         return ret;
3809 }
3810
3811 static void sienna_cichlid_stb_init(struct smu_context *smu)
3812 {
3813         struct amdgpu_device *adev = smu->adev;
3814         uint32_t reg;
3815
3816         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
3817         smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
3818
3819         /* STB is disabled */
3820         if (!smu->stb_context.enabled)
3821                 return;
3822
3823         spin_lock_init(&smu->stb_context.lock);
3824
3825         /* STB buffer size in bytes as function of FIFO depth */
3826         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
3827         smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
3828         smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
3829
3830         dev_info(smu->adev->dev, "STB initialized to %d entries",
3831                  smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
3832
3833 }
3834
3835 int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
3836                                        void *buf,
3837                                        uint32_t size)
3838 {
3839         uint32_t *p = buf;
3840         struct amdgpu_device *adev = smu->adev;
3841
3842         /* No need to disable interrupts for now as we don't lock it yet from ISR */
3843         spin_lock(&smu->stb_context.lock);
3844
3845         /*
3846          * Read the STB FIFO in units of 32bit since this is the accessor window
3847          * (register width) we have.
3848          */
3849         buf = ((char *) buf) + size;
3850         while ((void *)p < buf)
3851                 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
3852
3853         spin_unlock(&smu->stb_context.lock);
3854
3855         return 0;
3856 }
3857
3858 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3859         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3860         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3861         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3862         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3863         .i2c_init = sienna_cichlid_i2c_control_init,
3864         .i2c_fini = sienna_cichlid_i2c_control_fini,
3865         .print_clk_levels = sienna_cichlid_print_clk_levels,
3866         .force_clk_levels = sienna_cichlid_force_clk_levels,
3867         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3868         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3869         .display_config_changed = sienna_cichlid_display_config_changed,
3870         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3871         .is_dpm_running = sienna_cichlid_is_dpm_running,
3872         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3873         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
3874         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3875         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
3876         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3877         .read_sensor = sienna_cichlid_read_sensor,
3878         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
3879         .set_performance_level = smu_v11_0_set_performance_level,
3880         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3881         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3882         .get_power_limit = sienna_cichlid_get_power_limit,
3883         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
3884         .dump_pptable = sienna_cichlid_dump_pptable,
3885         .init_microcode = smu_v11_0_init_microcode,
3886         .load_microcode = smu_v11_0_load_microcode,
3887         .init_smc_tables = sienna_cichlid_init_smc_tables,
3888         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3889         .init_power = smu_v11_0_init_power,
3890         .fini_power = smu_v11_0_fini_power,
3891         .check_fw_status = smu_v11_0_check_fw_status,
3892         .setup_pptable = sienna_cichlid_setup_pptable,
3893         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3894         .check_fw_version = smu_v11_0_check_fw_version,
3895         .write_pptable = smu_cmn_write_pptable,
3896         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3897         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3898         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3899         .system_features_control = sienna_cichlid_system_features_control,
3900         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3901         .send_smc_msg = smu_cmn_send_smc_msg,
3902         .init_display_count = NULL,
3903         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3904         .get_enabled_mask = smu_cmn_get_enabled_mask,
3905         .feature_is_enabled = smu_cmn_feature_is_enabled,
3906         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3907         .notify_display_change = NULL,
3908         .set_power_limit = smu_v11_0_set_power_limit,
3909         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3910         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3911         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3912         .set_min_dcef_deep_sleep = NULL,
3913         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3914         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3915         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3916         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3917         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3918         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3919         .gfx_off_control = smu_v11_0_gfx_off_control,
3920         .register_irq_handler = smu_v11_0_register_irq_handler,
3921         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3922         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3923         .baco_is_support = smu_v11_0_baco_is_support,
3924         .baco_get_state = smu_v11_0_baco_get_state,
3925         .baco_set_state = smu_v11_0_baco_set_state,
3926         .baco_enter = sienna_cichlid_baco_enter,
3927         .baco_exit = sienna_cichlid_baco_exit,
3928         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3929         .mode1_reset = smu_v11_0_mode1_reset,
3930         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
3931         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3932         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
3933         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
3934         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3935         .run_btc = sienna_cichlid_run_btc,
3936         .set_power_source = smu_v11_0_set_power_source,
3937         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3938         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3939         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
3940         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
3941         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3942         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3943         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
3944         .interrupt_work = smu_v11_0_interrupt_work,
3945         .gpo_control = sienna_cichlid_gpo_control,
3946         .set_mp1_state = sienna_cichlid_set_mp1_state,
3947         .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3948 };
3949
3950 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3951 {
3952         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
3953         smu->message_map = sienna_cichlid_message_map;
3954         smu->clock_map = sienna_cichlid_clk_map;
3955         smu->feature_map = sienna_cichlid_feature_mask_map;
3956         smu->table_map = sienna_cichlid_table_map;
3957         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3958         smu->workload_map = sienna_cichlid_workload_map;
3959 }