drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "soc15_common.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_navi10.h"
  37 #include "atom.h"
  38 #include "navi10_ppt.h"
  39 #include "smu_v11_0_pptable.h"
  40 #include "smu_v11_0_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  60
  61 #define FEATURE_MASK(feature) (1ULL << feature)
  62 #define SMC_DPM_FEATURE ( \
  63         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  64         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  65         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  66         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  67         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  68         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  69         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  70         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  71
  72 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  73         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  74         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  75         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  76         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  77         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  78         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  79         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  80         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         1),
  81         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        1),
  82         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        1),
  83         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       1),
  84         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  85         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  86         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              1),
  87         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  88         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  89         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  90         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  91         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  92         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  93         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  94         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  95         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  96         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
  97         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
  98         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             0),
  99         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             0),
 100         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             1),
 101         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
 102         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
 103         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
 104         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
 105         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
 106         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
 107         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
 108         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
 109         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
 110         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
 111         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
 112         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 113         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 114         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 115         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 116         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 117         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 118         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 119         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 120         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 121         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 122         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 123         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 124         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 125         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 126         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 127         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 128         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 129         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 130         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 131         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 132         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 133         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 134         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 135         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 136         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 137         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,  0),
 138         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 139         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 140         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 141         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,      0),
 142 };
 143
 144 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 145         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 146         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 147         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 148         CLK_MAP(FCLK, PPCLK_SOCCLK),
 149         CLK_MAP(UCLK, PPCLK_UCLK),
 150         CLK_MAP(MCLK, PPCLK_UCLK),
 151         CLK_MAP(DCLK, PPCLK_DCLK),
 152         CLK_MAP(VCLK, PPCLK_VCLK),
 153         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 154         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 155         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 156         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 157 };
 158
 159 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 160         FEA_MAP(DPM_PREFETCHER),
 161         FEA_MAP(DPM_GFXCLK),
 162         FEA_MAP(DPM_GFX_PACE),
 163         FEA_MAP(DPM_UCLK),
 164         FEA_MAP(DPM_SOCCLK),
 165         FEA_MAP(DPM_MP0CLK),
 166         FEA_MAP(DPM_LINK),
 167         FEA_MAP(DPM_DCEFCLK),
 168         FEA_MAP(MEM_VDDCI_SCALING),
 169         FEA_MAP(MEM_MVDD_SCALING),
 170         FEA_MAP(DS_GFXCLK),
 171         FEA_MAP(DS_SOCCLK),
 172         FEA_MAP(DS_LCLK),
 173         FEA_MAP(DS_DCEFCLK),
 174         FEA_MAP(DS_UCLK),
 175         FEA_MAP(GFX_ULV),
 176         FEA_MAP(FW_DSTATE),
 177         FEA_MAP(GFXOFF),
 178         FEA_MAP(BACO),
 179         FEA_MAP(VCN_PG),
 180         FEA_MAP(JPEG_PG),
 181         FEA_MAP(USB_PG),
 182         FEA_MAP(RSMU_SMN_CG),
 183         FEA_MAP(PPT),
 184         FEA_MAP(TDC),
 185         FEA_MAP(GFX_EDC),
 186         FEA_MAP(APCC_PLUS),
 187         FEA_MAP(GTHR),
 188         FEA_MAP(ACDC),
 189         FEA_MAP(VR0HOT),
 190         FEA_MAP(VR1HOT),
 191         FEA_MAP(FW_CTF),
 192         FEA_MAP(FAN_CONTROL),
 193         FEA_MAP(THERMAL),
 194         FEA_MAP(GFX_DCS),
 195         FEA_MAP(RM),
 196         FEA_MAP(LED_DISPLAY),
 197         FEA_MAP(GFX_SS),
 198         FEA_MAP(OUT_OF_BAND_MONITOR),
 199         FEA_MAP(TEMP_DEPENDENT_VMIN),
 200         FEA_MAP(MMHUB_PG),
 201         FEA_MAP(ATHUB_PG),
 202         FEA_MAP(APCC_DFLL),
 203 };
 204
 205 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 206         TAB_MAP(PPTABLE),
 207         TAB_MAP(WATERMARKS),
 208         TAB_MAP(AVFS),
 209         TAB_MAP(AVFS_PSM_DEBUG),
 210         TAB_MAP(AVFS_FUSE_OVERRIDE),
 211         TAB_MAP(PMSTATUSLOG),
 212         TAB_MAP(SMU_METRICS),
 213         TAB_MAP(DRIVER_SMU_CONFIG),
 214         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 215         TAB_MAP(OVERDRIVE),
 216         TAB_MAP(I2C_COMMANDS),
 217         TAB_MAP(PACE),
 218 };
 219
 220 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 221         PWR_MAP(AC),
 222         PWR_MAP(DC),
 223 };
 224
 225 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 226         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 227         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 228         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 229         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 230         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 231         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 232         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 233 };
 234
 235 static bool is_asic_secure(struct smu_context *smu)
 236 {
 237         struct amdgpu_device *adev = smu->adev;
 238         bool is_secure = true;
 239         uint32_t mp0_fw_intf;
 240
 241         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 242                                    (smnMP0_FW_INTF & 0xffffffff));
 243
 244         if (!(mp0_fw_intf & (1 << 19)))
 245                 is_secure = false;
 246
 247         return is_secure;
 248 }
 249
 250 static int
 251 navi10_get_allowed_feature_mask(struct smu_context *smu,
 252                                   uint32_t *feature_mask, uint32_t num)
 253 {
 254         struct amdgpu_device *adev = smu->adev;
 255
 256         if (num > 2)
 257                 return -EINVAL;
 258
 259         memset(feature_mask, 0, sizeof(uint32_t) * num);
 260
 261         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 262                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 263                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 264                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 265                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 266                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 267                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 268                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 269                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 270                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 271                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 272                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 273                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 274                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 275                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 276                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 277                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 278                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 279                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 280                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 281
 282         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 283                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 284
 285         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 286                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 287
 288         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 289                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 290
 291         if (adev->pm.pp_feature & PP_ULV_MASK)
 292                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 293
 294         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 295                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 296
 297         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 298                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 299
 300         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 301                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 302
 303         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 304                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 305
 306         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 307                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 308
 309         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 310                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 311
 312         if (smu->dc_controlled_by_gpio)
 313                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 314
 315         /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
 316         if (is_asic_secure(smu) &&
 317             (adev->asic_type == CHIP_NAVI10) &&
 318             (adev->rev_id == 0))
 319                 *(uint64_t *)feature_mask &=
 320                                 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 321
 322         return 0;
 323 }
 324
 325 static int navi10_check_powerplay_table(struct smu_context *smu)
 326 {
 327         struct smu_table_context *table_context = &smu->smu_table;
 328         struct smu_11_0_powerplay_table *powerplay_table =
 329                 table_context->power_play_table;
 330         struct smu_baco_context *smu_baco = &smu->smu_baco;
 331
 332         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 333                 smu->dc_controlled_by_gpio = true;
 334
 335         mutex_lock(&smu_baco->mutex);
 336         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 337             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 338                 smu_baco->platform_support = true;
 339         mutex_unlock(&smu_baco->mutex);
 340
 341         table_context->thermal_controller_type =
 342                 powerplay_table->thermal_controller_type;
 343
 344         /*
 345          * Instead of having its own buffer space and get overdrive_table copied,
 346          * smu->od_settings just points to the actual overdrive_table
 347          */
 348         smu->od_settings = &powerplay_table->overdrive_table;
 349
 350         return 0;
 351 }
 352
 353 static int navi10_append_powerplay_table(struct smu_context *smu)
 354 {
 355         struct amdgpu_device *adev = smu->adev;
 356         struct smu_table_context *table_context = &smu->smu_table;
 357         PPTable_t *smc_pptable = table_context->driver_pptable;
 358         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 359         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 360         int index, ret;
 361
 362         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 363                                            smc_dpm_info);
 364
 365         ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 366                                       (uint8_t **)&smc_dpm_table);
 367         if (ret)
 368                 return ret;
 369
 370         dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 371                         smc_dpm_table->table_header.format_revision,
 372                         smc_dpm_table->table_header.content_revision);
 373
 374         if (smc_dpm_table->table_header.format_revision != 4) {
 375                 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
 376                 return -EINVAL;
 377         }
 378
 379         switch (smc_dpm_table->table_header.content_revision) {
 380         case 5: /* nv10 and nv14 */
 381                 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 382                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 383                 break;
 384         case 7: /* nv12 */
 385                 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 386                                               (uint8_t **)&smc_dpm_table_v4_7);
 387                 if (ret)
 388                         return ret;
 389                 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
 390                         sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
 391                 break;
 392         default:
 393                 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
 394                                 smc_dpm_table->table_header.content_revision);
 395                 return -EINVAL;
 396         }
 397
 398         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 399                 /* TODO: remove it once SMU fw fix it */
 400                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int navi10_store_powerplay_table(struct smu_context *smu)
 407 {
 408         struct smu_table_context *table_context = &smu->smu_table;
 409         struct smu_11_0_powerplay_table *powerplay_table =
 410                 table_context->power_play_table;
 411
 412         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 413                sizeof(PPTable_t));
 414
 415         return 0;
 416 }
 417
 418 static int navi10_setup_pptable(struct smu_context *smu)
 419 {
 420         int ret = 0;
 421
 422         ret = smu_v11_0_setup_pptable(smu);
 423         if (ret)
 424                 return ret;
 425
 426         ret = navi10_store_powerplay_table(smu);
 427         if (ret)
 428                 return ret;
 429
 430         ret = navi10_append_powerplay_table(smu);
 431         if (ret)
 432                 return ret;
 433
 434         ret = navi10_check_powerplay_table(smu);
 435         if (ret)
 436                 return ret;
 437
 438         return ret;
 439 }
 440
 441 static int navi10_tables_init(struct smu_context *smu)
 442 {
 443         struct smu_table_context *smu_table = &smu->smu_table;
 444         struct smu_table *tables = smu_table->tables;
 445         struct amdgpu_device *adev = smu->adev;
 446
 447         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 448                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 449         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 450                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 451         if (adev->asic_type == CHIP_NAVI12)
 452                 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV12_t),
 453                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 454         else
 455                 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 456                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 457         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 458                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 459         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 460                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 461         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 462                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 463         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 464                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 465                        AMDGPU_GEM_DOMAIN_VRAM);
 466
 467         smu_table->metrics_table = kzalloc(adev->asic_type == CHIP_NAVI12 ?
 468                                            sizeof(SmuMetrics_NV12_t) :
 469                                            sizeof(SmuMetrics_t), GFP_KERNEL);
 470         if (!smu_table->metrics_table)
 471                 goto err0_out;
 472         smu_table->metrics_time = 0;
 473
 474         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 475         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 476         if (!smu_table->gpu_metrics_table)
 477                 goto err1_out;
 478
 479         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 480         if (!smu_table->watermarks_table)
 481                 goto err2_out;
 482
 483         return 0;
 484
 485 err2_out:
 486         kfree(smu_table->gpu_metrics_table);
 487 err1_out:
 488         kfree(smu_table->metrics_table);
 489 err0_out:
 490         return -ENOMEM;
 491 }
 492
 493 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 494                                        MetricsMember_t member,
 495                                        uint32_t *value)
 496 {
 497         struct smu_table_context *smu_table= &smu->smu_table;
 498         /*
 499          * This works for NV12 also. As although NV12 uses a different
 500          * SmuMetrics structure from other NV1X ASICs, they share the
 501          * same offsets for the heading parts(those members used here).
 502          */
 503         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 504         int ret = 0;
 505
 506         mutex_lock(&smu->metrics_lock);
 507
 508         ret = smu_cmn_get_metrics_table_locked(smu,
 509                                                NULL,
 510                                                false);
 511         if (ret) {
 512                 mutex_unlock(&smu->metrics_lock);
 513                 return ret;
 514         }
 515
 516         switch (member) {
 517         case METRICS_CURR_GFXCLK:
 518                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 519                 break;
 520         case METRICS_CURR_SOCCLK:
 521                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 522                 break;
 523         case METRICS_CURR_UCLK:
 524                 *value = metrics->CurrClock[PPCLK_UCLK];
 525                 break;
 526         case METRICS_CURR_VCLK:
 527                 *value = metrics->CurrClock[PPCLK_VCLK];
 528                 break;
 529         case METRICS_CURR_DCLK:
 530                 *value = metrics->CurrClock[PPCLK_DCLK];
 531                 break;
 532         case METRICS_CURR_DCEFCLK:
 533                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 534                 break;
 535         case METRICS_AVERAGE_GFXCLK:
 536                 *value = metrics->AverageGfxclkFrequency;
 537                 break;
 538         case METRICS_AVERAGE_SOCCLK:
 539                 *value = metrics->AverageSocclkFrequency;
 540                 break;
 541         case METRICS_AVERAGE_UCLK:
 542                 *value = metrics->AverageUclkFrequency;
 543                 break;
 544         case METRICS_AVERAGE_GFXACTIVITY:
 545                 *value = metrics->AverageGfxActivity;
 546                 break;
 547         case METRICS_AVERAGE_MEMACTIVITY:
 548                 *value = metrics->AverageUclkActivity;
 549                 break;
 550         case METRICS_AVERAGE_SOCKETPOWER:
 551                 *value = metrics->AverageSocketPower << 8;
 552                 break;
 553         case METRICS_TEMPERATURE_EDGE:
 554                 *value = metrics->TemperatureEdge *
 555                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 556                 break;
 557         case METRICS_TEMPERATURE_HOTSPOT:
 558                 *value = metrics->TemperatureHotspot *
 559                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 560                 break;
 561         case METRICS_TEMPERATURE_MEM:
 562                 *value = metrics->TemperatureMem *
 563                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 564                 break;
 565         case METRICS_TEMPERATURE_VRGFX:
 566                 *value = metrics->TemperatureVrGfx *
 567                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 568                 break;
 569         case METRICS_TEMPERATURE_VRSOC:
 570                 *value = metrics->TemperatureVrSoc *
 571                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 572                 break;
 573         case METRICS_THROTTLER_STATUS:
 574                 *value = metrics->ThrottlerStatus;
 575                 break;
 576         case METRICS_CURR_FANSPEED:
 577                 *value = metrics->CurrFanSpeed;
 578                 break;
 579         default:
 580                 *value = UINT_MAX;
 581                 break;
 582         }
 583
 584         mutex_unlock(&smu->metrics_lock);
 585
 586         return ret;
 587 }
 588
 589 static int navi10_allocate_dpm_context(struct smu_context *smu)
 590 {
 591         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 592
 593         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 594                                        GFP_KERNEL);
 595         if (!smu_dpm->dpm_context)
 596                 return -ENOMEM;
 597
 598         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 599
 600         return 0;
 601 }
 602
 603 static int navi10_init_smc_tables(struct smu_context *smu)
 604 {
 605         int ret = 0;
 606
 607         ret = navi10_tables_init(smu);
 608         if (ret)
 609                 return ret;
 610
 611         ret = navi10_allocate_dpm_context(smu);
 612         if (ret)
 613                 return ret;
 614
 615         return smu_v11_0_init_smc_tables(smu);
 616 }
 617
 618 static int navi10_set_default_dpm_table(struct smu_context *smu)
 619 {
 620         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 621         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 622         struct smu_11_0_dpm_table *dpm_table;
 623         int ret = 0;
 624
 625         /* socclk dpm table setup */
 626         dpm_table = &dpm_context->dpm_tables.soc_table;
 627         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 628                 ret = smu_v11_0_set_single_dpm_table(smu,
 629                                                      SMU_SOCCLK,
 630                                                      dpm_table);
 631                 if (ret)
 632                         return ret;
 633                 dpm_table->is_fine_grained =
 634                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 635         } else {
 636                 dpm_table->count = 1;
 637                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 638                 dpm_table->dpm_levels[0].enabled = true;
 639                 dpm_table->min = dpm_table->dpm_levels[0].value;
 640                 dpm_table->max = dpm_table->dpm_levels[0].value;
 641         }
 642
 643         /* gfxclk dpm table setup */
 644         dpm_table = &dpm_context->dpm_tables.gfx_table;
 645         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 646                 ret = smu_v11_0_set_single_dpm_table(smu,
 647                                                      SMU_GFXCLK,
 648                                                      dpm_table);
 649                 if (ret)
 650                         return ret;
 651                 dpm_table->is_fine_grained =
 652                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 653         } else {
 654                 dpm_table->count = 1;
 655                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 656                 dpm_table->dpm_levels[0].enabled = true;
 657                 dpm_table->min = dpm_table->dpm_levels[0].value;
 658                 dpm_table->max = dpm_table->dpm_levels[0].value;
 659         }
 660
 661         /* uclk dpm table setup */
 662         dpm_table = &dpm_context->dpm_tables.uclk_table;
 663         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 664                 ret = smu_v11_0_set_single_dpm_table(smu,
 665                                                      SMU_UCLK,
 666                                                      dpm_table);
 667                 if (ret)
 668                         return ret;
 669                 dpm_table->is_fine_grained =
 670                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 671         } else {
 672                 dpm_table->count = 1;
 673                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 674                 dpm_table->dpm_levels[0].enabled = true;
 675                 dpm_table->min = dpm_table->dpm_levels[0].value;
 676                 dpm_table->max = dpm_table->dpm_levels[0].value;
 677         }
 678
 679         /* vclk dpm table setup */
 680         dpm_table = &dpm_context->dpm_tables.vclk_table;
 681         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 682                 ret = smu_v11_0_set_single_dpm_table(smu,
 683                                                      SMU_VCLK,
 684                                                      dpm_table);
 685                 if (ret)
 686                         return ret;
 687                 dpm_table->is_fine_grained =
 688                         !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
 689         } else {
 690                 dpm_table->count = 1;
 691                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 692                 dpm_table->dpm_levels[0].enabled = true;
 693                 dpm_table->min = dpm_table->dpm_levels[0].value;
 694                 dpm_table->max = dpm_table->dpm_levels[0].value;
 695         }
 696
 697         /* dclk dpm table setup */
 698         dpm_table = &dpm_context->dpm_tables.dclk_table;
 699         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 700                 ret = smu_v11_0_set_single_dpm_table(smu,
 701                                                      SMU_DCLK,
 702                                                      dpm_table);
 703                 if (ret)
 704                         return ret;
 705                 dpm_table->is_fine_grained =
 706                         !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
 707         } else {
 708                 dpm_table->count = 1;
 709                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 710                 dpm_table->dpm_levels[0].enabled = true;
 711                 dpm_table->min = dpm_table->dpm_levels[0].value;
 712                 dpm_table->max = dpm_table->dpm_levels[0].value;
 713         }
 714
 715         /* dcefclk dpm table setup */
 716         dpm_table = &dpm_context->dpm_tables.dcef_table;
 717         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 718                 ret = smu_v11_0_set_single_dpm_table(smu,
 719                                                      SMU_DCEFCLK,
 720                                                      dpm_table);
 721                 if (ret)
 722                         return ret;
 723                 dpm_table->is_fine_grained =
 724                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 725         } else {
 726                 dpm_table->count = 1;
 727                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 728                 dpm_table->dpm_levels[0].enabled = true;
 729                 dpm_table->min = dpm_table->dpm_levels[0].value;
 730                 dpm_table->max = dpm_table->dpm_levels[0].value;
 731         }
 732
 733         /* pixelclk dpm table setup */
 734         dpm_table = &dpm_context->dpm_tables.pixel_table;
 735         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 736                 ret = smu_v11_0_set_single_dpm_table(smu,
 737                                                      SMU_PIXCLK,
 738                                                      dpm_table);
 739                 if (ret)
 740                         return ret;
 741                 dpm_table->is_fine_grained =
 742                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 743         } else {
 744                 dpm_table->count = 1;
 745                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 746                 dpm_table->dpm_levels[0].enabled = true;
 747                 dpm_table->min = dpm_table->dpm_levels[0].value;
 748                 dpm_table->max = dpm_table->dpm_levels[0].value;
 749         }
 750
 751         /* displayclk dpm table setup */
 752         dpm_table = &dpm_context->dpm_tables.display_table;
 753         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 754                 ret = smu_v11_0_set_single_dpm_table(smu,
 755                                                      SMU_DISPCLK,
 756                                                      dpm_table);
 757                 if (ret)
 758                         return ret;
 759                 dpm_table->is_fine_grained =
 760                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 761         } else {
 762                 dpm_table->count = 1;
 763                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 764                 dpm_table->dpm_levels[0].enabled = true;
 765                 dpm_table->min = dpm_table->dpm_levels[0].value;
 766                 dpm_table->max = dpm_table->dpm_levels[0].value;
 767         }
 768
 769         /* phyclk dpm table setup */
 770         dpm_table = &dpm_context->dpm_tables.phy_table;
 771         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 772                 ret = smu_v11_0_set_single_dpm_table(smu,
 773                                                      SMU_PHYCLK,
 774                                                      dpm_table);
 775                 if (ret)
 776                         return ret;
 777                 dpm_table->is_fine_grained =
 778                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 779         } else {
 780                 dpm_table->count = 1;
 781                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 782                 dpm_table->dpm_levels[0].enabled = true;
 783                 dpm_table->min = dpm_table->dpm_levels[0].value;
 784                 dpm_table->max = dpm_table->dpm_levels[0].value;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 791 {
 792         int ret = 0;
 793
 794         if (enable) {
 795                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 796                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 797                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
 798                         if (ret)
 799                                 return ret;
 800                 }
 801         } else {
 802                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 803                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 804                         if (ret)
 805                                 return ret;
 806                 }
 807         }
 808
 809         return ret;
 810 }
 811
 812 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 813 {
 814         int ret = 0;
 815
 816         if (enable) {
 817                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 818                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
 819                         if (ret)
 820                                 return ret;
 821                 }
 822         } else {
 823                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 824                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
 825                         if (ret)
 826                                 return ret;
 827                 }
 828         }
 829
 830         return ret;
 831 }
 832
 833 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 834                                        enum smu_clk_type clk_type,
 835                                        uint32_t *value)
 836 {
 837         MetricsMember_t member_type;
 838         int clk_id = 0;
 839
 840         clk_id = smu_cmn_to_asic_specific_index(smu,
 841                                                 CMN2ASIC_MAPPING_CLK,
 842                                                 clk_type);
 843         if (clk_id < 0)
 844                 return clk_id;
 845
 846         switch (clk_id) {
 847         case PPCLK_GFXCLK:
 848                 member_type = METRICS_CURR_GFXCLK;
 849                 break;
 850         case PPCLK_UCLK:
 851                 member_type = METRICS_CURR_UCLK;
 852                 break;
 853         case PPCLK_SOCCLK:
 854                 member_type = METRICS_CURR_SOCCLK;
 855                 break;
 856         case PPCLK_VCLK:
 857                 member_type = METRICS_CURR_VCLK;
 858                 break;
 859         case PPCLK_DCLK:
 860                 member_type = METRICS_CURR_DCLK;
 861                 break;
 862         case PPCLK_DCEFCLK:
 863                 member_type = METRICS_CURR_DCEFCLK;
 864                 break;
 865         default:
 866                 return -EINVAL;
 867         }
 868
 869         return navi10_get_smu_metrics_data(smu,
 870                                            member_type,
 871                                            value);
 872 }
 873
 874 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 875 {
 876         PPTable_t *pptable = smu->smu_table.driver_pptable;
 877         DpmDescriptor_t *dpm_desc = NULL;
 878         uint32_t clk_index = 0;
 879
 880         clk_index = smu_cmn_to_asic_specific_index(smu,
 881                                                    CMN2ASIC_MAPPING_CLK,
 882                                                    clk_type);
 883         dpm_desc = &pptable->DpmDescriptor[clk_index];
 884
 885         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 886         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 887 }
 888
 889 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
 890 {
 891         return od_table->cap[cap];
 892 }
 893
 894 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
 895                                         enum SMU_11_0_ODSETTING_ID setting,
 896                                         uint32_t *min, uint32_t *max)
 897 {
 898         if (min)
 899                 *min = od_table->min[setting];
 900         if (max)
 901                 *max = od_table->max[setting];
 902 }
 903
 904 static int navi10_print_clk_levels(struct smu_context *smu,
 905                         enum smu_clk_type clk_type, char *buf)
 906 {
 907         uint16_t *curve_settings;
 908         int i, size = 0, ret = 0;
 909         uint32_t cur_value = 0, value = 0, count = 0;
 910         uint32_t freq_values[3] = {0};
 911         uint32_t mark_index = 0;
 912         struct smu_table_context *table_context = &smu->smu_table;
 913         uint32_t gen_speed, lane_width;
 914         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 915         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 916         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 917         OverDriveTable_t *od_table =
 918                 (OverDriveTable_t *)table_context->overdrive_table;
 919         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 920         uint32_t min_value, max_value;
 921
 922         switch (clk_type) {
 923         case SMU_GFXCLK:
 924         case SMU_SCLK:
 925         case SMU_SOCCLK:
 926         case SMU_MCLK:
 927         case SMU_UCLK:
 928         case SMU_FCLK:
 929         case SMU_DCEFCLK:
 930                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 931                 if (ret)
 932                         return size;
 933
 934                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 935                 if (ret)
 936                         return size;
 937
 938                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 939                         for (i = 0; i < count; i++) {
 940                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 941                                 if (ret)
 942                                         return size;
 943
 944                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 945                                                 cur_value == value ? "*" : "");
 946                         }
 947                 } else {
 948                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 949                         if (ret)
 950                                 return size;
 951                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 952                         if (ret)
 953                                 return size;
 954
 955                         freq_values[1] = cur_value;
 956                         mark_index = cur_value == freq_values[0] ? 0 :
 957                                      cur_value == freq_values[2] ? 2 : 1;
 958                         if (mark_index != 1)
 959                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 960
 961                         for (i = 0; i < 3; i++) {
 962                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 963                                                 i == mark_index ? "*" : "");
 964                         }
 965
 966                 }
 967                 break;
 968         case SMU_PCIE:
 969                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 970                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 971                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 972                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 973                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 974                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 975                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 976                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 977                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 978                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 979                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 980                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 981                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 982                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 983                                         pptable->LclkFreq[i],
 984                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 985                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 986                                         "*" : "");
 987                 break;
 988         case SMU_OD_SCLK:
 989                 if (!smu->od_enabled || !od_table || !od_settings)
 990                         break;
 991                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
 992                         break;
 993                 size += sprintf(buf + size, "OD_SCLK:\n");
 994                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 995                 break;
 996         case SMU_OD_MCLK:
 997                 if (!smu->od_enabled || !od_table || !od_settings)
 998                         break;
 999                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1000                         break;
1001                 size += sprintf(buf + size, "OD_MCLK:\n");
1002                 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
1003                 break;
1004         case SMU_OD_VDDC_CURVE:
1005                 if (!smu->od_enabled || !od_table || !od_settings)
1006                         break;
1007                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1008                         break;
1009                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
1010                 for (i = 0; i < 3; i++) {
1011                         switch (i) {
1012                         case 0:
1013                                 curve_settings = &od_table->GfxclkFreq1;
1014                                 break;
1015                         case 1:
1016                                 curve_settings = &od_table->GfxclkFreq2;
1017                                 break;
1018                         case 2:
1019                                 curve_settings = &od_table->GfxclkFreq3;
1020                                 break;
1021                         default:
1022                                 break;
1023                         }
1024                         size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1025                 }
1026                 break;
1027         case SMU_OD_RANGE:
1028                 if (!smu->od_enabled || !od_table || !od_settings)
1029                         break;
1030                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1031
1032                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1033                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1034                                                     &min_value, NULL);
1035                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1036                                                     NULL, &max_value);
1037                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1038                                         min_value, max_value);
1039                 }
1040
1041                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1042                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1043                                                     &min_value, &max_value);
1044                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1045                                         min_value, max_value);
1046                 }
1047
1048                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1049                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1050                                                     &min_value, &max_value);
1051                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1052                                         min_value, max_value);
1053                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1054                                                     &min_value, &max_value);
1055                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1056                                         min_value, max_value);
1057                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1058                                                     &min_value, &max_value);
1059                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1060                                         min_value, max_value);
1061                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1062                                                     &min_value, &max_value);
1063                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1064                                         min_value, max_value);
1065                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1066                                                     &min_value, &max_value);
1067                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1068                                         min_value, max_value);
1069                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1070                                                     &min_value, &max_value);
1071                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1072                                         min_value, max_value);
1073                 }
1074
1075                 break;
1076         default:
1077                 break;
1078         }
1079
1080         return size;
1081 }
1082
1083 static int navi10_force_clk_levels(struct smu_context *smu,
1084                                    enum smu_clk_type clk_type, uint32_t mask)
1085 {
1086
1087         int ret = 0, size = 0;
1088         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1089
1090         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1091         soft_max_level = mask ? (fls(mask) - 1) : 0;
1092
1093         switch (clk_type) {
1094         case SMU_GFXCLK:
1095         case SMU_SCLK:
1096         case SMU_SOCCLK:
1097         case SMU_MCLK:
1098         case SMU_UCLK:
1099         case SMU_DCEFCLK:
1100         case SMU_FCLK:
1101                 /* There is only 2 levels for fine grained DPM */
1102                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1103                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1104                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1105                 }
1106
1107                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1108                 if (ret)
1109                         return size;
1110
1111                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1112                 if (ret)
1113                         return size;
1114
1115                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1116                 if (ret)
1117                         return size;
1118                 break;
1119         default:
1120                 break;
1121         }
1122
1123         return size;
1124 }
1125
1126 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1127 {
1128         struct smu_11_0_dpm_context *dpm_context =
1129                                 smu->smu_dpm.dpm_context;
1130         struct smu_11_0_dpm_table *gfx_table =
1131                                 &dpm_context->dpm_tables.gfx_table;
1132         struct smu_11_0_dpm_table *mem_table =
1133                                 &dpm_context->dpm_tables.uclk_table;
1134         struct smu_11_0_dpm_table *soc_table =
1135                                 &dpm_context->dpm_tables.soc_table;
1136         struct smu_umd_pstate_table *pstate_table =
1137                                 &smu->pstate_table;
1138         struct amdgpu_device *adev = smu->adev;
1139         uint32_t sclk_freq;
1140
1141         pstate_table->gfxclk_pstate.min = gfx_table->min;
1142         switch (adev->asic_type) {
1143         case CHIP_NAVI10:
1144                 switch (adev->pdev->revision) {
1145                 case 0xf0: /* XTX */
1146                 case 0xc0:
1147                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1148                         break;
1149                 case 0xf1: /* XT */
1150                 case 0xc1:
1151                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1152                         break;
1153                 default: /* XL */
1154                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1155                         break;
1156                 }
1157                 break;
1158         case CHIP_NAVI14:
1159                 switch (adev->pdev->revision) {
1160                 case 0xc7: /* XT */
1161                 case 0xf4:
1162                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1163                         break;
1164                 case 0xc1: /* XTM */
1165                 case 0xf2:
1166                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1167                         break;
1168                 case 0xc3: /* XLM */
1169                 case 0xf3:
1170                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1171                         break;
1172                 case 0xc5: /* XTX */
1173                 case 0xf6:
1174                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1175                         break;
1176                 default: /* XL */
1177                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1178                         break;
1179                 }
1180                 break;
1181         case CHIP_NAVI12:
1182                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1183                 break;
1184         default:
1185                 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1186                 break;
1187         }
1188         pstate_table->gfxclk_pstate.peak = sclk_freq;
1189
1190         pstate_table->uclk_pstate.min = mem_table->min;
1191         pstate_table->uclk_pstate.peak = mem_table->max;
1192
1193         pstate_table->socclk_pstate.min = soc_table->min;
1194         pstate_table->socclk_pstate.peak = soc_table->max;
1195
1196         if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1197             mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1198             soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1199                 pstate_table->gfxclk_pstate.standard =
1200                         NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1201                 pstate_table->uclk_pstate.standard =
1202                         NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1203                 pstate_table->socclk_pstate.standard =
1204                         NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1205         } else {
1206                 pstate_table->gfxclk_pstate.standard =
1207                         pstate_table->gfxclk_pstate.min;
1208                 pstate_table->uclk_pstate.standard =
1209                         pstate_table->uclk_pstate.min;
1210                 pstate_table->socclk_pstate.standard =
1211                         pstate_table->socclk_pstate.min;
1212         }
1213
1214         return 0;
1215 }
1216
1217 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1218                                                  enum smu_clk_type clk_type,
1219                                                  struct pp_clock_levels_with_latency *clocks)
1220 {
1221         int ret = 0, i = 0;
1222         uint32_t level_count = 0, freq = 0;
1223
1224         switch (clk_type) {
1225         case SMU_GFXCLK:
1226         case SMU_DCEFCLK:
1227         case SMU_SOCCLK:
1228         case SMU_MCLK:
1229         case SMU_UCLK:
1230                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1231                 if (ret)
1232                         return ret;
1233
1234                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1235                 clocks->num_levels = level_count;
1236
1237                 for (i = 0; i < level_count; i++) {
1238                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1239                         if (ret)
1240                                 return ret;
1241
1242                         clocks->data[i].clocks_in_khz = freq * 1000;
1243                         clocks->data[i].latency_in_us = 0;
1244                 }
1245                 break;
1246         default:
1247                 break;
1248         }
1249
1250         return ret;
1251 }
1252
1253 static int navi10_pre_display_config_changed(struct smu_context *smu)
1254 {
1255         int ret = 0;
1256         uint32_t max_freq = 0;
1257
1258         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1259         if (ret)
1260                 return ret;
1261
1262         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1263                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1264                 if (ret)
1265                         return ret;
1266                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1267                 if (ret)
1268                         return ret;
1269         }
1270
1271         return ret;
1272 }
1273
1274 static int navi10_display_config_changed(struct smu_context *smu)
1275 {
1276         int ret = 0;
1277
1278         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1279             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1280             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1281                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1282                                                   smu->display_config->num_display,
1283                                                   NULL);
1284                 if (ret)
1285                         return ret;
1286         }
1287
1288         return ret;
1289 }
1290
1291 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1292 {
1293         if (!value)
1294                 return -EINVAL;
1295
1296         return navi10_get_smu_metrics_data(smu,
1297                                            METRICS_AVERAGE_SOCKETPOWER,
1298                                            value);
1299 }
1300
1301 static int navi10_get_current_activity_percent(struct smu_context *smu,
1302                                                enum amd_pp_sensors sensor,
1303                                                uint32_t *value)
1304 {
1305         int ret = 0;
1306
1307         if (!value)
1308                 return -EINVAL;
1309
1310         switch (sensor) {
1311         case AMDGPU_PP_SENSOR_GPU_LOAD:
1312                 ret = navi10_get_smu_metrics_data(smu,
1313                                                   METRICS_AVERAGE_GFXACTIVITY,
1314                                                   value);
1315                 break;
1316         case AMDGPU_PP_SENSOR_MEM_LOAD:
1317                 ret = navi10_get_smu_metrics_data(smu,
1318                                                   METRICS_AVERAGE_MEMACTIVITY,
1319                                                   value);
1320                 break;
1321         default:
1322                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1323                 return -EINVAL;
1324         }
1325
1326         return ret;
1327 }
1328
1329 static bool navi10_is_dpm_running(struct smu_context *smu)
1330 {
1331         int ret = 0;
1332         uint32_t feature_mask[2];
1333         uint64_t feature_enabled;
1334
1335         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1336         if (ret)
1337                 return false;
1338
1339         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1340
1341         return !!(feature_enabled & SMC_DPM_FEATURE);
1342 }
1343
1344 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1345                                     uint32_t *speed)
1346 {
1347         if (!speed)
1348                 return -EINVAL;
1349
1350         switch (smu_v11_0_get_fan_control_mode(smu)) {
1351         case AMD_FAN_CTRL_AUTO:
1352                 return navi10_get_smu_metrics_data(smu,
1353                                                    METRICS_CURR_FANSPEED,
1354                                                    speed);
1355         default:
1356                 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1357         }
1358 }
1359
1360 static int navi10_get_fan_parameters(struct smu_context *smu)
1361 {
1362         PPTable_t *pptable = smu->smu_table.driver_pptable;
1363
1364         smu->fan_max_rpm = pptable->FanMaximumRpm;
1365
1366         return 0;
1367 }
1368
1369 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1370 {
1371         DpmActivityMonitorCoeffInt_t activity_monitor;
1372         uint32_t i, size = 0;
1373         int16_t workload_type = 0;
1374         static const char *profile_name[] = {
1375                                         "BOOTUP_DEFAULT",
1376                                         "3D_FULL_SCREEN",
1377                                         "POWER_SAVING",
1378                                         "VIDEO",
1379                                         "VR",
1380                                         "COMPUTE",
1381                                         "CUSTOM"};
1382         static const char *title[] = {
1383                         "PROFILE_INDEX(NAME)",
1384                         "CLOCK_TYPE(NAME)",
1385                         "FPS",
1386                         "MinFreqType",
1387                         "MinActiveFreqType",
1388                         "MinActiveFreq",
1389                         "BoosterFreqType",
1390                         "BoosterFreq",
1391                         "PD_Data_limit_c",
1392                         "PD_Data_error_coeff",
1393                         "PD_Data_error_rate_coeff"};
1394         int result = 0;
1395
1396         if (!buf)
1397                 return -EINVAL;
1398
1399         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1400                         title[0], title[1], title[2], title[3], title[4], title[5],
1401                         title[6], title[7], title[8], title[9], title[10]);
1402
1403         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1404                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1405                 workload_type = smu_cmn_to_asic_specific_index(smu,
1406                                                                CMN2ASIC_MAPPING_WORKLOAD,
1407                                                                i);
1408                 if (workload_type < 0)
1409                         return -EINVAL;
1410
1411                 result = smu_cmn_update_table(smu,
1412                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1413                                           (void *)(&activity_monitor), false);
1414                 if (result) {
1415                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1416                         return result;
1417                 }
1418
1419                 size += sprintf(buf + size, "%2d %14s%s:\n",
1420                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1421
1422                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1423                         " ",
1424                         0,
1425                         "GFXCLK",
1426                         activity_monitor.Gfx_FPS,
1427                         activity_monitor.Gfx_MinFreqStep,
1428                         activity_monitor.Gfx_MinActiveFreqType,
1429                         activity_monitor.Gfx_MinActiveFreq,
1430                         activity_monitor.Gfx_BoosterFreqType,
1431                         activity_monitor.Gfx_BoosterFreq,
1432                         activity_monitor.Gfx_PD_Data_limit_c,
1433                         activity_monitor.Gfx_PD_Data_error_coeff,
1434                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1435
1436                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1437                         " ",
1438                         1,
1439                         "SOCCLK",
1440                         activity_monitor.Soc_FPS,
1441                         activity_monitor.Soc_MinFreqStep,
1442                         activity_monitor.Soc_MinActiveFreqType,
1443                         activity_monitor.Soc_MinActiveFreq,
1444                         activity_monitor.Soc_BoosterFreqType,
1445                         activity_monitor.Soc_BoosterFreq,
1446                         activity_monitor.Soc_PD_Data_limit_c,
1447                         activity_monitor.Soc_PD_Data_error_coeff,
1448                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1449
1450                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1451                         " ",
1452                         2,
1453                         "MEMLK",
1454                         activity_monitor.Mem_FPS,
1455                         activity_monitor.Mem_MinFreqStep,
1456                         activity_monitor.Mem_MinActiveFreqType,
1457                         activity_monitor.Mem_MinActiveFreq,
1458                         activity_monitor.Mem_BoosterFreqType,
1459                         activity_monitor.Mem_BoosterFreq,
1460                         activity_monitor.Mem_PD_Data_limit_c,
1461                         activity_monitor.Mem_PD_Data_error_coeff,
1462                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1463         }
1464
1465         return size;
1466 }
1467
1468 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1469 {
1470         DpmActivityMonitorCoeffInt_t activity_monitor;
1471         int workload_type, ret = 0;
1472
1473         smu->power_profile_mode = input[size];
1474
1475         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1476                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1477                 return -EINVAL;
1478         }
1479
1480         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1481
1482                 ret = smu_cmn_update_table(smu,
1483                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1484                                        (void *)(&activity_monitor), false);
1485                 if (ret) {
1486                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1487                         return ret;
1488                 }
1489
1490                 switch (input[0]) {
1491                 case 0: /* Gfxclk */
1492                         activity_monitor.Gfx_FPS = input[1];
1493                         activity_monitor.Gfx_MinFreqStep = input[2];
1494                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1495                         activity_monitor.Gfx_MinActiveFreq = input[4];
1496                         activity_monitor.Gfx_BoosterFreqType = input[5];
1497                         activity_monitor.Gfx_BoosterFreq = input[6];
1498                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1499                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1500                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1501                         break;
1502                 case 1: /* Socclk */
1503                         activity_monitor.Soc_FPS = input[1];
1504                         activity_monitor.Soc_MinFreqStep = input[2];
1505                         activity_monitor.Soc_MinActiveFreqType = input[3];
1506                         activity_monitor.Soc_MinActiveFreq = input[4];
1507                         activity_monitor.Soc_BoosterFreqType = input[5];
1508                         activity_monitor.Soc_BoosterFreq = input[6];
1509                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1510                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1511                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1512                         break;
1513                 case 2: /* Memlk */
1514                         activity_monitor.Mem_FPS = input[1];
1515                         activity_monitor.Mem_MinFreqStep = input[2];
1516                         activity_monitor.Mem_MinActiveFreqType = input[3];
1517                         activity_monitor.Mem_MinActiveFreq = input[4];
1518                         activity_monitor.Mem_BoosterFreqType = input[5];
1519                         activity_monitor.Mem_BoosterFreq = input[6];
1520                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1521                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1522                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1523                         break;
1524                 }
1525
1526                 ret = smu_cmn_update_table(smu,
1527                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1528                                        (void *)(&activity_monitor), true);
1529                 if (ret) {
1530                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1531                         return ret;
1532                 }
1533         }
1534
1535         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1536         workload_type = smu_cmn_to_asic_specific_index(smu,
1537                                                        CMN2ASIC_MAPPING_WORKLOAD,
1538                                                        smu->power_profile_mode);
1539         if (workload_type < 0)
1540                 return -EINVAL;
1541         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1542                                     1 << workload_type, NULL);
1543
1544         return ret;
1545 }
1546
1547 static int navi10_notify_smc_display_config(struct smu_context *smu)
1548 {
1549         struct smu_clocks min_clocks = {0};
1550         struct pp_display_clock_request clock_req;
1551         int ret = 0;
1552
1553         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1554         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1555         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1556
1557         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1558                 clock_req.clock_type = amd_pp_dcef_clock;
1559                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1560
1561                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1562                 if (!ret) {
1563                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1564                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1565                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1566                                                                   min_clocks.dcef_clock_in_sr/100,
1567                                                                   NULL);
1568                                 if (ret) {
1569                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1570                                         return ret;
1571                                 }
1572                         }
1573                 } else {
1574                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1575                 }
1576         }
1577
1578         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1579                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1580                 if (ret) {
1581                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1582                         return ret;
1583                 }
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int navi10_set_watermarks_table(struct smu_context *smu,
1590                                        struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1591 {
1592         Watermarks_t *table = smu->smu_table.watermarks_table;
1593         int ret = 0;
1594         int i;
1595
1596         if (clock_ranges) {
1597                 if (clock_ranges->num_wm_dmif_sets > 4 ||
1598                     clock_ranges->num_wm_mcif_sets > 4)
1599                         return -EINVAL;
1600
1601                 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1602                         table->WatermarkRow[1][i].MinClock =
1603                                 cpu_to_le16((uint16_t)
1604                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1605                                 1000));
1606                         table->WatermarkRow[1][i].MaxClock =
1607                                 cpu_to_le16((uint16_t)
1608                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1609                                 1000));
1610                         table->WatermarkRow[1][i].MinUclk =
1611                                 cpu_to_le16((uint16_t)
1612                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1613                                 1000));
1614                         table->WatermarkRow[1][i].MaxUclk =
1615                                 cpu_to_le16((uint16_t)
1616                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1617                                 1000));
1618                         table->WatermarkRow[1][i].WmSetting = (uint8_t)
1619                                         clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1620                 }
1621
1622                 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1623                         table->WatermarkRow[0][i].MinClock =
1624                                 cpu_to_le16((uint16_t)
1625                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1626                                 1000));
1627                         table->WatermarkRow[0][i].MaxClock =
1628                                 cpu_to_le16((uint16_t)
1629                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1630                                 1000));
1631                         table->WatermarkRow[0][i].MinUclk =
1632                                 cpu_to_le16((uint16_t)
1633                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1634                                 1000));
1635                         table->WatermarkRow[0][i].MaxUclk =
1636                                 cpu_to_le16((uint16_t)
1637                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1638                                 1000));
1639                         table->WatermarkRow[0][i].WmSetting = (uint8_t)
1640                                         clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1641                 }
1642
1643                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1644         }
1645
1646         /* pass data to smu controller */
1647         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1648              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1649                 ret = smu_cmn_write_watermarks_table(smu);
1650                 if (ret) {
1651                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1652                         return ret;
1653                 }
1654                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int navi10_thermal_get_temperature(struct smu_context *smu,
1661                                              enum amd_pp_sensors sensor,
1662                                              uint32_t *value)
1663 {
1664         int ret = 0;
1665
1666         if (!value)
1667                 return -EINVAL;
1668
1669         switch (sensor) {
1670         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1671                 ret = navi10_get_smu_metrics_data(smu,
1672                                                   METRICS_TEMPERATURE_HOTSPOT,
1673                                                   value);
1674                 break;
1675         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1676                 ret = navi10_get_smu_metrics_data(smu,
1677                                                   METRICS_TEMPERATURE_EDGE,
1678                                                   value);
1679                 break;
1680         case AMDGPU_PP_SENSOR_MEM_TEMP:
1681                 ret = navi10_get_smu_metrics_data(smu,
1682                                                   METRICS_TEMPERATURE_MEM,
1683                                                   value);
1684                 break;
1685         default:
1686                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1687                 return -EINVAL;
1688         }
1689
1690         return ret;
1691 }
1692
1693 static int navi10_read_sensor(struct smu_context *smu,
1694                                  enum amd_pp_sensors sensor,
1695                                  void *data, uint32_t *size)
1696 {
1697         int ret = 0;
1698         struct smu_table_context *table_context = &smu->smu_table;
1699         PPTable_t *pptable = table_context->driver_pptable;
1700
1701         if(!data || !size)
1702                 return -EINVAL;
1703
1704         mutex_lock(&smu->sensor_lock);
1705         switch (sensor) {
1706         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1707                 *(uint32_t *)data = pptable->FanMaximumRpm;
1708                 *size = 4;
1709                 break;
1710         case AMDGPU_PP_SENSOR_MEM_LOAD:
1711         case AMDGPU_PP_SENSOR_GPU_LOAD:
1712                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1713                 *size = 4;
1714                 break;
1715         case AMDGPU_PP_SENSOR_GPU_POWER:
1716                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1717                 *size = 4;
1718                 break;
1719         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1720         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1721         case AMDGPU_PP_SENSOR_MEM_TEMP:
1722                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1723                 *size = 4;
1724                 break;
1725         case AMDGPU_PP_SENSOR_GFX_MCLK:
1726                 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1727                 *(uint32_t *)data *= 100;
1728                 *size = 4;
1729                 break;
1730         case AMDGPU_PP_SENSOR_GFX_SCLK:
1731                 ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1732                 *(uint32_t *)data *= 100;
1733                 *size = 4;
1734                 break;
1735         case AMDGPU_PP_SENSOR_VDDGFX:
1736                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1737                 *size = 4;
1738                 break;
1739         default:
1740                 ret = -EOPNOTSUPP;
1741                 break;
1742         }
1743         mutex_unlock(&smu->sensor_lock);
1744
1745         return ret;
1746 }
1747
1748 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1749 {
1750         uint32_t num_discrete_levels = 0;
1751         uint16_t *dpm_levels = NULL;
1752         uint16_t i = 0;
1753         struct smu_table_context *table_context = &smu->smu_table;
1754         PPTable_t *driver_ppt = NULL;
1755
1756         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1757                 return -EINVAL;
1758
1759         driver_ppt = table_context->driver_pptable;
1760         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1761         dpm_levels = driver_ppt->FreqTableUclk;
1762
1763         if (num_discrete_levels == 0 || dpm_levels == NULL)
1764                 return -EINVAL;
1765
1766         *num_states = num_discrete_levels;
1767         for (i = 0; i < num_discrete_levels; i++) {
1768                 /* convert to khz */
1769                 *clocks_in_khz = (*dpm_levels) * 1000;
1770                 clocks_in_khz++;
1771                 dpm_levels++;
1772         }
1773
1774         return 0;
1775 }
1776
1777 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1778                                                 struct smu_temperature_range *range)
1779 {
1780         struct smu_table_context *table_context = &smu->smu_table;
1781         struct smu_11_0_powerplay_table *powerplay_table =
1782                                 table_context->power_play_table;
1783         PPTable_t *pptable = smu->smu_table.driver_pptable;
1784
1785         if (!range)
1786                 return -EINVAL;
1787
1788         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1789
1790         range->max = pptable->TedgeLimit *
1791                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1792         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1793                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1794         range->hotspot_crit_max = pptable->ThotspotLimit *
1795                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1796         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1797                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1798         range->mem_crit_max = pptable->TmemLimit *
1799                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1800         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1801                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1802         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1803
1804         return 0;
1805 }
1806
1807 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1808                                                 bool disable_memory_clock_switch)
1809 {
1810         int ret = 0;
1811         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1812                 (struct smu_11_0_max_sustainable_clocks *)
1813                         smu->smu_table.max_sustainable_clocks;
1814         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1815         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1816
1817         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1818                 return 0;
1819
1820         if(disable_memory_clock_switch)
1821                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1822         else
1823                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1824
1825         if(!ret)
1826                 smu->disable_uclk_switch = disable_memory_clock_switch;
1827
1828         return ret;
1829 }
1830
1831 static int navi10_get_power_limit(struct smu_context *smu)
1832 {
1833         struct smu_11_0_powerplay_table *powerplay_table =
1834                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1835         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1836         PPTable_t *pptable = smu->smu_table.driver_pptable;
1837         uint32_t power_limit, od_percent;
1838
1839         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1840                 /* the last hope to figure out the ppt limit */
1841                 if (!pptable) {
1842                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1843                         return -EINVAL;
1844                 }
1845                 power_limit =
1846                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1847         }
1848         smu->current_power_limit = power_limit;
1849
1850         if (smu->od_enabled &&
1851             navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
1852                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1853
1854                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1855
1856                 power_limit *= (100 + od_percent);
1857                 power_limit /= 100;
1858         }
1859         smu->max_power_limit = power_limit;
1860
1861         return 0;
1862 }
1863
1864 static int navi10_update_pcie_parameters(struct smu_context *smu,
1865                                      uint32_t pcie_gen_cap,
1866                                      uint32_t pcie_width_cap)
1867 {
1868         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1869         PPTable_t *pptable = smu->smu_table.driver_pptable;
1870         uint32_t smu_pcie_arg;
1871         int ret, i;
1872
1873         /* lclk dpm table setup */
1874         for (i = 0; i < MAX_PCIE_CONF; i++) {
1875                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1876                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1877         }
1878
1879         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1880                 smu_pcie_arg = (i << 16) |
1881                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1882                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1883                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1884                 ret = smu_cmn_send_smc_msg_with_param(smu,
1885                                           SMU_MSG_OverridePcieParameters,
1886                                           smu_pcie_arg,
1887                                           NULL);
1888
1889                 if (ret)
1890                         return ret;
1891
1892                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1893                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1894                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1895                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static inline void navi10_dump_od_table(struct smu_context *smu,
1902                                         OverDriveTable_t *od_table)
1903 {
1904         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1905         dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1906         dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1907         dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1908         dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
1909         dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1910 }
1911
1912 static int navi10_od_setting_check_range(struct smu_context *smu,
1913                                          struct smu_11_0_overdrive_table *od_table,
1914                                          enum SMU_11_0_ODSETTING_ID setting,
1915                                          uint32_t value)
1916 {
1917         if (value < od_table->min[setting]) {
1918                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1919                 return -EINVAL;
1920         }
1921         if (value > od_table->max[setting]) {
1922                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1923                 return -EINVAL;
1924         }
1925         return 0;
1926 }
1927
1928 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1929                                                      uint16_t *voltage,
1930                                                      uint32_t freq)
1931 {
1932         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
1933         uint32_t value = 0;
1934         int ret;
1935
1936         ret = smu_cmn_send_smc_msg_with_param(smu,
1937                                           SMU_MSG_GetVoltageByDpm,
1938                                           param,
1939                                           &value);
1940         if (ret) {
1941                 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1942                 return ret;
1943         }
1944
1945         *voltage = (uint16_t)value;
1946
1947         return 0;
1948 }
1949
1950 static bool navi10_is_baco_supported(struct smu_context *smu)
1951 {
1952         struct amdgpu_device *adev = smu->adev;
1953         uint32_t val;
1954
1955         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1956                 return false;
1957
1958         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1959         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1960 }
1961
1962 static int navi10_set_default_od_settings(struct smu_context *smu)
1963 {
1964         OverDriveTable_t *od_table =
1965                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1966         OverDriveTable_t *boot_od_table =
1967                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1968         int ret = 0;
1969
1970         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
1971         if (ret) {
1972                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1973                 return ret;
1974         }
1975
1976         if (!od_table->GfxclkVolt1) {
1977                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1978                                                                 &od_table->GfxclkVolt1,
1979                                                                 od_table->GfxclkFreq1);
1980                 if (ret)
1981                         return ret;
1982         }
1983
1984         if (!od_table->GfxclkVolt2) {
1985                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1986                                                                 &od_table->GfxclkVolt2,
1987                                                                 od_table->GfxclkFreq2);
1988                 if (ret)
1989                         return ret;
1990         }
1991
1992         if (!od_table->GfxclkVolt3) {
1993                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1994                                                                 &od_table->GfxclkVolt3,
1995                                                                 od_table->GfxclkFreq3);
1996                 if (ret)
1997                         return ret;
1998         }
1999
2000         memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2001
2002         navi10_dump_od_table(smu, od_table);
2003
2004         return 0;
2005 }
2006
2007 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2008         int i;
2009         int ret = 0;
2010         struct smu_table_context *table_context = &smu->smu_table;
2011         OverDriveTable_t *od_table;
2012         struct smu_11_0_overdrive_table *od_settings;
2013         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2014         uint16_t *freq_ptr, *voltage_ptr;
2015         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2016
2017         if (!smu->od_enabled) {
2018                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2019                 return -EINVAL;
2020         }
2021
2022         if (!smu->od_settings) {
2023                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2024                 return -ENOENT;
2025         }
2026
2027         od_settings = smu->od_settings;
2028
2029         switch (type) {
2030         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2031                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2032                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2033                         return -ENOTSUPP;
2034                 }
2035                 if (!table_context->overdrive_table) {
2036                         dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2037                         return -EINVAL;
2038                 }
2039                 for (i = 0; i < size; i += 2) {
2040                         if (i + 2 > size) {
2041                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2042                                 return -EINVAL;
2043                         }
2044                         switch (input[i]) {
2045                         case 0:
2046                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2047                                 freq_ptr = &od_table->GfxclkFmin;
2048                                 if (input[i + 1] > od_table->GfxclkFmax) {
2049                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2050                                                 input[i + 1],
2051                                                 od_table->GfxclkFmin);
2052                                         return -EINVAL;
2053                                 }
2054                                 break;
2055                         case 1:
2056                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2057                                 freq_ptr = &od_table->GfxclkFmax;
2058                                 if (input[i + 1] < od_table->GfxclkFmin) {
2059                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2060                                                 input[i + 1],
2061                                                 od_table->GfxclkFmax);
2062                                         return -EINVAL;
2063                                 }
2064                                 break;
2065                         default:
2066                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2067                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2068                                 return -EINVAL;
2069                         }
2070                         ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2071                         if (ret)
2072                                 return ret;
2073                         *freq_ptr = input[i + 1];
2074                 }
2075                 break;
2076         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2077                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2078                         dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2079                         return -ENOTSUPP;
2080                 }
2081                 if (size < 2) {
2082                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2083                         return -EINVAL;
2084                 }
2085                 if (input[0] != 1) {
2086                         dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2087                         dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2088                         return -EINVAL;
2089                 }
2090                 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2091                 if (ret)
2092                         return ret;
2093                 od_table->UclkFmax = input[1];
2094                 break;
2095         case PP_OD_RESTORE_DEFAULT_TABLE:
2096                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2097                         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2098                         return -EINVAL;
2099                 }
2100                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2101                 break;
2102         case PP_OD_COMMIT_DPM_TABLE:
2103                 navi10_dump_od_table(smu, od_table);
2104                 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2105                 if (ret) {
2106                         dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2107                         return ret;
2108                 }
2109                 break;
2110         case PP_OD_EDIT_VDDC_CURVE:
2111                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2112                         dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2113                         return -ENOTSUPP;
2114                 }
2115                 if (size < 3) {
2116                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2117                         return -EINVAL;
2118                 }
2119                 if (!od_table) {
2120                         dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2121                         return -EINVAL;
2122                 }
2123
2124                 switch (input[0]) {
2125                 case 0:
2126                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2127                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2128                         freq_ptr = &od_table->GfxclkFreq1;
2129                         voltage_ptr = &od_table->GfxclkVolt1;
2130                         break;
2131                 case 1:
2132                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2133                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2134                         freq_ptr = &od_table->GfxclkFreq2;
2135                         voltage_ptr = &od_table->GfxclkVolt2;
2136                         break;
2137                 case 2:
2138                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2139                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2140                         freq_ptr = &od_table->GfxclkFreq3;
2141                         voltage_ptr = &od_table->GfxclkVolt3;
2142                         break;
2143                 default:
2144                         dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2145                         dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2146                         return -EINVAL;
2147                 }
2148                 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2149                 if (ret)
2150                         return ret;
2151                 // Allow setting zero to disable the OverDrive VDDC curve
2152                 if (input[2] != 0) {
2153                         ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2154                         if (ret)
2155                                 return ret;
2156                         *freq_ptr = input[1];
2157                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2158                         dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2159                 } else {
2160                         // If setting 0, disable all voltage curve settings
2161                         od_table->GfxclkVolt1 = 0;
2162                         od_table->GfxclkVolt2 = 0;
2163                         od_table->GfxclkVolt3 = 0;
2164                 }
2165                 navi10_dump_od_table(smu, od_table);
2166                 break;
2167         default:
2168                 return -ENOSYS;
2169         }
2170         return ret;
2171 }
2172
2173 static int navi10_run_btc(struct smu_context *smu)
2174 {
2175         int ret = 0;
2176
2177         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2178         if (ret)
2179                 dev_err(smu->adev->dev, "RunBtc failed!\n");
2180
2181         return ret;
2182 }
2183
2184 static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
2185 {
2186         if (adev->asic_type != CHIP_NAVI10)
2187                 return false;
2188
2189         if (adev->pdev->device == 0x731f &&
2190             (adev->pdev->revision == 0xc2 ||
2191              adev->pdev->revision == 0xc3 ||
2192              adev->pdev->revision == 0xca ||
2193              adev->pdev->revision == 0xcb))
2194                 return true;
2195         else
2196                 return false;
2197 }
2198
2199 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2200 {
2201         uint32_t uclk_count, uclk_min, uclk_max;
2202         int ret = 0;
2203
2204         /* This workaround can be applied only with uclk dpm enabled */
2205         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2206                 return 0;
2207
2208         ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2209         if (ret)
2210                 return ret;
2211
2212         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2213         if (ret)
2214                 return ret;
2215
2216         /*
2217          * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2218          * This workaround is needed only when the max uclk frequency
2219          * not greater than that.
2220          */
2221         if (uclk_max > 0x2EE)
2222                 return 0;
2223
2224         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2225         if (ret)
2226                 return ret;
2227
2228         /* Force UCLK out of the highest DPM */
2229         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2230         if (ret)
2231                 return ret;
2232
2233         /* Revert the UCLK Hardmax */
2234         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2235         if (ret)
2236                 return ret;
2237
2238         /*
2239          * In this case, SMU already disabled dummy pstate during enablement
2240          * of UCLK DPM, we have to re-enabled it.
2241          */
2242         return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2243 }
2244
2245 static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2246 {
2247         uint32_t smu_version;
2248         int ret = 0;
2249
2250         if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
2251                 return 0;
2252
2253         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2254         if (ret)
2255                 return ret;
2256
2257         /* This workaround is available only for 42.50 or later SMC firmwares */
2258         if (smu_version < 0x2A3200)
2259                 return 0;
2260
2261         return navi10_umc_hybrid_cdr_workaround(smu);
2262 }
2263
2264 static void navi10_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2265                                   uint8_t address, uint32_t numbytes,
2266                                   uint8_t *data)
2267 {
2268         int i;
2269
2270         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2271
2272         req->I2CcontrollerPort = 0;
2273         req->I2CSpeed = 2;
2274         req->SlaveAddress = address;
2275         req->NumCmds = numbytes;
2276
2277         for (i = 0; i < numbytes; i++) {
2278                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2279
2280                 /* First 2 bytes are always write for lower 2b EEPROM address */
2281                 if (i < 2)
2282                         cmd->Cmd = 1;
2283                 else
2284                         cmd->Cmd = write;
2285
2286
2287                 /* Add RESTART for read  after address filled */
2288                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2289
2290                 /* Add STOP in the end */
2291                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2292
2293                 /* Fill with data regardless if read or write to simplify code */
2294                 cmd->RegisterAddr = data[i];
2295         }
2296 }
2297
2298 static int navi10_i2c_read_data(struct i2c_adapter *control,
2299                                                uint8_t address,
2300                                                uint8_t *data,
2301                                                uint32_t numbytes)
2302 {
2303         uint32_t  i, ret = 0;
2304         SwI2cRequest_t req;
2305         struct amdgpu_device *adev = to_amdgpu_device(control);
2306         struct smu_table_context *smu_table = &adev->smu.smu_table;
2307         struct smu_table *table = &smu_table->driver_table;
2308
2309         memset(&req, 0, sizeof(req));
2310         navi10_fill_i2c_req(&req, false, address, numbytes, data);
2311
2312         mutex_lock(&adev->smu.mutex);
2313         /* Now read data starting with that address */
2314         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2315                                    true);
2316         mutex_unlock(&adev->smu.mutex);
2317
2318         if (!ret) {
2319                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2320
2321                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2322                 for (i = 0; i < numbytes; i++)
2323                         data[i] = res->SwI2cCmds[i].Data;
2324
2325                 dev_dbg(adev->dev, "navi10_i2c_read_data, address = %x, bytes = %d, data :",
2326                                   (uint16_t)address, numbytes);
2327
2328                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2329                                8, 1, data, numbytes, false);
2330         } else
2331                 dev_err(adev->dev, "navi10_i2c_read_data - error occurred :%x", ret);
2332
2333         return ret;
2334 }
2335
2336 static int navi10_i2c_write_data(struct i2c_adapter *control,
2337                                                 uint8_t address,
2338                                                 uint8_t *data,
2339                                                 uint32_t numbytes)
2340 {
2341         uint32_t ret;
2342         SwI2cRequest_t req;
2343         struct amdgpu_device *adev = to_amdgpu_device(control);
2344
2345         memset(&req, 0, sizeof(req));
2346         navi10_fill_i2c_req(&req, true, address, numbytes, data);
2347
2348         mutex_lock(&adev->smu.mutex);
2349         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2350         mutex_unlock(&adev->smu.mutex);
2351
2352         if (!ret) {
2353                 dev_dbg(adev->dev, "navi10_i2c_write(), address = %x, bytes = %d , data: ",
2354                                          (uint16_t)address, numbytes);
2355
2356                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2357                                8, 1, data, numbytes, false);
2358                 /*
2359                  * According to EEPROM spec there is a MAX of 10 ms required for
2360                  * EEPROM to flush internal RX buffer after STOP was issued at the
2361                  * end of write transaction. During this time the EEPROM will not be
2362                  * responsive to any more commands - so wait a bit more.
2363                  */
2364                 msleep(10);
2365
2366         } else
2367                 dev_err(adev->dev, "navi10_i2c_write- error occurred :%x", ret);
2368
2369         return ret;
2370 }
2371
2372 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2373                               struct i2c_msg *msgs, int num)
2374 {
2375         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2376         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2377
2378         for (i = 0; i < num; i++) {
2379                 /*
2380                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2381                  * once and hence the data needs to be spliced into chunks and sent each
2382                  * chunk separately
2383                  */
2384                 data_size = msgs[i].len - 2;
2385                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2386                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2387                 data_ptr = msgs[i].buf + 2;
2388
2389                 for (j = 0; j < data_size / data_chunk_size; j++) {
2390                         /* Insert the EEPROM dest addess, bits 0-15 */
2391                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2392                         data_chunk[1] = (next_eeprom_addr & 0xff);
2393
2394                         if (msgs[i].flags & I2C_M_RD) {
2395                                 ret = navi10_i2c_read_data(i2c_adap,
2396                                                              (uint8_t)msgs[i].addr,
2397                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2398
2399                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2400                         } else {
2401
2402                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2403
2404                                 ret = navi10_i2c_write_data(i2c_adap,
2405                                                               (uint8_t)msgs[i].addr,
2406                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2407                         }
2408
2409                         if (ret) {
2410                                 num = -EIO;
2411                                 goto fail;
2412                         }
2413
2414                         next_eeprom_addr += data_chunk_size;
2415                         data_ptr += data_chunk_size;
2416                 }
2417
2418                 if (data_size % data_chunk_size) {
2419                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2420                         data_chunk[1] = (next_eeprom_addr & 0xff);
2421
2422                         if (msgs[i].flags & I2C_M_RD) {
2423                                 ret = navi10_i2c_read_data(i2c_adap,
2424                                                              (uint8_t)msgs[i].addr,
2425                                                              data_chunk, (data_size % data_chunk_size) + 2);
2426
2427                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2428                         } else {
2429                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2430
2431                                 ret = navi10_i2c_write_data(i2c_adap,
2432                                                               (uint8_t)msgs[i].addr,
2433                                                               data_chunk, (data_size % data_chunk_size) + 2);
2434                         }
2435
2436                         if (ret) {
2437                                 num = -EIO;
2438                                 goto fail;
2439                         }
2440                 }
2441         }
2442
2443 fail:
2444         return num;
2445 }
2446
2447 static u32 navi10_i2c_func(struct i2c_adapter *adap)
2448 {
2449         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2450 }
2451
2452
2453 static const struct i2c_algorithm navi10_i2c_algo = {
2454         .master_xfer = navi10_i2c_xfer,
2455         .functionality = navi10_i2c_func,
2456 };
2457
2458 static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2459 {
2460         struct amdgpu_device *adev = to_amdgpu_device(control);
2461         int res;
2462
2463         control->owner = THIS_MODULE;
2464         control->class = I2C_CLASS_SPD;
2465         control->dev.parent = &adev->pdev->dev;
2466         control->algo = &navi10_i2c_algo;
2467         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2468
2469         res = i2c_add_adapter(control);
2470         if (res)
2471                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2472
2473         return res;
2474 }
2475
2476 static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2477 {
2478         i2c_del_adapter(control);
2479 }
2480
2481 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2482                                       void **table)
2483 {
2484         struct smu_table_context *smu_table = &smu->smu_table;
2485         struct gpu_metrics_v1_0 *gpu_metrics =
2486                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2487         struct amdgpu_device *adev = smu->adev;
2488         SmuMetrics_NV12_t nv12_metrics = { 0 };
2489         SmuMetrics_t metrics;
2490         int ret = 0;
2491
2492         mutex_lock(&smu->metrics_lock);
2493
2494         ret = smu_cmn_get_metrics_table_locked(smu,
2495                                                NULL,
2496                                                true);
2497         if (ret) {
2498                 mutex_unlock(&smu->metrics_lock);
2499                 return ret;
2500         }
2501
2502         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2503         if (adev->asic_type == CHIP_NAVI12)
2504                 memcpy(&nv12_metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
2505
2506         mutex_unlock(&smu->metrics_lock);
2507
2508         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2509
2510         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2511         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2512         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2513         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2514         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2515         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2516
2517         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2518         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2519
2520         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2521
2522         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2523         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2524         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2525
2526         if (adev->asic_type == CHIP_NAVI12) {
2527                 gpu_metrics->energy_accumulator = nv12_metrics.EnergyAccumulator;
2528                 gpu_metrics->average_vclk0_frequency = nv12_metrics.AverageVclkFrequency;
2529                 gpu_metrics->average_dclk0_frequency = nv12_metrics.AverageDclkFrequency;
2530                 gpu_metrics->average_mm_activity = nv12_metrics.VcnActivityPercentage;
2531         }
2532
2533         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2534         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2535         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2536         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2537         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2538
2539         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2540
2541         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2542
2543         gpu_metrics->pcie_link_width =
2544                         smu_v11_0_get_current_pcie_link_width(smu);
2545         gpu_metrics->pcie_link_speed =
2546                         smu_v11_0_get_current_pcie_link_speed(smu);
2547
2548         *table = (void *)gpu_metrics;
2549
2550         return sizeof(struct gpu_metrics_v1_0);
2551 }
2552
2553 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
2554 {
2555         struct amdgpu_device *adev = smu->adev;
2556         uint32_t param = 0;
2557
2558         /* Navi12 does not support this */
2559         if (adev->asic_type == CHIP_NAVI12)
2560                 return 0;
2561
2562         /* Workaround for WS SKU */
2563         if (adev->pdev->device == 0x7312 &&
2564             adev->pdev->revision == 0)
2565                 param = 0xD188;
2566
2567         return smu_cmn_send_smc_msg_with_param(smu,
2568                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2569                                                param,
2570                                                NULL);
2571 }
2572
2573 static int navi10_post_smu_init(struct smu_context *smu)
2574 {
2575         struct smu_feature *feature = &smu->smu_feature;
2576         struct amdgpu_device *adev = smu->adev;
2577         uint64_t feature_mask = 0;
2578         int ret = 0;
2579
2580         /* For Naiv1x, enable these features only after DAL initialization */
2581         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
2582                 feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
2583
2584         /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
2585         if (!(is_asic_secure(smu) &&
2586              (adev->asic_type == CHIP_NAVI10) &&
2587              (adev->rev_id == 0)) &&
2588             (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
2589                 feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
2590                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
2591                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
2592
2593         if (!feature_mask)
2594                 return 0;
2595
2596         bitmap_or(feature->allowed,
2597                   feature->allowed,
2598                   (unsigned long *)(&feature_mask),
2599                   SMU_FEATURE_MAX);
2600
2601         ret = smu_cmn_feature_update_enable_state(smu,
2602                                                   feature_mask,
2603                                                   true);
2604         if (ret) {
2605                 dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
2606                 return ret;
2607         }
2608
2609         ret = navi10_disable_umc_cdr_12gbps_workaround(smu);
2610         if (ret)
2611                 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
2612
2613         return ret;
2614 }
2615
2616 static const struct pptable_funcs navi10_ppt_funcs = {
2617         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2618         .set_default_dpm_table = navi10_set_default_dpm_table,
2619         .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
2620         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2621         .i2c_init = navi10_i2c_control_init,
2622         .i2c_fini = navi10_i2c_control_fini,
2623         .print_clk_levels = navi10_print_clk_levels,
2624         .force_clk_levels = navi10_force_clk_levels,
2625         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2626         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2627         .pre_display_config_changed = navi10_pre_display_config_changed,
2628         .display_config_changed = navi10_display_config_changed,
2629         .notify_smc_display_config = navi10_notify_smc_display_config,
2630         .is_dpm_running = navi10_is_dpm_running,
2631         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2632         .get_power_profile_mode = navi10_get_power_profile_mode,
2633         .set_power_profile_mode = navi10_set_power_profile_mode,
2634         .set_watermarks_table = navi10_set_watermarks_table,
2635         .read_sensor = navi10_read_sensor,
2636         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2637         .set_performance_level = smu_v11_0_set_performance_level,
2638         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2639         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2640         .get_power_limit = navi10_get_power_limit,
2641         .update_pcie_parameters = navi10_update_pcie_parameters,
2642         .init_microcode = smu_v11_0_init_microcode,
2643         .load_microcode = smu_v11_0_load_microcode,
2644         .fini_microcode = smu_v11_0_fini_microcode,
2645         .init_smc_tables = navi10_init_smc_tables,
2646         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2647         .init_power = smu_v11_0_init_power,
2648         .fini_power = smu_v11_0_fini_power,
2649         .check_fw_status = smu_v11_0_check_fw_status,
2650         .setup_pptable = navi10_setup_pptable,
2651         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2652         .check_fw_version = smu_v11_0_check_fw_version,
2653         .write_pptable = smu_cmn_write_pptable,
2654         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2655         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2656         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2657         .system_features_control = smu_v11_0_system_features_control,
2658         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2659         .send_smc_msg = smu_cmn_send_smc_msg,
2660         .init_display_count = smu_v11_0_init_display_count,
2661         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2662         .get_enabled_mask = smu_cmn_get_enabled_mask,
2663         .feature_is_enabled = smu_cmn_feature_is_enabled,
2664         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2665         .notify_display_change = smu_v11_0_notify_display_change,
2666         .set_power_limit = smu_v11_0_set_power_limit,
2667         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2668         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2669         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2670         .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
2671         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2672         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2673         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2674         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2675         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2676         .gfx_off_control = smu_v11_0_gfx_off_control,
2677         .register_irq_handler = smu_v11_0_register_irq_handler,
2678         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2679         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2680         .baco_is_support= navi10_is_baco_supported,
2681         .baco_get_state = smu_v11_0_baco_get_state,
2682         .baco_set_state = smu_v11_0_baco_set_state,
2683         .baco_enter = smu_v11_0_baco_enter,
2684         .baco_exit = smu_v11_0_baco_exit,
2685         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2686         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2687         .set_default_od_settings = navi10_set_default_od_settings,
2688         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2689         .run_btc = navi10_run_btc,
2690         .set_power_source = smu_v11_0_set_power_source,
2691         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2692         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2693         .get_gpu_metrics = navi10_get_gpu_metrics,
2694         .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
2695         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2696         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2697         .get_fan_parameters = navi10_get_fan_parameters,
2698         .post_init = navi10_post_smu_init,
2699 };
2700
2701 void navi10_set_ppt_funcs(struct smu_context *smu)
2702 {
2703         smu->ppt_funcs = &navi10_ppt_funcs;
2704         smu->message_map = navi10_message_map;
2705         smu->clock_map = navi10_clk_map;
2706         smu->feature_map = navi10_feature_mask_map;
2707         smu->table_map = navi10_table_map;
2708         smu->pwr_src_map = navi10_pwr_src_map;
2709         smu->workload_map = navi10_workload_map;
2710 }