2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "soc15_common.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_navi10.h"
38 #include "navi10_ppt.h"
39 #include "smu_v11_0_pptable.h"
40 #include "smu_v11_0_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
48 #include "smu_11_0_cdr_table.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
98 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
99 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
108 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
109 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
110 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
111 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
113 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
115 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
116 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
117 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
118 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
119 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
120 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
121 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
122 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
123 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
126 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
127 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
129 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
130 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
131 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
132 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
133 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
134 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
135 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
136 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
137 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
138 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
139 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
140 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0),
141 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
142 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
143 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
146 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
147 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0),
150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_SOCCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK),
158 CLK_MAP(VCLK, PPCLK_VCLK),
159 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
160 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
161 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
162 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
166 FEA_MAP(DPM_PREFETCHER),
168 FEA_MAP(DPM_GFX_PACE),
173 FEA_MAP(DPM_DCEFCLK),
174 FEA_MAP(MEM_VDDCI_SCALING),
175 FEA_MAP(MEM_MVDD_SCALING),
188 FEA_MAP(RSMU_SMN_CG),
198 FEA_MAP(FAN_CONTROL),
202 FEA_MAP(LED_DISPLAY),
204 FEA_MAP(OUT_OF_BAND_MONITOR),
205 FEA_MAP(TEMP_DEPENDENT_VMIN),
211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
215 TAB_MAP(AVFS_PSM_DEBUG),
216 TAB_MAP(AVFS_FUSE_OVERRIDE),
217 TAB_MAP(PMSTATUSLOG),
218 TAB_MAP(SMU_METRICS),
219 TAB_MAP(DRIVER_SMU_CONFIG),
220 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(I2C_COMMANDS),
226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
241 static bool is_asic_secure(struct smu_context *smu)
243 struct amdgpu_device *adev = smu->adev;
244 bool is_secure = true;
245 uint32_t mp0_fw_intf;
247 mp0_fw_intf = RREG32_PCIE(MP0_Public |
248 (smnMP0_FW_INTF & 0xffffffff));
250 if (!(mp0_fw_intf & (1 << 19)))
257 navi10_get_allowed_feature_mask(struct smu_context *smu,
258 uint32_t *feature_mask, uint32_t num)
260 struct amdgpu_device *adev = smu->adev;
265 memset(feature_mask, 0, sizeof(uint32_t) * num);
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
268 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
269 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
270 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
271 | FEATURE_MASK(FEATURE_PPT_BIT)
272 | FEATURE_MASK(FEATURE_TDC_BIT)
273 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
274 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
275 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
276 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
277 | FEATURE_MASK(FEATURE_THERMAL_BIT)
278 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
279 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
280 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_BACO_BIT)
283 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
284 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
285 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
286 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
288 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
291 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
294 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
297 if (adev->pm.pp_feature & PP_ULV_MASK)
298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
300 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
304 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
306 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
309 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
312 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
315 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
318 if (smu->dc_controlled_by_gpio)
319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
321 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
324 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
325 if (!(is_asic_secure(smu) &&
326 (adev->asic_type == CHIP_NAVI10) &&
327 (adev->rev_id == 0)) &&
328 (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
330 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
331 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
333 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
334 if (is_asic_secure(smu) &&
335 (adev->asic_type == CHIP_NAVI10) &&
337 *(uint64_t *)feature_mask &=
338 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
343 static int navi10_check_powerplay_table(struct smu_context *smu)
345 struct smu_table_context *table_context = &smu->smu_table;
346 struct smu_11_0_powerplay_table *powerplay_table =
347 table_context->power_play_table;
348 struct smu_baco_context *smu_baco = &smu->smu_baco;
350 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
351 smu->dc_controlled_by_gpio = true;
353 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
354 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
355 smu_baco->platform_support = true;
357 table_context->thermal_controller_type =
358 powerplay_table->thermal_controller_type;
361 * Instead of having its own buffer space and get overdrive_table copied,
362 * smu->od_settings just points to the actual overdrive_table
364 smu->od_settings = &powerplay_table->overdrive_table;
369 static int navi10_append_powerplay_table(struct smu_context *smu)
371 struct amdgpu_device *adev = smu->adev;
372 struct smu_table_context *table_context = &smu->smu_table;
373 PPTable_t *smc_pptable = table_context->driver_pptable;
374 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
375 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
378 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
381 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
382 (uint8_t **)&smc_dpm_table);
386 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
387 smc_dpm_table->table_header.format_revision,
388 smc_dpm_table->table_header.content_revision);
390 if (smc_dpm_table->table_header.format_revision != 4) {
391 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
395 switch (smc_dpm_table->table_header.content_revision) {
396 case 5: /* nv10 and nv14 */
397 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
398 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
401 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
402 (uint8_t **)&smc_dpm_table_v4_7);
405 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
406 sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
409 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
410 smc_dpm_table->table_header.content_revision);
414 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
415 /* TODO: remove it once SMU fw fix it */
416 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
422 static int navi10_store_powerplay_table(struct smu_context *smu)
424 struct smu_table_context *table_context = &smu->smu_table;
425 struct smu_11_0_powerplay_table *powerplay_table =
426 table_context->power_play_table;
428 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
434 static int navi10_setup_pptable(struct smu_context *smu)
438 ret = smu_v11_0_setup_pptable(smu);
442 ret = navi10_store_powerplay_table(smu);
446 ret = navi10_append_powerplay_table(smu);
450 ret = navi10_check_powerplay_table(smu);
457 static int navi10_tables_init(struct smu_context *smu)
459 struct smu_table_context *smu_table = &smu->smu_table;
460 struct smu_table *tables = smu_table->tables;
462 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
464 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
465 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
466 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
468 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
469 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
470 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
471 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
472 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
473 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
474 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
475 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
476 AMDGPU_GEM_DOMAIN_VRAM);
478 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
480 if (!smu_table->metrics_table)
482 smu_table->metrics_time = 0;
484 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
485 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
486 if (!smu_table->gpu_metrics_table)
489 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
490 if (!smu_table->watermarks_table)
496 kfree(smu_table->gpu_metrics_table);
498 kfree(smu_table->metrics_table);
503 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
504 MetricsMember_t member,
507 struct smu_table_context *smu_table= &smu->smu_table;
508 SmuMetrics_legacy_t *metrics =
509 (SmuMetrics_legacy_t *)smu_table->metrics_table;
512 mutex_lock(&smu->metrics_lock);
514 ret = smu_cmn_get_metrics_table_locked(smu,
518 mutex_unlock(&smu->metrics_lock);
523 case METRICS_CURR_GFXCLK:
524 *value = metrics->CurrClock[PPCLK_GFXCLK];
526 case METRICS_CURR_SOCCLK:
527 *value = metrics->CurrClock[PPCLK_SOCCLK];
529 case METRICS_CURR_UCLK:
530 *value = metrics->CurrClock[PPCLK_UCLK];
532 case METRICS_CURR_VCLK:
533 *value = metrics->CurrClock[PPCLK_VCLK];
535 case METRICS_CURR_DCLK:
536 *value = metrics->CurrClock[PPCLK_DCLK];
538 case METRICS_CURR_DCEFCLK:
539 *value = metrics->CurrClock[PPCLK_DCEFCLK];
541 case METRICS_AVERAGE_GFXCLK:
542 *value = metrics->AverageGfxclkFrequency;
544 case METRICS_AVERAGE_SOCCLK:
545 *value = metrics->AverageSocclkFrequency;
547 case METRICS_AVERAGE_UCLK:
548 *value = metrics->AverageUclkFrequency;
550 case METRICS_AVERAGE_GFXACTIVITY:
551 *value = metrics->AverageGfxActivity;
553 case METRICS_AVERAGE_MEMACTIVITY:
554 *value = metrics->AverageUclkActivity;
556 case METRICS_AVERAGE_SOCKETPOWER:
557 *value = metrics->AverageSocketPower << 8;
559 case METRICS_TEMPERATURE_EDGE:
560 *value = metrics->TemperatureEdge *
561 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
563 case METRICS_TEMPERATURE_HOTSPOT:
564 *value = metrics->TemperatureHotspot *
565 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
567 case METRICS_TEMPERATURE_MEM:
568 *value = metrics->TemperatureMem *
569 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
571 case METRICS_TEMPERATURE_VRGFX:
572 *value = metrics->TemperatureVrGfx *
573 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
575 case METRICS_TEMPERATURE_VRSOC:
576 *value = metrics->TemperatureVrSoc *
577 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
579 case METRICS_THROTTLER_STATUS:
580 *value = metrics->ThrottlerStatus;
582 case METRICS_CURR_FANSPEED:
583 *value = metrics->CurrFanSpeed;
590 mutex_unlock(&smu->metrics_lock);
595 static int navi10_get_smu_metrics_data(struct smu_context *smu,
596 MetricsMember_t member,
599 struct smu_table_context *smu_table= &smu->smu_table;
600 SmuMetrics_t *metrics =
601 (SmuMetrics_t *)smu_table->metrics_table;
604 mutex_lock(&smu->metrics_lock);
606 ret = smu_cmn_get_metrics_table_locked(smu,
610 mutex_unlock(&smu->metrics_lock);
615 case METRICS_CURR_GFXCLK:
616 *value = metrics->CurrClock[PPCLK_GFXCLK];
618 case METRICS_CURR_SOCCLK:
619 *value = metrics->CurrClock[PPCLK_SOCCLK];
621 case METRICS_CURR_UCLK:
622 *value = metrics->CurrClock[PPCLK_UCLK];
624 case METRICS_CURR_VCLK:
625 *value = metrics->CurrClock[PPCLK_VCLK];
627 case METRICS_CURR_DCLK:
628 *value = metrics->CurrClock[PPCLK_DCLK];
630 case METRICS_CURR_DCEFCLK:
631 *value = metrics->CurrClock[PPCLK_DCEFCLK];
633 case METRICS_AVERAGE_GFXCLK:
634 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
635 *value = metrics->AverageGfxclkFrequencyPreDs;
637 *value = metrics->AverageGfxclkFrequencyPostDs;
639 case METRICS_AVERAGE_SOCCLK:
640 *value = metrics->AverageSocclkFrequency;
642 case METRICS_AVERAGE_UCLK:
643 *value = metrics->AverageUclkFrequencyPostDs;
645 case METRICS_AVERAGE_GFXACTIVITY:
646 *value = metrics->AverageGfxActivity;
648 case METRICS_AVERAGE_MEMACTIVITY:
649 *value = metrics->AverageUclkActivity;
651 case METRICS_AVERAGE_SOCKETPOWER:
652 *value = metrics->AverageSocketPower << 8;
654 case METRICS_TEMPERATURE_EDGE:
655 *value = metrics->TemperatureEdge *
656 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
658 case METRICS_TEMPERATURE_HOTSPOT:
659 *value = metrics->TemperatureHotspot *
660 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
662 case METRICS_TEMPERATURE_MEM:
663 *value = metrics->TemperatureMem *
664 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
666 case METRICS_TEMPERATURE_VRGFX:
667 *value = metrics->TemperatureVrGfx *
668 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
670 case METRICS_TEMPERATURE_VRSOC:
671 *value = metrics->TemperatureVrSoc *
672 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
674 case METRICS_THROTTLER_STATUS:
675 *value = metrics->ThrottlerStatus;
677 case METRICS_CURR_FANSPEED:
678 *value = metrics->CurrFanSpeed;
685 mutex_unlock(&smu->metrics_lock);
690 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
691 MetricsMember_t member,
694 struct smu_table_context *smu_table= &smu->smu_table;
695 SmuMetrics_NV12_legacy_t *metrics =
696 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
699 mutex_lock(&smu->metrics_lock);
701 ret = smu_cmn_get_metrics_table_locked(smu,
705 mutex_unlock(&smu->metrics_lock);
710 case METRICS_CURR_GFXCLK:
711 *value = metrics->CurrClock[PPCLK_GFXCLK];
713 case METRICS_CURR_SOCCLK:
714 *value = metrics->CurrClock[PPCLK_SOCCLK];
716 case METRICS_CURR_UCLK:
717 *value = metrics->CurrClock[PPCLK_UCLK];
719 case METRICS_CURR_VCLK:
720 *value = metrics->CurrClock[PPCLK_VCLK];
722 case METRICS_CURR_DCLK:
723 *value = metrics->CurrClock[PPCLK_DCLK];
725 case METRICS_CURR_DCEFCLK:
726 *value = metrics->CurrClock[PPCLK_DCEFCLK];
728 case METRICS_AVERAGE_GFXCLK:
729 *value = metrics->AverageGfxclkFrequency;
731 case METRICS_AVERAGE_SOCCLK:
732 *value = metrics->AverageSocclkFrequency;
734 case METRICS_AVERAGE_UCLK:
735 *value = metrics->AverageUclkFrequency;
737 case METRICS_AVERAGE_GFXACTIVITY:
738 *value = metrics->AverageGfxActivity;
740 case METRICS_AVERAGE_MEMACTIVITY:
741 *value = metrics->AverageUclkActivity;
743 case METRICS_AVERAGE_SOCKETPOWER:
744 *value = metrics->AverageSocketPower << 8;
746 case METRICS_TEMPERATURE_EDGE:
747 *value = metrics->TemperatureEdge *
748 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
750 case METRICS_TEMPERATURE_HOTSPOT:
751 *value = metrics->TemperatureHotspot *
752 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
754 case METRICS_TEMPERATURE_MEM:
755 *value = metrics->TemperatureMem *
756 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
758 case METRICS_TEMPERATURE_VRGFX:
759 *value = metrics->TemperatureVrGfx *
760 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
762 case METRICS_TEMPERATURE_VRSOC:
763 *value = metrics->TemperatureVrSoc *
764 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
766 case METRICS_THROTTLER_STATUS:
767 *value = metrics->ThrottlerStatus;
769 case METRICS_CURR_FANSPEED:
770 *value = metrics->CurrFanSpeed;
777 mutex_unlock(&smu->metrics_lock);
782 static int navi12_get_smu_metrics_data(struct smu_context *smu,
783 MetricsMember_t member,
786 struct smu_table_context *smu_table= &smu->smu_table;
787 SmuMetrics_NV12_t *metrics =
788 (SmuMetrics_NV12_t *)smu_table->metrics_table;
791 mutex_lock(&smu->metrics_lock);
793 ret = smu_cmn_get_metrics_table_locked(smu,
797 mutex_unlock(&smu->metrics_lock);
802 case METRICS_CURR_GFXCLK:
803 *value = metrics->CurrClock[PPCLK_GFXCLK];
805 case METRICS_CURR_SOCCLK:
806 *value = metrics->CurrClock[PPCLK_SOCCLK];
808 case METRICS_CURR_UCLK:
809 *value = metrics->CurrClock[PPCLK_UCLK];
811 case METRICS_CURR_VCLK:
812 *value = metrics->CurrClock[PPCLK_VCLK];
814 case METRICS_CURR_DCLK:
815 *value = metrics->CurrClock[PPCLK_DCLK];
817 case METRICS_CURR_DCEFCLK:
818 *value = metrics->CurrClock[PPCLK_DCEFCLK];
820 case METRICS_AVERAGE_GFXCLK:
821 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
822 *value = metrics->AverageGfxclkFrequencyPreDs;
824 *value = metrics->AverageGfxclkFrequencyPostDs;
826 case METRICS_AVERAGE_SOCCLK:
827 *value = metrics->AverageSocclkFrequency;
829 case METRICS_AVERAGE_UCLK:
830 *value = metrics->AverageUclkFrequencyPostDs;
832 case METRICS_AVERAGE_GFXACTIVITY:
833 *value = metrics->AverageGfxActivity;
835 case METRICS_AVERAGE_MEMACTIVITY:
836 *value = metrics->AverageUclkActivity;
838 case METRICS_AVERAGE_SOCKETPOWER:
839 *value = metrics->AverageSocketPower << 8;
841 case METRICS_TEMPERATURE_EDGE:
842 *value = metrics->TemperatureEdge *
843 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
845 case METRICS_TEMPERATURE_HOTSPOT:
846 *value = metrics->TemperatureHotspot *
847 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
849 case METRICS_TEMPERATURE_MEM:
850 *value = metrics->TemperatureMem *
851 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
853 case METRICS_TEMPERATURE_VRGFX:
854 *value = metrics->TemperatureVrGfx *
855 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
857 case METRICS_TEMPERATURE_VRSOC:
858 *value = metrics->TemperatureVrSoc *
859 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
861 case METRICS_THROTTLER_STATUS:
862 *value = metrics->ThrottlerStatus;
864 case METRICS_CURR_FANSPEED:
865 *value = metrics->CurrFanSpeed;
872 mutex_unlock(&smu->metrics_lock);
877 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
878 MetricsMember_t member,
881 struct amdgpu_device *adev = smu->adev;
882 uint32_t smu_version;
885 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
887 dev_err(adev->dev, "Failed to get smu version!\n");
891 switch (adev->asic_type) {
893 if (smu_version > 0x00341C00)
894 ret = navi12_get_smu_metrics_data(smu, member, value);
896 ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
901 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
902 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
903 ret = navi10_get_smu_metrics_data(smu, member, value);
905 ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
912 static int navi10_allocate_dpm_context(struct smu_context *smu)
914 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
916 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
918 if (!smu_dpm->dpm_context)
921 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
926 static int navi10_init_smc_tables(struct smu_context *smu)
930 ret = navi10_tables_init(smu);
934 ret = navi10_allocate_dpm_context(smu);
938 return smu_v11_0_init_smc_tables(smu);
941 static int navi10_set_default_dpm_table(struct smu_context *smu)
943 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
944 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
945 struct smu_11_0_dpm_table *dpm_table;
948 /* socclk dpm table setup */
949 dpm_table = &dpm_context->dpm_tables.soc_table;
950 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
951 ret = smu_v11_0_set_single_dpm_table(smu,
956 dpm_table->is_fine_grained =
957 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
959 dpm_table->count = 1;
960 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
961 dpm_table->dpm_levels[0].enabled = true;
962 dpm_table->min = dpm_table->dpm_levels[0].value;
963 dpm_table->max = dpm_table->dpm_levels[0].value;
966 /* gfxclk dpm table setup */
967 dpm_table = &dpm_context->dpm_tables.gfx_table;
968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
969 ret = smu_v11_0_set_single_dpm_table(smu,
974 dpm_table->is_fine_grained =
975 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
977 dpm_table->count = 1;
978 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
979 dpm_table->dpm_levels[0].enabled = true;
980 dpm_table->min = dpm_table->dpm_levels[0].value;
981 dpm_table->max = dpm_table->dpm_levels[0].value;
984 /* uclk dpm table setup */
985 dpm_table = &dpm_context->dpm_tables.uclk_table;
986 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
987 ret = smu_v11_0_set_single_dpm_table(smu,
992 dpm_table->is_fine_grained =
993 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
995 dpm_table->count = 1;
996 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
997 dpm_table->dpm_levels[0].enabled = true;
998 dpm_table->min = dpm_table->dpm_levels[0].value;
999 dpm_table->max = dpm_table->dpm_levels[0].value;
1002 /* vclk dpm table setup */
1003 dpm_table = &dpm_context->dpm_tables.vclk_table;
1004 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1005 ret = smu_v11_0_set_single_dpm_table(smu,
1010 dpm_table->is_fine_grained =
1011 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1013 dpm_table->count = 1;
1014 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1015 dpm_table->dpm_levels[0].enabled = true;
1016 dpm_table->min = dpm_table->dpm_levels[0].value;
1017 dpm_table->max = dpm_table->dpm_levels[0].value;
1020 /* dclk dpm table setup */
1021 dpm_table = &dpm_context->dpm_tables.dclk_table;
1022 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1023 ret = smu_v11_0_set_single_dpm_table(smu,
1028 dpm_table->is_fine_grained =
1029 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1031 dpm_table->count = 1;
1032 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1033 dpm_table->dpm_levels[0].enabled = true;
1034 dpm_table->min = dpm_table->dpm_levels[0].value;
1035 dpm_table->max = dpm_table->dpm_levels[0].value;
1038 /* dcefclk dpm table setup */
1039 dpm_table = &dpm_context->dpm_tables.dcef_table;
1040 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1041 ret = smu_v11_0_set_single_dpm_table(smu,
1046 dpm_table->is_fine_grained =
1047 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1049 dpm_table->count = 1;
1050 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1051 dpm_table->dpm_levels[0].enabled = true;
1052 dpm_table->min = dpm_table->dpm_levels[0].value;
1053 dpm_table->max = dpm_table->dpm_levels[0].value;
1056 /* pixelclk dpm table setup */
1057 dpm_table = &dpm_context->dpm_tables.pixel_table;
1058 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1059 ret = smu_v11_0_set_single_dpm_table(smu,
1064 dpm_table->is_fine_grained =
1065 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1067 dpm_table->count = 1;
1068 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1069 dpm_table->dpm_levels[0].enabled = true;
1070 dpm_table->min = dpm_table->dpm_levels[0].value;
1071 dpm_table->max = dpm_table->dpm_levels[0].value;
1074 /* displayclk dpm table setup */
1075 dpm_table = &dpm_context->dpm_tables.display_table;
1076 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1077 ret = smu_v11_0_set_single_dpm_table(smu,
1082 dpm_table->is_fine_grained =
1083 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1085 dpm_table->count = 1;
1086 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1087 dpm_table->dpm_levels[0].enabled = true;
1088 dpm_table->min = dpm_table->dpm_levels[0].value;
1089 dpm_table->max = dpm_table->dpm_levels[0].value;
1092 /* phyclk dpm table setup */
1093 dpm_table = &dpm_context->dpm_tables.phy_table;
1094 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1095 ret = smu_v11_0_set_single_dpm_table(smu,
1100 dpm_table->is_fine_grained =
1101 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1103 dpm_table->count = 1;
1104 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1105 dpm_table->dpm_levels[0].enabled = true;
1106 dpm_table->min = dpm_table->dpm_levels[0].value;
1107 dpm_table->max = dpm_table->dpm_levels[0].value;
1113 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1118 /* vcn dpm on is a prerequisite for vcn power gate messages */
1119 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1120 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1125 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1126 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1135 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1140 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1141 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1146 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1147 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1156 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1157 enum smu_clk_type clk_type,
1160 MetricsMember_t member_type;
1163 clk_id = smu_cmn_to_asic_specific_index(smu,
1164 CMN2ASIC_MAPPING_CLK,
1171 member_type = METRICS_CURR_GFXCLK;
1174 member_type = METRICS_CURR_UCLK;
1177 member_type = METRICS_CURR_SOCCLK;
1180 member_type = METRICS_CURR_VCLK;
1183 member_type = METRICS_CURR_DCLK;
1186 member_type = METRICS_CURR_DCEFCLK;
1192 return navi1x_get_smu_metrics_data(smu,
1197 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1199 PPTable_t *pptable = smu->smu_table.driver_pptable;
1200 DpmDescriptor_t *dpm_desc = NULL;
1201 uint32_t clk_index = 0;
1203 clk_index = smu_cmn_to_asic_specific_index(smu,
1204 CMN2ASIC_MAPPING_CLK,
1206 dpm_desc = &pptable->DpmDescriptor[clk_index];
1208 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1209 return dpm_desc->SnapToDiscrete == 0;
1212 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1214 return od_table->cap[cap];
1217 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1218 enum SMU_11_0_ODSETTING_ID setting,
1219 uint32_t *min, uint32_t *max)
1222 *min = od_table->min[setting];
1224 *max = od_table->max[setting];
1227 static int navi10_print_clk_levels(struct smu_context *smu,
1228 enum smu_clk_type clk_type, char *buf)
1230 uint16_t *curve_settings;
1231 int i, size = 0, ret = 0;
1232 uint32_t cur_value = 0, value = 0, count = 0;
1233 uint32_t freq_values[3] = {0};
1234 uint32_t mark_index = 0;
1235 struct smu_table_context *table_context = &smu->smu_table;
1236 uint32_t gen_speed, lane_width;
1237 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1238 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1239 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1240 OverDriveTable_t *od_table =
1241 (OverDriveTable_t *)table_context->overdrive_table;
1242 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1243 uint32_t min_value, max_value;
1253 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1257 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1261 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1262 for (i = 0; i < count; i++) {
1263 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1267 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1268 cur_value == value ? "*" : "");
1271 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1274 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1278 freq_values[1] = cur_value;
1279 mark_index = cur_value == freq_values[0] ? 0 :
1280 cur_value == freq_values[2] ? 2 : 1;
1281 if (mark_index != 1)
1282 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
1284 for (i = 0; i < 3; i++) {
1285 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
1286 i == mark_index ? "*" : "");
1292 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1293 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1294 for (i = 0; i < NUM_LINK_LEVELS; i++)
1295 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1296 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1297 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1298 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1299 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1300 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1301 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1302 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1303 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1304 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1305 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1306 pptable->LclkFreq[i],
1307 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1308 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1312 if (!smu->od_enabled || !od_table || !od_settings)
1314 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1316 size += sprintf(buf + size, "OD_SCLK:\n");
1317 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1320 if (!smu->od_enabled || !od_table || !od_settings)
1322 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1324 size += sprintf(buf + size, "OD_MCLK:\n");
1325 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
1327 case SMU_OD_VDDC_CURVE:
1328 if (!smu->od_enabled || !od_table || !od_settings)
1330 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1332 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
1333 for (i = 0; i < 3; i++) {
1336 curve_settings = &od_table->GfxclkFreq1;
1339 curve_settings = &od_table->GfxclkFreq2;
1342 curve_settings = &od_table->GfxclkFreq3;
1347 size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1351 if (!smu->od_enabled || !od_table || !od_settings)
1353 size = sprintf(buf, "%s:\n", "OD_RANGE");
1355 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1356 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1358 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1360 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1361 min_value, max_value);
1364 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1365 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1366 &min_value, &max_value);
1367 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1368 min_value, max_value);
1371 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1372 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1373 &min_value, &max_value);
1374 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1375 min_value, max_value);
1376 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1377 &min_value, &max_value);
1378 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1379 min_value, max_value);
1380 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1381 &min_value, &max_value);
1382 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1383 min_value, max_value);
1384 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1385 &min_value, &max_value);
1386 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1387 min_value, max_value);
1388 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1389 &min_value, &max_value);
1390 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1391 min_value, max_value);
1392 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1393 &min_value, &max_value);
1394 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1395 min_value, max_value);
1406 static int navi10_force_clk_levels(struct smu_context *smu,
1407 enum smu_clk_type clk_type, uint32_t mask)
1410 int ret = 0, size = 0;
1411 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1413 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1414 soft_max_level = mask ? (fls(mask) - 1) : 0;
1424 /* There is only 2 levels for fine grained DPM */
1425 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1426 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1427 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1430 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1434 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1438 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1449 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1451 struct smu_11_0_dpm_context *dpm_context =
1452 smu->smu_dpm.dpm_context;
1453 struct smu_11_0_dpm_table *gfx_table =
1454 &dpm_context->dpm_tables.gfx_table;
1455 struct smu_11_0_dpm_table *mem_table =
1456 &dpm_context->dpm_tables.uclk_table;
1457 struct smu_11_0_dpm_table *soc_table =
1458 &dpm_context->dpm_tables.soc_table;
1459 struct smu_umd_pstate_table *pstate_table =
1461 struct amdgpu_device *adev = smu->adev;
1464 pstate_table->gfxclk_pstate.min = gfx_table->min;
1465 switch (adev->asic_type) {
1467 switch (adev->pdev->revision) {
1468 case 0xf0: /* XTX */
1470 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1474 sclk_freq = NAVI10_PEAK_SCLK_XT;
1477 sclk_freq = NAVI10_PEAK_SCLK_XL;
1482 switch (adev->pdev->revision) {
1485 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1487 case 0xc1: /* XTM */
1489 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1491 case 0xc3: /* XLM */
1493 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1495 case 0xc5: /* XTX */
1497 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1500 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1505 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1508 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1511 pstate_table->gfxclk_pstate.peak = sclk_freq;
1513 pstate_table->uclk_pstate.min = mem_table->min;
1514 pstate_table->uclk_pstate.peak = mem_table->max;
1516 pstate_table->socclk_pstate.min = soc_table->min;
1517 pstate_table->socclk_pstate.peak = soc_table->max;
1519 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1520 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1521 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1522 pstate_table->gfxclk_pstate.standard =
1523 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1524 pstate_table->uclk_pstate.standard =
1525 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1526 pstate_table->socclk_pstate.standard =
1527 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1529 pstate_table->gfxclk_pstate.standard =
1530 pstate_table->gfxclk_pstate.min;
1531 pstate_table->uclk_pstate.standard =
1532 pstate_table->uclk_pstate.min;
1533 pstate_table->socclk_pstate.standard =
1534 pstate_table->socclk_pstate.min;
1540 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1541 enum smu_clk_type clk_type,
1542 struct pp_clock_levels_with_latency *clocks)
1545 uint32_t level_count = 0, freq = 0;
1553 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1557 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1558 clocks->num_levels = level_count;
1560 for (i = 0; i < level_count; i++) {
1561 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1565 clocks->data[i].clocks_in_khz = freq * 1000;
1566 clocks->data[i].latency_in_us = 0;
1576 static int navi10_pre_display_config_changed(struct smu_context *smu)
1579 uint32_t max_freq = 0;
1581 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1585 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1586 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1589 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1597 static int navi10_display_config_changed(struct smu_context *smu)
1601 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1602 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1603 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1604 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1605 smu->display_config->num_display,
1614 static bool navi10_is_dpm_running(struct smu_context *smu)
1617 uint32_t feature_mask[2];
1618 uint64_t feature_enabled;
1620 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1624 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1626 return !!(feature_enabled & SMC_DPM_FEATURE);
1629 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1638 switch (smu_v11_0_get_fan_control_mode(smu)) {
1639 case AMD_FAN_CTRL_AUTO:
1640 ret = navi1x_get_smu_metrics_data(smu,
1641 METRICS_CURR_FANSPEED,
1643 if (!ret && smu->fan_max_rpm)
1644 *speed = rpm * 100 / smu->fan_max_rpm;
1647 *speed = smu->user_dpm_profile.fan_speed_percent;
1652 static int navi10_get_fan_parameters(struct smu_context *smu)
1654 PPTable_t *pptable = smu->smu_table.driver_pptable;
1656 smu->fan_max_rpm = pptable->FanMaximumRpm;
1661 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1663 DpmActivityMonitorCoeffInt_t activity_monitor;
1664 uint32_t i, size = 0;
1665 int16_t workload_type = 0;
1666 static const char *profile_name[] = {
1674 static const char *title[] = {
1675 "PROFILE_INDEX(NAME)",
1679 "MinActiveFreqType",
1684 "PD_Data_error_coeff",
1685 "PD_Data_error_rate_coeff"};
1691 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1692 title[0], title[1], title[2], title[3], title[4], title[5],
1693 title[6], title[7], title[8], title[9], title[10]);
1695 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1696 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1697 workload_type = smu_cmn_to_asic_specific_index(smu,
1698 CMN2ASIC_MAPPING_WORKLOAD,
1700 if (workload_type < 0)
1703 result = smu_cmn_update_table(smu,
1704 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1705 (void *)(&activity_monitor), false);
1707 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1711 size += sprintf(buf + size, "%2d %14s%s:\n",
1712 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1714 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1718 activity_monitor.Gfx_FPS,
1719 activity_monitor.Gfx_MinFreqStep,
1720 activity_monitor.Gfx_MinActiveFreqType,
1721 activity_monitor.Gfx_MinActiveFreq,
1722 activity_monitor.Gfx_BoosterFreqType,
1723 activity_monitor.Gfx_BoosterFreq,
1724 activity_monitor.Gfx_PD_Data_limit_c,
1725 activity_monitor.Gfx_PD_Data_error_coeff,
1726 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1728 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1732 activity_monitor.Soc_FPS,
1733 activity_monitor.Soc_MinFreqStep,
1734 activity_monitor.Soc_MinActiveFreqType,
1735 activity_monitor.Soc_MinActiveFreq,
1736 activity_monitor.Soc_BoosterFreqType,
1737 activity_monitor.Soc_BoosterFreq,
1738 activity_monitor.Soc_PD_Data_limit_c,
1739 activity_monitor.Soc_PD_Data_error_coeff,
1740 activity_monitor.Soc_PD_Data_error_rate_coeff);
1742 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1746 activity_monitor.Mem_FPS,
1747 activity_monitor.Mem_MinFreqStep,
1748 activity_monitor.Mem_MinActiveFreqType,
1749 activity_monitor.Mem_MinActiveFreq,
1750 activity_monitor.Mem_BoosterFreqType,
1751 activity_monitor.Mem_BoosterFreq,
1752 activity_monitor.Mem_PD_Data_limit_c,
1753 activity_monitor.Mem_PD_Data_error_coeff,
1754 activity_monitor.Mem_PD_Data_error_rate_coeff);
1760 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1762 DpmActivityMonitorCoeffInt_t activity_monitor;
1763 int workload_type, ret = 0;
1765 smu->power_profile_mode = input[size];
1767 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1768 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1772 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1774 ret = smu_cmn_update_table(smu,
1775 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1776 (void *)(&activity_monitor), false);
1778 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1783 case 0: /* Gfxclk */
1784 activity_monitor.Gfx_FPS = input[1];
1785 activity_monitor.Gfx_MinFreqStep = input[2];
1786 activity_monitor.Gfx_MinActiveFreqType = input[3];
1787 activity_monitor.Gfx_MinActiveFreq = input[4];
1788 activity_monitor.Gfx_BoosterFreqType = input[5];
1789 activity_monitor.Gfx_BoosterFreq = input[6];
1790 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1791 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1792 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1794 case 1: /* Socclk */
1795 activity_monitor.Soc_FPS = input[1];
1796 activity_monitor.Soc_MinFreqStep = input[2];
1797 activity_monitor.Soc_MinActiveFreqType = input[3];
1798 activity_monitor.Soc_MinActiveFreq = input[4];
1799 activity_monitor.Soc_BoosterFreqType = input[5];
1800 activity_monitor.Soc_BoosterFreq = input[6];
1801 activity_monitor.Soc_PD_Data_limit_c = input[7];
1802 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1803 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1806 activity_monitor.Mem_FPS = input[1];
1807 activity_monitor.Mem_MinFreqStep = input[2];
1808 activity_monitor.Mem_MinActiveFreqType = input[3];
1809 activity_monitor.Mem_MinActiveFreq = input[4];
1810 activity_monitor.Mem_BoosterFreqType = input[5];
1811 activity_monitor.Mem_BoosterFreq = input[6];
1812 activity_monitor.Mem_PD_Data_limit_c = input[7];
1813 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1814 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1818 ret = smu_cmn_update_table(smu,
1819 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1820 (void *)(&activity_monitor), true);
1822 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1827 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1828 workload_type = smu_cmn_to_asic_specific_index(smu,
1829 CMN2ASIC_MAPPING_WORKLOAD,
1830 smu->power_profile_mode);
1831 if (workload_type < 0)
1833 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1834 1 << workload_type, NULL);
1839 static int navi10_notify_smc_display_config(struct smu_context *smu)
1841 struct smu_clocks min_clocks = {0};
1842 struct pp_display_clock_request clock_req;
1845 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1846 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1847 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1849 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1850 clock_req.clock_type = amd_pp_dcef_clock;
1851 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1853 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1855 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1856 ret = smu_cmn_send_smc_msg_with_param(smu,
1857 SMU_MSG_SetMinDeepSleepDcefclk,
1858 min_clocks.dcef_clock_in_sr/100,
1861 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1866 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1870 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1871 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1873 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1881 static int navi10_set_watermarks_table(struct smu_context *smu,
1882 struct pp_smu_wm_range_sets *clock_ranges)
1884 Watermarks_t *table = smu->smu_table.watermarks_table;
1889 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1890 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1893 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1894 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1895 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1896 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1897 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1898 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1899 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1900 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1901 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1903 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1904 clock_ranges->reader_wm_sets[i].wm_inst;
1907 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1908 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1909 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1910 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1911 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1912 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1913 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1914 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1915 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1917 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1918 clock_ranges->writer_wm_sets[i].wm_inst;
1921 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1924 /* pass data to smu controller */
1925 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1926 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1927 ret = smu_cmn_write_watermarks_table(smu);
1929 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1932 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1938 static int navi10_read_sensor(struct smu_context *smu,
1939 enum amd_pp_sensors sensor,
1940 void *data, uint32_t *size)
1943 struct smu_table_context *table_context = &smu->smu_table;
1944 PPTable_t *pptable = table_context->driver_pptable;
1949 mutex_lock(&smu->sensor_lock);
1951 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1952 *(uint32_t *)data = pptable->FanMaximumRpm;
1955 case AMDGPU_PP_SENSOR_MEM_LOAD:
1956 ret = navi1x_get_smu_metrics_data(smu,
1957 METRICS_AVERAGE_MEMACTIVITY,
1961 case AMDGPU_PP_SENSOR_GPU_LOAD:
1962 ret = navi1x_get_smu_metrics_data(smu,
1963 METRICS_AVERAGE_GFXACTIVITY,
1967 case AMDGPU_PP_SENSOR_GPU_POWER:
1968 ret = navi1x_get_smu_metrics_data(smu,
1969 METRICS_AVERAGE_SOCKETPOWER,
1973 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1974 ret = navi1x_get_smu_metrics_data(smu,
1975 METRICS_TEMPERATURE_HOTSPOT,
1979 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1980 ret = navi1x_get_smu_metrics_data(smu,
1981 METRICS_TEMPERATURE_EDGE,
1985 case AMDGPU_PP_SENSOR_MEM_TEMP:
1986 ret = navi1x_get_smu_metrics_data(smu,
1987 METRICS_TEMPERATURE_MEM,
1991 case AMDGPU_PP_SENSOR_GFX_MCLK:
1992 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1993 *(uint32_t *)data *= 100;
1996 case AMDGPU_PP_SENSOR_GFX_SCLK:
1997 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
1998 *(uint32_t *)data *= 100;
2001 case AMDGPU_PP_SENSOR_VDDGFX:
2002 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2009 mutex_unlock(&smu->sensor_lock);
2014 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2016 uint32_t num_discrete_levels = 0;
2017 uint16_t *dpm_levels = NULL;
2019 struct smu_table_context *table_context = &smu->smu_table;
2020 PPTable_t *driver_ppt = NULL;
2022 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2025 driver_ppt = table_context->driver_pptable;
2026 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2027 dpm_levels = driver_ppt->FreqTableUclk;
2029 if (num_discrete_levels == 0 || dpm_levels == NULL)
2032 *num_states = num_discrete_levels;
2033 for (i = 0; i < num_discrete_levels; i++) {
2034 /* convert to khz */
2035 *clocks_in_khz = (*dpm_levels) * 1000;
2043 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2044 struct smu_temperature_range *range)
2046 struct smu_table_context *table_context = &smu->smu_table;
2047 struct smu_11_0_powerplay_table *powerplay_table =
2048 table_context->power_play_table;
2049 PPTable_t *pptable = smu->smu_table.driver_pptable;
2054 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2056 range->max = pptable->TedgeLimit *
2057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2058 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2060 range->hotspot_crit_max = pptable->ThotspotLimit *
2061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2062 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2063 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2064 range->mem_crit_max = pptable->TmemLimit *
2065 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2066 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2067 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2068 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2073 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2074 bool disable_memory_clock_switch)
2077 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2078 (struct smu_11_0_max_sustainable_clocks *)
2079 smu->smu_table.max_sustainable_clocks;
2080 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2081 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2083 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2086 if(disable_memory_clock_switch)
2087 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2089 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2092 smu->disable_uclk_switch = disable_memory_clock_switch;
2097 static int navi10_get_power_limit(struct smu_context *smu)
2099 struct smu_11_0_powerplay_table *powerplay_table =
2100 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2101 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2102 PPTable_t *pptable = smu->smu_table.driver_pptable;
2103 uint32_t power_limit, od_percent;
2105 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2106 /* the last hope to figure out the ppt limit */
2108 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2112 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2114 smu->current_power_limit = smu->default_power_limit = power_limit;
2116 if (smu->od_enabled &&
2117 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2118 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2120 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2122 power_limit *= (100 + od_percent);
2125 smu->max_power_limit = power_limit;
2130 static int navi10_update_pcie_parameters(struct smu_context *smu,
2131 uint32_t pcie_gen_cap,
2132 uint32_t pcie_width_cap)
2134 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2135 PPTable_t *pptable = smu->smu_table.driver_pptable;
2136 uint32_t smu_pcie_arg;
2139 /* lclk dpm table setup */
2140 for (i = 0; i < MAX_PCIE_CONF; i++) {
2141 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2142 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2145 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2146 smu_pcie_arg = (i << 16) |
2147 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2148 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2149 pptable->PcieLaneCount[i] : pcie_width_cap);
2150 ret = smu_cmn_send_smc_msg_with_param(smu,
2151 SMU_MSG_OverridePcieParameters,
2158 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2159 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2160 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2161 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2167 static inline void navi10_dump_od_table(struct smu_context *smu,
2168 OverDriveTable_t *od_table)
2170 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2171 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2172 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2173 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2174 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2175 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2178 static int navi10_od_setting_check_range(struct smu_context *smu,
2179 struct smu_11_0_overdrive_table *od_table,
2180 enum SMU_11_0_ODSETTING_ID setting,
2183 if (value < od_table->min[setting]) {
2184 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2187 if (value > od_table->max[setting]) {
2188 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2194 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2198 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2202 ret = smu_cmn_send_smc_msg_with_param(smu,
2203 SMU_MSG_GetVoltageByDpm,
2207 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2211 *voltage = (uint16_t)value;
2216 static bool navi10_is_baco_supported(struct smu_context *smu)
2218 struct amdgpu_device *adev = smu->adev;
2221 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
2224 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2225 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2228 static int navi10_set_default_od_settings(struct smu_context *smu)
2230 OverDriveTable_t *od_table =
2231 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2232 OverDriveTable_t *boot_od_table =
2233 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2236 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
2238 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2242 if (!od_table->GfxclkVolt1) {
2243 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2244 &od_table->GfxclkVolt1,
2245 od_table->GfxclkFreq1);
2250 if (!od_table->GfxclkVolt2) {
2251 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2252 &od_table->GfxclkVolt2,
2253 od_table->GfxclkFreq2);
2258 if (!od_table->GfxclkVolt3) {
2259 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2260 &od_table->GfxclkVolt3,
2261 od_table->GfxclkFreq3);
2266 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2268 navi10_dump_od_table(smu, od_table);
2273 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2276 struct smu_table_context *table_context = &smu->smu_table;
2277 OverDriveTable_t *od_table;
2278 struct smu_11_0_overdrive_table *od_settings;
2279 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2280 uint16_t *freq_ptr, *voltage_ptr;
2281 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2283 if (!smu->od_enabled) {
2284 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2288 if (!smu->od_settings) {
2289 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2293 od_settings = smu->od_settings;
2296 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2297 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2298 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2301 if (!table_context->overdrive_table) {
2302 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2305 for (i = 0; i < size; i += 2) {
2307 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2312 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2313 freq_ptr = &od_table->GfxclkFmin;
2314 if (input[i + 1] > od_table->GfxclkFmax) {
2315 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2317 od_table->GfxclkFmin);
2322 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2323 freq_ptr = &od_table->GfxclkFmax;
2324 if (input[i + 1] < od_table->GfxclkFmin) {
2325 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2327 od_table->GfxclkFmax);
2332 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2333 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2336 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2339 *freq_ptr = input[i + 1];
2342 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2343 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2344 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2348 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2351 if (input[0] != 1) {
2352 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2353 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2356 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2359 od_table->UclkFmax = input[1];
2361 case PP_OD_RESTORE_DEFAULT_TABLE:
2362 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2363 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2366 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2368 case PP_OD_COMMIT_DPM_TABLE:
2369 navi10_dump_od_table(smu, od_table);
2370 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2372 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2376 case PP_OD_EDIT_VDDC_CURVE:
2377 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2378 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2382 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2386 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2392 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2393 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2394 freq_ptr = &od_table->GfxclkFreq1;
2395 voltage_ptr = &od_table->GfxclkVolt1;
2398 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2399 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2400 freq_ptr = &od_table->GfxclkFreq2;
2401 voltage_ptr = &od_table->GfxclkVolt2;
2404 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2405 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2406 freq_ptr = &od_table->GfxclkFreq3;
2407 voltage_ptr = &od_table->GfxclkVolt3;
2410 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2411 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2414 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2417 // Allow setting zero to disable the OverDrive VDDC curve
2418 if (input[2] != 0) {
2419 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2422 *freq_ptr = input[1];
2423 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2424 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2426 // If setting 0, disable all voltage curve settings
2427 od_table->GfxclkVolt1 = 0;
2428 od_table->GfxclkVolt2 = 0;
2429 od_table->GfxclkVolt3 = 0;
2431 navi10_dump_od_table(smu, od_table);
2439 static int navi10_run_btc(struct smu_context *smu)
2443 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2445 dev_err(smu->adev->dev, "RunBtc failed!\n");
2450 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2452 struct amdgpu_device *adev = smu->adev;
2454 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2457 if (adev->asic_type == CHIP_NAVI10 ||
2458 adev->asic_type == CHIP_NAVI14)
2464 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2466 uint32_t uclk_count, uclk_min, uclk_max;
2469 /* This workaround can be applied only with uclk dpm enabled */
2470 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2473 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2477 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2482 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2483 * This workaround is needed only when the max uclk frequency
2484 * not greater than that.
2486 if (uclk_max > 0x2EE)
2489 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2493 /* Force UCLK out of the highest DPM */
2494 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2498 /* Revert the UCLK Hardmax */
2499 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2504 * In this case, SMU already disabled dummy pstate during enablement
2505 * of UCLK DPM, we have to re-enabled it.
2507 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2510 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2512 struct smu_table_context *smu_table = &smu->smu_table;
2513 struct smu_table *dummy_read_table =
2514 &smu_table->dummy_read_1_table;
2515 char *dummy_table = dummy_read_table->cpu_addr;
2519 for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2520 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2521 dummy_table += 0x1000;
2522 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2523 dummy_table += 0x1000;
2526 amdgpu_asic_flush_hdp(smu->adev, NULL);
2528 ret = smu_cmn_send_smc_msg_with_param(smu,
2529 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2530 upper_32_bits(dummy_read_table->mc_address),
2535 return smu_cmn_send_smc_msg_with_param(smu,
2536 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2537 lower_32_bits(dummy_read_table->mc_address),
2541 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2543 struct amdgpu_device *adev = smu->adev;
2544 uint8_t umc_fw_greater_than_v136 = false;
2545 uint8_t umc_fw_disable_cdr = false;
2546 uint32_t pmfw_version;
2550 if (!navi10_need_umc_cdr_workaround(smu))
2553 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2555 dev_err(adev->dev, "Failed to get smu version!\n");
2560 * The messages below are only supported by Navi10 42.53.0 and later
2561 * PMFWs and Navi14 53.29.0 and later PMFWs.
2562 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2563 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2564 * - PPSMC_MSG_GetUMCFWWA
2566 if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
2567 ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
2568 ret = smu_cmn_send_smc_msg_with_param(smu,
2569 SMU_MSG_GET_UMC_FW_WA,
2575 /* First bit indicates if the UMC f/w is above v137 */
2576 umc_fw_greater_than_v136 = param & 0x1;
2578 /* Second bit indicates if hybrid-cdr is disabled */
2579 umc_fw_disable_cdr = param & 0x2;
2581 /* w/a only allowed if UMC f/w is <= 136 */
2582 if (umc_fw_greater_than_v136)
2585 if (umc_fw_disable_cdr) {
2586 if (adev->asic_type == CHIP_NAVI10)
2587 return navi10_umc_hybrid_cdr_workaround(smu);
2589 return navi10_set_dummy_pstates_table_location(smu);
2592 if (adev->asic_type == CHIP_NAVI10)
2593 return navi10_umc_hybrid_cdr_workaround(smu);
2599 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2602 struct smu_table_context *smu_table = &smu->smu_table;
2603 struct gpu_metrics_v1_1 *gpu_metrics =
2604 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
2605 SmuMetrics_legacy_t metrics;
2608 mutex_lock(&smu->metrics_lock);
2610 ret = smu_cmn_get_metrics_table_locked(smu,
2614 mutex_unlock(&smu->metrics_lock);
2618 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2620 mutex_unlock(&smu->metrics_lock);
2622 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
2624 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2625 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2626 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2627 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2628 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2629 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2631 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2632 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2634 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2636 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2637 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2638 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2640 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2641 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2642 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2643 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2644 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2646 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2648 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2650 gpu_metrics->pcie_link_width =
2651 smu_v11_0_get_current_pcie_link_width(smu);
2652 gpu_metrics->pcie_link_speed =
2653 smu_v11_0_get_current_pcie_link_speed(smu);
2655 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2657 *table = (void *)gpu_metrics;
2659 return sizeof(struct gpu_metrics_v1_1);
2662 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2665 struct smu_table_context *smu_table = &smu->smu_table;
2666 struct gpu_metrics_v1_1 *gpu_metrics =
2667 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
2668 SmuMetrics_t metrics;
2671 mutex_lock(&smu->metrics_lock);
2673 ret = smu_cmn_get_metrics_table_locked(smu,
2677 mutex_unlock(&smu->metrics_lock);
2681 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2683 mutex_unlock(&smu->metrics_lock);
2685 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
2687 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2688 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2689 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2690 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2691 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2692 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2694 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2695 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2697 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2699 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2700 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2702 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2704 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2705 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2707 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2708 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2709 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2710 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2711 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2713 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2715 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2717 gpu_metrics->pcie_link_width = metrics.PcieWidth;
2718 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2720 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2722 *table = (void *)gpu_metrics;
2724 return sizeof(struct gpu_metrics_v1_1);
2727 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
2730 struct smu_table_context *smu_table = &smu->smu_table;
2731 struct gpu_metrics_v1_1 *gpu_metrics =
2732 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
2733 SmuMetrics_NV12_legacy_t metrics;
2736 mutex_lock(&smu->metrics_lock);
2738 ret = smu_cmn_get_metrics_table_locked(smu,
2742 mutex_unlock(&smu->metrics_lock);
2746 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
2748 mutex_unlock(&smu->metrics_lock);
2750 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
2752 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2753 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2754 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2755 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2756 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2757 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2759 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2760 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2762 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2764 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2765 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2766 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2768 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2769 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2770 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2771 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2773 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2774 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2775 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2776 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2777 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2779 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2781 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2783 gpu_metrics->pcie_link_width =
2784 smu_v11_0_get_current_pcie_link_width(smu);
2785 gpu_metrics->pcie_link_speed =
2786 smu_v11_0_get_current_pcie_link_speed(smu);
2788 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2790 *table = (void *)gpu_metrics;
2792 return sizeof(struct gpu_metrics_v1_1);
2795 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
2798 struct smu_table_context *smu_table = &smu->smu_table;
2799 struct gpu_metrics_v1_1 *gpu_metrics =
2800 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
2801 SmuMetrics_NV12_t metrics;
2804 mutex_lock(&smu->metrics_lock);
2806 ret = smu_cmn_get_metrics_table_locked(smu,
2810 mutex_unlock(&smu->metrics_lock);
2814 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
2816 mutex_unlock(&smu->metrics_lock);
2818 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
2820 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2821 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2822 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2823 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2824 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2825 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2827 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2828 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2830 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2832 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2833 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2835 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2837 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2838 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2840 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2841 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2842 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2843 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2845 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2846 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2847 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2848 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2849 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2851 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2853 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2855 gpu_metrics->pcie_link_width = metrics.PcieWidth;
2856 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2858 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2860 *table = (void *)gpu_metrics;
2862 return sizeof(struct gpu_metrics_v1_1);
2865 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
2868 struct amdgpu_device *adev = smu->adev;
2869 uint32_t smu_version;
2872 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2874 dev_err(adev->dev, "Failed to get smu version!\n");
2878 switch (adev->asic_type) {
2880 if (smu_version > 0x00341C00)
2881 ret = navi12_get_gpu_metrics(smu, table);
2883 ret = navi12_get_legacy_gpu_metrics(smu, table);
2888 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
2889 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
2890 ret = navi10_get_gpu_metrics(smu, table);
2892 ret =navi10_get_legacy_gpu_metrics(smu, table);
2899 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
2901 struct amdgpu_device *adev = smu->adev;
2904 /* Navi12 does not support this */
2905 if (adev->asic_type == CHIP_NAVI12)
2908 /* Workaround for WS SKU */
2909 if (adev->pdev->device == 0x7312 &&
2910 adev->pdev->revision == 0)
2913 return smu_cmn_send_smc_msg_with_param(smu,
2914 SMU_MSG_SetMGpuFanBoostLimitRpm,
2919 static int navi10_post_smu_init(struct smu_context *smu)
2921 struct amdgpu_device *adev = smu->adev;
2924 if (amdgpu_sriov_vf(adev))
2927 ret = navi10_run_umc_cdr_workaround(smu);
2929 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
2933 if (!smu->dc_controlled_by_gpio) {
2935 * For Navi1X, manually switch it to AC mode as PMFW
2936 * may boot it with DC mode.
2938 ret = smu_v11_0_set_power_source(smu,
2940 SMU_POWER_SOURCE_AC :
2941 SMU_POWER_SOURCE_DC);
2943 dev_err(adev->dev, "Failed to switch to %s mode!\n",
2944 adev->pm.ac_power ? "AC" : "DC");
2952 static const struct pptable_funcs navi10_ppt_funcs = {
2953 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2954 .set_default_dpm_table = navi10_set_default_dpm_table,
2955 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
2956 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2957 .print_clk_levels = navi10_print_clk_levels,
2958 .force_clk_levels = navi10_force_clk_levels,
2959 .populate_umd_state_clk = navi10_populate_umd_state_clk,
2960 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2961 .pre_display_config_changed = navi10_pre_display_config_changed,
2962 .display_config_changed = navi10_display_config_changed,
2963 .notify_smc_display_config = navi10_notify_smc_display_config,
2964 .is_dpm_running = navi10_is_dpm_running,
2965 .get_fan_speed_percent = navi10_get_fan_speed_percent,
2966 .get_power_profile_mode = navi10_get_power_profile_mode,
2967 .set_power_profile_mode = navi10_set_power_profile_mode,
2968 .set_watermarks_table = navi10_set_watermarks_table,
2969 .read_sensor = navi10_read_sensor,
2970 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2971 .set_performance_level = smu_v11_0_set_performance_level,
2972 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2973 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2974 .get_power_limit = navi10_get_power_limit,
2975 .update_pcie_parameters = navi10_update_pcie_parameters,
2976 .init_microcode = smu_v11_0_init_microcode,
2977 .load_microcode = smu_v11_0_load_microcode,
2978 .fini_microcode = smu_v11_0_fini_microcode,
2979 .init_smc_tables = navi10_init_smc_tables,
2980 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2981 .init_power = smu_v11_0_init_power,
2982 .fini_power = smu_v11_0_fini_power,
2983 .check_fw_status = smu_v11_0_check_fw_status,
2984 .setup_pptable = navi10_setup_pptable,
2985 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2986 .check_fw_version = smu_v11_0_check_fw_version,
2987 .write_pptable = smu_cmn_write_pptable,
2988 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2989 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2990 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2991 .system_features_control = smu_v11_0_system_features_control,
2992 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2993 .send_smc_msg = smu_cmn_send_smc_msg,
2994 .init_display_count = smu_v11_0_init_display_count,
2995 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2996 .get_enabled_mask = smu_cmn_get_enabled_mask,
2997 .feature_is_enabled = smu_cmn_feature_is_enabled,
2998 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2999 .notify_display_change = smu_v11_0_notify_display_change,
3000 .set_power_limit = smu_v11_0_set_power_limit,
3001 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3002 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3003 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3004 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3005 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3006 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3007 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3008 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3009 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3010 .gfx_off_control = smu_v11_0_gfx_off_control,
3011 .register_irq_handler = smu_v11_0_register_irq_handler,
3012 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3013 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3014 .baco_is_support= navi10_is_baco_supported,
3015 .baco_get_state = smu_v11_0_baco_get_state,
3016 .baco_set_state = smu_v11_0_baco_set_state,
3017 .baco_enter = smu_v11_0_baco_enter,
3018 .baco_exit = smu_v11_0_baco_exit,
3019 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3020 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3021 .set_default_od_settings = navi10_set_default_od_settings,
3022 .od_edit_dpm_table = navi10_od_edit_dpm_table,
3023 .run_btc = navi10_run_btc,
3024 .set_power_source = smu_v11_0_set_power_source,
3025 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3026 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3027 .get_gpu_metrics = navi1x_get_gpu_metrics,
3028 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3029 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3030 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3031 .get_fan_parameters = navi10_get_fan_parameters,
3032 .post_init = navi10_post_smu_init,
3033 .interrupt_work = smu_v11_0_interrupt_work,
3036 void navi10_set_ppt_funcs(struct smu_context *smu)
3038 smu->ppt_funcs = &navi10_ppt_funcs;
3039 smu->message_map = navi10_message_map;
3040 smu->clock_map = navi10_clk_map;
3041 smu->feature_map = navi10_feature_mask_map;
3042 smu->table_map = navi10_table_map;
3043 smu->pwr_src_map = navi10_pwr_src_map;
3044 smu->workload_map = navi10_workload_map;