drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  85         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  86         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  87         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  88         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  89         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  90         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  91         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  92         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  93         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  94         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  95         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  96         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  97         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  98         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  99         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 100         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 101         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 102         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 103         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 104         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 105         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 108         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 109         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 110         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 111         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 112         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 113         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 114         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 115         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 116         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 117         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 118         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 119         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 120         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 121         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 122         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 123         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 124         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 125         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 126         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 127         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 128         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 129         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 130         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 131         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 132         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 133         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 134         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 135         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 136         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 137         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 138         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 139         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 140         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 141         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 142         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 143         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 144         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 145 };
 146
 147 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 148         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 149         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 150         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 151         CLK_MAP(FCLK, PPCLK_FCLK),
 152         CLK_MAP(UCLK, PPCLK_UCLK),
 153         CLK_MAP(MCLK, PPCLK_UCLK),
 154         CLK_MAP(DCLK, PPCLK_DCLK),
 155         CLK_MAP(VCLK, PPCLK_VCLK),
 156 };
 157
 158 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 159         FEA_MAP(DPM_PREFETCHER),
 160         FEA_MAP(DPM_GFXCLK),
 161         FEA_MAP(DPM_UCLK),
 162         FEA_MAP(DPM_SOCCLK),
 163         FEA_MAP(DPM_FCLK),
 164         FEA_MAP(DPM_MP0CLK),
 165         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 166         FEA_MAP(DS_GFXCLK),
 167         FEA_MAP(DS_SOCCLK),
 168         FEA_MAP(DS_LCLK),
 169         FEA_MAP(DS_FCLK),
 170         FEA_MAP(DS_UCLK),
 171         FEA_MAP(GFX_ULV),
 172         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 173         FEA_MAP(RSMU_SMN_CG),
 174         FEA_MAP(WAFL_CG),
 175         FEA_MAP(PPT),
 176         FEA_MAP(TDC),
 177         FEA_MAP(APCC_PLUS),
 178         FEA_MAP(VR0HOT),
 179         FEA_MAP(VR1HOT),
 180         FEA_MAP(FW_CTF),
 181         FEA_MAP(FAN_CONTROL),
 182         FEA_MAP(THERMAL),
 183         FEA_MAP(OUT_OF_BAND_MONITOR),
 184         FEA_MAP(TEMP_DEPENDENT_VMIN),
 185 };
 186
 187 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 188         TAB_MAP(PPTABLE),
 189         TAB_MAP(AVFS),
 190         TAB_MAP(AVFS_PSM_DEBUG),
 191         TAB_MAP(AVFS_FUSE_OVERRIDE),
 192         TAB_MAP(PMSTATUSLOG),
 193         TAB_MAP(SMU_METRICS),
 194         TAB_MAP(DRIVER_SMU_CONFIG),
 195         TAB_MAP(OVERDRIVE),
 196         TAB_MAP(I2C_COMMANDS),
 197         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 198 };
 199
 200 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 201         PWR_MAP(AC),
 202         PWR_MAP(DC),
 203 };
 204
 205 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 211 };
 212
 213 static int arcturus_tables_init(struct smu_context *smu)
 214 {
 215         struct smu_table_context *smu_table = &smu->smu_table;
 216         struct smu_table *tables = smu_table->tables;
 217
 218         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 219                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 220
 221         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 222                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 223
 224         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 225                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 226
 227         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 228                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 229
 230         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 231                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 232                        AMDGPU_GEM_DOMAIN_VRAM);
 233
 234         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 235         if (!smu_table->metrics_table)
 236                 return -ENOMEM;
 237         smu_table->metrics_time = 0;
 238
 239         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 240         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 241         if (!smu_table->gpu_metrics_table) {
 242                 kfree(smu_table->metrics_table);
 243                 return -ENOMEM;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 250 {
 251         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 252
 253         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 254                                        GFP_KERNEL);
 255         if (!smu_dpm->dpm_context)
 256                 return -ENOMEM;
 257         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 258
 259         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 260                                        GFP_KERNEL);
 261         if (!smu_dpm->dpm_current_power_state)
 262                 return -ENOMEM;
 263
 264         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 265                                        GFP_KERNEL);
 266         if (!smu_dpm->dpm_request_power_state)
 267                 return -ENOMEM;
 268
 269         return 0;
 270 }
 271
 272 static int arcturus_init_smc_tables(struct smu_context *smu)
 273 {
 274         int ret = 0;
 275
 276         ret = arcturus_tables_init(smu);
 277         if (ret)
 278                 return ret;
 279
 280         ret = arcturus_allocate_dpm_context(smu);
 281         if (ret)
 282                 return ret;
 283
 284         return smu_v11_0_init_smc_tables(smu);
 285 }
 286
 287 static int
 288 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 289                                   uint32_t *feature_mask, uint32_t num)
 290 {
 291         if (num > 2)
 292                 return -EINVAL;
 293
 294         /* pptable will handle the features to enable */
 295         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 296
 297         return 0;
 298 }
 299
 300 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 301 {
 302         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 303         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 304         struct smu_11_0_dpm_table *dpm_table = NULL;
 305         int ret = 0;
 306
 307         /* socclk dpm table setup */
 308         dpm_table = &dpm_context->dpm_tables.soc_table;
 309         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 310                 ret = smu_v11_0_set_single_dpm_table(smu,
 311                                                      SMU_SOCCLK,
 312                                                      dpm_table);
 313                 if (ret)
 314                         return ret;
 315                 dpm_table->is_fine_grained =
 316                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 317         } else {
 318                 dpm_table->count = 1;
 319                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 320                 dpm_table->dpm_levels[0].enabled = true;
 321                 dpm_table->min = dpm_table->dpm_levels[0].value;
 322                 dpm_table->max = dpm_table->dpm_levels[0].value;
 323         }
 324
 325         /* gfxclk dpm table setup */
 326         dpm_table = &dpm_context->dpm_tables.gfx_table;
 327         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 328                 ret = smu_v11_0_set_single_dpm_table(smu,
 329                                                      SMU_GFXCLK,
 330                                                      dpm_table);
 331                 if (ret)
 332                         return ret;
 333                 dpm_table->is_fine_grained =
 334                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 335         } else {
 336                 dpm_table->count = 1;
 337                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 338                 dpm_table->dpm_levels[0].enabled = true;
 339                 dpm_table->min = dpm_table->dpm_levels[0].value;
 340                 dpm_table->max = dpm_table->dpm_levels[0].value;
 341         }
 342
 343         /* memclk dpm table setup */
 344         dpm_table = &dpm_context->dpm_tables.uclk_table;
 345         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 346                 ret = smu_v11_0_set_single_dpm_table(smu,
 347                                                      SMU_UCLK,
 348                                                      dpm_table);
 349                 if (ret)
 350                         return ret;
 351                 dpm_table->is_fine_grained =
 352                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 353         } else {
 354                 dpm_table->count = 1;
 355                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 356                 dpm_table->dpm_levels[0].enabled = true;
 357                 dpm_table->min = dpm_table->dpm_levels[0].value;
 358                 dpm_table->max = dpm_table->dpm_levels[0].value;
 359         }
 360
 361         /* fclk dpm table setup */
 362         dpm_table = &dpm_context->dpm_tables.fclk_table;
 363         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 364                 ret = smu_v11_0_set_single_dpm_table(smu,
 365                                                      SMU_FCLK,
 366                                                      dpm_table);
 367                 if (ret)
 368                         return ret;
 369                 dpm_table->is_fine_grained =
 370                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 371         } else {
 372                 dpm_table->count = 1;
 373                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 374                 dpm_table->dpm_levels[0].enabled = true;
 375                 dpm_table->min = dpm_table->dpm_levels[0].value;
 376                 dpm_table->max = dpm_table->dpm_levels[0].value;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int arcturus_check_powerplay_table(struct smu_context *smu)
 383 {
 384         struct smu_table_context *table_context = &smu->smu_table;
 385         struct smu_11_0_powerplay_table *powerplay_table =
 386                 table_context->power_play_table;
 387         struct smu_baco_context *smu_baco = &smu->smu_baco;
 388
 389         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 390             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 391                 smu_baco->platform_support = true;
 392
 393         table_context->thermal_controller_type =
 394                 powerplay_table->thermal_controller_type;
 395
 396         return 0;
 397 }
 398
 399 static int arcturus_store_powerplay_table(struct smu_context *smu)
 400 {
 401         struct smu_table_context *table_context = &smu->smu_table;
 402         struct smu_11_0_powerplay_table *powerplay_table =
 403                 table_context->power_play_table;
 404
 405         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 406                sizeof(PPTable_t));
 407
 408         return 0;
 409 }
 410
 411 static int arcturus_append_powerplay_table(struct smu_context *smu)
 412 {
 413         struct smu_table_context *table_context = &smu->smu_table;
 414         PPTable_t *smc_pptable = table_context->driver_pptable;
 415         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 416         int index, ret;
 417
 418         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 419                                            smc_dpm_info);
 420
 421         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 422                                       (uint8_t **)&smc_dpm_table);
 423         if (ret)
 424                 return ret;
 425
 426         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 427                         smc_dpm_table->table_header.format_revision,
 428                         smc_dpm_table->table_header.content_revision);
 429
 430         if ((smc_dpm_table->table_header.format_revision == 4) &&
 431             (smc_dpm_table->table_header.content_revision == 6))
 432                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 433                        &smc_dpm_table->maxvoltagestepgfx,
 434                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 435
 436         return 0;
 437 }
 438
 439 static int arcturus_setup_pptable(struct smu_context *smu)
 440 {
 441         int ret = 0;
 442
 443         ret = smu_v11_0_setup_pptable(smu);
 444         if (ret)
 445                 return ret;
 446
 447         ret = arcturus_store_powerplay_table(smu);
 448         if (ret)
 449                 return ret;
 450
 451         ret = arcturus_append_powerplay_table(smu);
 452         if (ret)
 453                 return ret;
 454
 455         ret = arcturus_check_powerplay_table(smu);
 456         if (ret)
 457                 return ret;
 458
 459         return ret;
 460 }
 461
 462 static int arcturus_run_btc(struct smu_context *smu)
 463 {
 464         int ret = 0;
 465
 466         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 467         if (ret) {
 468                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 469                 return ret;
 470         }
 471
 472         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 473 }
 474
 475 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 476 {
 477         struct smu_11_0_dpm_context *dpm_context =
 478                                 smu->smu_dpm.dpm_context;
 479         struct smu_11_0_dpm_table *gfx_table =
 480                                 &dpm_context->dpm_tables.gfx_table;
 481         struct smu_11_0_dpm_table *mem_table =
 482                                 &dpm_context->dpm_tables.uclk_table;
 483         struct smu_11_0_dpm_table *soc_table =
 484                                 &dpm_context->dpm_tables.soc_table;
 485         struct smu_umd_pstate_table *pstate_table =
 486                                 &smu->pstate_table;
 487
 488         pstate_table->gfxclk_pstate.min = gfx_table->min;
 489         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 490
 491         pstate_table->uclk_pstate.min = mem_table->min;
 492         pstate_table->uclk_pstate.peak = mem_table->max;
 493
 494         pstate_table->socclk_pstate.min = soc_table->min;
 495         pstate_table->socclk_pstate.peak = soc_table->max;
 496
 497         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 498             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 499             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 500                 pstate_table->gfxclk_pstate.standard =
 501                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 502                 pstate_table->uclk_pstate.standard =
 503                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 504                 pstate_table->socclk_pstate.standard =
 505                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 506         } else {
 507                 pstate_table->gfxclk_pstate.standard =
 508                         pstate_table->gfxclk_pstate.min;
 509                 pstate_table->uclk_pstate.standard =
 510                         pstate_table->uclk_pstate.min;
 511                 pstate_table->socclk_pstate.standard =
 512                         pstate_table->socclk_pstate.min;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static int arcturus_get_clk_table(struct smu_context *smu,
 519                         struct pp_clock_levels_with_latency *clocks,
 520                         struct smu_11_0_dpm_table *dpm_table)
 521 {
 522         int i, count;
 523
 524         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 525         clocks->num_levels = count;
 526
 527         for (i = 0; i < count; i++) {
 528                 clocks->data[i].clocks_in_khz =
 529                         dpm_table->dpm_levels[i].value * 1000;
 530                 clocks->data[i].latency_in_us = 0;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int arcturus_freqs_in_same_level(int32_t frequency1,
 537                                         int32_t frequency2)
 538 {
 539         return (abs(frequency1 - frequency2) <= EPSILON);
 540 }
 541
 542 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 543                                          MetricsMember_t member,
 544                                          uint32_t *value)
 545 {
 546         struct smu_table_context *smu_table= &smu->smu_table;
 547         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 548         int ret = 0;
 549
 550         mutex_lock(&smu->metrics_lock);
 551
 552         ret = smu_cmn_get_metrics_table_locked(smu,
 553                                                NULL,
 554                                                false);
 555         if (ret) {
 556                 mutex_unlock(&smu->metrics_lock);
 557                 return ret;
 558         }
 559
 560         switch (member) {
 561         case METRICS_CURR_GFXCLK:
 562                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 563                 break;
 564         case METRICS_CURR_SOCCLK:
 565                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 566                 break;
 567         case METRICS_CURR_UCLK:
 568                 *value = metrics->CurrClock[PPCLK_UCLK];
 569                 break;
 570         case METRICS_CURR_VCLK:
 571                 *value = metrics->CurrClock[PPCLK_VCLK];
 572                 break;
 573         case METRICS_CURR_DCLK:
 574                 *value = metrics->CurrClock[PPCLK_DCLK];
 575                 break;
 576         case METRICS_CURR_FCLK:
 577                 *value = metrics->CurrClock[PPCLK_FCLK];
 578                 break;
 579         case METRICS_AVERAGE_GFXCLK:
 580                 *value = metrics->AverageGfxclkFrequency;
 581                 break;
 582         case METRICS_AVERAGE_SOCCLK:
 583                 *value = metrics->AverageSocclkFrequency;
 584                 break;
 585         case METRICS_AVERAGE_UCLK:
 586                 *value = metrics->AverageUclkFrequency;
 587                 break;
 588         case METRICS_AVERAGE_VCLK:
 589                 *value = metrics->AverageVclkFrequency;
 590                 break;
 591         case METRICS_AVERAGE_DCLK:
 592                 *value = metrics->AverageDclkFrequency;
 593                 break;
 594         case METRICS_AVERAGE_GFXACTIVITY:
 595                 *value = metrics->AverageGfxActivity;
 596                 break;
 597         case METRICS_AVERAGE_MEMACTIVITY:
 598                 *value = metrics->AverageUclkActivity;
 599                 break;
 600         case METRICS_AVERAGE_VCNACTIVITY:
 601                 *value = metrics->VcnActivityPercentage;
 602                 break;
 603         case METRICS_AVERAGE_SOCKETPOWER:
 604                 *value = metrics->AverageSocketPower << 8;
 605                 break;
 606         case METRICS_TEMPERATURE_EDGE:
 607                 *value = metrics->TemperatureEdge *
 608                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 609                 break;
 610         case METRICS_TEMPERATURE_HOTSPOT:
 611                 *value = metrics->TemperatureHotspot *
 612                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 613                 break;
 614         case METRICS_TEMPERATURE_MEM:
 615                 *value = metrics->TemperatureHBM *
 616                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 617                 break;
 618         case METRICS_TEMPERATURE_VRGFX:
 619                 *value = metrics->TemperatureVrGfx *
 620                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 621                 break;
 622         case METRICS_TEMPERATURE_VRSOC:
 623                 *value = metrics->TemperatureVrSoc *
 624                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 625                 break;
 626         case METRICS_TEMPERATURE_VRMEM:
 627                 *value = metrics->TemperatureVrMem *
 628                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 629                 break;
 630         case METRICS_THROTTLER_STATUS:
 631                 *value = metrics->ThrottlerStatus;
 632                 break;
 633         case METRICS_CURR_FANSPEED:
 634                 *value = metrics->CurrFanSpeed;
 635                 break;
 636         default:
 637                 *value = UINT_MAX;
 638                 break;
 639         }
 640
 641         mutex_unlock(&smu->metrics_lock);
 642
 643         return ret;
 644 }
 645
 646 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 647                                        enum smu_clk_type clk_type,
 648                                        uint32_t *value)
 649 {
 650         MetricsMember_t member_type;
 651         int clk_id = 0;
 652
 653         if (!value)
 654                 return -EINVAL;
 655
 656         clk_id = smu_cmn_to_asic_specific_index(smu,
 657                                                 CMN2ASIC_MAPPING_CLK,
 658                                                 clk_type);
 659         if (clk_id < 0)
 660                 return -EINVAL;
 661
 662         switch (clk_id) {
 663         case PPCLK_GFXCLK:
 664                 /*
 665                  * CurrClock[clk_id] can provide accurate
 666                  *   output only when the dpm feature is enabled.
 667                  * We can use Average_* for dpm disabled case.
 668                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 669                  */
 670                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 671                         member_type = METRICS_CURR_GFXCLK;
 672                 else
 673                         member_type = METRICS_AVERAGE_GFXCLK;
 674                 break;
 675         case PPCLK_UCLK:
 676                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 677                         member_type = METRICS_CURR_UCLK;
 678                 else
 679                         member_type = METRICS_AVERAGE_UCLK;
 680                 break;
 681         case PPCLK_SOCCLK:
 682                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 683                         member_type = METRICS_CURR_SOCCLK;
 684                 else
 685                         member_type = METRICS_AVERAGE_SOCCLK;
 686                 break;
 687         case PPCLK_VCLK:
 688                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 689                         member_type = METRICS_CURR_VCLK;
 690                 else
 691                         member_type = METRICS_AVERAGE_VCLK;
 692                 break;
 693         case PPCLK_DCLK:
 694                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 695                         member_type = METRICS_CURR_DCLK;
 696                 else
 697                         member_type = METRICS_AVERAGE_DCLK;
 698                 break;
 699         case PPCLK_FCLK:
 700                 member_type = METRICS_CURR_FCLK;
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705
 706         return arcturus_get_smu_metrics_data(smu,
 707                                              member_type,
 708                                              value);
 709 }
 710
 711 static int arcturus_print_clk_levels(struct smu_context *smu,
 712                         enum smu_clk_type type, char *buf)
 713 {
 714         int i, now, size = 0;
 715         int ret = 0;
 716         struct pp_clock_levels_with_latency clocks;
 717         struct smu_11_0_dpm_table *single_dpm_table;
 718         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 719         struct smu_11_0_dpm_context *dpm_context = NULL;
 720         uint32_t gen_speed, lane_width;
 721
 722         if (amdgpu_ras_intr_triggered())
 723                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 724
 725         dpm_context = smu_dpm->dpm_context;
 726
 727         switch (type) {
 728         case SMU_SCLK:
 729                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 730                 if (ret) {
 731                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 732                         return ret;
 733                 }
 734
 735                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 736                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 737                 if (ret) {
 738                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 739                         return ret;
 740                 }
 741
 742                 /*
 743                  * For DPM disabled case, there will be only one clock level.
 744                  * And it's safe to assume that is always the current clock.
 745                  */
 746                 for (i = 0; i < clocks.num_levels; i++)
 747                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 748                                         clocks.data[i].clocks_in_khz / 1000,
 749                                         (clocks.num_levels == 1) ? "*" :
 750                                         (arcturus_freqs_in_same_level(
 751                                         clocks.data[i].clocks_in_khz / 1000,
 752                                         now) ? "*" : ""));
 753                 break;
 754
 755         case SMU_MCLK:
 756                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 757                 if (ret) {
 758                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 759                         return ret;
 760                 }
 761
 762                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 763                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 764                 if (ret) {
 765                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 766                         return ret;
 767                 }
 768
 769                 for (i = 0; i < clocks.num_levels; i++)
 770                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 771                                 i, clocks.data[i].clocks_in_khz / 1000,
 772                                 (clocks.num_levels == 1) ? "*" :
 773                                 (arcturus_freqs_in_same_level(
 774                                 clocks.data[i].clocks_in_khz / 1000,
 775                                 now) ? "*" : ""));
 776                 break;
 777
 778         case SMU_SOCCLK:
 779                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 780                 if (ret) {
 781                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 782                         return ret;
 783                 }
 784
 785                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 786                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 787                 if (ret) {
 788                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 789                         return ret;
 790                 }
 791
 792                 for (i = 0; i < clocks.num_levels; i++)
 793                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 794                                 i, clocks.data[i].clocks_in_khz / 1000,
 795                                 (clocks.num_levels == 1) ? "*" :
 796                                 (arcturus_freqs_in_same_level(
 797                                 clocks.data[i].clocks_in_khz / 1000,
 798                                 now) ? "*" : ""));
 799                 break;
 800
 801         case SMU_FCLK:
 802                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 803                 if (ret) {
 804                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 805                         return ret;
 806                 }
 807
 808                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 809                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 810                 if (ret) {
 811                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 812                         return ret;
 813                 }
 814
 815                 for (i = 0; i < single_dpm_table->count; i++)
 816                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 817                                 i, single_dpm_table->dpm_levels[i].value,
 818                                 (clocks.num_levels == 1) ? "*" :
 819                                 (arcturus_freqs_in_same_level(
 820                                 clocks.data[i].clocks_in_khz / 1000,
 821                                 now) ? "*" : ""));
 822                 break;
 823
 824         case SMU_PCIE:
 825                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 826                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 827                 size += sprintf(buf + size, "0: %s %s %dMhz *\n",
 828                                 (gen_speed == 0) ? "2.5GT/s," :
 829                                 (gen_speed == 1) ? "5.0GT/s," :
 830                                 (gen_speed == 2) ? "8.0GT/s," :
 831                                 (gen_speed == 3) ? "16.0GT/s," : "",
 832                                 (lane_width == 1) ? "x1" :
 833                                 (lane_width == 2) ? "x2" :
 834                                 (lane_width == 3) ? "x4" :
 835                                 (lane_width == 4) ? "x8" :
 836                                 (lane_width == 5) ? "x12" :
 837                                 (lane_width == 6) ? "x16" : "",
 838                                 smu->smu_table.boot_values.lclk / 100);
 839                 break;
 840
 841         default:
 842                 break;
 843         }
 844
 845         return size;
 846 }
 847
 848 static int arcturus_upload_dpm_level(struct smu_context *smu,
 849                                      bool max,
 850                                      uint32_t feature_mask,
 851                                      uint32_t level)
 852 {
 853         struct smu_11_0_dpm_context *dpm_context =
 854                         smu->smu_dpm.dpm_context;
 855         uint32_t freq;
 856         int ret = 0;
 857
 858         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 859             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 860                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 861                 ret = smu_cmn_send_smc_msg_with_param(smu,
 862                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 863                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 864                         NULL);
 865                 if (ret) {
 866                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 867                                                 max ? "max" : "min");
 868                         return ret;
 869                 }
 870         }
 871
 872         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 873             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 874                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 875                 ret = smu_cmn_send_smc_msg_with_param(smu,
 876                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 877                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 878                         NULL);
 879                 if (ret) {
 880                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 881                                                 max ? "max" : "min");
 882                         return ret;
 883                 }
 884         }
 885
 886         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 887             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 888                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 889                 ret = smu_cmn_send_smc_msg_with_param(smu,
 890                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 891                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 892                         NULL);
 893                 if (ret) {
 894                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 895                                                 max ? "max" : "min");
 896                         return ret;
 897                 }
 898         }
 899
 900         return ret;
 901 }
 902
 903 static int arcturus_force_clk_levels(struct smu_context *smu,
 904                         enum smu_clk_type type, uint32_t mask)
 905 {
 906         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 907         struct smu_11_0_dpm_table *single_dpm_table = NULL;
 908         uint32_t soft_min_level, soft_max_level;
 909         uint32_t smu_version;
 910         int ret = 0;
 911
 912         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 913         if (ret) {
 914                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 915                 return ret;
 916         }
 917
 918         if ((smu_version >= 0x361200) &&
 919             (smu_version <= 0x361a00)) {
 920                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
 921                        "54.18 - 54.26(included) SMU firmwares\n");
 922                 return -EOPNOTSUPP;
 923         }
 924
 925         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 926         soft_max_level = mask ? (fls(mask) - 1) : 0;
 927
 928         switch (type) {
 929         case SMU_SCLK:
 930                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 931                 if (soft_max_level >= single_dpm_table->count) {
 932                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 933                                         soft_max_level, single_dpm_table->count - 1);
 934                         ret = -EINVAL;
 935                         break;
 936                 }
 937
 938                 ret = arcturus_upload_dpm_level(smu,
 939                                                 false,
 940                                                 FEATURE_DPM_GFXCLK_MASK,
 941                                                 soft_min_level);
 942                 if (ret) {
 943                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 944                         break;
 945                 }
 946
 947                 ret = arcturus_upload_dpm_level(smu,
 948                                                 true,
 949                                                 FEATURE_DPM_GFXCLK_MASK,
 950                                                 soft_max_level);
 951                 if (ret)
 952                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 953
 954                 break;
 955
 956         case SMU_MCLK:
 957         case SMU_SOCCLK:
 958         case SMU_FCLK:
 959                 /*
 960                  * Should not arrive here since Arcturus does not
 961                  * support mclk/socclk/fclk softmin/softmax settings
 962                  */
 963                 ret = -EINVAL;
 964                 break;
 965
 966         default:
 967                 break;
 968         }
 969
 970         return ret;
 971 }
 972
 973 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 974                                                 struct smu_temperature_range *range)
 975 {
 976         struct smu_table_context *table_context = &smu->smu_table;
 977         struct smu_11_0_powerplay_table *powerplay_table =
 978                                 table_context->power_play_table;
 979         PPTable_t *pptable = smu->smu_table.driver_pptable;
 980
 981         if (!range)
 982                 return -EINVAL;
 983
 984         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
 985
 986         range->max = pptable->TedgeLimit *
 987                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 988         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 989                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 990         range->hotspot_crit_max = pptable->ThotspotLimit *
 991                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 992         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 993                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 994         range->mem_crit_max = pptable->TmemLimit *
 995                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 996         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
 997                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 998         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
 999
1000         return 0;
1001 }
1002
1003 static int arcturus_read_sensor(struct smu_context *smu,
1004                                 enum amd_pp_sensors sensor,
1005                                 void *data, uint32_t *size)
1006 {
1007         struct smu_table_context *table_context = &smu->smu_table;
1008         PPTable_t *pptable = table_context->driver_pptable;
1009         int ret = 0;
1010
1011         if (amdgpu_ras_intr_triggered())
1012                 return 0;
1013
1014         if (!data || !size)
1015                 return -EINVAL;
1016
1017         mutex_lock(&smu->sensor_lock);
1018         switch (sensor) {
1019         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1020                 *(uint32_t *)data = pptable->FanMaximumRpm;
1021                 *size = 4;
1022                 break;
1023         case AMDGPU_PP_SENSOR_MEM_LOAD:
1024                 ret = arcturus_get_smu_metrics_data(smu,
1025                                                     METRICS_AVERAGE_MEMACTIVITY,
1026                                                     (uint32_t *)data);
1027                 *size = 4;
1028                 break;
1029         case AMDGPU_PP_SENSOR_GPU_LOAD:
1030                 ret = arcturus_get_smu_metrics_data(smu,
1031                                                     METRICS_AVERAGE_GFXACTIVITY,
1032                                                     (uint32_t *)data);
1033                 *size = 4;
1034                 break;
1035         case AMDGPU_PP_SENSOR_GPU_POWER:
1036                 ret = arcturus_get_smu_metrics_data(smu,
1037                                                     METRICS_AVERAGE_SOCKETPOWER,
1038                                                     (uint32_t *)data);
1039                 *size = 4;
1040                 break;
1041         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1042                 ret = arcturus_get_smu_metrics_data(smu,
1043                                                     METRICS_TEMPERATURE_HOTSPOT,
1044                                                     (uint32_t *)data);
1045                 *size = 4;
1046                 break;
1047         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1048                 ret = arcturus_get_smu_metrics_data(smu,
1049                                                     METRICS_TEMPERATURE_EDGE,
1050                                                     (uint32_t *)data);
1051                 *size = 4;
1052                 break;
1053         case AMDGPU_PP_SENSOR_MEM_TEMP:
1054                 ret = arcturus_get_smu_metrics_data(smu,
1055                                                     METRICS_TEMPERATURE_MEM,
1056                                                     (uint32_t *)data);
1057                 *size = 4;
1058                 break;
1059         case AMDGPU_PP_SENSOR_GFX_MCLK:
1060                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1061                 /* the output clock frequency in 10K unit */
1062                 *(uint32_t *)data *= 100;
1063                 *size = 4;
1064                 break;
1065         case AMDGPU_PP_SENSOR_GFX_SCLK:
1066                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1067                 *(uint32_t *)data *= 100;
1068                 *size = 4;
1069                 break;
1070         case AMDGPU_PP_SENSOR_VDDGFX:
1071                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1072                 *size = 4;
1073                 break;
1074         default:
1075                 ret = -EOPNOTSUPP;
1076                 break;
1077         }
1078         mutex_unlock(&smu->sensor_lock);
1079
1080         return ret;
1081 }
1082
1083 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1084                                       uint32_t *speed)
1085 {
1086         if (!speed)
1087                 return -EINVAL;
1088
1089         return arcturus_get_smu_metrics_data(smu,
1090                                              METRICS_CURR_FANSPEED,
1091                                              speed);
1092 }
1093
1094 static int arcturus_get_fan_parameters(struct smu_context *smu)
1095 {
1096         PPTable_t *pptable = smu->smu_table.driver_pptable;
1097
1098         smu->fan_max_rpm = pptable->FanMaximumRpm;
1099
1100         return 0;
1101 }
1102
1103 static int arcturus_get_power_limit(struct smu_context *smu)
1104 {
1105         struct smu_11_0_powerplay_table *powerplay_table =
1106                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1107         PPTable_t *pptable = smu->smu_table.driver_pptable;
1108         uint32_t power_limit, od_percent;
1109
1110         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1111                 /* the last hope to figure out the ppt limit */
1112                 if (!pptable) {
1113                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1114                         return -EINVAL;
1115                 }
1116                 power_limit =
1117                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1118         }
1119         smu->current_power_limit = power_limit;
1120
1121         if (smu->od_enabled) {
1122                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1123
1124                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1125
1126                 power_limit *= (100 + od_percent);
1127                 power_limit /= 100;
1128         }
1129         smu->max_power_limit = power_limit;
1130
1131         return 0;
1132 }
1133
1134 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1135                                            char *buf)
1136 {
1137         DpmActivityMonitorCoeffInt_t activity_monitor;
1138         static const char *profile_name[] = {
1139                                         "BOOTUP_DEFAULT",
1140                                         "3D_FULL_SCREEN",
1141                                         "POWER_SAVING",
1142                                         "VIDEO",
1143                                         "VR",
1144                                         "COMPUTE",
1145                                         "CUSTOM"};
1146         static const char *title[] = {
1147                         "PROFILE_INDEX(NAME)",
1148                         "CLOCK_TYPE(NAME)",
1149                         "FPS",
1150                         "UseRlcBusy",
1151                         "MinActiveFreqType",
1152                         "MinActiveFreq",
1153                         "BoosterFreqType",
1154                         "BoosterFreq",
1155                         "PD_Data_limit_c",
1156                         "PD_Data_error_coeff",
1157                         "PD_Data_error_rate_coeff"};
1158         uint32_t i, size = 0;
1159         int16_t workload_type = 0;
1160         int result = 0;
1161         uint32_t smu_version;
1162
1163         if (!buf)
1164                 return -EINVAL;
1165
1166         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1167         if (result)
1168                 return result;
1169
1170         if (smu_version >= 0x360d00)
1171                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1172                         title[0], title[1], title[2], title[3], title[4], title[5],
1173                         title[6], title[7], title[8], title[9], title[10]);
1174         else
1175                 size += sprintf(buf + size, "%16s\n",
1176                         title[0]);
1177
1178         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1179                 /*
1180                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1181                  * Not all profile modes are supported on arcturus.
1182                  */
1183                 workload_type = smu_cmn_to_asic_specific_index(smu,
1184                                                                CMN2ASIC_MAPPING_WORKLOAD,
1185                                                                i);
1186                 if (workload_type < 0)
1187                         continue;
1188
1189                 if (smu_version >= 0x360d00) {
1190                         result = smu_cmn_update_table(smu,
1191                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1192                                                   workload_type,
1193                                                   (void *)(&activity_monitor),
1194                                                   false);
1195                         if (result) {
1196                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1197                                 return result;
1198                         }
1199                 }
1200
1201                 size += sprintf(buf + size, "%2d %14s%s\n",
1202                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1203
1204                 if (smu_version >= 0x360d00) {
1205                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1206                                 " ",
1207                                 0,
1208                                 "GFXCLK",
1209                                 activity_monitor.Gfx_FPS,
1210                                 activity_monitor.Gfx_UseRlcBusy,
1211                                 activity_monitor.Gfx_MinActiveFreqType,
1212                                 activity_monitor.Gfx_MinActiveFreq,
1213                                 activity_monitor.Gfx_BoosterFreqType,
1214                                 activity_monitor.Gfx_BoosterFreq,
1215                                 activity_monitor.Gfx_PD_Data_limit_c,
1216                                 activity_monitor.Gfx_PD_Data_error_coeff,
1217                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1218
1219                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1220                                 " ",
1221                                 1,
1222                                 "UCLK",
1223                                 activity_monitor.Mem_FPS,
1224                                 activity_monitor.Mem_UseRlcBusy,
1225                                 activity_monitor.Mem_MinActiveFreqType,
1226                                 activity_monitor.Mem_MinActiveFreq,
1227                                 activity_monitor.Mem_BoosterFreqType,
1228                                 activity_monitor.Mem_BoosterFreq,
1229                                 activity_monitor.Mem_PD_Data_limit_c,
1230                                 activity_monitor.Mem_PD_Data_error_coeff,
1231                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1232                 }
1233         }
1234
1235         return size;
1236 }
1237
1238 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1239                                            long *input,
1240                                            uint32_t size)
1241 {
1242         DpmActivityMonitorCoeffInt_t activity_monitor;
1243         int workload_type = 0;
1244         uint32_t profile_mode = input[size];
1245         int ret = 0;
1246         uint32_t smu_version;
1247
1248         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1249                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1250                 return -EINVAL;
1251         }
1252
1253         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1254         if (ret)
1255                 return ret;
1256
1257         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1258              (smu_version >=0x360d00)) {
1259                 ret = smu_cmn_update_table(smu,
1260                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1261                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1262                                        (void *)(&activity_monitor),
1263                                        false);
1264                 if (ret) {
1265                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1266                         return ret;
1267                 }
1268
1269                 switch (input[0]) {
1270                 case 0: /* Gfxclk */
1271                         activity_monitor.Gfx_FPS = input[1];
1272                         activity_monitor.Gfx_UseRlcBusy = input[2];
1273                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1274                         activity_monitor.Gfx_MinActiveFreq = input[4];
1275                         activity_monitor.Gfx_BoosterFreqType = input[5];
1276                         activity_monitor.Gfx_BoosterFreq = input[6];
1277                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1278                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1279                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1280                         break;
1281                 case 1: /* Uclk */
1282                         activity_monitor.Mem_FPS = input[1];
1283                         activity_monitor.Mem_UseRlcBusy = input[2];
1284                         activity_monitor.Mem_MinActiveFreqType = input[3];
1285                         activity_monitor.Mem_MinActiveFreq = input[4];
1286                         activity_monitor.Mem_BoosterFreqType = input[5];
1287                         activity_monitor.Mem_BoosterFreq = input[6];
1288                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1289                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1290                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1291                         break;
1292                 }
1293
1294                 ret = smu_cmn_update_table(smu,
1295                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1296                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1297                                        (void *)(&activity_monitor),
1298                                        true);
1299                 if (ret) {
1300                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1301                         return ret;
1302                 }
1303         }
1304
1305         /*
1306          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1307          * Not all profile modes are supported on arcturus.
1308          */
1309         workload_type = smu_cmn_to_asic_specific_index(smu,
1310                                                        CMN2ASIC_MAPPING_WORKLOAD,
1311                                                        profile_mode);
1312         if (workload_type < 0) {
1313                 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1314                 return -EINVAL;
1315         }
1316
1317         ret = smu_cmn_send_smc_msg_with_param(smu,
1318                                           SMU_MSG_SetWorkloadMask,
1319                                           1 << workload_type,
1320                                           NULL);
1321         if (ret) {
1322                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1323                 return ret;
1324         }
1325
1326         smu->power_profile_mode = profile_mode;
1327
1328         return 0;
1329 }
1330
1331 static int arcturus_set_performance_level(struct smu_context *smu,
1332                                           enum amd_dpm_forced_level level)
1333 {
1334         uint32_t smu_version;
1335         int ret;
1336
1337         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1338         if (ret) {
1339                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1340                 return ret;
1341         }
1342
1343         switch (level) {
1344         case AMD_DPM_FORCED_LEVEL_HIGH:
1345         case AMD_DPM_FORCED_LEVEL_LOW:
1346         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1347         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1348         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1349         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1350                 if ((smu_version >= 0x361200) &&
1351                     (smu_version <= 0x361a00)) {
1352                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1353                                "54.18 - 54.26(included) SMU firmwares\n");
1354                         return -EOPNOTSUPP;
1355                 }
1356                 break;
1357         default:
1358                 break;
1359         }
1360
1361         return smu_v11_0_set_performance_level(smu, level);
1362 }
1363
1364 static void arcturus_dump_pptable(struct smu_context *smu)
1365 {
1366         struct smu_table_context *table_context = &smu->smu_table;
1367         PPTable_t *pptable = table_context->driver_pptable;
1368         int i;
1369
1370         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1371
1372         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1373
1374         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1375         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1376
1377         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1378                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1379                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1380         }
1381
1382         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1383         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1384         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1385         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1386
1387         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1388         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1389         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1390         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1391         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1392         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1393         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1394
1395         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1396         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1397
1398         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1399
1400         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1401         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1402
1403         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1404         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1405         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1406         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1407
1408         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1409         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1410         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1411         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1412
1413         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1414         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1415
1416         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1417                         "  .VoltageMode          = 0x%02x\n"
1418                         "  .SnapToDiscrete       = 0x%02x\n"
1419                         "  .NumDiscreteLevels    = 0x%02x\n"
1420                         "  .padding              = 0x%02x\n"
1421                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1422                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1423                         "  .SsFmin               = 0x%04x\n"
1424                         "  .Padding_16           = 0x%04x\n",
1425                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1426                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1427                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1428                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1429                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1430                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1431                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1432                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1433                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1434                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1435                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1436
1437         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1438                         "  .VoltageMode          = 0x%02x\n"
1439                         "  .SnapToDiscrete       = 0x%02x\n"
1440                         "  .NumDiscreteLevels    = 0x%02x\n"
1441                         "  .padding              = 0x%02x\n"
1442                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1443                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1444                         "  .SsFmin               = 0x%04x\n"
1445                         "  .Padding_16           = 0x%04x\n",
1446                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1447                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1448                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1449                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1450                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1451                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1452                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1453                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1454                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1455                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1456                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1457
1458         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1459                         "  .VoltageMode          = 0x%02x\n"
1460                         "  .SnapToDiscrete       = 0x%02x\n"
1461                         "  .NumDiscreteLevels    = 0x%02x\n"
1462                         "  .padding              = 0x%02x\n"
1463                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1464                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1465                         "  .SsFmin               = 0x%04x\n"
1466                         "  .Padding_16           = 0x%04x\n",
1467                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1468                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1469                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1470                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1471                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1472                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1473                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1474                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1475                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1476                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1477                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1478
1479         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1480                         "  .VoltageMode          = 0x%02x\n"
1481                         "  .SnapToDiscrete       = 0x%02x\n"
1482                         "  .NumDiscreteLevels    = 0x%02x\n"
1483                         "  .padding              = 0x%02x\n"
1484                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1485                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1486                         "  .SsFmin               = 0x%04x\n"
1487                         "  .Padding_16           = 0x%04x\n",
1488                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1489                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1490                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1491                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1492                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1493                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1494                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1495                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1496                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1497                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1498                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1499
1500         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1501                         "  .VoltageMode          = 0x%02x\n"
1502                         "  .SnapToDiscrete       = 0x%02x\n"
1503                         "  .NumDiscreteLevels    = 0x%02x\n"
1504                         "  .padding              = 0x%02x\n"
1505                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1506                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1507                         "  .SsFmin               = 0x%04x\n"
1508                         "  .Padding_16           = 0x%04x\n",
1509                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1510                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1511                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1512                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1513                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1514                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1515                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1516                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1517                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1518                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1519                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1520
1521         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1522                         "  .VoltageMode          = 0x%02x\n"
1523                         "  .SnapToDiscrete       = 0x%02x\n"
1524                         "  .NumDiscreteLevels    = 0x%02x\n"
1525                         "  .padding              = 0x%02x\n"
1526                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1527                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1528                         "  .SsFmin               = 0x%04x\n"
1529                         "  .Padding_16           = 0x%04x\n",
1530                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1531                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1532                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1533                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1534                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1535                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1536                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1537                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1538                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1539                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1540                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1541
1542
1543         dev_info(smu->adev->dev, "FreqTableGfx\n");
1544         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1545                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1546
1547         dev_info(smu->adev->dev, "FreqTableVclk\n");
1548         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1549                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1550
1551         dev_info(smu->adev->dev, "FreqTableDclk\n");
1552         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1553                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1554
1555         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1556         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1557                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1558
1559         dev_info(smu->adev->dev, "FreqTableUclk\n");
1560         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1561                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1562
1563         dev_info(smu->adev->dev, "FreqTableFclk\n");
1564         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1565                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1566
1567         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1568         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1569                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1570
1571         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1572         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1573                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1574
1575         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1576         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1577         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1578         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1579         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1580         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1581         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1582         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1583         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1584
1585         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1586         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1587         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1588         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1589
1590         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1591         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1592
1593         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1594         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1595         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1596         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1597         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1598         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1599
1600         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1601         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1602         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1603         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1604         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1605         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1606         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1607         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1608         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1609
1610         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1611         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1612         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1613         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1614
1615         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1616         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1617         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1618         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1619
1620         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1621                         pptable->dBtcGbGfxPll.a,
1622                         pptable->dBtcGbGfxPll.b,
1623                         pptable->dBtcGbGfxPll.c);
1624         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1625                         pptable->dBtcGbGfxAfll.a,
1626                         pptable->dBtcGbGfxAfll.b,
1627                         pptable->dBtcGbGfxAfll.c);
1628         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1629                         pptable->dBtcGbSoc.a,
1630                         pptable->dBtcGbSoc.b,
1631                         pptable->dBtcGbSoc.c);
1632
1633         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1634                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1635                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1636         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1637                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1638                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1639
1640         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1641                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1642                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1643                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1644         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1645                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1646                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1647                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1648
1649         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1650         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1651
1652         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1653         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1654         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1655         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1656
1657         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1658         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1659         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1660         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1661
1662         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1663         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1664
1665         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1666         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1667                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1668         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1669         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1670
1671         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1672         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1673         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1674         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1675         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1676         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1677         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1678         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1679
1680         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1681         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1682                         pptable->ReservedEquation0.a,
1683                         pptable->ReservedEquation0.b,
1684                         pptable->ReservedEquation0.c);
1685         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1686                         pptable->ReservedEquation1.a,
1687                         pptable->ReservedEquation1.b,
1688                         pptable->ReservedEquation1.c);
1689         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1690                         pptable->ReservedEquation2.a,
1691                         pptable->ReservedEquation2.b,
1692                         pptable->ReservedEquation2.c);
1693         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1694                         pptable->ReservedEquation3.a,
1695                         pptable->ReservedEquation3.b,
1696                         pptable->ReservedEquation3.c);
1697
1698         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1699         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1700
1701         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1702         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1703         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1704
1705         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1706         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1707
1708         dev_info(smu->adev->dev, "Board Parameters:\n");
1709         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1710         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1711
1712         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1713         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1714         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1715         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1716
1717         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1718         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1719
1720         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1721         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1722         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1723
1724         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1725         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1726         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1727
1728         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1729         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1730         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1731
1732         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1733         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1734         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1735
1736         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1737         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1738         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1739         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1740
1741         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1742         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1743         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1744
1745         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1746         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1747         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1748
1749         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1750         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1751         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1752
1753         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1754         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1755         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1756
1757         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1758                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1759                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1760                                 pptable->I2cControllers[i].Enabled);
1761                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1762                                 pptable->I2cControllers[i].SlaveAddress);
1763                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1764                                 pptable->I2cControllers[i].ControllerPort);
1765                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1766                                 pptable->I2cControllers[i].ControllerName);
1767                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1768                                 pptable->I2cControllers[i].ThermalThrotter);
1769                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1770                                 pptable->I2cControllers[i].I2cProtocol);
1771                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
1772                                 pptable->I2cControllers[i].Speed);
1773         }
1774
1775         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1776         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1777
1778         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1779
1780         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1781         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1782                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1783         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1784         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1785                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1786         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1787         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1788                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1789         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1790         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1791                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1792
1793 }
1794
1795 static bool arcturus_is_dpm_running(struct smu_context *smu)
1796 {
1797         int ret = 0;
1798         uint32_t feature_mask[2];
1799         uint64_t feature_enabled;
1800
1801         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1802         if (ret)
1803                 return false;
1804
1805         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1806
1807         return !!(feature_enabled & SMC_DPM_FEATURE);
1808 }
1809
1810 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1811 {
1812         int ret = 0;
1813
1814         if (enable) {
1815                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1816                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1817                         if (ret) {
1818                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1819                                 return ret;
1820                         }
1821                 }
1822         } else {
1823                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1824                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1825                         if (ret) {
1826                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1827                                 return ret;
1828                         }
1829                 }
1830         }
1831
1832         return ret;
1833 }
1834
1835 static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1836                                   uint8_t address, uint32_t numbytes,
1837                                   uint8_t *data)
1838 {
1839         int i;
1840
1841         req->I2CcontrollerPort = 0;
1842         req->I2CSpeed = 2;
1843         req->SlaveAddress = address;
1844         req->NumCmds = numbytes;
1845
1846         for (i = 0; i < numbytes; i++) {
1847                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1848
1849                 /* First 2 bytes are always write for lower 2b EEPROM address */
1850                 if (i < 2)
1851                         cmd->Cmd = 1;
1852                 else
1853                         cmd->Cmd = write;
1854
1855
1856                 /* Add RESTART for read  after address filled */
1857                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1858
1859                 /* Add STOP in the end */
1860                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1861
1862                 /* Fill with data regardless if read or write to simplify code */
1863                 cmd->RegisterAddr = data[i];
1864         }
1865 }
1866
1867 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1868                                                uint8_t address,
1869                                                uint8_t *data,
1870                                                uint32_t numbytes)
1871 {
1872         uint32_t  i, ret = 0;
1873         SwI2cRequest_t req;
1874         struct amdgpu_device *adev = to_amdgpu_device(control);
1875         struct smu_table_context *smu_table = &adev->smu.smu_table;
1876         struct smu_table *table = &smu_table->driver_table;
1877
1878         if (numbytes > MAX_SW_I2C_COMMANDS) {
1879                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1880                         numbytes, MAX_SW_I2C_COMMANDS);
1881                 return -EINVAL;
1882         }
1883
1884         memset(&req, 0, sizeof(req));
1885         arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1886
1887         mutex_lock(&adev->smu.mutex);
1888         /* Now read data starting with that address */
1889         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1890                                         true);
1891         mutex_unlock(&adev->smu.mutex);
1892
1893         if (!ret) {
1894                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1895
1896                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1897                 for (i = 0; i < numbytes; i++)
1898                         data[i] = res->SwI2cCmds[i].Data;
1899
1900                 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1901                                   (uint16_t)address, numbytes);
1902
1903                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1904                                8, 1, data, numbytes, false);
1905         } else
1906                 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1907
1908         return ret;
1909 }
1910
1911 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1912                                                 uint8_t address,
1913                                                 uint8_t *data,
1914                                                 uint32_t numbytes)
1915 {
1916         uint32_t ret;
1917         SwI2cRequest_t req;
1918         struct amdgpu_device *adev = to_amdgpu_device(control);
1919
1920         if (numbytes > MAX_SW_I2C_COMMANDS) {
1921                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1922                         numbytes, MAX_SW_I2C_COMMANDS);
1923                 return -EINVAL;
1924         }
1925
1926         memset(&req, 0, sizeof(req));
1927         arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1928
1929         mutex_lock(&adev->smu.mutex);
1930         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1931         mutex_unlock(&adev->smu.mutex);
1932
1933         if (!ret) {
1934                 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1935                                          (uint16_t)address, numbytes);
1936
1937                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1938                                8, 1, data, numbytes, false);
1939                 /*
1940                  * According to EEPROM spec there is a MAX of 10 ms required for
1941                  * EEPROM to flush internal RX buffer after STOP was issued at the
1942                  * end of write transaction. During this time the EEPROM will not be
1943                  * responsive to any more commands - so wait a bit more.
1944                  */
1945                 msleep(10);
1946
1947         } else
1948                 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1949
1950         return ret;
1951 }
1952
1953 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1954                               struct i2c_msg *msgs, int num)
1955 {
1956         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1957         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1958
1959         for (i = 0; i < num; i++) {
1960                 /*
1961                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1962                  * once and hence the data needs to be spliced into chunks and sent each
1963                  * chunk separately
1964                  */
1965                 data_size = msgs[i].len - 2;
1966                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1967                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1968                 data_ptr = msgs[i].buf + 2;
1969
1970                 for (j = 0; j < data_size / data_chunk_size; j++) {
1971                         /* Insert the EEPROM dest addess, bits 0-15 */
1972                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1973                         data_chunk[1] = (next_eeprom_addr & 0xff);
1974
1975                         if (msgs[i].flags & I2C_M_RD) {
1976                                 ret = arcturus_i2c_read_data(i2c_adap,
1977                                                              (uint8_t)msgs[i].addr,
1978                                                              data_chunk, MAX_SW_I2C_COMMANDS);
1979
1980                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1981                         } else {
1982
1983                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1984
1985                                 ret = arcturus_i2c_write_data(i2c_adap,
1986                                                               (uint8_t)msgs[i].addr,
1987                                                               data_chunk, MAX_SW_I2C_COMMANDS);
1988                         }
1989
1990                         if (ret) {
1991                                 num = -EIO;
1992                                 goto fail;
1993                         }
1994
1995                         next_eeprom_addr += data_chunk_size;
1996                         data_ptr += data_chunk_size;
1997                 }
1998
1999                 if (data_size % data_chunk_size) {
2000                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2001                         data_chunk[1] = (next_eeprom_addr & 0xff);
2002
2003                         if (msgs[i].flags & I2C_M_RD) {
2004                                 ret = arcturus_i2c_read_data(i2c_adap,
2005                                                              (uint8_t)msgs[i].addr,
2006                                                              data_chunk, (data_size % data_chunk_size) + 2);
2007
2008                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2009                         } else {
2010                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2011
2012                                 ret = arcturus_i2c_write_data(i2c_adap,
2013                                                               (uint8_t)msgs[i].addr,
2014                                                               data_chunk, (data_size % data_chunk_size) + 2);
2015                         }
2016
2017                         if (ret) {
2018                                 num = -EIO;
2019                                 goto fail;
2020                         }
2021                 }
2022         }
2023
2024 fail:
2025         return num;
2026 }
2027
2028 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2029 {
2030         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2031 }
2032
2033
2034 static const struct i2c_algorithm arcturus_i2c_algo = {
2035         .master_xfer = arcturus_i2c_xfer,
2036         .functionality = arcturus_i2c_func,
2037 };
2038
2039 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2040 {
2041         struct amdgpu_device *adev = to_amdgpu_device(control);
2042         int res;
2043
2044         control->owner = THIS_MODULE;
2045         control->class = I2C_CLASS_SPD;
2046         control->dev.parent = &adev->pdev->dev;
2047         control->algo = &arcturus_i2c_algo;
2048         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2049
2050         res = i2c_add_adapter(control);
2051         if (res)
2052                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2053
2054         return res;
2055 }
2056
2057 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2058 {
2059         i2c_del_adapter(control);
2060 }
2061
2062 static void arcturus_get_unique_id(struct smu_context *smu)
2063 {
2064         struct amdgpu_device *adev = smu->adev;
2065         uint32_t top32 = 0, bottom32 = 0, smu_version;
2066         uint64_t id;
2067
2068         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2069                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2070                 return;
2071         }
2072
2073         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2074         if (smu_version < 0x361700) {
2075                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2076                 return;
2077         }
2078
2079         /* Get the SN to turn into a Unique ID */
2080         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2081         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2082
2083         id = ((uint64_t)bottom32 << 32) | top32;
2084         adev->unique_id = id;
2085         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2086          * 16-digit HEX string for convenience and backwards-compatibility
2087          */
2088         sprintf(adev->serial, "%llx", id);
2089 }
2090
2091 static bool arcturus_is_baco_supported(struct smu_context *smu)
2092 {
2093         struct amdgpu_device *adev = smu->adev;
2094         uint32_t val;
2095
2096         if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2097                 return false;
2098
2099         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2100         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2101 }
2102
2103 static int arcturus_set_df_cstate(struct smu_context *smu,
2104                                   enum pp_df_cstate state)
2105 {
2106         uint32_t smu_version;
2107         int ret;
2108
2109         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2110         if (ret) {
2111                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2112                 return ret;
2113         }
2114
2115         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2116         if (smu_version < 0x360F00) {
2117                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2118                 return -EINVAL;
2119         }
2120
2121         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2122 }
2123
2124 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2125 {
2126         uint32_t smu_version;
2127         int ret;
2128
2129         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2130         if (ret) {
2131                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2132                 return ret;
2133         }
2134
2135         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2136         if (smu_version < 0x00361700) {
2137                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2138                 return -EINVAL;
2139         }
2140
2141         if (en)
2142                 return smu_cmn_send_smc_msg_with_param(smu,
2143                                                    SMU_MSG_GmiPwrDnControl,
2144                                                    1,
2145                                                    NULL);
2146
2147         return smu_cmn_send_smc_msg_with_param(smu,
2148                                            SMU_MSG_GmiPwrDnControl,
2149                                            0,
2150                                            NULL);
2151 }
2152
2153 static const struct throttling_logging_label {
2154         uint32_t feature_mask;
2155         const char *label;
2156 } logging_label[] = {
2157         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2158         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2159         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2160         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2161         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2162         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2163         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2164 };
2165 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2166 {
2167         int ret;
2168         int throttler_idx, throtting_events = 0, buf_idx = 0;
2169         struct amdgpu_device *adev = smu->adev;
2170         uint32_t throttler_status;
2171         char log_buf[256];
2172
2173         ret = arcturus_get_smu_metrics_data(smu,
2174                                             METRICS_THROTTLER_STATUS,
2175                                             &throttler_status);
2176         if (ret)
2177                 return;
2178
2179         memset(log_buf, 0, sizeof(log_buf));
2180         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2181              throttler_idx++) {
2182                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2183                         throtting_events++;
2184                         buf_idx += snprintf(log_buf + buf_idx,
2185                                             sizeof(log_buf) - buf_idx,
2186                                             "%s%s",
2187                                             throtting_events > 1 ? " and " : "",
2188                                             logging_label[throttler_idx].label);
2189                         if (buf_idx >= sizeof(log_buf)) {
2190                                 dev_err(adev->dev, "buffer overflow!\n");
2191                                 log_buf[sizeof(log_buf) - 1] = '\0';
2192                                 break;
2193                         }
2194                 }
2195         }
2196
2197         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2198                         log_buf);
2199         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2200 }
2201
2202 static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2203 {
2204         struct amdgpu_device *adev = smu->adev;
2205         uint32_t esm_ctrl;
2206
2207         /* TODO: confirm this on real target */
2208         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2209         if ((esm_ctrl >> 15) & 0x1FFFF)
2210                 return (((esm_ctrl >> 8) & 0x3F) + 128);
2211
2212         return smu_v11_0_get_current_pcie_link_speed(smu);
2213 }
2214
2215 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2216                                         void **table)
2217 {
2218         struct smu_table_context *smu_table = &smu->smu_table;
2219         struct gpu_metrics_v1_0 *gpu_metrics =
2220                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2221         SmuMetrics_t metrics;
2222         int ret = 0;
2223
2224         ret = smu_cmn_get_metrics_table(smu,
2225                                         &metrics,
2226                                         true);
2227         if (ret)
2228                 return ret;
2229
2230         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2231
2232         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2233         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2234         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2235         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2236         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2237         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2238
2239         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2240         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2241         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2242
2243         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2244         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2245
2246         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2247         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2248         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2249         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2250         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2251
2252         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2253         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2254         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2255         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2256         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2257
2258         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2259
2260         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2261
2262         gpu_metrics->pcie_link_width =
2263                         smu_v11_0_get_current_pcie_link_width(smu);
2264         gpu_metrics->pcie_link_speed =
2265                         arcturus_get_current_pcie_link_speed(smu);
2266
2267         *table = (void *)gpu_metrics;
2268
2269         return sizeof(struct gpu_metrics_v1_0);
2270 }
2271
2272 static const struct pptable_funcs arcturus_ppt_funcs = {
2273         /* init dpm */
2274         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2275         /* btc */
2276         .run_btc = arcturus_run_btc,
2277         /* dpm/clk tables */
2278         .set_default_dpm_table = arcturus_set_default_dpm_table,
2279         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2280         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2281         .print_clk_levels = arcturus_print_clk_levels,
2282         .force_clk_levels = arcturus_force_clk_levels,
2283         .read_sensor = arcturus_read_sensor,
2284         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2285         .get_power_profile_mode = arcturus_get_power_profile_mode,
2286         .set_power_profile_mode = arcturus_set_power_profile_mode,
2287         .set_performance_level = arcturus_set_performance_level,
2288         /* debug (internal used) */
2289         .dump_pptable = arcturus_dump_pptable,
2290         .get_power_limit = arcturus_get_power_limit,
2291         .is_dpm_running = arcturus_is_dpm_running,
2292         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2293         .i2c_init = arcturus_i2c_control_init,
2294         .i2c_fini = arcturus_i2c_control_fini,
2295         .get_unique_id = arcturus_get_unique_id,
2296         .init_microcode = smu_v11_0_init_microcode,
2297         .load_microcode = smu_v11_0_load_microcode,
2298         .fini_microcode = smu_v11_0_fini_microcode,
2299         .init_smc_tables = arcturus_init_smc_tables,
2300         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2301         .init_power = smu_v11_0_init_power,
2302         .fini_power = smu_v11_0_fini_power,
2303         .check_fw_status = smu_v11_0_check_fw_status,
2304         /* pptable related */
2305         .setup_pptable = arcturus_setup_pptable,
2306         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2307         .check_fw_version = smu_v11_0_check_fw_version,
2308         .write_pptable = smu_cmn_write_pptable,
2309         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2310         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2311         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2312         .system_features_control = smu_v11_0_system_features_control,
2313         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2314         .send_smc_msg = smu_cmn_send_smc_msg,
2315         .init_display_count = NULL,
2316         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2317         .get_enabled_mask = smu_cmn_get_enabled_mask,
2318         .feature_is_enabled = smu_cmn_feature_is_enabled,
2319         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2320         .notify_display_change = NULL,
2321         .set_power_limit = smu_v11_0_set_power_limit,
2322         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2323         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2324         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2325         .set_min_dcef_deep_sleep = NULL,
2326         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2327         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2328         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2329         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2330         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2331         .gfx_off_control = smu_v11_0_gfx_off_control,
2332         .register_irq_handler = smu_v11_0_register_irq_handler,
2333         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2334         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2335         .baco_is_support= arcturus_is_baco_supported,
2336         .baco_get_state = smu_v11_0_baco_get_state,
2337         .baco_set_state = smu_v11_0_baco_set_state,
2338         .baco_enter = smu_v11_0_baco_enter,
2339         .baco_exit = smu_v11_0_baco_exit,
2340         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2341         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2342         .set_df_cstate = arcturus_set_df_cstate,
2343         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2344         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2345         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2346         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2347         .get_gpu_metrics = arcturus_get_gpu_metrics,
2348         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2349         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2350         .get_fan_parameters = arcturus_get_fan_parameters,
2351         .interrupt_work = smu_v11_0_interrupt_work,
2352 };
2353
2354 void arcturus_set_ppt_funcs(struct smu_context *smu)
2355 {
2356         smu->ppt_funcs = &arcturus_ppt_funcs;
2357         smu->message_map = arcturus_message_map;
2358         smu->clock_map = arcturus_clk_map;
2359         smu->feature_map = arcturus_feature_mask_map;
2360         smu->table_map = arcturus_table_map;
2361         smu->pwr_src_map = arcturus_pwr_src_map;
2362         smu->workload_map = arcturus_workload_map;
2363 }