drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 #define mmCG_FDO_CTRL0_ARCT                     0x8B
  85 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX            0
  86
  87 #define mmCG_FDO_CTRL1_ARCT                     0x8C
  88 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX            0
  89
  90 #define mmCG_FDO_CTRL2_ARCT                     0x8D
  91 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX            0
  92
  93 #define mmCG_TACH_CTRL_ARCT                     0x8E
  94 #define mmCG_TACH_CTRL_ARCT_BASE_IDX            0
  95
  96 #define mmCG_TACH_STATUS_ARCT                   0x8F
  97 #define mmCG_TACH_STATUS_ARCT_BASE_IDX          0
  98
  99 #define mmCG_THERMAL_STATUS_ARCT                0x90
 100 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX       0
 101
 102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
 103         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 104         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 105         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 106         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
 107         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
 108         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 109         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 110         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
 111         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
 112         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
 113         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
 114         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
 115         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
 116         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 117         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 118         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 119         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 120         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 121         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 122         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 123         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 124         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 125         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 126         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 127         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 128         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 129         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 130         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 131         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 132         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 133         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 134         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 135         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 136         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 137         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 138         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 139         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 140         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 141         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 142         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 143         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 144         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 145         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 146         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 147         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 148         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 149         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 150         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 151         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 152         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 153         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 154         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 155         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 156         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 157         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 158         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 159         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 160         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 161         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 162         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 163         MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 164 };
 165
 166 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 167         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 168         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 169         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 170         CLK_MAP(FCLK, PPCLK_FCLK),
 171         CLK_MAP(UCLK, PPCLK_UCLK),
 172         CLK_MAP(MCLK, PPCLK_UCLK),
 173         CLK_MAP(DCLK, PPCLK_DCLK),
 174         CLK_MAP(VCLK, PPCLK_VCLK),
 175 };
 176
 177 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 178         FEA_MAP(DPM_PREFETCHER),
 179         FEA_MAP(DPM_GFXCLK),
 180         FEA_MAP(DPM_UCLK),
 181         FEA_MAP(DPM_SOCCLK),
 182         FEA_MAP(DPM_FCLK),
 183         FEA_MAP(DPM_MP0CLK),
 184         FEA_MAP(DPM_XGMI),
 185         FEA_MAP(DS_GFXCLK),
 186         FEA_MAP(DS_SOCCLK),
 187         FEA_MAP(DS_LCLK),
 188         FEA_MAP(DS_FCLK),
 189         FEA_MAP(DS_UCLK),
 190         FEA_MAP(GFX_ULV),
 191         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
 192         FEA_MAP(RSMU_SMN_CG),
 193         FEA_MAP(WAFL_CG),
 194         FEA_MAP(PPT),
 195         FEA_MAP(TDC),
 196         FEA_MAP(APCC_PLUS),
 197         FEA_MAP(VR0HOT),
 198         FEA_MAP(VR1HOT),
 199         FEA_MAP(FW_CTF),
 200         FEA_MAP(FAN_CONTROL),
 201         FEA_MAP(THERMAL),
 202         FEA_MAP(OUT_OF_BAND_MONITOR),
 203         FEA_MAP(TEMP_DEPENDENT_VMIN),
 204 };
 205
 206 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 207         TAB_MAP(PPTABLE),
 208         TAB_MAP(AVFS),
 209         TAB_MAP(AVFS_PSM_DEBUG),
 210         TAB_MAP(AVFS_FUSE_OVERRIDE),
 211         TAB_MAP(PMSTATUSLOG),
 212         TAB_MAP(SMU_METRICS),
 213         TAB_MAP(DRIVER_SMU_CONFIG),
 214         TAB_MAP(OVERDRIVE),
 215         TAB_MAP(I2C_COMMANDS),
 216         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 217 };
 218
 219 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 220         PWR_MAP(AC),
 221         PWR_MAP(DC),
 222 };
 223
 224 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 225         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 226         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 227         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 228         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 229         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 230 };
 231
 232 static const uint8_t arcturus_throttler_map[] = {
 233         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 234         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 235         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 236         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 237         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 238         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 239         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 240         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 241         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 242         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 243         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 244         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 245         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 246         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 247         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 248         [THROTTLER_VRHOT0_BIT]          = (SMU_THROTTLER_VRHOT0_BIT),
 249         [THROTTLER_VRHOT1_BIT]          = (SMU_THROTTLER_VRHOT1_BIT),
 250 };
 251
 252 static int arcturus_tables_init(struct smu_context *smu)
 253 {
 254         struct smu_table_context *smu_table = &smu->smu_table;
 255         struct smu_table *tables = smu_table->tables;
 256
 257         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 258                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 259
 260         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 261                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 262
 263         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 264                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 265
 266         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 267                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 268
 269         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 270                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 271                        AMDGPU_GEM_DOMAIN_VRAM);
 272
 273         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 274         if (!smu_table->metrics_table)
 275                 return -ENOMEM;
 276         smu_table->metrics_time = 0;
 277
 278         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 279         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 280         if (!smu_table->gpu_metrics_table) {
 281                 kfree(smu_table->metrics_table);
 282                 return -ENOMEM;
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 289 {
 290         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 291
 292         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 293                                        GFP_KERNEL);
 294         if (!smu_dpm->dpm_context)
 295                 return -ENOMEM;
 296         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 297
 298         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 299                                        GFP_KERNEL);
 300         if (!smu_dpm->dpm_current_power_state)
 301                 return -ENOMEM;
 302
 303         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 304                                        GFP_KERNEL);
 305         if (!smu_dpm->dpm_request_power_state)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int arcturus_init_smc_tables(struct smu_context *smu)
 312 {
 313         int ret = 0;
 314
 315         ret = arcturus_tables_init(smu);
 316         if (ret)
 317                 return ret;
 318
 319         ret = arcturus_allocate_dpm_context(smu);
 320         if (ret)
 321                 return ret;
 322
 323         return smu_v11_0_init_smc_tables(smu);
 324 }
 325
 326 static int
 327 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 328                                   uint32_t *feature_mask, uint32_t num)
 329 {
 330         if (num > 2)
 331                 return -EINVAL;
 332
 333         /* pptable will handle the features to enable */
 334         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 335
 336         return 0;
 337 }
 338
 339 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 340 {
 341         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 342         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 343         struct smu_11_0_dpm_table *dpm_table = NULL;
 344         int ret = 0;
 345
 346         /* socclk dpm table setup */
 347         dpm_table = &dpm_context->dpm_tables.soc_table;
 348         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 349                 ret = smu_v11_0_set_single_dpm_table(smu,
 350                                                      SMU_SOCCLK,
 351                                                      dpm_table);
 352                 if (ret)
 353                         return ret;
 354                 dpm_table->is_fine_grained =
 355                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 356         } else {
 357                 dpm_table->count = 1;
 358                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 359                 dpm_table->dpm_levels[0].enabled = true;
 360                 dpm_table->min = dpm_table->dpm_levels[0].value;
 361                 dpm_table->max = dpm_table->dpm_levels[0].value;
 362         }
 363
 364         /* gfxclk dpm table setup */
 365         dpm_table = &dpm_context->dpm_tables.gfx_table;
 366         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 367                 ret = smu_v11_0_set_single_dpm_table(smu,
 368                                                      SMU_GFXCLK,
 369                                                      dpm_table);
 370                 if (ret)
 371                         return ret;
 372                 dpm_table->is_fine_grained =
 373                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 374         } else {
 375                 dpm_table->count = 1;
 376                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 377                 dpm_table->dpm_levels[0].enabled = true;
 378                 dpm_table->min = dpm_table->dpm_levels[0].value;
 379                 dpm_table->max = dpm_table->dpm_levels[0].value;
 380         }
 381
 382         /* memclk dpm table setup */
 383         dpm_table = &dpm_context->dpm_tables.uclk_table;
 384         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 385                 ret = smu_v11_0_set_single_dpm_table(smu,
 386                                                      SMU_UCLK,
 387                                                      dpm_table);
 388                 if (ret)
 389                         return ret;
 390                 dpm_table->is_fine_grained =
 391                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 392         } else {
 393                 dpm_table->count = 1;
 394                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 395                 dpm_table->dpm_levels[0].enabled = true;
 396                 dpm_table->min = dpm_table->dpm_levels[0].value;
 397                 dpm_table->max = dpm_table->dpm_levels[0].value;
 398         }
 399
 400         /* fclk dpm table setup */
 401         dpm_table = &dpm_context->dpm_tables.fclk_table;
 402         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 403                 ret = smu_v11_0_set_single_dpm_table(smu,
 404                                                      SMU_FCLK,
 405                                                      dpm_table);
 406                 if (ret)
 407                         return ret;
 408                 dpm_table->is_fine_grained =
 409                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 410         } else {
 411                 dpm_table->count = 1;
 412                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 413                 dpm_table->dpm_levels[0].enabled = true;
 414                 dpm_table->min = dpm_table->dpm_levels[0].value;
 415                 dpm_table->max = dpm_table->dpm_levels[0].value;
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void arcturus_check_bxco_support(struct smu_context *smu)
 422 {
 423         struct smu_table_context *table_context = &smu->smu_table;
 424         struct smu_11_0_powerplay_table *powerplay_table =
 425                 table_context->power_play_table;
 426         struct smu_baco_context *smu_baco = &smu->smu_baco;
 427         struct amdgpu_device *adev = smu->adev;
 428         uint32_t val;
 429
 430         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 431             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 432                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 433                 smu_baco->platform_support =
 434                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 435                                                                         false;
 436         }
 437 }
 438
 439 static void arcturus_check_fan_support(struct smu_context *smu)
 440 {
 441         struct smu_table_context *table_context = &smu->smu_table;
 442         PPTable_t *pptable = table_context->driver_pptable;
 443
 444         /* No sort of fan control possible if PPTable has it disabled */
 445         smu->adev->pm.no_fan =
 446                 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK);
 447         if (smu->adev->pm.no_fan)
 448                 dev_info_once(smu->adev->dev,
 449                               "PMFW based fan control disabled");
 450 }
 451
 452 static int arcturus_check_powerplay_table(struct smu_context *smu)
 453 {
 454         struct smu_table_context *table_context = &smu->smu_table;
 455         struct smu_11_0_powerplay_table *powerplay_table =
 456                 table_context->power_play_table;
 457
 458         arcturus_check_bxco_support(smu);
 459         arcturus_check_fan_support(smu);
 460
 461         table_context->thermal_controller_type =
 462                 powerplay_table->thermal_controller_type;
 463
 464         return 0;
 465 }
 466
 467 static int arcturus_store_powerplay_table(struct smu_context *smu)
 468 {
 469         struct smu_table_context *table_context = &smu->smu_table;
 470         struct smu_11_0_powerplay_table *powerplay_table =
 471                 table_context->power_play_table;
 472
 473         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 474                sizeof(PPTable_t));
 475
 476         return 0;
 477 }
 478
 479 static int arcturus_append_powerplay_table(struct smu_context *smu)
 480 {
 481         struct smu_table_context *table_context = &smu->smu_table;
 482         PPTable_t *smc_pptable = table_context->driver_pptable;
 483         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 484         int index, ret;
 485
 486         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 487                                            smc_dpm_info);
 488
 489         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 490                                       (uint8_t **)&smc_dpm_table);
 491         if (ret)
 492                 return ret;
 493
 494         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 495                         smc_dpm_table->table_header.format_revision,
 496                         smc_dpm_table->table_header.content_revision);
 497
 498         if ((smc_dpm_table->table_header.format_revision == 4) &&
 499             (smc_dpm_table->table_header.content_revision == 6))
 500                 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
 501                                     smc_dpm_table, maxvoltagestepgfx);
 502         return 0;
 503 }
 504
 505 static int arcturus_setup_pptable(struct smu_context *smu)
 506 {
 507         int ret = 0;
 508
 509         ret = smu_v11_0_setup_pptable(smu);
 510         if (ret)
 511                 return ret;
 512
 513         ret = arcturus_store_powerplay_table(smu);
 514         if (ret)
 515                 return ret;
 516
 517         ret = arcturus_append_powerplay_table(smu);
 518         if (ret)
 519                 return ret;
 520
 521         ret = arcturus_check_powerplay_table(smu);
 522         if (ret)
 523                 return ret;
 524
 525         return ret;
 526 }
 527
 528 static int arcturus_run_btc(struct smu_context *smu)
 529 {
 530         int ret = 0;
 531
 532         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 533         if (ret) {
 534                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 535                 return ret;
 536         }
 537
 538         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 539 }
 540
 541 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 542 {
 543         struct smu_11_0_dpm_context *dpm_context =
 544                                 smu->smu_dpm.dpm_context;
 545         struct smu_11_0_dpm_table *gfx_table =
 546                                 &dpm_context->dpm_tables.gfx_table;
 547         struct smu_11_0_dpm_table *mem_table =
 548                                 &dpm_context->dpm_tables.uclk_table;
 549         struct smu_11_0_dpm_table *soc_table =
 550                                 &dpm_context->dpm_tables.soc_table;
 551         struct smu_umd_pstate_table *pstate_table =
 552                                 &smu->pstate_table;
 553
 554         pstate_table->gfxclk_pstate.min = gfx_table->min;
 555         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 556
 557         pstate_table->uclk_pstate.min = mem_table->min;
 558         pstate_table->uclk_pstate.peak = mem_table->max;
 559
 560         pstate_table->socclk_pstate.min = soc_table->min;
 561         pstate_table->socclk_pstate.peak = soc_table->max;
 562
 563         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 564             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 565             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 566                 pstate_table->gfxclk_pstate.standard =
 567                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 568                 pstate_table->uclk_pstate.standard =
 569                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 570                 pstate_table->socclk_pstate.standard =
 571                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 572         } else {
 573                 pstate_table->gfxclk_pstate.standard =
 574                         pstate_table->gfxclk_pstate.min;
 575                 pstate_table->uclk_pstate.standard =
 576                         pstate_table->uclk_pstate.min;
 577                 pstate_table->socclk_pstate.standard =
 578                         pstate_table->socclk_pstate.min;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int arcturus_get_clk_table(struct smu_context *smu,
 585                         struct pp_clock_levels_with_latency *clocks,
 586                         struct smu_11_0_dpm_table *dpm_table)
 587 {
 588         int i, count;
 589
 590         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 591         clocks->num_levels = count;
 592
 593         for (i = 0; i < count; i++) {
 594                 clocks->data[i].clocks_in_khz =
 595                         dpm_table->dpm_levels[i].value * 1000;
 596                 clocks->data[i].latency_in_us = 0;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int arcturus_freqs_in_same_level(int32_t frequency1,
 603                                         int32_t frequency2)
 604 {
 605         return (abs(frequency1 - frequency2) <= EPSILON);
 606 }
 607
 608 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 609                                          MetricsMember_t member,
 610                                          uint32_t *value)
 611 {
 612         struct smu_table_context *smu_table= &smu->smu_table;
 613         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 614         int ret = 0;
 615
 616         mutex_lock(&smu->metrics_lock);
 617
 618         ret = smu_cmn_get_metrics_table_locked(smu,
 619                                                NULL,
 620                                                false);
 621         if (ret) {
 622                 mutex_unlock(&smu->metrics_lock);
 623                 return ret;
 624         }
 625
 626         switch (member) {
 627         case METRICS_CURR_GFXCLK:
 628                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 629                 break;
 630         case METRICS_CURR_SOCCLK:
 631                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 632                 break;
 633         case METRICS_CURR_UCLK:
 634                 *value = metrics->CurrClock[PPCLK_UCLK];
 635                 break;
 636         case METRICS_CURR_VCLK:
 637                 *value = metrics->CurrClock[PPCLK_VCLK];
 638                 break;
 639         case METRICS_CURR_DCLK:
 640                 *value = metrics->CurrClock[PPCLK_DCLK];
 641                 break;
 642         case METRICS_CURR_FCLK:
 643                 *value = metrics->CurrClock[PPCLK_FCLK];
 644                 break;
 645         case METRICS_AVERAGE_GFXCLK:
 646                 *value = metrics->AverageGfxclkFrequency;
 647                 break;
 648         case METRICS_AVERAGE_SOCCLK:
 649                 *value = metrics->AverageSocclkFrequency;
 650                 break;
 651         case METRICS_AVERAGE_UCLK:
 652                 *value = metrics->AverageUclkFrequency;
 653                 break;
 654         case METRICS_AVERAGE_VCLK:
 655                 *value = metrics->AverageVclkFrequency;
 656                 break;
 657         case METRICS_AVERAGE_DCLK:
 658                 *value = metrics->AverageDclkFrequency;
 659                 break;
 660         case METRICS_AVERAGE_GFXACTIVITY:
 661                 *value = metrics->AverageGfxActivity;
 662                 break;
 663         case METRICS_AVERAGE_MEMACTIVITY:
 664                 *value = metrics->AverageUclkActivity;
 665                 break;
 666         case METRICS_AVERAGE_VCNACTIVITY:
 667                 *value = metrics->VcnActivityPercentage;
 668                 break;
 669         case METRICS_AVERAGE_SOCKETPOWER:
 670                 *value = metrics->AverageSocketPower << 8;
 671                 break;
 672         case METRICS_TEMPERATURE_EDGE:
 673                 *value = metrics->TemperatureEdge *
 674                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 675                 break;
 676         case METRICS_TEMPERATURE_HOTSPOT:
 677                 *value = metrics->TemperatureHotspot *
 678                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 679                 break;
 680         case METRICS_TEMPERATURE_MEM:
 681                 *value = metrics->TemperatureHBM *
 682                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 683                 break;
 684         case METRICS_TEMPERATURE_VRGFX:
 685                 *value = metrics->TemperatureVrGfx *
 686                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 687                 break;
 688         case METRICS_TEMPERATURE_VRSOC:
 689                 *value = metrics->TemperatureVrSoc *
 690                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 691                 break;
 692         case METRICS_TEMPERATURE_VRMEM:
 693                 *value = metrics->TemperatureVrMem *
 694                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 695                 break;
 696         case METRICS_THROTTLER_STATUS:
 697                 *value = metrics->ThrottlerStatus;
 698                 break;
 699         case METRICS_CURR_FANSPEED:
 700                 *value = metrics->CurrFanSpeed;
 701                 break;
 702         default:
 703                 *value = UINT_MAX;
 704                 break;
 705         }
 706
 707         mutex_unlock(&smu->metrics_lock);
 708
 709         return ret;
 710 }
 711
 712 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 713                                        enum smu_clk_type clk_type,
 714                                        uint32_t *value)
 715 {
 716         MetricsMember_t member_type;
 717         int clk_id = 0;
 718
 719         if (!value)
 720                 return -EINVAL;
 721
 722         clk_id = smu_cmn_to_asic_specific_index(smu,
 723                                                 CMN2ASIC_MAPPING_CLK,
 724                                                 clk_type);
 725         if (clk_id < 0)
 726                 return -EINVAL;
 727
 728         switch (clk_id) {
 729         case PPCLK_GFXCLK:
 730                 /*
 731                  * CurrClock[clk_id] can provide accurate
 732                  *   output only when the dpm feature is enabled.
 733                  * We can use Average_* for dpm disabled case.
 734                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 735                  */
 736                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 737                         member_type = METRICS_CURR_GFXCLK;
 738                 else
 739                         member_type = METRICS_AVERAGE_GFXCLK;
 740                 break;
 741         case PPCLK_UCLK:
 742                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 743                         member_type = METRICS_CURR_UCLK;
 744                 else
 745                         member_type = METRICS_AVERAGE_UCLK;
 746                 break;
 747         case PPCLK_SOCCLK:
 748                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 749                         member_type = METRICS_CURR_SOCCLK;
 750                 else
 751                         member_type = METRICS_AVERAGE_SOCCLK;
 752                 break;
 753         case PPCLK_VCLK:
 754                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 755                         member_type = METRICS_CURR_VCLK;
 756                 else
 757                         member_type = METRICS_AVERAGE_VCLK;
 758                 break;
 759         case PPCLK_DCLK:
 760                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 761                         member_type = METRICS_CURR_DCLK;
 762                 else
 763                         member_type = METRICS_AVERAGE_DCLK;
 764                 break;
 765         case PPCLK_FCLK:
 766                 member_type = METRICS_CURR_FCLK;
 767                 break;
 768         default:
 769                 return -EINVAL;
 770         }
 771
 772         return arcturus_get_smu_metrics_data(smu,
 773                                              member_type,
 774                                              value);
 775 }
 776
 777 static int arcturus_print_clk_levels(struct smu_context *smu,
 778                         enum smu_clk_type type, char *buf)
 779 {
 780         int i, now, size = 0;
 781         int ret = 0;
 782         struct pp_clock_levels_with_latency clocks;
 783         struct smu_11_0_dpm_table *single_dpm_table;
 784         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 785         struct smu_11_0_dpm_context *dpm_context = NULL;
 786         uint32_t gen_speed, lane_width;
 787
 788         smu_cmn_get_sysfs_buf(&buf, &size);
 789
 790         if (amdgpu_ras_intr_triggered()) {
 791                 size += sysfs_emit_at(buf, size, "unavailable\n");
 792                 return size;
 793         }
 794
 795         dpm_context = smu_dpm->dpm_context;
 796
 797         switch (type) {
 798         case SMU_SCLK:
 799                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 800                 if (ret) {
 801                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 802                         return ret;
 803                 }
 804
 805                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 806                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 807                 if (ret) {
 808                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 809                         return ret;
 810                 }
 811
 812                 /*
 813                  * For DPM disabled case, there will be only one clock level.
 814                  * And it's safe to assume that is always the current clock.
 815                  */
 816                 for (i = 0; i < clocks.num_levels; i++)
 817                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 818                                         clocks.data[i].clocks_in_khz / 1000,
 819                                         (clocks.num_levels == 1) ? "*" :
 820                                         (arcturus_freqs_in_same_level(
 821                                         clocks.data[i].clocks_in_khz / 1000,
 822                                         now) ? "*" : ""));
 823                 break;
 824
 825         case SMU_MCLK:
 826                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 827                 if (ret) {
 828                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 829                         return ret;
 830                 }
 831
 832                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 833                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 834                 if (ret) {
 835                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 836                         return ret;
 837                 }
 838
 839                 for (i = 0; i < clocks.num_levels; i++)
 840                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 841                                 i, clocks.data[i].clocks_in_khz / 1000,
 842                                 (clocks.num_levels == 1) ? "*" :
 843                                 (arcturus_freqs_in_same_level(
 844                                 clocks.data[i].clocks_in_khz / 1000,
 845                                 now) ? "*" : ""));
 846                 break;
 847
 848         case SMU_SOCCLK:
 849                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 850                 if (ret) {
 851                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 852                         return ret;
 853                 }
 854
 855                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 856                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 857                 if (ret) {
 858                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 859                         return ret;
 860                 }
 861
 862                 for (i = 0; i < clocks.num_levels; i++)
 863                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 864                                 i, clocks.data[i].clocks_in_khz / 1000,
 865                                 (clocks.num_levels == 1) ? "*" :
 866                                 (arcturus_freqs_in_same_level(
 867                                 clocks.data[i].clocks_in_khz / 1000,
 868                                 now) ? "*" : ""));
 869                 break;
 870
 871         case SMU_FCLK:
 872                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 873                 if (ret) {
 874                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 875                         return ret;
 876                 }
 877
 878                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 879                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 882                         return ret;
 883                 }
 884
 885                 for (i = 0; i < single_dpm_table->count; i++)
 886                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 887                                 i, single_dpm_table->dpm_levels[i].value,
 888                                 (clocks.num_levels == 1) ? "*" :
 889                                 (arcturus_freqs_in_same_level(
 890                                 clocks.data[i].clocks_in_khz / 1000,
 891                                 now) ? "*" : ""));
 892                 break;
 893
 894         case SMU_VCLK:
 895                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 896                 if (ret) {
 897                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 898                         return ret;
 899                 }
 900
 901                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 902                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 903                 if (ret) {
 904                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 905                         return ret;
 906                 }
 907
 908                 for (i = 0; i < single_dpm_table->count; i++)
 909                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 910                                 i, single_dpm_table->dpm_levels[i].value,
 911                                 (clocks.num_levels == 1) ? "*" :
 912                                 (arcturus_freqs_in_same_level(
 913                                 clocks.data[i].clocks_in_khz / 1000,
 914                                 now) ? "*" : ""));
 915                 break;
 916
 917         case SMU_DCLK:
 918                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 919                 if (ret) {
 920                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 921                         return ret;
 922                 }
 923
 924                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 925                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 926                 if (ret) {
 927                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 928                         return ret;
 929                 }
 930
 931                 for (i = 0; i < single_dpm_table->count; i++)
 932                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 933                                 i, single_dpm_table->dpm_levels[i].value,
 934                                 (clocks.num_levels == 1) ? "*" :
 935                                 (arcturus_freqs_in_same_level(
 936                                 clocks.data[i].clocks_in_khz / 1000,
 937                                 now) ? "*" : ""));
 938                 break;
 939
 940         case SMU_PCIE:
 941                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 942                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 943                 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
 944                                 (gen_speed == 0) ? "2.5GT/s," :
 945                                 (gen_speed == 1) ? "5.0GT/s," :
 946                                 (gen_speed == 2) ? "8.0GT/s," :
 947                                 (gen_speed == 3) ? "16.0GT/s," : "",
 948                                 (lane_width == 1) ? "x1" :
 949                                 (lane_width == 2) ? "x2" :
 950                                 (lane_width == 3) ? "x4" :
 951                                 (lane_width == 4) ? "x8" :
 952                                 (lane_width == 5) ? "x12" :
 953                                 (lane_width == 6) ? "x16" : "",
 954                                 smu->smu_table.boot_values.lclk / 100);
 955                 break;
 956
 957         default:
 958                 break;
 959         }
 960
 961         return size;
 962 }
 963
 964 static int arcturus_upload_dpm_level(struct smu_context *smu,
 965                                      bool max,
 966                                      uint32_t feature_mask,
 967                                      uint32_t level)
 968 {
 969         struct smu_11_0_dpm_context *dpm_context =
 970                         smu->smu_dpm.dpm_context;
 971         uint32_t freq;
 972         int ret = 0;
 973
 974         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 975             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 976                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 977                 ret = smu_cmn_send_smc_msg_with_param(smu,
 978                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 979                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 980                         NULL);
 981                 if (ret) {
 982                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 983                                                 max ? "max" : "min");
 984                         return ret;
 985                 }
 986         }
 987
 988         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 989             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 990                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 991                 ret = smu_cmn_send_smc_msg_with_param(smu,
 992                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 993                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 994                         NULL);
 995                 if (ret) {
 996                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 997                                                 max ? "max" : "min");
 998                         return ret;
 999                 }
1000         }
1001
1002         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1003             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1004                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1005                 ret = smu_cmn_send_smc_msg_with_param(smu,
1006                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1007                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
1008                         NULL);
1009                 if (ret) {
1010                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
1011                                                 max ? "max" : "min");
1012                         return ret;
1013                 }
1014         }
1015
1016         return ret;
1017 }
1018
1019 static int arcturus_force_clk_levels(struct smu_context *smu,
1020                         enum smu_clk_type type, uint32_t mask)
1021 {
1022         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1023         struct smu_11_0_dpm_table *single_dpm_table = NULL;
1024         uint32_t soft_min_level, soft_max_level;
1025         uint32_t smu_version;
1026         int ret = 0;
1027
1028         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1029         if (ret) {
1030                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1031                 return ret;
1032         }
1033
1034         if ((smu_version >= 0x361200) &&
1035             (smu_version <= 0x361a00)) {
1036                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1037                        "54.18 - 54.26(included) SMU firmwares\n");
1038                 return -EOPNOTSUPP;
1039         }
1040
1041         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1042         soft_max_level = mask ? (fls(mask) - 1) : 0;
1043
1044         switch (type) {
1045         case SMU_SCLK:
1046                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1047                 if (soft_max_level >= single_dpm_table->count) {
1048                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1049                                         soft_max_level, single_dpm_table->count - 1);
1050                         ret = -EINVAL;
1051                         break;
1052                 }
1053
1054                 ret = arcturus_upload_dpm_level(smu,
1055                                                 false,
1056                                                 FEATURE_DPM_GFXCLK_MASK,
1057                                                 soft_min_level);
1058                 if (ret) {
1059                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1060                         break;
1061                 }
1062
1063                 ret = arcturus_upload_dpm_level(smu,
1064                                                 true,
1065                                                 FEATURE_DPM_GFXCLK_MASK,
1066                                                 soft_max_level);
1067                 if (ret)
1068                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1069
1070                 break;
1071
1072         case SMU_MCLK:
1073         case SMU_SOCCLK:
1074         case SMU_FCLK:
1075                 /*
1076                  * Should not arrive here since Arcturus does not
1077                  * support mclk/socclk/fclk softmin/softmax settings
1078                  */
1079                 ret = -EINVAL;
1080                 break;
1081
1082         default:
1083                 break;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1090                                                 struct smu_temperature_range *range)
1091 {
1092         struct smu_table_context *table_context = &smu->smu_table;
1093         struct smu_11_0_powerplay_table *powerplay_table =
1094                                 table_context->power_play_table;
1095         PPTable_t *pptable = smu->smu_table.driver_pptable;
1096
1097         if (!range)
1098                 return -EINVAL;
1099
1100         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1101
1102         range->max = pptable->TedgeLimit *
1103                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1104         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1105                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1106         range->hotspot_crit_max = pptable->ThotspotLimit *
1107                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1108         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1109                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1110         range->mem_crit_max = pptable->TmemLimit *
1111                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1112         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1113                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1114         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1115
1116         return 0;
1117 }
1118
1119 static int arcturus_read_sensor(struct smu_context *smu,
1120                                 enum amd_pp_sensors sensor,
1121                                 void *data, uint32_t *size)
1122 {
1123         struct smu_table_context *table_context = &smu->smu_table;
1124         PPTable_t *pptable = table_context->driver_pptable;
1125         int ret = 0;
1126
1127         if (amdgpu_ras_intr_triggered())
1128                 return 0;
1129
1130         if (!data || !size)
1131                 return -EINVAL;
1132
1133         mutex_lock(&smu->sensor_lock);
1134         switch (sensor) {
1135         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1136                 *(uint32_t *)data = pptable->FanMaximumRpm;
1137                 *size = 4;
1138                 break;
1139         case AMDGPU_PP_SENSOR_MEM_LOAD:
1140                 ret = arcturus_get_smu_metrics_data(smu,
1141                                                     METRICS_AVERAGE_MEMACTIVITY,
1142                                                     (uint32_t *)data);
1143                 *size = 4;
1144                 break;
1145         case AMDGPU_PP_SENSOR_GPU_LOAD:
1146                 ret = arcturus_get_smu_metrics_data(smu,
1147                                                     METRICS_AVERAGE_GFXACTIVITY,
1148                                                     (uint32_t *)data);
1149                 *size = 4;
1150                 break;
1151         case AMDGPU_PP_SENSOR_GPU_POWER:
1152                 ret = arcturus_get_smu_metrics_data(smu,
1153                                                     METRICS_AVERAGE_SOCKETPOWER,
1154                                                     (uint32_t *)data);
1155                 *size = 4;
1156                 break;
1157         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1158                 ret = arcturus_get_smu_metrics_data(smu,
1159                                                     METRICS_TEMPERATURE_HOTSPOT,
1160                                                     (uint32_t *)data);
1161                 *size = 4;
1162                 break;
1163         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1164                 ret = arcturus_get_smu_metrics_data(smu,
1165                                                     METRICS_TEMPERATURE_EDGE,
1166                                                     (uint32_t *)data);
1167                 *size = 4;
1168                 break;
1169         case AMDGPU_PP_SENSOR_MEM_TEMP:
1170                 ret = arcturus_get_smu_metrics_data(smu,
1171                                                     METRICS_TEMPERATURE_MEM,
1172                                                     (uint32_t *)data);
1173                 *size = 4;
1174                 break;
1175         case AMDGPU_PP_SENSOR_GFX_MCLK:
1176                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1177                 /* the output clock frequency in 10K unit */
1178                 *(uint32_t *)data *= 100;
1179                 *size = 4;
1180                 break;
1181         case AMDGPU_PP_SENSOR_GFX_SCLK:
1182                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1183                 *(uint32_t *)data *= 100;
1184                 *size = 4;
1185                 break;
1186         case AMDGPU_PP_SENSOR_VDDGFX:
1187                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1188                 *size = 4;
1189                 break;
1190         default:
1191                 ret = -EOPNOTSUPP;
1192                 break;
1193         }
1194         mutex_unlock(&smu->sensor_lock);
1195
1196         return ret;
1197 }
1198
1199 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1200                                         uint32_t mode)
1201 {
1202         struct amdgpu_device *adev = smu->adev;
1203
1204         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1205                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1206                                    CG_FDO_CTRL2, TMIN, 0));
1207         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1208                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1209                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1210
1211         return 0;
1212 }
1213
1214 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1215                                       uint32_t *speed)
1216 {
1217         struct amdgpu_device *adev = smu->adev;
1218         uint32_t crystal_clock_freq = 2500;
1219         uint32_t tach_status;
1220         uint64_t tmp64;
1221         int ret = 0;
1222
1223         if (!speed)
1224                 return -EINVAL;
1225
1226         switch (smu_v11_0_get_fan_control_mode(smu)) {
1227         case AMD_FAN_CTRL_AUTO:
1228                 ret = arcturus_get_smu_metrics_data(smu,
1229                                                     METRICS_CURR_FANSPEED,
1230                                                     speed);
1231                 break;
1232         default:
1233                 /*
1234                  * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1235                  * detected via register retrieving. To workaround this, we will
1236                  * report the fan speed as 0 RPM if user just requested such.
1237                  */
1238                 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1239                      && !smu->user_dpm_profile.fan_speed_rpm) {
1240                         *speed = 0;
1241                         return 0;
1242                 }
1243
1244                 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1245                 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1246                 if (tach_status) {
1247                         do_div(tmp64, tach_status);
1248                         *speed = (uint32_t)tmp64;
1249                 } else {
1250                         *speed = 0;
1251                 }
1252
1253                 break;
1254         }
1255
1256         return ret;
1257 }
1258
1259 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1260                                       uint32_t speed)
1261 {
1262         struct amdgpu_device *adev = smu->adev;
1263         uint32_t duty100, duty;
1264         uint64_t tmp64;
1265
1266         speed = MIN(speed, 255);
1267
1268         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1269                                 CG_FDO_CTRL1, FMAX_DUTY100);
1270         if (!duty100)
1271                 return -EINVAL;
1272
1273         tmp64 = (uint64_t)speed * duty100;
1274         do_div(tmp64, 255);
1275         duty = (uint32_t)tmp64;
1276
1277         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1278                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1279                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1280
1281         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1282 }
1283
1284 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1285                                       uint32_t speed)
1286 {
1287         struct amdgpu_device *adev = smu->adev;
1288         /*
1289          * crystal_clock_freq used for fan speed rpm calculation is
1290          * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1291          */
1292         uint32_t crystal_clock_freq = 2500;
1293         uint32_t tach_period;
1294
1295         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1296         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1297                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1298                                    CG_TACH_CTRL, TARGET_PERIOD,
1299                                    tach_period));
1300
1301         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1302 }
1303
1304 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1305                                       uint32_t *speed)
1306 {
1307         struct amdgpu_device *adev = smu->adev;
1308         uint32_t duty100, duty;
1309         uint64_t tmp64;
1310
1311         /*
1312          * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1313          * detected via register retrieving. To workaround this, we will
1314          * report the fan speed as 0 PWM if user just requested such.
1315          */
1316         if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1317              && !smu->user_dpm_profile.fan_speed_pwm) {
1318                 *speed = 0;
1319                 return 0;
1320         }
1321
1322         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1323                                 CG_FDO_CTRL1, FMAX_DUTY100);
1324         duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1325                                 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1326
1327         if (duty100) {
1328                 tmp64 = (uint64_t)duty * 255;
1329                 do_div(tmp64, duty100);
1330                 *speed = MIN((uint32_t)tmp64, 255);
1331         } else {
1332                 *speed = 0;
1333         }
1334
1335         return 0;
1336 }
1337
1338 static int arcturus_get_fan_parameters(struct smu_context *smu)
1339 {
1340         PPTable_t *pptable = smu->smu_table.driver_pptable;
1341
1342         smu->fan_max_rpm = pptable->FanMaximumRpm;
1343
1344         return 0;
1345 }
1346
1347 static int arcturus_get_power_limit(struct smu_context *smu,
1348                                     uint32_t *current_power_limit,
1349                                     uint32_t *default_power_limit,
1350                                     uint32_t *max_power_limit)
1351 {
1352         struct smu_11_0_powerplay_table *powerplay_table =
1353                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1354         PPTable_t *pptable = smu->smu_table.driver_pptable;
1355         uint32_t power_limit, od_percent;
1356
1357         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1358                 /* the last hope to figure out the ppt limit */
1359                 if (!pptable) {
1360                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1361                         return -EINVAL;
1362                 }
1363                 power_limit =
1364                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1365         }
1366
1367         if (current_power_limit)
1368                 *current_power_limit = power_limit;
1369         if (default_power_limit)
1370                 *default_power_limit = power_limit;
1371
1372         if (max_power_limit) {
1373                 if (smu->od_enabled) {
1374                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1375
1376                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1377
1378                         power_limit *= (100 + od_percent);
1379                         power_limit /= 100;
1380                 }
1381
1382                 *max_power_limit = power_limit;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1389                                            char *buf)
1390 {
1391         DpmActivityMonitorCoeffInt_t activity_monitor;
1392         static const char *profile_name[] = {
1393                                         "BOOTUP_DEFAULT",
1394                                         "3D_FULL_SCREEN",
1395                                         "POWER_SAVING",
1396                                         "VIDEO",
1397                                         "VR",
1398                                         "COMPUTE",
1399                                         "CUSTOM"};
1400         static const char *title[] = {
1401                         "PROFILE_INDEX(NAME)",
1402                         "CLOCK_TYPE(NAME)",
1403                         "FPS",
1404                         "UseRlcBusy",
1405                         "MinActiveFreqType",
1406                         "MinActiveFreq",
1407                         "BoosterFreqType",
1408                         "BoosterFreq",
1409                         "PD_Data_limit_c",
1410                         "PD_Data_error_coeff",
1411                         "PD_Data_error_rate_coeff"};
1412         uint32_t i, size = 0;
1413         int16_t workload_type = 0;
1414         int result = 0;
1415         uint32_t smu_version;
1416
1417         if (!buf)
1418                 return -EINVAL;
1419
1420         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1421         if (result)
1422                 return result;
1423
1424         if (smu_version >= 0x360d00)
1425                 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1426                         title[0], title[1], title[2], title[3], title[4], title[5],
1427                         title[6], title[7], title[8], title[9], title[10]);
1428         else
1429                 size += sysfs_emit_at(buf, size, "%16s\n",
1430                         title[0]);
1431
1432         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1433                 /*
1434                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1435                  * Not all profile modes are supported on arcturus.
1436                  */
1437                 workload_type = smu_cmn_to_asic_specific_index(smu,
1438                                                                CMN2ASIC_MAPPING_WORKLOAD,
1439                                                                i);
1440                 if (workload_type < 0)
1441                         continue;
1442
1443                 if (smu_version >= 0x360d00) {
1444                         result = smu_cmn_update_table(smu,
1445                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1446                                                   workload_type,
1447                                                   (void *)(&activity_monitor),
1448                                                   false);
1449                         if (result) {
1450                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1451                                 return result;
1452                         }
1453                 }
1454
1455                 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1456                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1457
1458                 if (smu_version >= 0x360d00) {
1459                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1460                                 " ",
1461                                 0,
1462                                 "GFXCLK",
1463                                 activity_monitor.Gfx_FPS,
1464                                 activity_monitor.Gfx_UseRlcBusy,
1465                                 activity_monitor.Gfx_MinActiveFreqType,
1466                                 activity_monitor.Gfx_MinActiveFreq,
1467                                 activity_monitor.Gfx_BoosterFreqType,
1468                                 activity_monitor.Gfx_BoosterFreq,
1469                                 activity_monitor.Gfx_PD_Data_limit_c,
1470                                 activity_monitor.Gfx_PD_Data_error_coeff,
1471                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1472
1473                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1474                                 " ",
1475                                 1,
1476                                 "UCLK",
1477                                 activity_monitor.Mem_FPS,
1478                                 activity_monitor.Mem_UseRlcBusy,
1479                                 activity_monitor.Mem_MinActiveFreqType,
1480                                 activity_monitor.Mem_MinActiveFreq,
1481                                 activity_monitor.Mem_BoosterFreqType,
1482                                 activity_monitor.Mem_BoosterFreq,
1483                                 activity_monitor.Mem_PD_Data_limit_c,
1484                                 activity_monitor.Mem_PD_Data_error_coeff,
1485                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1486                 }
1487         }
1488
1489         return size;
1490 }
1491
1492 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1493                                            long *input,
1494                                            uint32_t size)
1495 {
1496         DpmActivityMonitorCoeffInt_t activity_monitor;
1497         int workload_type = 0;
1498         uint32_t profile_mode = input[size];
1499         int ret = 0;
1500         uint32_t smu_version;
1501
1502         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1503                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1504                 return -EINVAL;
1505         }
1506
1507         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1508         if (ret)
1509                 return ret;
1510
1511         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1512              (smu_version >=0x360d00)) {
1513                 ret = smu_cmn_update_table(smu,
1514                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1515                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1516                                        (void *)(&activity_monitor),
1517                                        false);
1518                 if (ret) {
1519                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1520                         return ret;
1521                 }
1522
1523                 switch (input[0]) {
1524                 case 0: /* Gfxclk */
1525                         activity_monitor.Gfx_FPS = input[1];
1526                         activity_monitor.Gfx_UseRlcBusy = input[2];
1527                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1528                         activity_monitor.Gfx_MinActiveFreq = input[4];
1529                         activity_monitor.Gfx_BoosterFreqType = input[5];
1530                         activity_monitor.Gfx_BoosterFreq = input[6];
1531                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1532                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1533                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1534                         break;
1535                 case 1: /* Uclk */
1536                         activity_monitor.Mem_FPS = input[1];
1537                         activity_monitor.Mem_UseRlcBusy = input[2];
1538                         activity_monitor.Mem_MinActiveFreqType = input[3];
1539                         activity_monitor.Mem_MinActiveFreq = input[4];
1540                         activity_monitor.Mem_BoosterFreqType = input[5];
1541                         activity_monitor.Mem_BoosterFreq = input[6];
1542                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1543                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1544                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1545                         break;
1546                 }
1547
1548                 ret = smu_cmn_update_table(smu,
1549                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1550                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1551                                        (void *)(&activity_monitor),
1552                                        true);
1553                 if (ret) {
1554                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1555                         return ret;
1556                 }
1557         }
1558
1559         /*
1560          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1561          * Not all profile modes are supported on arcturus.
1562          */
1563         workload_type = smu_cmn_to_asic_specific_index(smu,
1564                                                        CMN2ASIC_MAPPING_WORKLOAD,
1565                                                        profile_mode);
1566         if (workload_type < 0) {
1567                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1568                 return -EINVAL;
1569         }
1570
1571         ret = smu_cmn_send_smc_msg_with_param(smu,
1572                                           SMU_MSG_SetWorkloadMask,
1573                                           1 << workload_type,
1574                                           NULL);
1575         if (ret) {
1576                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1577                 return ret;
1578         }
1579
1580         smu->power_profile_mode = profile_mode;
1581
1582         return 0;
1583 }
1584
1585 static int arcturus_set_performance_level(struct smu_context *smu,
1586                                           enum amd_dpm_forced_level level)
1587 {
1588         uint32_t smu_version;
1589         int ret;
1590
1591         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1592         if (ret) {
1593                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1594                 return ret;
1595         }
1596
1597         switch (level) {
1598         case AMD_DPM_FORCED_LEVEL_HIGH:
1599         case AMD_DPM_FORCED_LEVEL_LOW:
1600         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1601         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1602         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1603         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1604                 if ((smu_version >= 0x361200) &&
1605                     (smu_version <= 0x361a00)) {
1606                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1607                                "54.18 - 54.26(included) SMU firmwares\n");
1608                         return -EOPNOTSUPP;
1609                 }
1610                 break;
1611         default:
1612                 break;
1613         }
1614
1615         return smu_v11_0_set_performance_level(smu, level);
1616 }
1617
1618 static void arcturus_dump_pptable(struct smu_context *smu)
1619 {
1620         struct smu_table_context *table_context = &smu->smu_table;
1621         PPTable_t *pptable = table_context->driver_pptable;
1622         int i;
1623
1624         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1625
1626         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1627
1628         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1629         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1630
1631         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1632                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1633                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1634         }
1635
1636         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1637         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1638         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1639         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1640
1641         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1642         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1643         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1644         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1645         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1646         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1647         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1648
1649         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1650         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1651
1652         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1653
1654         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1655         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1656
1657         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1658         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1659         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1660         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1661
1662         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1663         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1664         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1665         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1666
1667         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1668         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1669
1670         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1671                         "  .VoltageMode          = 0x%02x\n"
1672                         "  .SnapToDiscrete       = 0x%02x\n"
1673                         "  .NumDiscreteLevels    = 0x%02x\n"
1674                         "  .padding              = 0x%02x\n"
1675                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1676                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1677                         "  .SsFmin               = 0x%04x\n"
1678                         "  .Padding_16           = 0x%04x\n",
1679                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1680                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1681                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1682                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1683                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1684                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1685                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1686                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1687                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1688                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1689                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1690
1691         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1692                         "  .VoltageMode          = 0x%02x\n"
1693                         "  .SnapToDiscrete       = 0x%02x\n"
1694                         "  .NumDiscreteLevels    = 0x%02x\n"
1695                         "  .padding              = 0x%02x\n"
1696                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1697                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1698                         "  .SsFmin               = 0x%04x\n"
1699                         "  .Padding_16           = 0x%04x\n",
1700                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1701                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1702                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1703                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1704                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1705                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1706                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1707                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1708                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1709                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1710                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1711
1712         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1713                         "  .VoltageMode          = 0x%02x\n"
1714                         "  .SnapToDiscrete       = 0x%02x\n"
1715                         "  .NumDiscreteLevels    = 0x%02x\n"
1716                         "  .padding              = 0x%02x\n"
1717                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1718                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1719                         "  .SsFmin               = 0x%04x\n"
1720                         "  .Padding_16           = 0x%04x\n",
1721                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1722                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1723                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1724                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1725                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1726                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1727                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1728                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1729                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1730                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1731                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1732
1733         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1734                         "  .VoltageMode          = 0x%02x\n"
1735                         "  .SnapToDiscrete       = 0x%02x\n"
1736                         "  .NumDiscreteLevels    = 0x%02x\n"
1737                         "  .padding              = 0x%02x\n"
1738                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1739                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1740                         "  .SsFmin               = 0x%04x\n"
1741                         "  .Padding_16           = 0x%04x\n",
1742                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1743                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1744                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1745                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1746                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1747                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1748                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1749                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1750                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1751                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1752                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1753
1754         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1755                         "  .VoltageMode          = 0x%02x\n"
1756                         "  .SnapToDiscrete       = 0x%02x\n"
1757                         "  .NumDiscreteLevels    = 0x%02x\n"
1758                         "  .padding              = 0x%02x\n"
1759                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1760                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1761                         "  .SsFmin               = 0x%04x\n"
1762                         "  .Padding_16           = 0x%04x\n",
1763                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1764                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1765                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1766                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1767                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1768                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1769                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1770                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1771                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1772                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1773                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1774
1775         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1776                         "  .VoltageMode          = 0x%02x\n"
1777                         "  .SnapToDiscrete       = 0x%02x\n"
1778                         "  .NumDiscreteLevels    = 0x%02x\n"
1779                         "  .padding              = 0x%02x\n"
1780                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1781                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1782                         "  .SsFmin               = 0x%04x\n"
1783                         "  .Padding_16           = 0x%04x\n",
1784                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1785                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1786                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1787                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1788                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1789                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1790                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1791                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1792                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1793                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1794                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1795
1796
1797         dev_info(smu->adev->dev, "FreqTableGfx\n");
1798         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1799                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1800
1801         dev_info(smu->adev->dev, "FreqTableVclk\n");
1802         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1803                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1804
1805         dev_info(smu->adev->dev, "FreqTableDclk\n");
1806         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1807                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1808
1809         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1810         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1811                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1812
1813         dev_info(smu->adev->dev, "FreqTableUclk\n");
1814         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1815                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1816
1817         dev_info(smu->adev->dev, "FreqTableFclk\n");
1818         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1819                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1820
1821         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1822         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1823                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1824
1825         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1826         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1827                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1828
1829         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1830         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1831         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1832         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1833         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1834         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1835         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1836         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1837         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1838
1839         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1840         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1841         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1842         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1843
1844         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1845         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1846
1847         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1848         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1849         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1850         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1851         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1852         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1853
1854         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1855         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1856         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1857         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1858         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1859         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1860         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1861         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1862         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1863
1864         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1865         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1866         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1867         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1868
1869         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1870         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1871         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1872         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1873
1874         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1875                         pptable->dBtcGbGfxPll.a,
1876                         pptable->dBtcGbGfxPll.b,
1877                         pptable->dBtcGbGfxPll.c);
1878         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1879                         pptable->dBtcGbGfxAfll.a,
1880                         pptable->dBtcGbGfxAfll.b,
1881                         pptable->dBtcGbGfxAfll.c);
1882         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1883                         pptable->dBtcGbSoc.a,
1884                         pptable->dBtcGbSoc.b,
1885                         pptable->dBtcGbSoc.c);
1886
1887         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1888                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1889                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1890         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1891                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1892                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1893
1894         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1895                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1896                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1897                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1898         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1899                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1900                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1901                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1902
1903         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1904         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1905
1906         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1907         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1908         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1909         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1910
1911         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1912         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1913         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1914         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1915
1916         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1917         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1918
1919         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1920         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1921                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1922         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1923         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1924
1925         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1926         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1927         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1928         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1929         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1930         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1931         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1932         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1933
1934         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1935         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1936                         pptable->ReservedEquation0.a,
1937                         pptable->ReservedEquation0.b,
1938                         pptable->ReservedEquation0.c);
1939         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1940                         pptable->ReservedEquation1.a,
1941                         pptable->ReservedEquation1.b,
1942                         pptable->ReservedEquation1.c);
1943         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1944                         pptable->ReservedEquation2.a,
1945                         pptable->ReservedEquation2.b,
1946                         pptable->ReservedEquation2.c);
1947         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1948                         pptable->ReservedEquation3.a,
1949                         pptable->ReservedEquation3.b,
1950                         pptable->ReservedEquation3.c);
1951
1952         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1953         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1954
1955         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1956         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1957         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1958
1959         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1960         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1961
1962         dev_info(smu->adev->dev, "Board Parameters:\n");
1963         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1964         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1965
1966         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1967         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1968         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1969         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1970
1971         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1972         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1973
1974         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1975         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1976         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1977
1978         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1979         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1980         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1981
1982         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1983         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1984         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1985
1986         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1987         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1988         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1989
1990         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1991         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1992         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1993         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1994
1995         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1996         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1997         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1998
1999         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
2000         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
2001         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
2002
2003         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
2004         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
2005         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
2006
2007         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
2008         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
2009         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
2010
2011         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2012                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2013                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
2014                                 pptable->I2cControllers[i].Enabled);
2015                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2016                                 pptable->I2cControllers[i].SlaveAddress);
2017                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
2018                                 pptable->I2cControllers[i].ControllerPort);
2019                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
2020                                 pptable->I2cControllers[i].ControllerName);
2021                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
2022                                 pptable->I2cControllers[i].ThermalThrotter);
2023                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
2024                                 pptable->I2cControllers[i].I2cProtocol);
2025                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
2026                                 pptable->I2cControllers[i].Speed);
2027         }
2028
2029         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
2030         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
2031
2032         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
2033
2034         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2035         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2036                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2037         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2038         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2039                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2040         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2041         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2042                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2043         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2044         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2045                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2046
2047 }
2048
2049 static bool arcturus_is_dpm_running(struct smu_context *smu)
2050 {
2051         int ret = 0;
2052         uint32_t feature_mask[2];
2053         uint64_t feature_enabled;
2054
2055         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
2056         if (ret)
2057                 return false;
2058
2059         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
2060
2061         return !!(feature_enabled & SMC_DPM_FEATURE);
2062 }
2063
2064 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
2065 {
2066         int ret = 0;
2067
2068         if (enable) {
2069                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2070                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
2071                         if (ret) {
2072                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
2073                                 return ret;
2074                         }
2075                 }
2076         } else {
2077                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2078                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
2079                         if (ret) {
2080                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
2081                                 return ret;
2082                         }
2083                 }
2084         }
2085
2086         return ret;
2087 }
2088
2089 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2090                              struct i2c_msg *msg, int num_msgs)
2091 {
2092         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2093         struct smu_table_context *smu_table = &adev->smu.smu_table;
2094         struct smu_table *table = &smu_table->driver_table;
2095         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2096         int i, j, r, c;
2097         u16 dir;
2098
2099         req = kzalloc(sizeof(*req), GFP_KERNEL);
2100         if (!req)
2101                 return -ENOMEM;
2102
2103         req->I2CcontrollerPort = 0;
2104         req->I2CSpeed = I2C_SPEED_FAST_400K;
2105         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2106         dir = msg[0].flags & I2C_M_RD;
2107
2108         for (c = i = 0; i < num_msgs; i++) {
2109                 for (j = 0; j < msg[i].len; j++, c++) {
2110                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2111
2112                         if (!(msg[i].flags & I2C_M_RD)) {
2113                                 /* write */
2114                                 cmd->Cmd = I2C_CMD_WRITE;
2115                                 cmd->RegisterAddr = msg[i].buf[j];
2116                         }
2117
2118                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
2119                                 /* The direction changes.
2120                                  */
2121                                 dir = msg[i].flags & I2C_M_RD;
2122                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2123                         }
2124
2125                         req->NumCmds++;
2126
2127                         /*
2128                          * Insert STOP if we are at the last byte of either last
2129                          * message for the transaction or the client explicitly
2130                          * requires a STOP at this particular message.
2131                          */
2132                         if ((j == msg[i].len - 1) &&
2133                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2134                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2135                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2136                         }
2137                 }
2138         }
2139         mutex_lock(&adev->smu.mutex);
2140         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2141         mutex_unlock(&adev->smu.mutex);
2142         if (r)
2143                 goto fail;
2144
2145         for (c = i = 0; i < num_msgs; i++) {
2146                 if (!(msg[i].flags & I2C_M_RD)) {
2147                         c += msg[i].len;
2148                         continue;
2149                 }
2150                 for (j = 0; j < msg[i].len; j++, c++) {
2151                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2152
2153                         msg[i].buf[j] = cmd->Data;
2154                 }
2155         }
2156         r = num_msgs;
2157 fail:
2158         kfree(req);
2159         return r;
2160 }
2161
2162 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2163 {
2164         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2165 }
2166
2167
2168 static const struct i2c_algorithm arcturus_i2c_algo = {
2169         .master_xfer = arcturus_i2c_xfer,
2170         .functionality = arcturus_i2c_func,
2171 };
2172
2173
2174 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2175         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2176         .max_read_len  = MAX_SW_I2C_COMMANDS,
2177         .max_write_len = MAX_SW_I2C_COMMANDS,
2178         .max_comb_1st_msg_len = 2,
2179         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2180 };
2181
2182 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2183 {
2184         struct amdgpu_device *adev = to_amdgpu_device(control);
2185         int res;
2186
2187         control->owner = THIS_MODULE;
2188         control->class = I2C_CLASS_HWMON;
2189         control->dev.parent = &adev->pdev->dev;
2190         control->algo = &arcturus_i2c_algo;
2191         control->quirks = &arcturus_i2c_control_quirks;
2192         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2193
2194         res = i2c_add_adapter(control);
2195         if (res)
2196                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2197
2198         return res;
2199 }
2200
2201 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2202 {
2203         i2c_del_adapter(control);
2204 }
2205
2206 static void arcturus_get_unique_id(struct smu_context *smu)
2207 {
2208         struct amdgpu_device *adev = smu->adev;
2209         uint32_t top32 = 0, bottom32 = 0, smu_version;
2210         uint64_t id;
2211
2212         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2213                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2214                 return;
2215         }
2216
2217         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2218         if (smu_version < 0x361700) {
2219                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2220                 return;
2221         }
2222
2223         /* Get the SN to turn into a Unique ID */
2224         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2225         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2226
2227         id = ((uint64_t)bottom32 << 32) | top32;
2228         adev->unique_id = id;
2229         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2230          * 16-digit HEX string for convenience and backwards-compatibility
2231          */
2232         sprintf(adev->serial, "%llx", id);
2233 }
2234
2235 static int arcturus_set_df_cstate(struct smu_context *smu,
2236                                   enum pp_df_cstate state)
2237 {
2238         uint32_t smu_version;
2239         int ret;
2240
2241         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2242         if (ret) {
2243                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2244                 return ret;
2245         }
2246
2247         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2248         if (smu_version < 0x360F00) {
2249                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2250                 return -EINVAL;
2251         }
2252
2253         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2254 }
2255
2256 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2257 {
2258         uint32_t smu_version;
2259         int ret;
2260
2261         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2262         if (ret) {
2263                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2264                 return ret;
2265         }
2266
2267         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2268         if (smu_version < 0x00361700) {
2269                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2270                 return -EINVAL;
2271         }
2272
2273         if (en)
2274                 return smu_cmn_send_smc_msg_with_param(smu,
2275                                                    SMU_MSG_GmiPwrDnControl,
2276                                                    1,
2277                                                    NULL);
2278
2279         return smu_cmn_send_smc_msg_with_param(smu,
2280                                            SMU_MSG_GmiPwrDnControl,
2281                                            0,
2282                                            NULL);
2283 }
2284
2285 static const struct throttling_logging_label {
2286         uint32_t feature_mask;
2287         const char *label;
2288 } logging_label[] = {
2289         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2290         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2291         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2292         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2293         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2294         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2295         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2296 };
2297 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2298 {
2299         int ret;
2300         int throttler_idx, throtting_events = 0, buf_idx = 0;
2301         struct amdgpu_device *adev = smu->adev;
2302         uint32_t throttler_status;
2303         char log_buf[256];
2304
2305         ret = arcturus_get_smu_metrics_data(smu,
2306                                             METRICS_THROTTLER_STATUS,
2307                                             &throttler_status);
2308         if (ret)
2309                 return;
2310
2311         memset(log_buf, 0, sizeof(log_buf));
2312         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2313              throttler_idx++) {
2314                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2315                         throtting_events++;
2316                         buf_idx += snprintf(log_buf + buf_idx,
2317                                             sizeof(log_buf) - buf_idx,
2318                                             "%s%s",
2319                                             throtting_events > 1 ? " and " : "",
2320                                             logging_label[throttler_idx].label);
2321                         if (buf_idx >= sizeof(log_buf)) {
2322                                 dev_err(adev->dev, "buffer overflow!\n");
2323                                 log_buf[sizeof(log_buf) - 1] = '\0';
2324                                 break;
2325                         }
2326                 }
2327         }
2328
2329         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2330                         log_buf);
2331         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2332                 smu_cmn_get_indep_throttler_status(throttler_status,
2333                                                    arcturus_throttler_map));
2334 }
2335
2336 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2337 {
2338         struct amdgpu_device *adev = smu->adev;
2339         uint32_t esm_ctrl;
2340
2341         /* TODO: confirm this on real target */
2342         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2343         if ((esm_ctrl >> 15) & 0x1FFFF)
2344                 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2345
2346         return smu_v11_0_get_current_pcie_link_speed(smu);
2347 }
2348
2349 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2350                                         void **table)
2351 {
2352         struct smu_table_context *smu_table = &smu->smu_table;
2353         struct gpu_metrics_v1_3 *gpu_metrics =
2354                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2355         SmuMetrics_t metrics;
2356         int ret = 0;
2357
2358         ret = smu_cmn_get_metrics_table(smu,
2359                                         &metrics,
2360                                         true);
2361         if (ret)
2362                 return ret;
2363
2364         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2365
2366         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2367         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2368         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2369         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2370         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2371         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2372
2373         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2374         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2375         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2376
2377         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2378         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2379
2380         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2381         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2382         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2383         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2384         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2385
2386         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2387         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2388         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2389         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2390         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2391
2392         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2393         gpu_metrics->indep_throttle_status =
2394                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2395                                                            arcturus_throttler_map);
2396
2397         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2398
2399         gpu_metrics->pcie_link_width =
2400                         smu_v11_0_get_current_pcie_link_width(smu);
2401         gpu_metrics->pcie_link_speed =
2402                         arcturus_get_current_pcie_link_speed(smu);
2403
2404         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2405
2406         *table = (void *)gpu_metrics;
2407
2408         return sizeof(struct gpu_metrics_v1_3);
2409 }
2410
2411 static const struct pptable_funcs arcturus_ppt_funcs = {
2412         /* init dpm */
2413         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2414         /* btc */
2415         .run_btc = arcturus_run_btc,
2416         /* dpm/clk tables */
2417         .set_default_dpm_table = arcturus_set_default_dpm_table,
2418         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2419         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2420         .print_clk_levels = arcturus_print_clk_levels,
2421         .force_clk_levels = arcturus_force_clk_levels,
2422         .read_sensor = arcturus_read_sensor,
2423         .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2424         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2425         .get_power_profile_mode = arcturus_get_power_profile_mode,
2426         .set_power_profile_mode = arcturus_set_power_profile_mode,
2427         .set_performance_level = arcturus_set_performance_level,
2428         /* debug (internal used) */
2429         .dump_pptable = arcturus_dump_pptable,
2430         .get_power_limit = arcturus_get_power_limit,
2431         .is_dpm_running = arcturus_is_dpm_running,
2432         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2433         .i2c_init = arcturus_i2c_control_init,
2434         .i2c_fini = arcturus_i2c_control_fini,
2435         .get_unique_id = arcturus_get_unique_id,
2436         .init_microcode = smu_v11_0_init_microcode,
2437         .load_microcode = smu_v11_0_load_microcode,
2438         .fini_microcode = smu_v11_0_fini_microcode,
2439         .init_smc_tables = arcturus_init_smc_tables,
2440         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2441         .init_power = smu_v11_0_init_power,
2442         .fini_power = smu_v11_0_fini_power,
2443         .check_fw_status = smu_v11_0_check_fw_status,
2444         /* pptable related */
2445         .setup_pptable = arcturus_setup_pptable,
2446         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2447         .check_fw_version = smu_v11_0_check_fw_version,
2448         .write_pptable = smu_cmn_write_pptable,
2449         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2450         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2451         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2452         .system_features_control = smu_v11_0_system_features_control,
2453         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2454         .send_smc_msg = smu_cmn_send_smc_msg,
2455         .init_display_count = NULL,
2456         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2457         .get_enabled_mask = smu_cmn_get_enabled_mask,
2458         .feature_is_enabled = smu_cmn_feature_is_enabled,
2459         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2460         .notify_display_change = NULL,
2461         .set_power_limit = smu_v11_0_set_power_limit,
2462         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2463         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2464         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2465         .set_min_dcef_deep_sleep = NULL,
2466         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2467         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2468         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2469         .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2470         .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2471         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2472         .gfx_off_control = smu_v11_0_gfx_off_control,
2473         .register_irq_handler = smu_v11_0_register_irq_handler,
2474         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2475         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2476         .baco_is_support = smu_v11_0_baco_is_support,
2477         .baco_get_state = smu_v11_0_baco_get_state,
2478         .baco_set_state = smu_v11_0_baco_set_state,
2479         .baco_enter = smu_v11_0_baco_enter,
2480         .baco_exit = smu_v11_0_baco_exit,
2481         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2482         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2483         .set_df_cstate = arcturus_set_df_cstate,
2484         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2485         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2486         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2487         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2488         .get_gpu_metrics = arcturus_get_gpu_metrics,
2489         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2490         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2491         .get_fan_parameters = arcturus_get_fan_parameters,
2492         .interrupt_work = smu_v11_0_interrupt_work,
2493         .set_light_sbr = smu_v11_0_set_light_sbr,
2494         .set_mp1_state = smu_cmn_set_mp1_state,
2495 };
2496
2497 void arcturus_set_ppt_funcs(struct smu_context *smu)
2498 {
2499         smu->ppt_funcs = &arcturus_ppt_funcs;
2500         smu->message_map = arcturus_message_map;
2501         smu->clock_map = arcturus_clk_map;
2502         smu->feature_map = arcturus_feature_mask_map;
2503         smu->table_map = arcturus_table_map;
2504         smu->pwr_src_map = arcturus_pwr_src_map;
2505         smu->workload_map = arcturus_workload_map;
2506 }