2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define SWSMU_CODE_LAYER_L2
26 #include <linux/firmware.h>
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_arcturus.h"
34 #include "soc15_common.h"
36 #include "power_state.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
63 [smu_feature] = {1, (arcturus_feature)}
65 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
66 #define SMU_FEATURES_LOW_SHIFT 0
67 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
68 #define SMU_FEATURES_HIGH_SHIFT 32
70 #define SMC_DPM_FEATURE ( \
71 FEATURE_DPM_PREFETCHER_MASK | \
72 FEATURE_DPM_GFXCLK_MASK | \
73 FEATURE_DPM_UCLK_MASK | \
74 FEATURE_DPM_SOCCLK_MASK | \
75 FEATURE_DPM_MP0CLK_MASK | \
76 FEATURE_DPM_FCLK_MASK | \
77 FEATURE_DPM_XGMI_MASK)
79 /* possible frequency drift (1Mhz) */
82 #define smnPCIE_ESM_CTRL 0x111003D0
84 #define mmCG_FDO_CTRL0_ARCT 0x8B
85 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0
87 #define mmCG_FDO_CTRL1_ARCT 0x8C
88 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0
90 #define mmCG_FDO_CTRL2_ARCT 0x8D
91 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0
93 #define mmCG_TACH_CTRL_ARCT 0x8E
94 #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0
96 #define mmCG_TACH_STATUS_ARCT 0x8F
97 #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0
99 #define mmCG_THERMAL_STATUS_ARCT 0x90
100 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
106 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
107 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
108 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
109 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
110 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
111 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
112 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
113 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
114 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
115 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
123 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
126 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
127 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
128 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
136 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
137 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
138 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
139 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
140 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
141 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
142 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
143 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
144 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
145 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
146 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
147 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
148 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
149 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
150 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
151 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
152 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
153 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
154 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
155 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
156 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
157 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
158 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
159 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
160 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
161 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
162 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
163 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0),
166 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
167 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
168 CLK_MAP(SCLK, PPCLK_GFXCLK),
169 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
170 CLK_MAP(FCLK, PPCLK_FCLK),
171 CLK_MAP(UCLK, PPCLK_UCLK),
172 CLK_MAP(MCLK, PPCLK_UCLK),
173 CLK_MAP(DCLK, PPCLK_DCLK),
174 CLK_MAP(VCLK, PPCLK_VCLK),
177 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
178 FEA_MAP(DPM_PREFETCHER),
191 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
192 FEA_MAP(RSMU_SMN_CG),
200 FEA_MAP(FAN_CONTROL),
202 FEA_MAP(OUT_OF_BAND_MONITOR),
203 FEA_MAP(TEMP_DEPENDENT_VMIN),
206 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
209 TAB_MAP(AVFS_PSM_DEBUG),
210 TAB_MAP(AVFS_FUSE_OVERRIDE),
211 TAB_MAP(PMSTATUSLOG),
212 TAB_MAP(SMU_METRICS),
213 TAB_MAP(DRIVER_SMU_CONFIG),
215 TAB_MAP(I2C_COMMANDS),
216 TAB_MAP(ACTIVITY_MONITOR_COEFF),
219 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
224 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
228 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
229 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
232 static const uint8_t arcturus_throttler_map[] = {
233 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
234 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
235 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
236 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
237 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
238 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
239 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
240 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
241 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
242 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
243 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
244 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
245 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
246 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
247 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
248 [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT),
249 [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT),
252 static int arcturus_tables_init(struct smu_context *smu)
254 struct smu_table_context *smu_table = &smu->smu_table;
255 struct smu_table *tables = smu_table->tables;
257 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
258 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
260 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
261 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
263 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
264 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
266 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
267 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
269 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
270 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
271 AMDGPU_GEM_DOMAIN_VRAM);
273 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
274 if (!smu_table->metrics_table)
276 smu_table->metrics_time = 0;
278 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
279 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
280 if (!smu_table->gpu_metrics_table) {
281 kfree(smu_table->metrics_table);
288 static int arcturus_allocate_dpm_context(struct smu_context *smu)
290 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
292 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
294 if (!smu_dpm->dpm_context)
296 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
298 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
300 if (!smu_dpm->dpm_current_power_state)
303 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
305 if (!smu_dpm->dpm_request_power_state)
311 static int arcturus_init_smc_tables(struct smu_context *smu)
315 ret = arcturus_tables_init(smu);
319 ret = arcturus_allocate_dpm_context(smu);
323 return smu_v11_0_init_smc_tables(smu);
327 arcturus_get_allowed_feature_mask(struct smu_context *smu,
328 uint32_t *feature_mask, uint32_t num)
333 /* pptable will handle the features to enable */
334 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
339 static int arcturus_set_default_dpm_table(struct smu_context *smu)
341 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
342 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
343 struct smu_11_0_dpm_table *dpm_table = NULL;
346 /* socclk dpm table setup */
347 dpm_table = &dpm_context->dpm_tables.soc_table;
348 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
349 ret = smu_v11_0_set_single_dpm_table(smu,
354 dpm_table->is_fine_grained =
355 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
357 dpm_table->count = 1;
358 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
359 dpm_table->dpm_levels[0].enabled = true;
360 dpm_table->min = dpm_table->dpm_levels[0].value;
361 dpm_table->max = dpm_table->dpm_levels[0].value;
364 /* gfxclk dpm table setup */
365 dpm_table = &dpm_context->dpm_tables.gfx_table;
366 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
367 ret = smu_v11_0_set_single_dpm_table(smu,
372 dpm_table->is_fine_grained =
373 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
375 dpm_table->count = 1;
376 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
377 dpm_table->dpm_levels[0].enabled = true;
378 dpm_table->min = dpm_table->dpm_levels[0].value;
379 dpm_table->max = dpm_table->dpm_levels[0].value;
382 /* memclk dpm table setup */
383 dpm_table = &dpm_context->dpm_tables.uclk_table;
384 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
385 ret = smu_v11_0_set_single_dpm_table(smu,
390 dpm_table->is_fine_grained =
391 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
393 dpm_table->count = 1;
394 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
395 dpm_table->dpm_levels[0].enabled = true;
396 dpm_table->min = dpm_table->dpm_levels[0].value;
397 dpm_table->max = dpm_table->dpm_levels[0].value;
400 /* fclk dpm table setup */
401 dpm_table = &dpm_context->dpm_tables.fclk_table;
402 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
403 ret = smu_v11_0_set_single_dpm_table(smu,
408 dpm_table->is_fine_grained =
409 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
411 dpm_table->count = 1;
412 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
413 dpm_table->dpm_levels[0].enabled = true;
414 dpm_table->min = dpm_table->dpm_levels[0].value;
415 dpm_table->max = dpm_table->dpm_levels[0].value;
421 static void arcturus_check_bxco_support(struct smu_context *smu)
423 struct smu_table_context *table_context = &smu->smu_table;
424 struct smu_11_0_powerplay_table *powerplay_table =
425 table_context->power_play_table;
426 struct smu_baco_context *smu_baco = &smu->smu_baco;
427 struct amdgpu_device *adev = smu->adev;
430 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
431 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
432 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
433 smu_baco->platform_support =
434 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
439 static void arcturus_check_fan_support(struct smu_context *smu)
441 struct smu_table_context *table_context = &smu->smu_table;
442 PPTable_t *pptable = table_context->driver_pptable;
444 /* No sort of fan control possible if PPTable has it disabled */
445 smu->adev->pm.no_fan =
446 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK);
447 if (smu->adev->pm.no_fan)
448 dev_info_once(smu->adev->dev,
449 "PMFW based fan control disabled");
452 static int arcturus_check_powerplay_table(struct smu_context *smu)
454 struct smu_table_context *table_context = &smu->smu_table;
455 struct smu_11_0_powerplay_table *powerplay_table =
456 table_context->power_play_table;
458 arcturus_check_bxco_support(smu);
459 arcturus_check_fan_support(smu);
461 table_context->thermal_controller_type =
462 powerplay_table->thermal_controller_type;
467 static int arcturus_store_powerplay_table(struct smu_context *smu)
469 struct smu_table_context *table_context = &smu->smu_table;
470 struct smu_11_0_powerplay_table *powerplay_table =
471 table_context->power_play_table;
473 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
479 static int arcturus_append_powerplay_table(struct smu_context *smu)
481 struct smu_table_context *table_context = &smu->smu_table;
482 PPTable_t *smc_pptable = table_context->driver_pptable;
483 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
486 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
489 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
490 (uint8_t **)&smc_dpm_table);
494 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
495 smc_dpm_table->table_header.format_revision,
496 smc_dpm_table->table_header.content_revision);
498 if ((smc_dpm_table->table_header.format_revision == 4) &&
499 (smc_dpm_table->table_header.content_revision == 6))
500 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
501 smc_dpm_table, maxvoltagestepgfx);
505 static int arcturus_setup_pptable(struct smu_context *smu)
509 ret = smu_v11_0_setup_pptable(smu);
513 ret = arcturus_store_powerplay_table(smu);
517 ret = arcturus_append_powerplay_table(smu);
521 ret = arcturus_check_powerplay_table(smu);
528 static int arcturus_run_btc(struct smu_context *smu)
532 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
534 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
538 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
541 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
543 struct smu_11_0_dpm_context *dpm_context =
544 smu->smu_dpm.dpm_context;
545 struct smu_11_0_dpm_table *gfx_table =
546 &dpm_context->dpm_tables.gfx_table;
547 struct smu_11_0_dpm_table *mem_table =
548 &dpm_context->dpm_tables.uclk_table;
549 struct smu_11_0_dpm_table *soc_table =
550 &dpm_context->dpm_tables.soc_table;
551 struct smu_umd_pstate_table *pstate_table =
554 pstate_table->gfxclk_pstate.min = gfx_table->min;
555 pstate_table->gfxclk_pstate.peak = gfx_table->max;
557 pstate_table->uclk_pstate.min = mem_table->min;
558 pstate_table->uclk_pstate.peak = mem_table->max;
560 pstate_table->socclk_pstate.min = soc_table->min;
561 pstate_table->socclk_pstate.peak = soc_table->max;
563 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
564 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
565 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
566 pstate_table->gfxclk_pstate.standard =
567 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
568 pstate_table->uclk_pstate.standard =
569 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
570 pstate_table->socclk_pstate.standard =
571 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
573 pstate_table->gfxclk_pstate.standard =
574 pstate_table->gfxclk_pstate.min;
575 pstate_table->uclk_pstate.standard =
576 pstate_table->uclk_pstate.min;
577 pstate_table->socclk_pstate.standard =
578 pstate_table->socclk_pstate.min;
584 static int arcturus_get_clk_table(struct smu_context *smu,
585 struct pp_clock_levels_with_latency *clocks,
586 struct smu_11_0_dpm_table *dpm_table)
590 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
591 clocks->num_levels = count;
593 for (i = 0; i < count; i++) {
594 clocks->data[i].clocks_in_khz =
595 dpm_table->dpm_levels[i].value * 1000;
596 clocks->data[i].latency_in_us = 0;
602 static int arcturus_freqs_in_same_level(int32_t frequency1,
605 return (abs(frequency1 - frequency2) <= EPSILON);
608 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
609 MetricsMember_t member,
612 struct smu_table_context *smu_table= &smu->smu_table;
613 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
616 mutex_lock(&smu->metrics_lock);
618 ret = smu_cmn_get_metrics_table_locked(smu,
622 mutex_unlock(&smu->metrics_lock);
627 case METRICS_CURR_GFXCLK:
628 *value = metrics->CurrClock[PPCLK_GFXCLK];
630 case METRICS_CURR_SOCCLK:
631 *value = metrics->CurrClock[PPCLK_SOCCLK];
633 case METRICS_CURR_UCLK:
634 *value = metrics->CurrClock[PPCLK_UCLK];
636 case METRICS_CURR_VCLK:
637 *value = metrics->CurrClock[PPCLK_VCLK];
639 case METRICS_CURR_DCLK:
640 *value = metrics->CurrClock[PPCLK_DCLK];
642 case METRICS_CURR_FCLK:
643 *value = metrics->CurrClock[PPCLK_FCLK];
645 case METRICS_AVERAGE_GFXCLK:
646 *value = metrics->AverageGfxclkFrequency;
648 case METRICS_AVERAGE_SOCCLK:
649 *value = metrics->AverageSocclkFrequency;
651 case METRICS_AVERAGE_UCLK:
652 *value = metrics->AverageUclkFrequency;
654 case METRICS_AVERAGE_VCLK:
655 *value = metrics->AverageVclkFrequency;
657 case METRICS_AVERAGE_DCLK:
658 *value = metrics->AverageDclkFrequency;
660 case METRICS_AVERAGE_GFXACTIVITY:
661 *value = metrics->AverageGfxActivity;
663 case METRICS_AVERAGE_MEMACTIVITY:
664 *value = metrics->AverageUclkActivity;
666 case METRICS_AVERAGE_VCNACTIVITY:
667 *value = metrics->VcnActivityPercentage;
669 case METRICS_AVERAGE_SOCKETPOWER:
670 *value = metrics->AverageSocketPower << 8;
672 case METRICS_TEMPERATURE_EDGE:
673 *value = metrics->TemperatureEdge *
674 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
676 case METRICS_TEMPERATURE_HOTSPOT:
677 *value = metrics->TemperatureHotspot *
678 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
680 case METRICS_TEMPERATURE_MEM:
681 *value = metrics->TemperatureHBM *
682 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
684 case METRICS_TEMPERATURE_VRGFX:
685 *value = metrics->TemperatureVrGfx *
686 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
688 case METRICS_TEMPERATURE_VRSOC:
689 *value = metrics->TemperatureVrSoc *
690 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
692 case METRICS_TEMPERATURE_VRMEM:
693 *value = metrics->TemperatureVrMem *
694 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
696 case METRICS_THROTTLER_STATUS:
697 *value = metrics->ThrottlerStatus;
699 case METRICS_CURR_FANSPEED:
700 *value = metrics->CurrFanSpeed;
707 mutex_unlock(&smu->metrics_lock);
712 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
713 enum smu_clk_type clk_type,
716 MetricsMember_t member_type;
722 clk_id = smu_cmn_to_asic_specific_index(smu,
723 CMN2ASIC_MAPPING_CLK,
731 * CurrClock[clk_id] can provide accurate
732 * output only when the dpm feature is enabled.
733 * We can use Average_* for dpm disabled case.
734 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
736 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
737 member_type = METRICS_CURR_GFXCLK;
739 member_type = METRICS_AVERAGE_GFXCLK;
742 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
743 member_type = METRICS_CURR_UCLK;
745 member_type = METRICS_AVERAGE_UCLK;
748 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
749 member_type = METRICS_CURR_SOCCLK;
751 member_type = METRICS_AVERAGE_SOCCLK;
754 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
755 member_type = METRICS_CURR_VCLK;
757 member_type = METRICS_AVERAGE_VCLK;
760 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
761 member_type = METRICS_CURR_DCLK;
763 member_type = METRICS_AVERAGE_DCLK;
766 member_type = METRICS_CURR_FCLK;
772 return arcturus_get_smu_metrics_data(smu,
777 static int arcturus_print_clk_levels(struct smu_context *smu,
778 enum smu_clk_type type, char *buf)
780 int i, now, size = 0;
782 struct pp_clock_levels_with_latency clocks;
783 struct smu_11_0_dpm_table *single_dpm_table;
784 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
785 struct smu_11_0_dpm_context *dpm_context = NULL;
786 uint32_t gen_speed, lane_width;
788 smu_cmn_get_sysfs_buf(&buf, &size);
790 if (amdgpu_ras_intr_triggered()) {
791 size += sysfs_emit_at(buf, size, "unavailable\n");
795 dpm_context = smu_dpm->dpm_context;
799 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
801 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
805 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
806 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
808 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
813 * For DPM disabled case, there will be only one clock level.
814 * And it's safe to assume that is always the current clock.
816 for (i = 0; i < clocks.num_levels; i++)
817 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
818 clocks.data[i].clocks_in_khz / 1000,
819 (clocks.num_levels == 1) ? "*" :
820 (arcturus_freqs_in_same_level(
821 clocks.data[i].clocks_in_khz / 1000,
826 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
828 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
832 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
833 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
835 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
839 for (i = 0; i < clocks.num_levels; i++)
840 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
841 i, clocks.data[i].clocks_in_khz / 1000,
842 (clocks.num_levels == 1) ? "*" :
843 (arcturus_freqs_in_same_level(
844 clocks.data[i].clocks_in_khz / 1000,
849 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
851 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
855 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
856 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
858 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
862 for (i = 0; i < clocks.num_levels; i++)
863 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
864 i, clocks.data[i].clocks_in_khz / 1000,
865 (clocks.num_levels == 1) ? "*" :
866 (arcturus_freqs_in_same_level(
867 clocks.data[i].clocks_in_khz / 1000,
872 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
874 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
878 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
879 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
881 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
885 for (i = 0; i < single_dpm_table->count; i++)
886 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
887 i, single_dpm_table->dpm_levels[i].value,
888 (clocks.num_levels == 1) ? "*" :
889 (arcturus_freqs_in_same_level(
890 clocks.data[i].clocks_in_khz / 1000,
895 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
897 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
901 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
902 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
904 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
908 for (i = 0; i < single_dpm_table->count; i++)
909 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
910 i, single_dpm_table->dpm_levels[i].value,
911 (clocks.num_levels == 1) ? "*" :
912 (arcturus_freqs_in_same_level(
913 clocks.data[i].clocks_in_khz / 1000,
918 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
920 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
924 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
925 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
927 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
931 for (i = 0; i < single_dpm_table->count; i++)
932 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
933 i, single_dpm_table->dpm_levels[i].value,
934 (clocks.num_levels == 1) ? "*" :
935 (arcturus_freqs_in_same_level(
936 clocks.data[i].clocks_in_khz / 1000,
941 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
942 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
943 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
944 (gen_speed == 0) ? "2.5GT/s," :
945 (gen_speed == 1) ? "5.0GT/s," :
946 (gen_speed == 2) ? "8.0GT/s," :
947 (gen_speed == 3) ? "16.0GT/s," : "",
948 (lane_width == 1) ? "x1" :
949 (lane_width == 2) ? "x2" :
950 (lane_width == 3) ? "x4" :
951 (lane_width == 4) ? "x8" :
952 (lane_width == 5) ? "x12" :
953 (lane_width == 6) ? "x16" : "",
954 smu->smu_table.boot_values.lclk / 100);
964 static int arcturus_upload_dpm_level(struct smu_context *smu,
966 uint32_t feature_mask,
969 struct smu_11_0_dpm_context *dpm_context =
970 smu->smu_dpm.dpm_context;
974 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
975 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
976 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
977 ret = smu_cmn_send_smc_msg_with_param(smu,
978 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
979 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
982 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
983 max ? "max" : "min");
988 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
989 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
990 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
991 ret = smu_cmn_send_smc_msg_with_param(smu,
992 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
993 (PPCLK_UCLK << 16) | (freq & 0xffff),
996 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
997 max ? "max" : "min");
1002 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1003 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1004 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1005 ret = smu_cmn_send_smc_msg_with_param(smu,
1006 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1007 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
1010 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
1011 max ? "max" : "min");
1019 static int arcturus_force_clk_levels(struct smu_context *smu,
1020 enum smu_clk_type type, uint32_t mask)
1022 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1023 struct smu_11_0_dpm_table *single_dpm_table = NULL;
1024 uint32_t soft_min_level, soft_max_level;
1025 uint32_t smu_version;
1028 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1030 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1034 if ((smu_version >= 0x361200) &&
1035 (smu_version <= 0x361a00)) {
1036 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1037 "54.18 - 54.26(included) SMU firmwares\n");
1041 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1042 soft_max_level = mask ? (fls(mask) - 1) : 0;
1046 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1047 if (soft_max_level >= single_dpm_table->count) {
1048 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1049 soft_max_level, single_dpm_table->count - 1);
1054 ret = arcturus_upload_dpm_level(smu,
1056 FEATURE_DPM_GFXCLK_MASK,
1059 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1063 ret = arcturus_upload_dpm_level(smu,
1065 FEATURE_DPM_GFXCLK_MASK,
1068 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1076 * Should not arrive here since Arcturus does not
1077 * support mclk/socclk/fclk softmin/softmax settings
1089 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1090 struct smu_temperature_range *range)
1092 struct smu_table_context *table_context = &smu->smu_table;
1093 struct smu_11_0_powerplay_table *powerplay_table =
1094 table_context->power_play_table;
1095 PPTable_t *pptable = smu->smu_table.driver_pptable;
1100 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1102 range->max = pptable->TedgeLimit *
1103 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1104 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1105 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1106 range->hotspot_crit_max = pptable->ThotspotLimit *
1107 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1108 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1109 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1110 range->mem_crit_max = pptable->TmemLimit *
1111 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1112 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1113 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1114 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1119 static int arcturus_read_sensor(struct smu_context *smu,
1120 enum amd_pp_sensors sensor,
1121 void *data, uint32_t *size)
1123 struct smu_table_context *table_context = &smu->smu_table;
1124 PPTable_t *pptable = table_context->driver_pptable;
1127 if (amdgpu_ras_intr_triggered())
1133 mutex_lock(&smu->sensor_lock);
1135 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1136 *(uint32_t *)data = pptable->FanMaximumRpm;
1139 case AMDGPU_PP_SENSOR_MEM_LOAD:
1140 ret = arcturus_get_smu_metrics_data(smu,
1141 METRICS_AVERAGE_MEMACTIVITY,
1145 case AMDGPU_PP_SENSOR_GPU_LOAD:
1146 ret = arcturus_get_smu_metrics_data(smu,
1147 METRICS_AVERAGE_GFXACTIVITY,
1151 case AMDGPU_PP_SENSOR_GPU_POWER:
1152 ret = arcturus_get_smu_metrics_data(smu,
1153 METRICS_AVERAGE_SOCKETPOWER,
1157 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1158 ret = arcturus_get_smu_metrics_data(smu,
1159 METRICS_TEMPERATURE_HOTSPOT,
1163 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1164 ret = arcturus_get_smu_metrics_data(smu,
1165 METRICS_TEMPERATURE_EDGE,
1169 case AMDGPU_PP_SENSOR_MEM_TEMP:
1170 ret = arcturus_get_smu_metrics_data(smu,
1171 METRICS_TEMPERATURE_MEM,
1175 case AMDGPU_PP_SENSOR_GFX_MCLK:
1176 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1177 /* the output clock frequency in 10K unit */
1178 *(uint32_t *)data *= 100;
1181 case AMDGPU_PP_SENSOR_GFX_SCLK:
1182 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1183 *(uint32_t *)data *= 100;
1186 case AMDGPU_PP_SENSOR_VDDGFX:
1187 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1194 mutex_unlock(&smu->sensor_lock);
1199 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1202 struct amdgpu_device *adev = smu->adev;
1204 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1205 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1206 CG_FDO_CTRL2, TMIN, 0));
1207 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1208 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1209 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1214 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1217 struct amdgpu_device *adev = smu->adev;
1218 uint32_t crystal_clock_freq = 2500;
1219 uint32_t tach_status;
1226 switch (smu_v11_0_get_fan_control_mode(smu)) {
1227 case AMD_FAN_CTRL_AUTO:
1228 ret = arcturus_get_smu_metrics_data(smu,
1229 METRICS_CURR_FANSPEED,
1234 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1235 * detected via register retrieving. To workaround this, we will
1236 * report the fan speed as 0 RPM if user just requested such.
1238 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1239 && !smu->user_dpm_profile.fan_speed_rpm) {
1244 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1245 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1247 do_div(tmp64, tach_status);
1248 *speed = (uint32_t)tmp64;
1259 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1262 struct amdgpu_device *adev = smu->adev;
1263 uint32_t duty100, duty;
1266 speed = MIN(speed, 255);
1268 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1269 CG_FDO_CTRL1, FMAX_DUTY100);
1273 tmp64 = (uint64_t)speed * duty100;
1275 duty = (uint32_t)tmp64;
1277 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1279 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1281 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1284 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1287 struct amdgpu_device *adev = smu->adev;
1289 * crystal_clock_freq used for fan speed rpm calculation is
1290 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1292 uint32_t crystal_clock_freq = 2500;
1293 uint32_t tach_period;
1295 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1296 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1297 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1298 CG_TACH_CTRL, TARGET_PERIOD,
1301 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1304 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1307 struct amdgpu_device *adev = smu->adev;
1308 uint32_t duty100, duty;
1312 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1313 * detected via register retrieving. To workaround this, we will
1314 * report the fan speed as 0 PWM if user just requested such.
1316 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1317 && !smu->user_dpm_profile.fan_speed_pwm) {
1322 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1323 CG_FDO_CTRL1, FMAX_DUTY100);
1324 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1325 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1328 tmp64 = (uint64_t)duty * 255;
1329 do_div(tmp64, duty100);
1330 *speed = MIN((uint32_t)tmp64, 255);
1338 static int arcturus_get_fan_parameters(struct smu_context *smu)
1340 PPTable_t *pptable = smu->smu_table.driver_pptable;
1342 smu->fan_max_rpm = pptable->FanMaximumRpm;
1347 static int arcturus_get_power_limit(struct smu_context *smu,
1348 uint32_t *current_power_limit,
1349 uint32_t *default_power_limit,
1350 uint32_t *max_power_limit)
1352 struct smu_11_0_powerplay_table *powerplay_table =
1353 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1354 PPTable_t *pptable = smu->smu_table.driver_pptable;
1355 uint32_t power_limit, od_percent;
1357 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1358 /* the last hope to figure out the ppt limit */
1360 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1364 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1367 if (current_power_limit)
1368 *current_power_limit = power_limit;
1369 if (default_power_limit)
1370 *default_power_limit = power_limit;
1372 if (max_power_limit) {
1373 if (smu->od_enabled) {
1374 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1376 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1378 power_limit *= (100 + od_percent);
1382 *max_power_limit = power_limit;
1388 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1391 DpmActivityMonitorCoeffInt_t activity_monitor;
1392 static const char *title[] = {
1393 "PROFILE_INDEX(NAME)",
1397 "MinActiveFreqType",
1402 "PD_Data_error_coeff",
1403 "PD_Data_error_rate_coeff"};
1404 uint32_t i, size = 0;
1405 int16_t workload_type = 0;
1407 uint32_t smu_version;
1412 result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1416 if (smu_version >= 0x360d00)
1417 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1418 title[0], title[1], title[2], title[3], title[4], title[5],
1419 title[6], title[7], title[8], title[9], title[10]);
1421 size += sysfs_emit_at(buf, size, "%16s\n",
1424 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1426 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1427 * Not all profile modes are supported on arcturus.
1429 workload_type = smu_cmn_to_asic_specific_index(smu,
1430 CMN2ASIC_MAPPING_WORKLOAD,
1432 if (workload_type < 0)
1435 if (smu_version >= 0x360d00) {
1436 result = smu_cmn_update_table(smu,
1437 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1439 (void *)(&activity_monitor),
1442 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1447 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1448 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1450 if (smu_version >= 0x360d00) {
1451 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1455 activity_monitor.Gfx_FPS,
1456 activity_monitor.Gfx_UseRlcBusy,
1457 activity_monitor.Gfx_MinActiveFreqType,
1458 activity_monitor.Gfx_MinActiveFreq,
1459 activity_monitor.Gfx_BoosterFreqType,
1460 activity_monitor.Gfx_BoosterFreq,
1461 activity_monitor.Gfx_PD_Data_limit_c,
1462 activity_monitor.Gfx_PD_Data_error_coeff,
1463 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1465 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1469 activity_monitor.Mem_FPS,
1470 activity_monitor.Mem_UseRlcBusy,
1471 activity_monitor.Mem_MinActiveFreqType,
1472 activity_monitor.Mem_MinActiveFreq,
1473 activity_monitor.Mem_BoosterFreqType,
1474 activity_monitor.Mem_BoosterFreq,
1475 activity_monitor.Mem_PD_Data_limit_c,
1476 activity_monitor.Mem_PD_Data_error_coeff,
1477 activity_monitor.Mem_PD_Data_error_rate_coeff);
1484 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1488 DpmActivityMonitorCoeffInt_t activity_monitor;
1489 int workload_type = 0;
1490 uint32_t profile_mode = input[size];
1492 uint32_t smu_version;
1494 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1495 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1499 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1503 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1504 (smu_version >=0x360d00)) {
1505 ret = smu_cmn_update_table(smu,
1506 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1507 WORKLOAD_PPLIB_CUSTOM_BIT,
1508 (void *)(&activity_monitor),
1511 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1516 case 0: /* Gfxclk */
1517 activity_monitor.Gfx_FPS = input[1];
1518 activity_monitor.Gfx_UseRlcBusy = input[2];
1519 activity_monitor.Gfx_MinActiveFreqType = input[3];
1520 activity_monitor.Gfx_MinActiveFreq = input[4];
1521 activity_monitor.Gfx_BoosterFreqType = input[5];
1522 activity_monitor.Gfx_BoosterFreq = input[6];
1523 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1524 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1525 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1528 activity_monitor.Mem_FPS = input[1];
1529 activity_monitor.Mem_UseRlcBusy = input[2];
1530 activity_monitor.Mem_MinActiveFreqType = input[3];
1531 activity_monitor.Mem_MinActiveFreq = input[4];
1532 activity_monitor.Mem_BoosterFreqType = input[5];
1533 activity_monitor.Mem_BoosterFreq = input[6];
1534 activity_monitor.Mem_PD_Data_limit_c = input[7];
1535 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1536 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1540 ret = smu_cmn_update_table(smu,
1541 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1542 WORKLOAD_PPLIB_CUSTOM_BIT,
1543 (void *)(&activity_monitor),
1546 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1552 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1553 * Not all profile modes are supported on arcturus.
1555 workload_type = smu_cmn_to_asic_specific_index(smu,
1556 CMN2ASIC_MAPPING_WORKLOAD,
1558 if (workload_type < 0) {
1559 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1563 ret = smu_cmn_send_smc_msg_with_param(smu,
1564 SMU_MSG_SetWorkloadMask,
1568 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1572 smu->power_profile_mode = profile_mode;
1577 static int arcturus_set_performance_level(struct smu_context *smu,
1578 enum amd_dpm_forced_level level)
1580 uint32_t smu_version;
1583 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1585 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1590 case AMD_DPM_FORCED_LEVEL_HIGH:
1591 case AMD_DPM_FORCED_LEVEL_LOW:
1592 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1593 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1594 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1595 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1596 if ((smu_version >= 0x361200) &&
1597 (smu_version <= 0x361a00)) {
1598 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1599 "54.18 - 54.26(included) SMU firmwares\n");
1607 return smu_v11_0_set_performance_level(smu, level);
1610 static void arcturus_dump_pptable(struct smu_context *smu)
1612 struct smu_table_context *table_context = &smu->smu_table;
1613 PPTable_t *pptable = table_context->driver_pptable;
1616 dev_info(smu->adev->dev, "Dumped PPTable:\n");
1618 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1620 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1621 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1623 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1624 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1625 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1628 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1629 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1630 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1631 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1633 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1634 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1635 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1636 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1637 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1638 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1639 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1641 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1642 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1644 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1646 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1647 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1649 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1650 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1651 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1652 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1654 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1655 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1656 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1657 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1659 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1660 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1662 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1663 " .VoltageMode = 0x%02x\n"
1664 " .SnapToDiscrete = 0x%02x\n"
1665 " .NumDiscreteLevels = 0x%02x\n"
1666 " .padding = 0x%02x\n"
1667 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1668 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1669 " .SsFmin = 0x%04x\n"
1670 " .Padding_16 = 0x%04x\n",
1671 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1672 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1673 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1674 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1675 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1676 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1677 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1678 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1679 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1680 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1681 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1683 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1684 " .VoltageMode = 0x%02x\n"
1685 " .SnapToDiscrete = 0x%02x\n"
1686 " .NumDiscreteLevels = 0x%02x\n"
1687 " .padding = 0x%02x\n"
1688 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1689 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1690 " .SsFmin = 0x%04x\n"
1691 " .Padding_16 = 0x%04x\n",
1692 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1693 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1694 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1695 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1696 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1697 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1698 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1699 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1700 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1701 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1702 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1704 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1705 " .VoltageMode = 0x%02x\n"
1706 " .SnapToDiscrete = 0x%02x\n"
1707 " .NumDiscreteLevels = 0x%02x\n"
1708 " .padding = 0x%02x\n"
1709 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1710 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1711 " .SsFmin = 0x%04x\n"
1712 " .Padding_16 = 0x%04x\n",
1713 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1714 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1715 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1716 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1717 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1718 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1719 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1720 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1721 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1722 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1723 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1725 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1726 " .VoltageMode = 0x%02x\n"
1727 " .SnapToDiscrete = 0x%02x\n"
1728 " .NumDiscreteLevels = 0x%02x\n"
1729 " .padding = 0x%02x\n"
1730 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1731 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1732 " .SsFmin = 0x%04x\n"
1733 " .Padding_16 = 0x%04x\n",
1734 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1735 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1736 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1737 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1738 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1739 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1740 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1741 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1742 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1743 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1744 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1746 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1747 " .VoltageMode = 0x%02x\n"
1748 " .SnapToDiscrete = 0x%02x\n"
1749 " .NumDiscreteLevels = 0x%02x\n"
1750 " .padding = 0x%02x\n"
1751 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1752 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1753 " .SsFmin = 0x%04x\n"
1754 " .Padding_16 = 0x%04x\n",
1755 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1756 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1757 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1758 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1759 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1760 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1761 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1762 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1763 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1764 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1765 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1767 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1768 " .VoltageMode = 0x%02x\n"
1769 " .SnapToDiscrete = 0x%02x\n"
1770 " .NumDiscreteLevels = 0x%02x\n"
1771 " .padding = 0x%02x\n"
1772 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1773 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1774 " .SsFmin = 0x%04x\n"
1775 " .Padding_16 = 0x%04x\n",
1776 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1777 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1778 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1779 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1780 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1781 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1782 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1783 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1784 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1785 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1786 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1789 dev_info(smu->adev->dev, "FreqTableGfx\n");
1790 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1791 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1793 dev_info(smu->adev->dev, "FreqTableVclk\n");
1794 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1795 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1797 dev_info(smu->adev->dev, "FreqTableDclk\n");
1798 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1799 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1801 dev_info(smu->adev->dev, "FreqTableSocclk\n");
1802 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1803 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1805 dev_info(smu->adev->dev, "FreqTableUclk\n");
1806 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1807 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1809 dev_info(smu->adev->dev, "FreqTableFclk\n");
1810 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1811 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1813 dev_info(smu->adev->dev, "Mp0clkFreq\n");
1814 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1815 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1817 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1818 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1819 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1821 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1822 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1823 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1824 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1825 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1826 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1827 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1828 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1829 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1831 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1832 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1833 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1834 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1836 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1837 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1839 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1840 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1841 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1842 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1843 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1844 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1846 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1847 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1848 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1849 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1850 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1851 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1852 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1853 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1854 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1856 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1857 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1858 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1859 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1861 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1862 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1863 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1864 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1866 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1867 pptable->dBtcGbGfxPll.a,
1868 pptable->dBtcGbGfxPll.b,
1869 pptable->dBtcGbGfxPll.c);
1870 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1871 pptable->dBtcGbGfxAfll.a,
1872 pptable->dBtcGbGfxAfll.b,
1873 pptable->dBtcGbGfxAfll.c);
1874 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1875 pptable->dBtcGbSoc.a,
1876 pptable->dBtcGbSoc.b,
1877 pptable->dBtcGbSoc.c);
1879 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1880 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1881 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1882 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1883 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1884 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1886 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1887 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1888 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1889 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1890 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1891 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1892 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1893 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1895 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1896 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1898 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1899 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1900 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1901 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1903 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1904 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1905 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1906 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1908 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1909 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1911 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1912 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1913 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1914 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1915 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1917 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1918 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1919 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1920 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1921 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1922 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1923 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1924 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1926 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1927 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1928 pptable->ReservedEquation0.a,
1929 pptable->ReservedEquation0.b,
1930 pptable->ReservedEquation0.c);
1931 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1932 pptable->ReservedEquation1.a,
1933 pptable->ReservedEquation1.b,
1934 pptable->ReservedEquation1.c);
1935 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1936 pptable->ReservedEquation2.a,
1937 pptable->ReservedEquation2.b,
1938 pptable->ReservedEquation2.c);
1939 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1940 pptable->ReservedEquation3.a,
1941 pptable->ReservedEquation3.b,
1942 pptable->ReservedEquation3.c);
1944 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1945 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1947 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1948 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1949 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1951 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1952 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1954 dev_info(smu->adev->dev, "Board Parameters:\n");
1955 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1956 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1958 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1959 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1960 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1961 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1963 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1964 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1966 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1967 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1968 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1970 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1971 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1972 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1974 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1975 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1976 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1978 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1979 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1980 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1982 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1983 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1984 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1985 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1987 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1988 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1989 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1991 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1992 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1993 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1995 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1996 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1997 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1999 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
2000 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
2001 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
2003 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2004 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2005 dev_info(smu->adev->dev, " .Enabled = %d\n",
2006 pptable->I2cControllers[i].Enabled);
2007 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2008 pptable->I2cControllers[i].SlaveAddress);
2009 dev_info(smu->adev->dev, " .ControllerPort = %d\n",
2010 pptable->I2cControllers[i].ControllerPort);
2011 dev_info(smu->adev->dev, " .ControllerName = %d\n",
2012 pptable->I2cControllers[i].ControllerName);
2013 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",
2014 pptable->I2cControllers[i].ThermalThrotter);
2015 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",
2016 pptable->I2cControllers[i].I2cProtocol);
2017 dev_info(smu->adev->dev, " .Speed = %d\n",
2018 pptable->I2cControllers[i].Speed);
2021 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
2022 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
2024 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
2026 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2027 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2028 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2029 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2030 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2031 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2032 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2033 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2034 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2035 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2036 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2037 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2041 static bool arcturus_is_dpm_running(struct smu_context *smu)
2044 uint32_t feature_mask[2];
2045 uint64_t feature_enabled;
2047 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
2051 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
2053 return !!(feature_enabled & SMC_DPM_FEATURE);
2056 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
2061 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2062 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
2064 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
2069 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2070 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
2072 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
2081 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2082 struct i2c_msg *msg, int num_msgs)
2084 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2085 struct smu_table_context *smu_table = &adev->smu.smu_table;
2086 struct smu_table *table = &smu_table->driver_table;
2087 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2091 req = kzalloc(sizeof(*req), GFP_KERNEL);
2095 req->I2CcontrollerPort = 0;
2096 req->I2CSpeed = I2C_SPEED_FAST_400K;
2097 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2098 dir = msg[0].flags & I2C_M_RD;
2100 for (c = i = 0; i < num_msgs; i++) {
2101 for (j = 0; j < msg[i].len; j++, c++) {
2102 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2104 if (!(msg[i].flags & I2C_M_RD)) {
2106 cmd->Cmd = I2C_CMD_WRITE;
2107 cmd->RegisterAddr = msg[i].buf[j];
2110 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2111 /* The direction changes.
2113 dir = msg[i].flags & I2C_M_RD;
2114 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2120 * Insert STOP if we are at the last byte of either last
2121 * message for the transaction or the client explicitly
2122 * requires a STOP at this particular message.
2124 if ((j == msg[i].len - 1) &&
2125 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2126 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2127 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2131 mutex_lock(&adev->smu.mutex);
2132 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2133 mutex_unlock(&adev->smu.mutex);
2137 for (c = i = 0; i < num_msgs; i++) {
2138 if (!(msg[i].flags & I2C_M_RD)) {
2142 for (j = 0; j < msg[i].len; j++, c++) {
2143 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2145 msg[i].buf[j] = cmd->Data;
2154 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2156 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2160 static const struct i2c_algorithm arcturus_i2c_algo = {
2161 .master_xfer = arcturus_i2c_xfer,
2162 .functionality = arcturus_i2c_func,
2166 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2167 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2168 .max_read_len = MAX_SW_I2C_COMMANDS,
2169 .max_write_len = MAX_SW_I2C_COMMANDS,
2170 .max_comb_1st_msg_len = 2,
2171 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2174 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2176 struct amdgpu_device *adev = to_amdgpu_device(control);
2179 control->owner = THIS_MODULE;
2180 control->class = I2C_CLASS_HWMON;
2181 control->dev.parent = &adev->pdev->dev;
2182 control->algo = &arcturus_i2c_algo;
2183 control->quirks = &arcturus_i2c_control_quirks;
2184 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2186 res = i2c_add_adapter(control);
2188 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2193 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2195 i2c_del_adapter(control);
2198 static void arcturus_get_unique_id(struct smu_context *smu)
2200 struct amdgpu_device *adev = smu->adev;
2201 uint32_t top32 = 0, bottom32 = 0, smu_version;
2204 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2205 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2209 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2210 if (smu_version < 0x361700) {
2211 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2215 /* Get the SN to turn into a Unique ID */
2216 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2217 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2219 id = ((uint64_t)bottom32 << 32) | top32;
2220 adev->unique_id = id;
2221 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2222 * 16-digit HEX string for convenience and backwards-compatibility
2224 sprintf(adev->serial, "%llx", id);
2227 static int arcturus_set_df_cstate(struct smu_context *smu,
2228 enum pp_df_cstate state)
2230 uint32_t smu_version;
2233 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2235 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2239 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2240 if (smu_version < 0x360F00) {
2241 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2245 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2248 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2250 uint32_t smu_version;
2253 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2255 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2259 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2260 if (smu_version < 0x00361700) {
2261 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2266 return smu_cmn_send_smc_msg_with_param(smu,
2267 SMU_MSG_GmiPwrDnControl,
2271 return smu_cmn_send_smc_msg_with_param(smu,
2272 SMU_MSG_GmiPwrDnControl,
2277 static const struct throttling_logging_label {
2278 uint32_t feature_mask;
2280 } logging_label[] = {
2281 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2282 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2283 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2284 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2285 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2286 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2287 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2289 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2292 int throttler_idx, throtting_events = 0, buf_idx = 0;
2293 struct amdgpu_device *adev = smu->adev;
2294 uint32_t throttler_status;
2297 ret = arcturus_get_smu_metrics_data(smu,
2298 METRICS_THROTTLER_STATUS,
2303 memset(log_buf, 0, sizeof(log_buf));
2304 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2306 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2308 buf_idx += snprintf(log_buf + buf_idx,
2309 sizeof(log_buf) - buf_idx,
2311 throtting_events > 1 ? " and " : "",
2312 logging_label[throttler_idx].label);
2313 if (buf_idx >= sizeof(log_buf)) {
2314 dev_err(adev->dev, "buffer overflow!\n");
2315 log_buf[sizeof(log_buf) - 1] = '\0';
2321 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2323 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2324 smu_cmn_get_indep_throttler_status(throttler_status,
2325 arcturus_throttler_map));
2328 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2330 struct amdgpu_device *adev = smu->adev;
2333 /* TODO: confirm this on real target */
2334 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2335 if ((esm_ctrl >> 15) & 0x1FFFF)
2336 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2338 return smu_v11_0_get_current_pcie_link_speed(smu);
2341 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2344 struct smu_table_context *smu_table = &smu->smu_table;
2345 struct gpu_metrics_v1_3 *gpu_metrics =
2346 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2347 SmuMetrics_t metrics;
2350 ret = smu_cmn_get_metrics_table(smu,
2356 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2358 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2359 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2360 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2361 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2362 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2363 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2365 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2366 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2367 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2369 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2370 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2372 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2373 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2374 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2375 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2376 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2378 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2379 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2380 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2381 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2382 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2384 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2385 gpu_metrics->indep_throttle_status =
2386 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2387 arcturus_throttler_map);
2389 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2391 gpu_metrics->pcie_link_width =
2392 smu_v11_0_get_current_pcie_link_width(smu);
2393 gpu_metrics->pcie_link_speed =
2394 arcturus_get_current_pcie_link_speed(smu);
2396 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2398 *table = (void *)gpu_metrics;
2400 return sizeof(struct gpu_metrics_v1_3);
2403 static const struct pptable_funcs arcturus_ppt_funcs = {
2405 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2407 .run_btc = arcturus_run_btc,
2408 /* dpm/clk tables */
2409 .set_default_dpm_table = arcturus_set_default_dpm_table,
2410 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2411 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2412 .print_clk_levels = arcturus_print_clk_levels,
2413 .force_clk_levels = arcturus_force_clk_levels,
2414 .read_sensor = arcturus_read_sensor,
2415 .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2416 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2417 .get_power_profile_mode = arcturus_get_power_profile_mode,
2418 .set_power_profile_mode = arcturus_set_power_profile_mode,
2419 .set_performance_level = arcturus_set_performance_level,
2420 /* debug (internal used) */
2421 .dump_pptable = arcturus_dump_pptable,
2422 .get_power_limit = arcturus_get_power_limit,
2423 .is_dpm_running = arcturus_is_dpm_running,
2424 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2425 .i2c_init = arcturus_i2c_control_init,
2426 .i2c_fini = arcturus_i2c_control_fini,
2427 .get_unique_id = arcturus_get_unique_id,
2428 .init_microcode = smu_v11_0_init_microcode,
2429 .load_microcode = smu_v11_0_load_microcode,
2430 .fini_microcode = smu_v11_0_fini_microcode,
2431 .init_smc_tables = arcturus_init_smc_tables,
2432 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2433 .init_power = smu_v11_0_init_power,
2434 .fini_power = smu_v11_0_fini_power,
2435 .check_fw_status = smu_v11_0_check_fw_status,
2436 /* pptable related */
2437 .setup_pptable = arcturus_setup_pptable,
2438 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2439 .check_fw_version = smu_v11_0_check_fw_version,
2440 .write_pptable = smu_cmn_write_pptable,
2441 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2442 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2443 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2444 .system_features_control = smu_v11_0_system_features_control,
2445 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2446 .send_smc_msg = smu_cmn_send_smc_msg,
2447 .init_display_count = NULL,
2448 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2449 .get_enabled_mask = smu_cmn_get_enabled_mask,
2450 .feature_is_enabled = smu_cmn_feature_is_enabled,
2451 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2452 .notify_display_change = NULL,
2453 .set_power_limit = smu_v11_0_set_power_limit,
2454 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2455 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2456 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2457 .set_min_dcef_deep_sleep = NULL,
2458 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2459 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2460 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2461 .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2462 .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2463 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2464 .gfx_off_control = smu_v11_0_gfx_off_control,
2465 .register_irq_handler = smu_v11_0_register_irq_handler,
2466 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2467 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2468 .baco_is_support = smu_v11_0_baco_is_support,
2469 .baco_get_state = smu_v11_0_baco_get_state,
2470 .baco_set_state = smu_v11_0_baco_set_state,
2471 .baco_enter = smu_v11_0_baco_enter,
2472 .baco_exit = smu_v11_0_baco_exit,
2473 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2474 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2475 .set_df_cstate = arcturus_set_df_cstate,
2476 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2477 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2478 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2479 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2480 .get_gpu_metrics = arcturus_get_gpu_metrics,
2481 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2482 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2483 .get_fan_parameters = arcturus_get_fan_parameters,
2484 .interrupt_work = smu_v11_0_interrupt_work,
2485 .set_light_sbr = smu_v11_0_set_light_sbr,
2486 .set_mp1_state = smu_cmn_set_mp1_state,
2489 void arcturus_set_ppt_funcs(struct smu_context *smu)
2491 smu->ppt_funcs = &arcturus_ppt_funcs;
2492 smu->message_map = arcturus_message_map;
2493 smu->clock_map = arcturus_clk_map;
2494 smu->feature_map = arcturus_feature_mask_map;
2495 smu->table_map = arcturus_table_map;
2496 smu->pwr_src_map = arcturus_pwr_src_map;
2497 smu->workload_map = arcturus_workload_map;