drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  85         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  86         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  87         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  88         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  89         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  90         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  91         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  92         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  93         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  94         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  95         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  96         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  97         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  98         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  99         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 100         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 101         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 102         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 103         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 104         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 105         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 108         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 109         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 110         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 111         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 112         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 113         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 114         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 115         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 116         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 117         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 118         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 119         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 120         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 121         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 122         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 123         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 124         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 125         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 126         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 127         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 128         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 129         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 130         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 131         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 132         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 133         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 134         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 135         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 136         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 137         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 138         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 139         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 140         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 141         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 142         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 143         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 144         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 145         MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 146 };
 147
 148 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 149         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 150         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 151         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 152         CLK_MAP(FCLK, PPCLK_FCLK),
 153         CLK_MAP(UCLK, PPCLK_UCLK),
 154         CLK_MAP(MCLK, PPCLK_UCLK),
 155         CLK_MAP(DCLK, PPCLK_DCLK),
 156         CLK_MAP(VCLK, PPCLK_VCLK),
 157 };
 158
 159 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 160         FEA_MAP(DPM_PREFETCHER),
 161         FEA_MAP(DPM_GFXCLK),
 162         FEA_MAP(DPM_UCLK),
 163         FEA_MAP(DPM_SOCCLK),
 164         FEA_MAP(DPM_FCLK),
 165         FEA_MAP(DPM_MP0CLK),
 166         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 167         FEA_MAP(DS_GFXCLK),
 168         FEA_MAP(DS_SOCCLK),
 169         FEA_MAP(DS_LCLK),
 170         FEA_MAP(DS_FCLK),
 171         FEA_MAP(DS_UCLK),
 172         FEA_MAP(GFX_ULV),
 173         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 174         FEA_MAP(RSMU_SMN_CG),
 175         FEA_MAP(WAFL_CG),
 176         FEA_MAP(PPT),
 177         FEA_MAP(TDC),
 178         FEA_MAP(APCC_PLUS),
 179         FEA_MAP(VR0HOT),
 180         FEA_MAP(VR1HOT),
 181         FEA_MAP(FW_CTF),
 182         FEA_MAP(FAN_CONTROL),
 183         FEA_MAP(THERMAL),
 184         FEA_MAP(OUT_OF_BAND_MONITOR),
 185         FEA_MAP(TEMP_DEPENDENT_VMIN),
 186 };
 187
 188 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 189         TAB_MAP(PPTABLE),
 190         TAB_MAP(AVFS),
 191         TAB_MAP(AVFS_PSM_DEBUG),
 192         TAB_MAP(AVFS_FUSE_OVERRIDE),
 193         TAB_MAP(PMSTATUSLOG),
 194         TAB_MAP(SMU_METRICS),
 195         TAB_MAP(DRIVER_SMU_CONFIG),
 196         TAB_MAP(OVERDRIVE),
 197         TAB_MAP(I2C_COMMANDS),
 198         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 199 };
 200
 201 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 202         PWR_MAP(AC),
 203         PWR_MAP(DC),
 204 };
 205
 206 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 212 };
 213
 214 static int arcturus_tables_init(struct smu_context *smu)
 215 {
 216         struct smu_table_context *smu_table = &smu->smu_table;
 217         struct smu_table *tables = smu_table->tables;
 218
 219         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 220                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 221
 222         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 223                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 224
 225         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 226                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 227
 228         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 229                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 230
 231         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 232                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 233                        AMDGPU_GEM_DOMAIN_VRAM);
 234
 235         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 236         if (!smu_table->metrics_table)
 237                 return -ENOMEM;
 238         smu_table->metrics_time = 0;
 239
 240         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
 241         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 242         if (!smu_table->gpu_metrics_table) {
 243                 kfree(smu_table->metrics_table);
 244                 return -ENOMEM;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 251 {
 252         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 253
 254         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 255                                        GFP_KERNEL);
 256         if (!smu_dpm->dpm_context)
 257                 return -ENOMEM;
 258         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 259
 260         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 261                                        GFP_KERNEL);
 262         if (!smu_dpm->dpm_current_power_state)
 263                 return -ENOMEM;
 264
 265         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 266                                        GFP_KERNEL);
 267         if (!smu_dpm->dpm_request_power_state)
 268                 return -ENOMEM;
 269
 270         return 0;
 271 }
 272
 273 static int arcturus_init_smc_tables(struct smu_context *smu)
 274 {
 275         int ret = 0;
 276
 277         ret = arcturus_tables_init(smu);
 278         if (ret)
 279                 return ret;
 280
 281         ret = arcturus_allocate_dpm_context(smu);
 282         if (ret)
 283                 return ret;
 284
 285         return smu_v11_0_init_smc_tables(smu);
 286 }
 287
 288 static int
 289 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 290                                   uint32_t *feature_mask, uint32_t num)
 291 {
 292         if (num > 2)
 293                 return -EINVAL;
 294
 295         /* pptable will handle the features to enable */
 296         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 297
 298         return 0;
 299 }
 300
 301 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 302 {
 303         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 304         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 305         struct smu_11_0_dpm_table *dpm_table = NULL;
 306         int ret = 0;
 307
 308         /* socclk dpm table setup */
 309         dpm_table = &dpm_context->dpm_tables.soc_table;
 310         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 311                 ret = smu_v11_0_set_single_dpm_table(smu,
 312                                                      SMU_SOCCLK,
 313                                                      dpm_table);
 314                 if (ret)
 315                         return ret;
 316                 dpm_table->is_fine_grained =
 317                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 318         } else {
 319                 dpm_table->count = 1;
 320                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 321                 dpm_table->dpm_levels[0].enabled = true;
 322                 dpm_table->min = dpm_table->dpm_levels[0].value;
 323                 dpm_table->max = dpm_table->dpm_levels[0].value;
 324         }
 325
 326         /* gfxclk dpm table setup */
 327         dpm_table = &dpm_context->dpm_tables.gfx_table;
 328         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 329                 ret = smu_v11_0_set_single_dpm_table(smu,
 330                                                      SMU_GFXCLK,
 331                                                      dpm_table);
 332                 if (ret)
 333                         return ret;
 334                 dpm_table->is_fine_grained =
 335                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 336         } else {
 337                 dpm_table->count = 1;
 338                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 339                 dpm_table->dpm_levels[0].enabled = true;
 340                 dpm_table->min = dpm_table->dpm_levels[0].value;
 341                 dpm_table->max = dpm_table->dpm_levels[0].value;
 342         }
 343
 344         /* memclk dpm table setup */
 345         dpm_table = &dpm_context->dpm_tables.uclk_table;
 346         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 347                 ret = smu_v11_0_set_single_dpm_table(smu,
 348                                                      SMU_UCLK,
 349                                                      dpm_table);
 350                 if (ret)
 351                         return ret;
 352                 dpm_table->is_fine_grained =
 353                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 354         } else {
 355                 dpm_table->count = 1;
 356                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 357                 dpm_table->dpm_levels[0].enabled = true;
 358                 dpm_table->min = dpm_table->dpm_levels[0].value;
 359                 dpm_table->max = dpm_table->dpm_levels[0].value;
 360         }
 361
 362         /* fclk dpm table setup */
 363         dpm_table = &dpm_context->dpm_tables.fclk_table;
 364         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 365                 ret = smu_v11_0_set_single_dpm_table(smu,
 366                                                      SMU_FCLK,
 367                                                      dpm_table);
 368                 if (ret)
 369                         return ret;
 370                 dpm_table->is_fine_grained =
 371                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 372         } else {
 373                 dpm_table->count = 1;
 374                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 375                 dpm_table->dpm_levels[0].enabled = true;
 376                 dpm_table->min = dpm_table->dpm_levels[0].value;
 377                 dpm_table->max = dpm_table->dpm_levels[0].value;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int arcturus_check_powerplay_table(struct smu_context *smu)
 384 {
 385         struct smu_table_context *table_context = &smu->smu_table;
 386         struct smu_11_0_powerplay_table *powerplay_table =
 387                 table_context->power_play_table;
 388         struct smu_baco_context *smu_baco = &smu->smu_baco;
 389
 390         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 391             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 392                 smu_baco->platform_support = true;
 393
 394         table_context->thermal_controller_type =
 395                 powerplay_table->thermal_controller_type;
 396
 397         return 0;
 398 }
 399
 400 static int arcturus_store_powerplay_table(struct smu_context *smu)
 401 {
 402         struct smu_table_context *table_context = &smu->smu_table;
 403         struct smu_11_0_powerplay_table *powerplay_table =
 404                 table_context->power_play_table;
 405
 406         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 407                sizeof(PPTable_t));
 408
 409         return 0;
 410 }
 411
 412 static int arcturus_append_powerplay_table(struct smu_context *smu)
 413 {
 414         struct smu_table_context *table_context = &smu->smu_table;
 415         PPTable_t *smc_pptable = table_context->driver_pptable;
 416         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 417         int index, ret;
 418
 419         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 420                                            smc_dpm_info);
 421
 422         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 423                                       (uint8_t **)&smc_dpm_table);
 424         if (ret)
 425                 return ret;
 426
 427         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 428                         smc_dpm_table->table_header.format_revision,
 429                         smc_dpm_table->table_header.content_revision);
 430
 431         if ((smc_dpm_table->table_header.format_revision == 4) &&
 432             (smc_dpm_table->table_header.content_revision == 6))
 433                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 434                        &smc_dpm_table->maxvoltagestepgfx,
 435                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 436
 437         return 0;
 438 }
 439
 440 static int arcturus_setup_pptable(struct smu_context *smu)
 441 {
 442         int ret = 0;
 443
 444         ret = smu_v11_0_setup_pptable(smu);
 445         if (ret)
 446                 return ret;
 447
 448         ret = arcturus_store_powerplay_table(smu);
 449         if (ret)
 450                 return ret;
 451
 452         ret = arcturus_append_powerplay_table(smu);
 453         if (ret)
 454                 return ret;
 455
 456         ret = arcturus_check_powerplay_table(smu);
 457         if (ret)
 458                 return ret;
 459
 460         return ret;
 461 }
 462
 463 static int arcturus_run_btc(struct smu_context *smu)
 464 {
 465         int ret = 0;
 466
 467         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 468         if (ret) {
 469                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 470                 return ret;
 471         }
 472
 473         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 474 }
 475
 476 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 477 {
 478         struct smu_11_0_dpm_context *dpm_context =
 479                                 smu->smu_dpm.dpm_context;
 480         struct smu_11_0_dpm_table *gfx_table =
 481                                 &dpm_context->dpm_tables.gfx_table;
 482         struct smu_11_0_dpm_table *mem_table =
 483                                 &dpm_context->dpm_tables.uclk_table;
 484         struct smu_11_0_dpm_table *soc_table =
 485                                 &dpm_context->dpm_tables.soc_table;
 486         struct smu_umd_pstate_table *pstate_table =
 487                                 &smu->pstate_table;
 488
 489         pstate_table->gfxclk_pstate.min = gfx_table->min;
 490         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 491
 492         pstate_table->uclk_pstate.min = mem_table->min;
 493         pstate_table->uclk_pstate.peak = mem_table->max;
 494
 495         pstate_table->socclk_pstate.min = soc_table->min;
 496         pstate_table->socclk_pstate.peak = soc_table->max;
 497
 498         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 499             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 500             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 501                 pstate_table->gfxclk_pstate.standard =
 502                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 503                 pstate_table->uclk_pstate.standard =
 504                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 505                 pstate_table->socclk_pstate.standard =
 506                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 507         } else {
 508                 pstate_table->gfxclk_pstate.standard =
 509                         pstate_table->gfxclk_pstate.min;
 510                 pstate_table->uclk_pstate.standard =
 511                         pstate_table->uclk_pstate.min;
 512                 pstate_table->socclk_pstate.standard =
 513                         pstate_table->socclk_pstate.min;
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int arcturus_get_clk_table(struct smu_context *smu,
 520                         struct pp_clock_levels_with_latency *clocks,
 521                         struct smu_11_0_dpm_table *dpm_table)
 522 {
 523         int i, count;
 524
 525         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 526         clocks->num_levels = count;
 527
 528         for (i = 0; i < count; i++) {
 529                 clocks->data[i].clocks_in_khz =
 530                         dpm_table->dpm_levels[i].value * 1000;
 531                 clocks->data[i].latency_in_us = 0;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int arcturus_freqs_in_same_level(int32_t frequency1,
 538                                         int32_t frequency2)
 539 {
 540         return (abs(frequency1 - frequency2) <= EPSILON);
 541 }
 542
 543 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 544                                          MetricsMember_t member,
 545                                          uint32_t *value)
 546 {
 547         struct smu_table_context *smu_table= &smu->smu_table;
 548         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 549         int ret = 0;
 550
 551         mutex_lock(&smu->metrics_lock);
 552
 553         ret = smu_cmn_get_metrics_table_locked(smu,
 554                                                NULL,
 555                                                false);
 556         if (ret) {
 557                 mutex_unlock(&smu->metrics_lock);
 558                 return ret;
 559         }
 560
 561         switch (member) {
 562         case METRICS_CURR_GFXCLK:
 563                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 564                 break;
 565         case METRICS_CURR_SOCCLK:
 566                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 567                 break;
 568         case METRICS_CURR_UCLK:
 569                 *value = metrics->CurrClock[PPCLK_UCLK];
 570                 break;
 571         case METRICS_CURR_VCLK:
 572                 *value = metrics->CurrClock[PPCLK_VCLK];
 573                 break;
 574         case METRICS_CURR_DCLK:
 575                 *value = metrics->CurrClock[PPCLK_DCLK];
 576                 break;
 577         case METRICS_CURR_FCLK:
 578                 *value = metrics->CurrClock[PPCLK_FCLK];
 579                 break;
 580         case METRICS_AVERAGE_GFXCLK:
 581                 *value = metrics->AverageGfxclkFrequency;
 582                 break;
 583         case METRICS_AVERAGE_SOCCLK:
 584                 *value = metrics->AverageSocclkFrequency;
 585                 break;
 586         case METRICS_AVERAGE_UCLK:
 587                 *value = metrics->AverageUclkFrequency;
 588                 break;
 589         case METRICS_AVERAGE_VCLK:
 590                 *value = metrics->AverageVclkFrequency;
 591                 break;
 592         case METRICS_AVERAGE_DCLK:
 593                 *value = metrics->AverageDclkFrequency;
 594                 break;
 595         case METRICS_AVERAGE_GFXACTIVITY:
 596                 *value = metrics->AverageGfxActivity;
 597                 break;
 598         case METRICS_AVERAGE_MEMACTIVITY:
 599                 *value = metrics->AverageUclkActivity;
 600                 break;
 601         case METRICS_AVERAGE_VCNACTIVITY:
 602                 *value = metrics->VcnActivityPercentage;
 603                 break;
 604         case METRICS_AVERAGE_SOCKETPOWER:
 605                 *value = metrics->AverageSocketPower << 8;
 606                 break;
 607         case METRICS_TEMPERATURE_EDGE:
 608                 *value = metrics->TemperatureEdge *
 609                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 610                 break;
 611         case METRICS_TEMPERATURE_HOTSPOT:
 612                 *value = metrics->TemperatureHotspot *
 613                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 614                 break;
 615         case METRICS_TEMPERATURE_MEM:
 616                 *value = metrics->TemperatureHBM *
 617                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 618                 break;
 619         case METRICS_TEMPERATURE_VRGFX:
 620                 *value = metrics->TemperatureVrGfx *
 621                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 622                 break;
 623         case METRICS_TEMPERATURE_VRSOC:
 624                 *value = metrics->TemperatureVrSoc *
 625                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 626                 break;
 627         case METRICS_TEMPERATURE_VRMEM:
 628                 *value = metrics->TemperatureVrMem *
 629                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 630                 break;
 631         case METRICS_THROTTLER_STATUS:
 632                 *value = metrics->ThrottlerStatus;
 633                 break;
 634         case METRICS_CURR_FANSPEED:
 635                 *value = metrics->CurrFanSpeed;
 636                 break;
 637         default:
 638                 *value = UINT_MAX;
 639                 break;
 640         }
 641
 642         mutex_unlock(&smu->metrics_lock);
 643
 644         return ret;
 645 }
 646
 647 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 648                                        enum smu_clk_type clk_type,
 649                                        uint32_t *value)
 650 {
 651         MetricsMember_t member_type;
 652         int clk_id = 0;
 653
 654         if (!value)
 655                 return -EINVAL;
 656
 657         clk_id = smu_cmn_to_asic_specific_index(smu,
 658                                                 CMN2ASIC_MAPPING_CLK,
 659                                                 clk_type);
 660         if (clk_id < 0)
 661                 return -EINVAL;
 662
 663         switch (clk_id) {
 664         case PPCLK_GFXCLK:
 665                 /*
 666                  * CurrClock[clk_id] can provide accurate
 667                  *   output only when the dpm feature is enabled.
 668                  * We can use Average_* for dpm disabled case.
 669                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 670                  */
 671                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 672                         member_type = METRICS_CURR_GFXCLK;
 673                 else
 674                         member_type = METRICS_AVERAGE_GFXCLK;
 675                 break;
 676         case PPCLK_UCLK:
 677                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 678                         member_type = METRICS_CURR_UCLK;
 679                 else
 680                         member_type = METRICS_AVERAGE_UCLK;
 681                 break;
 682         case PPCLK_SOCCLK:
 683                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 684                         member_type = METRICS_CURR_SOCCLK;
 685                 else
 686                         member_type = METRICS_AVERAGE_SOCCLK;
 687                 break;
 688         case PPCLK_VCLK:
 689                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 690                         member_type = METRICS_CURR_VCLK;
 691                 else
 692                         member_type = METRICS_AVERAGE_VCLK;
 693                 break;
 694         case PPCLK_DCLK:
 695                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 696                         member_type = METRICS_CURR_DCLK;
 697                 else
 698                         member_type = METRICS_AVERAGE_DCLK;
 699                 break;
 700         case PPCLK_FCLK:
 701                 member_type = METRICS_CURR_FCLK;
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         return arcturus_get_smu_metrics_data(smu,
 708                                              member_type,
 709                                              value);
 710 }
 711
 712 static int arcturus_print_clk_levels(struct smu_context *smu,
 713                         enum smu_clk_type type, char *buf)
 714 {
 715         int i, now, size = 0;
 716         int ret = 0;
 717         struct pp_clock_levels_with_latency clocks;
 718         struct smu_11_0_dpm_table *single_dpm_table;
 719         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 720         struct smu_11_0_dpm_context *dpm_context = NULL;
 721         uint32_t gen_speed, lane_width;
 722
 723         if (amdgpu_ras_intr_triggered())
 724                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 725
 726         dpm_context = smu_dpm->dpm_context;
 727
 728         switch (type) {
 729         case SMU_SCLK:
 730                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 731                 if (ret) {
 732                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 733                         return ret;
 734                 }
 735
 736                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 737                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 738                 if (ret) {
 739                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 740                         return ret;
 741                 }
 742
 743                 /*
 744                  * For DPM disabled case, there will be only one clock level.
 745                  * And it's safe to assume that is always the current clock.
 746                  */
 747                 for (i = 0; i < clocks.num_levels; i++)
 748                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 749                                         clocks.data[i].clocks_in_khz / 1000,
 750                                         (clocks.num_levels == 1) ? "*" :
 751                                         (arcturus_freqs_in_same_level(
 752                                         clocks.data[i].clocks_in_khz / 1000,
 753                                         now) ? "*" : ""));
 754                 break;
 755
 756         case SMU_MCLK:
 757                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 758                 if (ret) {
 759                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 760                         return ret;
 761                 }
 762
 763                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 764                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 765                 if (ret) {
 766                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 767                         return ret;
 768                 }
 769
 770                 for (i = 0; i < clocks.num_levels; i++)
 771                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 772                                 i, clocks.data[i].clocks_in_khz / 1000,
 773                                 (clocks.num_levels == 1) ? "*" :
 774                                 (arcturus_freqs_in_same_level(
 775                                 clocks.data[i].clocks_in_khz / 1000,
 776                                 now) ? "*" : ""));
 777                 break;
 778
 779         case SMU_SOCCLK:
 780                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 781                 if (ret) {
 782                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 783                         return ret;
 784                 }
 785
 786                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 787                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 788                 if (ret) {
 789                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 790                         return ret;
 791                 }
 792
 793                 for (i = 0; i < clocks.num_levels; i++)
 794                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 795                                 i, clocks.data[i].clocks_in_khz / 1000,
 796                                 (clocks.num_levels == 1) ? "*" :
 797                                 (arcturus_freqs_in_same_level(
 798                                 clocks.data[i].clocks_in_khz / 1000,
 799                                 now) ? "*" : ""));
 800                 break;
 801
 802         case SMU_FCLK:
 803                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 804                 if (ret) {
 805                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 806                         return ret;
 807                 }
 808
 809                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 810                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 811                 if (ret) {
 812                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 813                         return ret;
 814                 }
 815
 816                 for (i = 0; i < single_dpm_table->count; i++)
 817                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 818                                 i, single_dpm_table->dpm_levels[i].value,
 819                                 (clocks.num_levels == 1) ? "*" :
 820                                 (arcturus_freqs_in_same_level(
 821                                 clocks.data[i].clocks_in_khz / 1000,
 822                                 now) ? "*" : ""));
 823                 break;
 824
 825         case SMU_PCIE:
 826                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 827                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 828                 size += sprintf(buf + size, "0: %s %s %dMhz *\n",
 829                                 (gen_speed == 0) ? "2.5GT/s," :
 830                                 (gen_speed == 1) ? "5.0GT/s," :
 831                                 (gen_speed == 2) ? "8.0GT/s," :
 832                                 (gen_speed == 3) ? "16.0GT/s," : "",
 833                                 (lane_width == 1) ? "x1" :
 834                                 (lane_width == 2) ? "x2" :
 835                                 (lane_width == 3) ? "x4" :
 836                                 (lane_width == 4) ? "x8" :
 837                                 (lane_width == 5) ? "x12" :
 838                                 (lane_width == 6) ? "x16" : "",
 839                                 smu->smu_table.boot_values.lclk / 100);
 840                 break;
 841
 842         default:
 843                 break;
 844         }
 845
 846         return size;
 847 }
 848
 849 static int arcturus_upload_dpm_level(struct smu_context *smu,
 850                                      bool max,
 851                                      uint32_t feature_mask,
 852                                      uint32_t level)
 853 {
 854         struct smu_11_0_dpm_context *dpm_context =
 855                         smu->smu_dpm.dpm_context;
 856         uint32_t freq;
 857         int ret = 0;
 858
 859         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 860             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 861                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 862                 ret = smu_cmn_send_smc_msg_with_param(smu,
 863                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 864                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 865                         NULL);
 866                 if (ret) {
 867                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 868                                                 max ? "max" : "min");
 869                         return ret;
 870                 }
 871         }
 872
 873         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 874             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 875                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 876                 ret = smu_cmn_send_smc_msg_with_param(smu,
 877                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 878                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 879                         NULL);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 882                                                 max ? "max" : "min");
 883                         return ret;
 884                 }
 885         }
 886
 887         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 888             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 889                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 890                 ret = smu_cmn_send_smc_msg_with_param(smu,
 891                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 892                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 893                         NULL);
 894                 if (ret) {
 895                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 896                                                 max ? "max" : "min");
 897                         return ret;
 898                 }
 899         }
 900
 901         return ret;
 902 }
 903
 904 static int arcturus_force_clk_levels(struct smu_context *smu,
 905                         enum smu_clk_type type, uint32_t mask)
 906 {
 907         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 908         struct smu_11_0_dpm_table *single_dpm_table = NULL;
 909         uint32_t soft_min_level, soft_max_level;
 910         uint32_t smu_version;
 911         int ret = 0;
 912
 913         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 914         if (ret) {
 915                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 916                 return ret;
 917         }
 918
 919         if ((smu_version >= 0x361200) &&
 920             (smu_version <= 0x361a00)) {
 921                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
 922                        "54.18 - 54.26(included) SMU firmwares\n");
 923                 return -EOPNOTSUPP;
 924         }
 925
 926         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 927         soft_max_level = mask ? (fls(mask) - 1) : 0;
 928
 929         switch (type) {
 930         case SMU_SCLK:
 931                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 932                 if (soft_max_level >= single_dpm_table->count) {
 933                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 934                                         soft_max_level, single_dpm_table->count - 1);
 935                         ret = -EINVAL;
 936                         break;
 937                 }
 938
 939                 ret = arcturus_upload_dpm_level(smu,
 940                                                 false,
 941                                                 FEATURE_DPM_GFXCLK_MASK,
 942                                                 soft_min_level);
 943                 if (ret) {
 944                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 945                         break;
 946                 }
 947
 948                 ret = arcturus_upload_dpm_level(smu,
 949                                                 true,
 950                                                 FEATURE_DPM_GFXCLK_MASK,
 951                                                 soft_max_level);
 952                 if (ret)
 953                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 954
 955                 break;
 956
 957         case SMU_MCLK:
 958         case SMU_SOCCLK:
 959         case SMU_FCLK:
 960                 /*
 961                  * Should not arrive here since Arcturus does not
 962                  * support mclk/socclk/fclk softmin/softmax settings
 963                  */
 964                 ret = -EINVAL;
 965                 break;
 966
 967         default:
 968                 break;
 969         }
 970
 971         return ret;
 972 }
 973
 974 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 975                                                 struct smu_temperature_range *range)
 976 {
 977         struct smu_table_context *table_context = &smu->smu_table;
 978         struct smu_11_0_powerplay_table *powerplay_table =
 979                                 table_context->power_play_table;
 980         PPTable_t *pptable = smu->smu_table.driver_pptable;
 981
 982         if (!range)
 983                 return -EINVAL;
 984
 985         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
 986
 987         range->max = pptable->TedgeLimit *
 988                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 989         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 990                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 991         range->hotspot_crit_max = pptable->ThotspotLimit *
 992                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 993         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 994                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 995         range->mem_crit_max = pptable->TmemLimit *
 996                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 997         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
 998                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 999         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1000
1001         return 0;
1002 }
1003
1004 static int arcturus_read_sensor(struct smu_context *smu,
1005                                 enum amd_pp_sensors sensor,
1006                                 void *data, uint32_t *size)
1007 {
1008         struct smu_table_context *table_context = &smu->smu_table;
1009         PPTable_t *pptable = table_context->driver_pptable;
1010         int ret = 0;
1011
1012         if (amdgpu_ras_intr_triggered())
1013                 return 0;
1014
1015         if (!data || !size)
1016                 return -EINVAL;
1017
1018         mutex_lock(&smu->sensor_lock);
1019         switch (sensor) {
1020         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1021                 *(uint32_t *)data = pptable->FanMaximumRpm;
1022                 *size = 4;
1023                 break;
1024         case AMDGPU_PP_SENSOR_MEM_LOAD:
1025                 ret = arcturus_get_smu_metrics_data(smu,
1026                                                     METRICS_AVERAGE_MEMACTIVITY,
1027                                                     (uint32_t *)data);
1028                 *size = 4;
1029                 break;
1030         case AMDGPU_PP_SENSOR_GPU_LOAD:
1031                 ret = arcturus_get_smu_metrics_data(smu,
1032                                                     METRICS_AVERAGE_GFXACTIVITY,
1033                                                     (uint32_t *)data);
1034                 *size = 4;
1035                 break;
1036         case AMDGPU_PP_SENSOR_GPU_POWER:
1037                 ret = arcturus_get_smu_metrics_data(smu,
1038                                                     METRICS_AVERAGE_SOCKETPOWER,
1039                                                     (uint32_t *)data);
1040                 *size = 4;
1041                 break;
1042         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1043                 ret = arcturus_get_smu_metrics_data(smu,
1044                                                     METRICS_TEMPERATURE_HOTSPOT,
1045                                                     (uint32_t *)data);
1046                 *size = 4;
1047                 break;
1048         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1049                 ret = arcturus_get_smu_metrics_data(smu,
1050                                                     METRICS_TEMPERATURE_EDGE,
1051                                                     (uint32_t *)data);
1052                 *size = 4;
1053                 break;
1054         case AMDGPU_PP_SENSOR_MEM_TEMP:
1055                 ret = arcturus_get_smu_metrics_data(smu,
1056                                                     METRICS_TEMPERATURE_MEM,
1057                                                     (uint32_t *)data);
1058                 *size = 4;
1059                 break;
1060         case AMDGPU_PP_SENSOR_GFX_MCLK:
1061                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1062                 /* the output clock frequency in 10K unit */
1063                 *(uint32_t *)data *= 100;
1064                 *size = 4;
1065                 break;
1066         case AMDGPU_PP_SENSOR_GFX_SCLK:
1067                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1068                 *(uint32_t *)data *= 100;
1069                 *size = 4;
1070                 break;
1071         case AMDGPU_PP_SENSOR_VDDGFX:
1072                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1073                 *size = 4;
1074                 break;
1075         default:
1076                 ret = -EOPNOTSUPP;
1077                 break;
1078         }
1079         mutex_unlock(&smu->sensor_lock);
1080
1081         return ret;
1082 }
1083
1084 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1085                                           uint32_t *speed)
1086 {
1087         int ret;
1088         u32 rpm;
1089
1090         if (!speed)
1091                 return -EINVAL;
1092
1093         switch (smu_v11_0_get_fan_control_mode(smu)) {
1094         case AMD_FAN_CTRL_AUTO:
1095                 ret = arcturus_get_smu_metrics_data(smu,
1096                                                     METRICS_CURR_FANSPEED,
1097                                                     &rpm);
1098                 if (!ret && smu->fan_max_rpm)
1099                         *speed = rpm * 100 / smu->fan_max_rpm;
1100                 return ret;
1101         default:
1102                 *speed = smu->user_dpm_profile.fan_speed_percent;
1103                 return 0;
1104         }
1105 }
1106
1107 static int arcturus_get_fan_parameters(struct smu_context *smu)
1108 {
1109         PPTable_t *pptable = smu->smu_table.driver_pptable;
1110
1111         smu->fan_max_rpm = pptable->FanMaximumRpm;
1112
1113         return 0;
1114 }
1115
1116 static int arcturus_get_power_limit(struct smu_context *smu)
1117 {
1118         struct smu_11_0_powerplay_table *powerplay_table =
1119                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1120         PPTable_t *pptable = smu->smu_table.driver_pptable;
1121         uint32_t power_limit, od_percent;
1122
1123         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1124                 /* the last hope to figure out the ppt limit */
1125                 if (!pptable) {
1126                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1127                         return -EINVAL;
1128                 }
1129                 power_limit =
1130                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1131         }
1132         smu->current_power_limit = smu->default_power_limit = power_limit;
1133
1134         if (smu->od_enabled) {
1135                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1136
1137                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1138
1139                 power_limit *= (100 + od_percent);
1140                 power_limit /= 100;
1141         }
1142         smu->max_power_limit = power_limit;
1143
1144         return 0;
1145 }
1146
1147 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1148                                            char *buf)
1149 {
1150         DpmActivityMonitorCoeffInt_t activity_monitor;
1151         static const char *profile_name[] = {
1152                                         "BOOTUP_DEFAULT",
1153                                         "3D_FULL_SCREEN",
1154                                         "POWER_SAVING",
1155                                         "VIDEO",
1156                                         "VR",
1157                                         "COMPUTE",
1158                                         "CUSTOM"};
1159         static const char *title[] = {
1160                         "PROFILE_INDEX(NAME)",
1161                         "CLOCK_TYPE(NAME)",
1162                         "FPS",
1163                         "UseRlcBusy",
1164                         "MinActiveFreqType",
1165                         "MinActiveFreq",
1166                         "BoosterFreqType",
1167                         "BoosterFreq",
1168                         "PD_Data_limit_c",
1169                         "PD_Data_error_coeff",
1170                         "PD_Data_error_rate_coeff"};
1171         uint32_t i, size = 0;
1172         int16_t workload_type = 0;
1173         int result = 0;
1174         uint32_t smu_version;
1175
1176         if (!buf)
1177                 return -EINVAL;
1178
1179         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1180         if (result)
1181                 return result;
1182
1183         if (smu_version >= 0x360d00)
1184                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1185                         title[0], title[1], title[2], title[3], title[4], title[5],
1186                         title[6], title[7], title[8], title[9], title[10]);
1187         else
1188                 size += sprintf(buf + size, "%16s\n",
1189                         title[0]);
1190
1191         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1192                 /*
1193                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1194                  * Not all profile modes are supported on arcturus.
1195                  */
1196                 workload_type = smu_cmn_to_asic_specific_index(smu,
1197                                                                CMN2ASIC_MAPPING_WORKLOAD,
1198                                                                i);
1199                 if (workload_type < 0)
1200                         continue;
1201
1202                 if (smu_version >= 0x360d00) {
1203                         result = smu_cmn_update_table(smu,
1204                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1205                                                   workload_type,
1206                                                   (void *)(&activity_monitor),
1207                                                   false);
1208                         if (result) {
1209                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1210                                 return result;
1211                         }
1212                 }
1213
1214                 size += sprintf(buf + size, "%2d %14s%s\n",
1215                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1216
1217                 if (smu_version >= 0x360d00) {
1218                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1219                                 " ",
1220                                 0,
1221                                 "GFXCLK",
1222                                 activity_monitor.Gfx_FPS,
1223                                 activity_monitor.Gfx_UseRlcBusy,
1224                                 activity_monitor.Gfx_MinActiveFreqType,
1225                                 activity_monitor.Gfx_MinActiveFreq,
1226                                 activity_monitor.Gfx_BoosterFreqType,
1227                                 activity_monitor.Gfx_BoosterFreq,
1228                                 activity_monitor.Gfx_PD_Data_limit_c,
1229                                 activity_monitor.Gfx_PD_Data_error_coeff,
1230                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1231
1232                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1233                                 " ",
1234                                 1,
1235                                 "UCLK",
1236                                 activity_monitor.Mem_FPS,
1237                                 activity_monitor.Mem_UseRlcBusy,
1238                                 activity_monitor.Mem_MinActiveFreqType,
1239                                 activity_monitor.Mem_MinActiveFreq,
1240                                 activity_monitor.Mem_BoosterFreqType,
1241                                 activity_monitor.Mem_BoosterFreq,
1242                                 activity_monitor.Mem_PD_Data_limit_c,
1243                                 activity_monitor.Mem_PD_Data_error_coeff,
1244                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1245                 }
1246         }
1247
1248         return size;
1249 }
1250
1251 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1252                                            long *input,
1253                                            uint32_t size)
1254 {
1255         DpmActivityMonitorCoeffInt_t activity_monitor;
1256         int workload_type = 0;
1257         uint32_t profile_mode = input[size];
1258         int ret = 0;
1259         uint32_t smu_version;
1260
1261         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1262                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1263                 return -EINVAL;
1264         }
1265
1266         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1267         if (ret)
1268                 return ret;
1269
1270         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1271              (smu_version >=0x360d00)) {
1272                 ret = smu_cmn_update_table(smu,
1273                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1274                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1275                                        (void *)(&activity_monitor),
1276                                        false);
1277                 if (ret) {
1278                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1279                         return ret;
1280                 }
1281
1282                 switch (input[0]) {
1283                 case 0: /* Gfxclk */
1284                         activity_monitor.Gfx_FPS = input[1];
1285                         activity_monitor.Gfx_UseRlcBusy = input[2];
1286                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1287                         activity_monitor.Gfx_MinActiveFreq = input[4];
1288                         activity_monitor.Gfx_BoosterFreqType = input[5];
1289                         activity_monitor.Gfx_BoosterFreq = input[6];
1290                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1291                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1292                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1293                         break;
1294                 case 1: /* Uclk */
1295                         activity_monitor.Mem_FPS = input[1];
1296                         activity_monitor.Mem_UseRlcBusy = input[2];
1297                         activity_monitor.Mem_MinActiveFreqType = input[3];
1298                         activity_monitor.Mem_MinActiveFreq = input[4];
1299                         activity_monitor.Mem_BoosterFreqType = input[5];
1300                         activity_monitor.Mem_BoosterFreq = input[6];
1301                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1302                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1303                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1304                         break;
1305                 }
1306
1307                 ret = smu_cmn_update_table(smu,
1308                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1309                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1310                                        (void *)(&activity_monitor),
1311                                        true);
1312                 if (ret) {
1313                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1314                         return ret;
1315                 }
1316         }
1317
1318         /*
1319          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1320          * Not all profile modes are supported on arcturus.
1321          */
1322         workload_type = smu_cmn_to_asic_specific_index(smu,
1323                                                        CMN2ASIC_MAPPING_WORKLOAD,
1324                                                        profile_mode);
1325         if (workload_type < 0) {
1326                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1327                 return -EINVAL;
1328         }
1329
1330         ret = smu_cmn_send_smc_msg_with_param(smu,
1331                                           SMU_MSG_SetWorkloadMask,
1332                                           1 << workload_type,
1333                                           NULL);
1334         if (ret) {
1335                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1336                 return ret;
1337         }
1338
1339         smu->power_profile_mode = profile_mode;
1340
1341         return 0;
1342 }
1343
1344 static int arcturus_set_performance_level(struct smu_context *smu,
1345                                           enum amd_dpm_forced_level level)
1346 {
1347         uint32_t smu_version;
1348         int ret;
1349
1350         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1351         if (ret) {
1352                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1353                 return ret;
1354         }
1355
1356         switch (level) {
1357         case AMD_DPM_FORCED_LEVEL_HIGH:
1358         case AMD_DPM_FORCED_LEVEL_LOW:
1359         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1360         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1361         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1362         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1363                 if ((smu_version >= 0x361200) &&
1364                     (smu_version <= 0x361a00)) {
1365                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1366                                "54.18 - 54.26(included) SMU firmwares\n");
1367                         return -EOPNOTSUPP;
1368                 }
1369                 break;
1370         default:
1371                 break;
1372         }
1373
1374         return smu_v11_0_set_performance_level(smu, level);
1375 }
1376
1377 static void arcturus_dump_pptable(struct smu_context *smu)
1378 {
1379         struct smu_table_context *table_context = &smu->smu_table;
1380         PPTable_t *pptable = table_context->driver_pptable;
1381         int i;
1382
1383         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1384
1385         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1386
1387         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1388         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1389
1390         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1391                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1392                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1393         }
1394
1395         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1396         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1397         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1398         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1399
1400         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1401         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1402         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1403         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1404         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1405         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1406         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1407
1408         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1409         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1410
1411         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1412
1413         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1414         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1415
1416         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1417         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1418         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1419         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1420
1421         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1422         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1423         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1424         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1425
1426         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1427         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1428
1429         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1430                         "  .VoltageMode          = 0x%02x\n"
1431                         "  .SnapToDiscrete       = 0x%02x\n"
1432                         "  .NumDiscreteLevels    = 0x%02x\n"
1433                         "  .padding              = 0x%02x\n"
1434                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1435                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1436                         "  .SsFmin               = 0x%04x\n"
1437                         "  .Padding_16           = 0x%04x\n",
1438                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1439                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1440                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1441                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1442                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1443                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1444                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1445                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1446                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1447                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1448                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1449
1450         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1451                         "  .VoltageMode          = 0x%02x\n"
1452                         "  .SnapToDiscrete       = 0x%02x\n"
1453                         "  .NumDiscreteLevels    = 0x%02x\n"
1454                         "  .padding              = 0x%02x\n"
1455                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1456                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1457                         "  .SsFmin               = 0x%04x\n"
1458                         "  .Padding_16           = 0x%04x\n",
1459                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1460                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1461                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1462                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1463                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1464                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1465                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1466                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1467                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1468                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1469                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1470
1471         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1472                         "  .VoltageMode          = 0x%02x\n"
1473                         "  .SnapToDiscrete       = 0x%02x\n"
1474                         "  .NumDiscreteLevels    = 0x%02x\n"
1475                         "  .padding              = 0x%02x\n"
1476                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1477                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1478                         "  .SsFmin               = 0x%04x\n"
1479                         "  .Padding_16           = 0x%04x\n",
1480                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1481                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1482                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1483                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1484                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1485                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1486                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1487                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1488                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1489                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1490                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1491
1492         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1493                         "  .VoltageMode          = 0x%02x\n"
1494                         "  .SnapToDiscrete       = 0x%02x\n"
1495                         "  .NumDiscreteLevels    = 0x%02x\n"
1496                         "  .padding              = 0x%02x\n"
1497                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1498                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1499                         "  .SsFmin               = 0x%04x\n"
1500                         "  .Padding_16           = 0x%04x\n",
1501                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1502                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1503                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1504                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1505                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1506                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1507                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1508                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1509                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1510                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1511                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1512
1513         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1514                         "  .VoltageMode          = 0x%02x\n"
1515                         "  .SnapToDiscrete       = 0x%02x\n"
1516                         "  .NumDiscreteLevels    = 0x%02x\n"
1517                         "  .padding              = 0x%02x\n"
1518                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1519                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1520                         "  .SsFmin               = 0x%04x\n"
1521                         "  .Padding_16           = 0x%04x\n",
1522                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1523                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1524                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1525                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1526                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1527                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1528                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1529                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1530                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1531                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1532                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1533
1534         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1535                         "  .VoltageMode          = 0x%02x\n"
1536                         "  .SnapToDiscrete       = 0x%02x\n"
1537                         "  .NumDiscreteLevels    = 0x%02x\n"
1538                         "  .padding              = 0x%02x\n"
1539                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1540                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1541                         "  .SsFmin               = 0x%04x\n"
1542                         "  .Padding_16           = 0x%04x\n",
1543                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1544                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1545                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1546                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1547                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1548                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1549                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1550                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1551                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1552                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1553                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1554
1555
1556         dev_info(smu->adev->dev, "FreqTableGfx\n");
1557         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1558                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1559
1560         dev_info(smu->adev->dev, "FreqTableVclk\n");
1561         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1562                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1563
1564         dev_info(smu->adev->dev, "FreqTableDclk\n");
1565         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1566                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1567
1568         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1569         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1570                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1571
1572         dev_info(smu->adev->dev, "FreqTableUclk\n");
1573         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1574                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1575
1576         dev_info(smu->adev->dev, "FreqTableFclk\n");
1577         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1578                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1579
1580         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1581         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1582                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1583
1584         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1585         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1586                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1587
1588         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1589         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1590         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1591         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1592         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1593         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1594         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1595         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1596         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1597
1598         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1599         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1600         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1601         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1602
1603         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1604         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1605
1606         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1607         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1608         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1609         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1610         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1611         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1612
1613         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1614         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1615         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1616         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1617         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1618         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1619         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1620         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1621         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1622
1623         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1624         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1625         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1626         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1627
1628         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1629         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1630         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1631         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1632
1633         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1634                         pptable->dBtcGbGfxPll.a,
1635                         pptable->dBtcGbGfxPll.b,
1636                         pptable->dBtcGbGfxPll.c);
1637         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1638                         pptable->dBtcGbGfxAfll.a,
1639                         pptable->dBtcGbGfxAfll.b,
1640                         pptable->dBtcGbGfxAfll.c);
1641         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1642                         pptable->dBtcGbSoc.a,
1643                         pptable->dBtcGbSoc.b,
1644                         pptable->dBtcGbSoc.c);
1645
1646         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1647                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1648                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1649         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1650                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1651                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1652
1653         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1654                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1655                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1656                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1657         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1658                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1659                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1660                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1661
1662         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1663         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1664
1665         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1666         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1667         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1668         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1669
1670         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1671         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1672         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1673         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1674
1675         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1676         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1677
1678         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1679         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1680                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1681         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1682         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1683
1684         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1685         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1686         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1687         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1688         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1689         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1690         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1691         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1692
1693         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1694         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1695                         pptable->ReservedEquation0.a,
1696                         pptable->ReservedEquation0.b,
1697                         pptable->ReservedEquation0.c);
1698         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1699                         pptable->ReservedEquation1.a,
1700                         pptable->ReservedEquation1.b,
1701                         pptable->ReservedEquation1.c);
1702         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1703                         pptable->ReservedEquation2.a,
1704                         pptable->ReservedEquation2.b,
1705                         pptable->ReservedEquation2.c);
1706         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1707                         pptable->ReservedEquation3.a,
1708                         pptable->ReservedEquation3.b,
1709                         pptable->ReservedEquation3.c);
1710
1711         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1712         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1713
1714         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1715         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1716         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1717
1718         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1719         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1720
1721         dev_info(smu->adev->dev, "Board Parameters:\n");
1722         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1723         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1724
1725         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1726         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1727         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1728         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1729
1730         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1731         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1732
1733         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1734         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1735         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1736
1737         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1738         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1739         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1740
1741         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1742         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1743         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1744
1745         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1746         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1747         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1748
1749         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1750         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1751         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1752         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1753
1754         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1755         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1756         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1757
1758         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1759         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1760         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1761
1762         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1763         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1764         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1765
1766         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1767         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1768         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1769
1770         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1771                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1772                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1773                                 pptable->I2cControllers[i].Enabled);
1774                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1775                                 pptable->I2cControllers[i].SlaveAddress);
1776                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1777                                 pptable->I2cControllers[i].ControllerPort);
1778                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1779                                 pptable->I2cControllers[i].ControllerName);
1780                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1781                                 pptable->I2cControllers[i].ThermalThrotter);
1782                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1783                                 pptable->I2cControllers[i].I2cProtocol);
1784                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
1785                                 pptable->I2cControllers[i].Speed);
1786         }
1787
1788         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1789         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1790
1791         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1792
1793         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1794         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1795                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1796         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1797         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1798                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1799         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1800         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1801                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1802         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1803         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1804                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1805
1806 }
1807
1808 static bool arcturus_is_dpm_running(struct smu_context *smu)
1809 {
1810         int ret = 0;
1811         uint32_t feature_mask[2];
1812         uint64_t feature_enabled;
1813
1814         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1815         if (ret)
1816                 return false;
1817
1818         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1819
1820         return !!(feature_enabled & SMC_DPM_FEATURE);
1821 }
1822
1823 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1824 {
1825         int ret = 0;
1826
1827         if (enable) {
1828                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1829                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1830                         if (ret) {
1831                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1832                                 return ret;
1833                         }
1834                 }
1835         } else {
1836                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1837                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1838                         if (ret) {
1839                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1840                                 return ret;
1841                         }
1842                 }
1843         }
1844
1845         return ret;
1846 }
1847
1848 static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1849                                   uint8_t address, uint32_t numbytes,
1850                                   uint8_t *data)
1851 {
1852         int i;
1853
1854         req->I2CcontrollerPort = 0;
1855         req->I2CSpeed = 2;
1856         req->SlaveAddress = address;
1857         req->NumCmds = numbytes;
1858
1859         for (i = 0; i < numbytes; i++) {
1860                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1861
1862                 /* First 2 bytes are always write for lower 2b EEPROM address */
1863                 if (i < 2)
1864                         cmd->Cmd = 1;
1865                 else
1866                         cmd->Cmd = write;
1867
1868
1869                 /* Add RESTART for read  after address filled */
1870                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1871
1872                 /* Add STOP in the end */
1873                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1874
1875                 /* Fill with data regardless if read or write to simplify code */
1876                 cmd->RegisterAddr = data[i];
1877         }
1878 }
1879
1880 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1881                                                uint8_t address,
1882                                                uint8_t *data,
1883                                                uint32_t numbytes)
1884 {
1885         uint32_t  i, ret = 0;
1886         SwI2cRequest_t req;
1887         struct amdgpu_device *adev = to_amdgpu_device(control);
1888         struct smu_table_context *smu_table = &adev->smu.smu_table;
1889         struct smu_table *table = &smu_table->driver_table;
1890
1891         if (numbytes > MAX_SW_I2C_COMMANDS) {
1892                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1893                         numbytes, MAX_SW_I2C_COMMANDS);
1894                 return -EINVAL;
1895         }
1896
1897         memset(&req, 0, sizeof(req));
1898         arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1899
1900         mutex_lock(&adev->smu.mutex);
1901         /* Now read data starting with that address */
1902         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1903                                         true);
1904         mutex_unlock(&adev->smu.mutex);
1905
1906         if (!ret) {
1907                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1908
1909                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1910                 for (i = 0; i < numbytes; i++)
1911                         data[i] = res->SwI2cCmds[i].Data;
1912
1913                 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1914                                   (uint16_t)address, numbytes);
1915
1916                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1917                                8, 1, data, numbytes, false);
1918         } else
1919                 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1920
1921         return ret;
1922 }
1923
1924 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1925                                                 uint8_t address,
1926                                                 uint8_t *data,
1927                                                 uint32_t numbytes)
1928 {
1929         uint32_t ret;
1930         SwI2cRequest_t req;
1931         struct amdgpu_device *adev = to_amdgpu_device(control);
1932
1933         if (numbytes > MAX_SW_I2C_COMMANDS) {
1934                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1935                         numbytes, MAX_SW_I2C_COMMANDS);
1936                 return -EINVAL;
1937         }
1938
1939         memset(&req, 0, sizeof(req));
1940         arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1941
1942         mutex_lock(&adev->smu.mutex);
1943         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1944         mutex_unlock(&adev->smu.mutex);
1945
1946         if (!ret) {
1947                 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1948                                          (uint16_t)address, numbytes);
1949
1950                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1951                                8, 1, data, numbytes, false);
1952                 /*
1953                  * According to EEPROM spec there is a MAX of 10 ms required for
1954                  * EEPROM to flush internal RX buffer after STOP was issued at the
1955                  * end of write transaction. During this time the EEPROM will not be
1956                  * responsive to any more commands - so wait a bit more.
1957                  */
1958                 msleep(10);
1959
1960         } else
1961                 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1962
1963         return ret;
1964 }
1965
1966 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1967                               struct i2c_msg *msgs, int num)
1968 {
1969         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1970         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1971
1972         for (i = 0; i < num; i++) {
1973                 /*
1974                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1975                  * once and hence the data needs to be spliced into chunks and sent each
1976                  * chunk separately
1977                  */
1978                 data_size = msgs[i].len - 2;
1979                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1980                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1981                 data_ptr = msgs[i].buf + 2;
1982
1983                 for (j = 0; j < data_size / data_chunk_size; j++) {
1984                         /* Insert the EEPROM dest addess, bits 0-15 */
1985                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1986                         data_chunk[1] = (next_eeprom_addr & 0xff);
1987
1988                         if (msgs[i].flags & I2C_M_RD) {
1989                                 ret = arcturus_i2c_read_data(i2c_adap,
1990                                                              (uint8_t)msgs[i].addr,
1991                                                              data_chunk, MAX_SW_I2C_COMMANDS);
1992
1993                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1994                         } else {
1995
1996                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1997
1998                                 ret = arcturus_i2c_write_data(i2c_adap,
1999                                                               (uint8_t)msgs[i].addr,
2000                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2001                         }
2002
2003                         if (ret) {
2004                                 num = -EIO;
2005                                 goto fail;
2006                         }
2007
2008                         next_eeprom_addr += data_chunk_size;
2009                         data_ptr += data_chunk_size;
2010                 }
2011
2012                 if (data_size % data_chunk_size) {
2013                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2014                         data_chunk[1] = (next_eeprom_addr & 0xff);
2015
2016                         if (msgs[i].flags & I2C_M_RD) {
2017                                 ret = arcturus_i2c_read_data(i2c_adap,
2018                                                              (uint8_t)msgs[i].addr,
2019                                                              data_chunk, (data_size % data_chunk_size) + 2);
2020
2021                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2022                         } else {
2023                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2024
2025                                 ret = arcturus_i2c_write_data(i2c_adap,
2026                                                               (uint8_t)msgs[i].addr,
2027                                                               data_chunk, (data_size % data_chunk_size) + 2);
2028                         }
2029
2030                         if (ret) {
2031                                 num = -EIO;
2032                                 goto fail;
2033                         }
2034                 }
2035         }
2036
2037 fail:
2038         return num;
2039 }
2040
2041 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2042 {
2043         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2044 }
2045
2046
2047 static const struct i2c_algorithm arcturus_i2c_algo = {
2048         .master_xfer = arcturus_i2c_xfer,
2049         .functionality = arcturus_i2c_func,
2050 };
2051
2052 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2053 {
2054         struct amdgpu_device *adev = to_amdgpu_device(control);
2055         int res;
2056
2057         control->owner = THIS_MODULE;
2058         control->class = I2C_CLASS_SPD;
2059         control->dev.parent = &adev->pdev->dev;
2060         control->algo = &arcturus_i2c_algo;
2061         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2062
2063         res = i2c_add_adapter(control);
2064         if (res)
2065                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2066
2067         return res;
2068 }
2069
2070 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2071 {
2072         i2c_del_adapter(control);
2073 }
2074
2075 static void arcturus_get_unique_id(struct smu_context *smu)
2076 {
2077         struct amdgpu_device *adev = smu->adev;
2078         uint32_t top32 = 0, bottom32 = 0, smu_version;
2079         uint64_t id;
2080
2081         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2082                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2083                 return;
2084         }
2085
2086         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2087         if (smu_version < 0x361700) {
2088                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2089                 return;
2090         }
2091
2092         /* Get the SN to turn into a Unique ID */
2093         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2094         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2095
2096         id = ((uint64_t)bottom32 << 32) | top32;
2097         adev->unique_id = id;
2098         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2099          * 16-digit HEX string for convenience and backwards-compatibility
2100          */
2101         sprintf(adev->serial, "%llx", id);
2102 }
2103
2104 static bool arcturus_is_baco_supported(struct smu_context *smu)
2105 {
2106         struct amdgpu_device *adev = smu->adev;
2107         uint32_t val;
2108
2109         if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2110                 return false;
2111
2112         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2113         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2114 }
2115
2116 static int arcturus_set_df_cstate(struct smu_context *smu,
2117                                   enum pp_df_cstate state)
2118 {
2119         uint32_t smu_version;
2120         int ret;
2121
2122         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2123         if (ret) {
2124                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2125                 return ret;
2126         }
2127
2128         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2129         if (smu_version < 0x360F00) {
2130                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2131                 return -EINVAL;
2132         }
2133
2134         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2135 }
2136
2137 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2138 {
2139         uint32_t smu_version;
2140         int ret;
2141
2142         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2143         if (ret) {
2144                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2145                 return ret;
2146         }
2147
2148         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2149         if (smu_version < 0x00361700) {
2150                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2151                 return -EINVAL;
2152         }
2153
2154         if (en)
2155                 return smu_cmn_send_smc_msg_with_param(smu,
2156                                                    SMU_MSG_GmiPwrDnControl,
2157                                                    1,
2158                                                    NULL);
2159
2160         return smu_cmn_send_smc_msg_with_param(smu,
2161                                            SMU_MSG_GmiPwrDnControl,
2162                                            0,
2163                                            NULL);
2164 }
2165
2166 static const struct throttling_logging_label {
2167         uint32_t feature_mask;
2168         const char *label;
2169 } logging_label[] = {
2170         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2171         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2172         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2173         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2174         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2175         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2176         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2177 };
2178 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2179 {
2180         int ret;
2181         int throttler_idx, throtting_events = 0, buf_idx = 0;
2182         struct amdgpu_device *adev = smu->adev;
2183         uint32_t throttler_status;
2184         char log_buf[256];
2185
2186         ret = arcturus_get_smu_metrics_data(smu,
2187                                             METRICS_THROTTLER_STATUS,
2188                                             &throttler_status);
2189         if (ret)
2190                 return;
2191
2192         memset(log_buf, 0, sizeof(log_buf));
2193         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2194              throttler_idx++) {
2195                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2196                         throtting_events++;
2197                         buf_idx += snprintf(log_buf + buf_idx,
2198                                             sizeof(log_buf) - buf_idx,
2199                                             "%s%s",
2200                                             throtting_events > 1 ? " and " : "",
2201                                             logging_label[throttler_idx].label);
2202                         if (buf_idx >= sizeof(log_buf)) {
2203                                 dev_err(adev->dev, "buffer overflow!\n");
2204                                 log_buf[sizeof(log_buf) - 1] = '\0';
2205                                 break;
2206                         }
2207                 }
2208         }
2209
2210         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2211                         log_buf);
2212         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2213 }
2214
2215 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2216 {
2217         struct amdgpu_device *adev = smu->adev;
2218         uint32_t esm_ctrl;
2219
2220         /* TODO: confirm this on real target */
2221         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2222         if ((esm_ctrl >> 15) & 0x1FFFF)
2223                 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2224
2225         return smu_v11_0_get_current_pcie_link_speed(smu);
2226 }
2227
2228 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2229                                         void **table)
2230 {
2231         struct smu_table_context *smu_table = &smu->smu_table;
2232         struct gpu_metrics_v1_1 *gpu_metrics =
2233                 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
2234         SmuMetrics_t metrics;
2235         int ret = 0;
2236
2237         ret = smu_cmn_get_metrics_table(smu,
2238                                         &metrics,
2239                                         true);
2240         if (ret)
2241                 return ret;
2242
2243         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
2244
2245         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2246         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2247         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2248         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2249         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2250         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2251
2252         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2253         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2254         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2255
2256         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2257         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2258
2259         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2260         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2261         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2262         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2263         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2264
2265         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2266         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2267         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2268         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2269         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2270
2271         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2272
2273         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2274
2275         gpu_metrics->pcie_link_width =
2276                         smu_v11_0_get_current_pcie_link_width(smu);
2277         gpu_metrics->pcie_link_speed =
2278                         arcturus_get_current_pcie_link_speed(smu);
2279
2280         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2281
2282         *table = (void *)gpu_metrics;
2283
2284         return sizeof(struct gpu_metrics_v1_1);
2285 }
2286
2287 static const struct pptable_funcs arcturus_ppt_funcs = {
2288         /* init dpm */
2289         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2290         /* btc */
2291         .run_btc = arcturus_run_btc,
2292         /* dpm/clk tables */
2293         .set_default_dpm_table = arcturus_set_default_dpm_table,
2294         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2295         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2296         .print_clk_levels = arcturus_print_clk_levels,
2297         .force_clk_levels = arcturus_force_clk_levels,
2298         .read_sensor = arcturus_read_sensor,
2299         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2300         .get_power_profile_mode = arcturus_get_power_profile_mode,
2301         .set_power_profile_mode = arcturus_set_power_profile_mode,
2302         .set_performance_level = arcturus_set_performance_level,
2303         /* debug (internal used) */
2304         .dump_pptable = arcturus_dump_pptable,
2305         .get_power_limit = arcturus_get_power_limit,
2306         .is_dpm_running = arcturus_is_dpm_running,
2307         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2308         .i2c_init = arcturus_i2c_control_init,
2309         .i2c_fini = arcturus_i2c_control_fini,
2310         .get_unique_id = arcturus_get_unique_id,
2311         .init_microcode = smu_v11_0_init_microcode,
2312         .load_microcode = smu_v11_0_load_microcode,
2313         .fini_microcode = smu_v11_0_fini_microcode,
2314         .init_smc_tables = arcturus_init_smc_tables,
2315         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2316         .init_power = smu_v11_0_init_power,
2317         .fini_power = smu_v11_0_fini_power,
2318         .check_fw_status = smu_v11_0_check_fw_status,
2319         /* pptable related */
2320         .setup_pptable = arcturus_setup_pptable,
2321         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2322         .check_fw_version = smu_v11_0_check_fw_version,
2323         .write_pptable = smu_cmn_write_pptable,
2324         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2325         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2326         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2327         .system_features_control = smu_v11_0_system_features_control,
2328         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2329         .send_smc_msg = smu_cmn_send_smc_msg,
2330         .init_display_count = NULL,
2331         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2332         .get_enabled_mask = smu_cmn_get_enabled_mask,
2333         .feature_is_enabled = smu_cmn_feature_is_enabled,
2334         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2335         .notify_display_change = NULL,
2336         .set_power_limit = smu_v11_0_set_power_limit,
2337         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2338         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2339         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2340         .set_min_dcef_deep_sleep = NULL,
2341         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2342         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2343         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2344         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2345         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2346         .gfx_off_control = smu_v11_0_gfx_off_control,
2347         .register_irq_handler = smu_v11_0_register_irq_handler,
2348         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2349         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2350         .baco_is_support= arcturus_is_baco_supported,
2351         .baco_get_state = smu_v11_0_baco_get_state,
2352         .baco_set_state = smu_v11_0_baco_set_state,
2353         .baco_enter = smu_v11_0_baco_enter,
2354         .baco_exit = smu_v11_0_baco_exit,
2355         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2356         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2357         .set_df_cstate = arcturus_set_df_cstate,
2358         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2359         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2360         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2361         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2362         .get_gpu_metrics = arcturus_get_gpu_metrics,
2363         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2364         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2365         .get_fan_parameters = arcturus_get_fan_parameters,
2366         .interrupt_work = smu_v11_0_interrupt_work,
2367         .set_light_sbr = smu_v11_0_set_light_sbr,
2368 };
2369
2370 void arcturus_set_ppt_funcs(struct smu_context *smu)
2371 {
2372         smu->ppt_funcs = &arcturus_ppt_funcs;
2373         smu->message_map = arcturus_message_map;
2374         smu->clock_map = arcturus_clk_map;
2375         smu->feature_map = arcturus_feature_mask_map;
2376         smu->table_map = arcturus_table_map;
2377         smu->pwr_src_map = arcturus_pwr_src_map;
2378         smu->workload_map = arcturus_workload_map;
2379 }