drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 365
 366         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 367                                              SMU_FEATURE_MAX/32);
 368         if (ret)
 369                 return ret;
 370
 371         bitmap_or(feature->allowed, feature->allowed,
 372                       (unsigned long *)allowed_feature_mask,
 373                       feature->feature_num);
 374
 375         return ret;
 376 }
 377
 378 static int smu_set_funcs(struct amdgpu_device *adev)
 379 {
 380         struct smu_context *smu = &adev->smu;
 381
 382         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 383                 smu->od_enabled = true;
 384
 385         switch (adev->asic_type) {
 386         case CHIP_NAVI10:
 387         case CHIP_NAVI14:
 388         case CHIP_NAVI12:
 389                 navi10_set_ppt_funcs(smu);
 390                 break;
 391         case CHIP_ARCTURUS:
 392                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 393                 arcturus_set_ppt_funcs(smu);
 394                 /* OD is not supported on Arcturus */
 395                 smu->od_enabled =false;
 396                 break;
 397         case CHIP_SIENNA_CICHLID:
 398         case CHIP_NAVY_FLOUNDER:
 399                 sienna_cichlid_set_ppt_funcs(smu);
 400                 break;
 401         case CHIP_RENOIR:
 402                 renoir_set_ppt_funcs(smu);
 403                 break;
 404         default:
 405                 return -EINVAL;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int smu_early_init(void *handle)
 412 {
 413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 414         struct smu_context *smu = &adev->smu;
 415
 416         smu->adev = adev;
 417         smu->pm_enabled = !!amdgpu_dpm;
 418         smu->is_apu = false;
 419         mutex_init(&smu->mutex);
 420         mutex_init(&smu->smu_baco.mutex);
 421         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 422         smu->smu_baco.platform_support = false;
 423
 424         return smu_set_funcs(adev);
 425 }
 426
 427 static int smu_set_default_dpm_table(struct smu_context *smu)
 428 {
 429         struct smu_power_context *smu_power = &smu->smu_power;
 430         struct smu_power_gate *power_gate = &smu_power->power_gate;
 431         int vcn_gate, jpeg_gate;
 432         int ret = 0;
 433
 434         if (!smu->ppt_funcs->set_default_dpm_table)
 435                 return 0;
 436
 437         mutex_lock(&power_gate->vcn_gate_lock);
 438         mutex_lock(&power_gate->jpeg_gate_lock);
 439
 440         vcn_gate = atomic_read(&power_gate->vcn_gated);
 441         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 442
 443         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 444         if (ret)
 445                 goto err0_out;
 446
 447         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 448         if (ret)
 449                 goto err1_out;
 450
 451         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 452         if (ret)
 453                 dev_err(smu->adev->dev,
 454                         "Failed to setup default dpm clock tables!\n");
 455
 456         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 457 err1_out:
 458         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 459 err0_out:
 460         mutex_unlock(&power_gate->jpeg_gate_lock);
 461         mutex_unlock(&power_gate->vcn_gate_lock);
 462
 463         return ret;
 464 }
 465
 466 static int smu_late_init(void *handle)
 467 {
 468         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 469         struct smu_context *smu = &adev->smu;
 470         int ret = 0;
 471
 472         if (!smu->pm_enabled)
 473                 return 0;
 474
 475         ret = smu_post_init(smu);
 476         if (ret) {
 477                 dev_err(adev->dev, "Failed to post smu init!\n");
 478                 return ret;
 479         }
 480
 481         ret = smu_set_default_od_settings(smu);
 482         if (ret) {
 483                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 484                 return ret;
 485         }
 486
 487         ret = smu_populate_umd_state_clk(smu);
 488         if (ret) {
 489                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 490                 return ret;
 491         }
 492
 493         ret = smu_get_asic_power_limits(smu);
 494         if (ret) {
 495                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 496                 return ret;
 497         }
 498
 499         smu_get_unique_id(smu);
 500
 501         smu_get_fan_parameters(smu);
 502
 503         smu_handle_task(&adev->smu,
 504                         smu->smu_dpm.dpm_level,
 505                         AMD_PP_TASK_COMPLETE_INIT,
 506                         false);
 507
 508         return 0;
 509 }
 510
 511 static int smu_init_fb_allocations(struct smu_context *smu)
 512 {
 513         struct amdgpu_device *adev = smu->adev;
 514         struct smu_table_context *smu_table = &smu->smu_table;
 515         struct smu_table *tables = smu_table->tables;
 516         struct smu_table *driver_table = &(smu_table->driver_table);
 517         uint32_t max_table_size = 0;
 518         int ret, i;
 519
 520         /* VRAM allocation for tool table */
 521         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 522                 ret = amdgpu_bo_create_kernel(adev,
 523                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 524                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 525                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 526                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 527                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 528                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 529                 if (ret) {
 530                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 531                         return ret;
 532                 }
 533         }
 534
 535         /* VRAM allocation for driver table */
 536         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 537                 if (tables[i].size == 0)
 538                         continue;
 539
 540                 if (i == SMU_TABLE_PMSTATUSLOG)
 541                         continue;
 542
 543                 if (max_table_size < tables[i].size)
 544                         max_table_size = tables[i].size;
 545         }
 546
 547         driver_table->size = max_table_size;
 548         driver_table->align = PAGE_SIZE;
 549         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 550
 551         ret = amdgpu_bo_create_kernel(adev,
 552                                       driver_table->size,
 553                                       driver_table->align,
 554                                       driver_table->domain,
 555                                       &driver_table->bo,
 556                                       &driver_table->mc_address,
 557                                       &driver_table->cpu_addr);
 558         if (ret) {
 559                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 560                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 561                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 562                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 563                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 564         }
 565
 566         return ret;
 567 }
 568
 569 static int smu_fini_fb_allocations(struct smu_context *smu)
 570 {
 571         struct smu_table_context *smu_table = &smu->smu_table;
 572         struct smu_table *tables = smu_table->tables;
 573         struct smu_table *driver_table = &(smu_table->driver_table);
 574
 575         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 576                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 577                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 578                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 579
 580         amdgpu_bo_free_kernel(&driver_table->bo,
 581                               &driver_table->mc_address,
 582                               &driver_table->cpu_addr);
 583
 584         return 0;
 585 }
 586
 587 /**
 588  * smu_alloc_memory_pool - allocate memory pool in the system memory
 589  *
 590  * @smu: amdgpu_device pointer
 591  *
 592  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 593  * and DramLogSetDramAddr can notify it changed.
 594  *
 595  * Returns 0 on success, error on failure.
 596  */
 597 static int smu_alloc_memory_pool(struct smu_context *smu)
 598 {
 599         struct amdgpu_device *adev = smu->adev;
 600         struct smu_table_context *smu_table = &smu->smu_table;
 601         struct smu_table *memory_pool = &smu_table->memory_pool;
 602         uint64_t pool_size = smu->pool_size;
 603         int ret = 0;
 604
 605         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 606                 return ret;
 607
 608         memory_pool->size = pool_size;
 609         memory_pool->align = PAGE_SIZE;
 610         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 611
 612         switch (pool_size) {
 613         case SMU_MEMORY_POOL_SIZE_256_MB:
 614         case SMU_MEMORY_POOL_SIZE_512_MB:
 615         case SMU_MEMORY_POOL_SIZE_1_GB:
 616         case SMU_MEMORY_POOL_SIZE_2_GB:
 617                 ret = amdgpu_bo_create_kernel(adev,
 618                                               memory_pool->size,
 619                                               memory_pool->align,
 620                                               memory_pool->domain,
 621                                               &memory_pool->bo,
 622                                               &memory_pool->mc_address,
 623                                               &memory_pool->cpu_addr);
 624                 if (ret)
 625                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static int smu_free_memory_pool(struct smu_context *smu)
 635 {
 636         struct smu_table_context *smu_table = &smu->smu_table;
 637         struct smu_table *memory_pool = &smu_table->memory_pool;
 638
 639         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 640                 return 0;
 641
 642         amdgpu_bo_free_kernel(&memory_pool->bo,
 643                               &memory_pool->mc_address,
 644                               &memory_pool->cpu_addr);
 645
 646         memset(memory_pool, 0, sizeof(struct smu_table));
 647
 648         return 0;
 649 }
 650
 651 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 652 {
 653         struct smu_table_context *smu_table = &smu->smu_table;
 654         struct smu_table *dummy_read_1_table =
 655                         &smu_table->dummy_read_1_table;
 656         struct amdgpu_device *adev = smu->adev;
 657         int ret = 0;
 658
 659         dummy_read_1_table->size = 0x40000;
 660         dummy_read_1_table->align = PAGE_SIZE;
 661         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 662
 663         ret = amdgpu_bo_create_kernel(adev,
 664                                       dummy_read_1_table->size,
 665                                       dummy_read_1_table->align,
 666                                       dummy_read_1_table->domain,
 667                                       &dummy_read_1_table->bo,
 668                                       &dummy_read_1_table->mc_address,
 669                                       &dummy_read_1_table->cpu_addr);
 670         if (ret)
 671                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 672
 673         return ret;
 674 }
 675
 676 static void smu_free_dummy_read_table(struct smu_context *smu)
 677 {
 678         struct smu_table_context *smu_table = &smu->smu_table;
 679         struct smu_table *dummy_read_1_table =
 680                         &smu_table->dummy_read_1_table;
 681
 682
 683         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 684                               &dummy_read_1_table->mc_address,
 685                               &dummy_read_1_table->cpu_addr);
 686
 687         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 688 }
 689
 690 static int smu_smc_table_sw_init(struct smu_context *smu)
 691 {
 692         int ret;
 693
 694         /**
 695          * Create smu_table structure, and init smc tables such as
 696          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 697          */
 698         ret = smu_init_smc_tables(smu);
 699         if (ret) {
 700                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 701                 return ret;
 702         }
 703
 704         /**
 705          * Create smu_power_context structure, and allocate smu_dpm_context and
 706          * context size to fill the smu_power_context data.
 707          */
 708         ret = smu_init_power(smu);
 709         if (ret) {
 710                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 711                 return ret;
 712         }
 713
 714         /*
 715          * allocate vram bos to store smc table contents.
 716          */
 717         ret = smu_init_fb_allocations(smu);
 718         if (ret)
 719                 return ret;
 720
 721         ret = smu_alloc_memory_pool(smu);
 722         if (ret)
 723                 return ret;
 724
 725         ret = smu_alloc_dummy_read_table(smu);
 726         if (ret)
 727                 return ret;
 728
 729         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 730         if (ret)
 731                 return ret;
 732
 733         return 0;
 734 }
 735
 736 static int smu_smc_table_sw_fini(struct smu_context *smu)
 737 {
 738         int ret;
 739
 740         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 741
 742         smu_free_dummy_read_table(smu);
 743
 744         ret = smu_free_memory_pool(smu);
 745         if (ret)
 746                 return ret;
 747
 748         ret = smu_fini_fb_allocations(smu);
 749         if (ret)
 750                 return ret;
 751
 752         ret = smu_fini_power(smu);
 753         if (ret) {
 754                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 755                 return ret;
 756         }
 757
 758         ret = smu_fini_smc_tables(smu);
 759         if (ret) {
 760                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 761                 return ret;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static void smu_throttling_logging_work_fn(struct work_struct *work)
 768 {
 769         struct smu_context *smu = container_of(work, struct smu_context,
 770                                                throttling_logging_work);
 771
 772         smu_log_thermal_throttling(smu);
 773 }
 774
 775 static void smu_interrupt_work_fn(struct work_struct *work)
 776 {
 777         struct smu_context *smu = container_of(work, struct smu_context,
 778                                                interrupt_work);
 779
 780         mutex_lock(&smu->mutex);
 781
 782         if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
 783                 smu->ppt_funcs->interrupt_work(smu);
 784
 785         mutex_unlock(&smu->mutex);
 786 }
 787
 788 static int smu_sw_init(void *handle)
 789 {
 790         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 791         struct smu_context *smu = &adev->smu;
 792         int ret;
 793
 794         smu->pool_size = adev->pm.smu_prv_buffer_size;
 795         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 796         mutex_init(&smu->smu_feature.mutex);
 797         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 798         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 799         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 800
 801         mutex_init(&smu->sensor_lock);
 802         mutex_init(&smu->metrics_lock);
 803         mutex_init(&smu->message_lock);
 804
 805         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 806         INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
 807         atomic64_set(&smu->throttle_int_counter, 0);
 808         smu->watermarks_bitmap = 0;
 809         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 810         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 811
 812         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 813         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 814         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 815         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 816
 817         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 818         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 819         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 820         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 821         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 822         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 823         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 824         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 825
 826         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 827         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 828         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 829         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 830         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 831         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 832         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 833         smu->display_config = &adev->pm.pm_display_cfg;
 834
 835         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 836         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 837
 838         if (!amdgpu_sriov_vf(adev)) {
 839                 ret = smu_init_microcode(smu);
 840                 if (ret) {
 841                         dev_err(adev->dev, "Failed to load smu firmware!\n");
 842                         return ret;
 843                 }
 844         }
 845
 846         ret = smu_smc_table_sw_init(smu);
 847         if (ret) {
 848                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 849                 return ret;
 850         }
 851
 852         ret = smu_register_irq_handler(smu);
 853         if (ret) {
 854                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 855                 return ret;
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int smu_sw_fini(void *handle)
 862 {
 863         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 864         struct smu_context *smu = &adev->smu;
 865         int ret;
 866
 867         ret = smu_smc_table_sw_fini(smu);
 868         if (ret) {
 869                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 870                 return ret;
 871         }
 872
 873         smu_fini_microcode(smu);
 874
 875         return 0;
 876 }
 877
 878 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 879 {
 880         struct amdgpu_device *adev = smu->adev;
 881         struct smu_temperature_range *range =
 882                                 &smu->thermal_range;
 883         int ret = 0;
 884
 885         if (!smu->ppt_funcs->get_thermal_temperature_range)
 886                 return 0;
 887
 888         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 889         if (ret)
 890                 return ret;
 891
 892         adev->pm.dpm.thermal.min_temp = range->min;
 893         adev->pm.dpm.thermal.max_temp = range->max;
 894         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 895         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 896         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 897         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 898         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 899         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 900         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 901
 902         return ret;
 903 }
 904
 905 static int smu_smc_hw_setup(struct smu_context *smu)
 906 {
 907         struct amdgpu_device *adev = smu->adev;
 908         uint32_t pcie_gen = 0, pcie_width = 0;
 909         int ret;
 910
 911         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 912                 dev_info(adev->dev, "dpm has been enabled\n");
 913                 return 0;
 914         }
 915
 916         ret = smu_init_display_count(smu, 0);
 917         if (ret) {
 918                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 919                 return ret;
 920         }
 921
 922         ret = smu_set_driver_table_location(smu);
 923         if (ret) {
 924                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 925                 return ret;
 926         }
 927
 928         /*
 929          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 930          */
 931         ret = smu_set_tool_table_location(smu);
 932         if (ret) {
 933                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 934                 return ret;
 935         }
 936
 937         /*
 938          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 939          * pool location.
 940          */
 941         ret = smu_notify_memory_pool_location(smu);
 942         if (ret) {
 943                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 944                 return ret;
 945         }
 946
 947         /* smu_dump_pptable(smu); */
 948         /*
 949          * Copy pptable bo in the vram to smc with SMU MSGs such as
 950          * SetDriverDramAddr and TransferTableDram2Smu.
 951          */
 952         ret = smu_write_pptable(smu);
 953         if (ret) {
 954                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 955                 return ret;
 956         }
 957
 958         /* issue Run*Btc msg */
 959         ret = smu_run_btc(smu);
 960         if (ret)
 961                 return ret;
 962
 963         ret = smu_feature_set_allowed_mask(smu);
 964         if (ret) {
 965                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 966                 return ret;
 967         }
 968
 969         ret = smu_system_features_control(smu, true);
 970         if (ret) {
 971                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 972                 return ret;
 973         }
 974
 975         if (!smu_is_dpm_running(smu))
 976                 dev_info(adev->dev, "dpm has been disabled\n");
 977
 978         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 979                 pcie_gen = 3;
 980         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 981                 pcie_gen = 2;
 982         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 983                 pcie_gen = 1;
 984         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 985                 pcie_gen = 0;
 986
 987         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 988          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 989          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 990          */
 991         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 992                 pcie_width = 6;
 993         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 994                 pcie_width = 5;
 995         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 996                 pcie_width = 4;
 997         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 998                 pcie_width = 3;
 999         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1000                 pcie_width = 2;
1001         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1002                 pcie_width = 1;
1003         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1004         if (ret) {
1005                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1006                 return ret;
1007         }
1008
1009         ret = smu_get_thermal_temperature_range(smu);
1010         if (ret) {
1011                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1012                 return ret;
1013         }
1014
1015         ret = smu_enable_thermal_alert(smu);
1016         if (ret) {
1017                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1018                 return ret;
1019         }
1020
1021         /*
1022          * Set initialized values (get from vbios) to dpm tables context such as
1023          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1024          * type of clks.
1025          */
1026         ret = smu_set_default_dpm_table(smu);
1027         if (ret) {
1028                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1029                 return ret;
1030         }
1031
1032         /*
1033          * Set initialized values (get from vbios) to dpm tables context such as
1034          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1035          * type of clks.
1036          */
1037         ret = smu_set_default_dpm_table(smu);
1038         if (ret) {
1039                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1040                 return ret;
1041         }
1042
1043         ret = smu_notify_display_change(smu);
1044         if (ret)
1045                 return ret;
1046
1047         /*
1048          * Set min deep sleep dce fclk with bootup value from vbios via
1049          * SetMinDeepSleepDcefclk MSG.
1050          */
1051         ret = smu_set_min_dcef_deep_sleep(smu,
1052                                           smu->smu_table.boot_values.dcefclk / 100);
1053         if (ret)
1054                 return ret;
1055
1056         return ret;
1057 }
1058
1059 static int smu_start_smc_engine(struct smu_context *smu)
1060 {
1061         struct amdgpu_device *adev = smu->adev;
1062         int ret = 0;
1063
1064         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1065                 if (adev->asic_type < CHIP_NAVI10) {
1066                         if (smu->ppt_funcs->load_microcode) {
1067                                 ret = smu->ppt_funcs->load_microcode(smu);
1068                                 if (ret)
1069                                         return ret;
1070                         }
1071                 }
1072         }
1073
1074         if (smu->ppt_funcs->check_fw_status) {
1075                 ret = smu->ppt_funcs->check_fw_status(smu);
1076                 if (ret) {
1077                         dev_err(adev->dev, "SMC is not ready\n");
1078                         return ret;
1079                 }
1080         }
1081
1082         /*
1083          * Send msg GetDriverIfVersion to check if the return value is equal
1084          * with DRIVER_IF_VERSION of smc header.
1085          */
1086         ret = smu_check_fw_version(smu);
1087         if (ret)
1088                 return ret;
1089
1090         return ret;
1091 }
1092
1093 static int smu_hw_init(void *handle)
1094 {
1095         int ret;
1096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097         struct smu_context *smu = &adev->smu;
1098
1099         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1100                 smu->pm_enabled = false;
1101                 return 0;
1102         }
1103
1104         ret = smu_start_smc_engine(smu);
1105         if (ret) {
1106                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1107                 return ret;
1108         }
1109
1110         if (smu->is_apu) {
1111                 smu_powergate_sdma(&adev->smu, false);
1112                 smu_dpm_set_vcn_enable(smu, true);
1113                 smu_dpm_set_jpeg_enable(smu, true);
1114                 smu_set_gfx_cgpg(&adev->smu, true);
1115         }
1116
1117         if (!smu->pm_enabled)
1118                 return 0;
1119
1120         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1121         ret = smu_get_vbios_bootup_values(smu);
1122         if (ret) {
1123                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1124                 return ret;
1125         }
1126
1127         ret = smu_setup_pptable(smu);
1128         if (ret) {
1129                 dev_err(adev->dev, "Failed to setup pptable!\n");
1130                 return ret;
1131         }
1132
1133         ret = smu_get_driver_allowed_feature_mask(smu);
1134         if (ret)
1135                 return ret;
1136
1137         ret = smu_smc_hw_setup(smu);
1138         if (ret) {
1139                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1140                 return ret;
1141         }
1142
1143         /*
1144          * Move maximum sustainable clock retrieving here considering
1145          * 1. It is not needed on resume(from S3).
1146          * 2. DAL settings come between .hw_init and .late_init of SMU.
1147          *    And DAL needs to know the maximum sustainable clocks. Thus
1148          *    it cannot be put in .late_init().
1149          */
1150         ret = smu_init_max_sustainable_clocks(smu);
1151         if (ret) {
1152                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1153                 return ret;
1154         }
1155
1156         adev->pm.dpm_enabled = true;
1157
1158         dev_info(adev->dev, "SMU is initialized successfully!\n");
1159
1160         return 0;
1161 }
1162
1163 static int smu_disable_dpms(struct smu_context *smu)
1164 {
1165         struct amdgpu_device *adev = smu->adev;
1166         int ret = 0;
1167         bool use_baco = !smu->is_apu &&
1168                 ((amdgpu_in_reset(adev) &&
1169                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1170                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1171
1172         /*
1173          * For custom pptable uploading, skip the DPM features
1174          * disable process on Navi1x ASICs.
1175          *   - As the gfx related features are under control of
1176          *     RLC on those ASICs. RLC reinitialization will be
1177          *     needed to reenable them. That will cost much more
1178          *     efforts.
1179          *
1180          *   - SMU firmware can handle the DPM reenablement
1181          *     properly.
1182          */
1183         if (smu->uploading_custom_pp_table &&
1184             (adev->asic_type >= CHIP_NAVI10) &&
1185             (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1186                 return 0;
1187
1188         /*
1189          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1190          * on BACO in. Driver involvement is unnecessary.
1191          */
1192         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1193              use_baco)
1194                 return 0;
1195
1196         /*
1197          * For gpu reset, runpm and hibernation through BACO,
1198          * BACO feature has to be kept enabled.
1199          */
1200         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1201                 ret = smu_disable_all_features_with_exception(smu,
1202                                                               SMU_FEATURE_BACO_BIT);
1203                 if (ret)
1204                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1205         } else {
1206                 ret = smu_system_features_control(smu, false);
1207                 if (ret)
1208                         dev_err(adev->dev, "Failed to disable smu features.\n");
1209         }
1210
1211         if (adev->asic_type >= CHIP_NAVI10 &&
1212             adev->gfx.rlc.funcs->stop)
1213                 adev->gfx.rlc.funcs->stop(adev);
1214
1215         return ret;
1216 }
1217
1218 static int smu_smc_hw_cleanup(struct smu_context *smu)
1219 {
1220         struct amdgpu_device *adev = smu->adev;
1221         int ret = 0;
1222
1223         cancel_work_sync(&smu->throttling_logging_work);
1224         cancel_work_sync(&smu->interrupt_work);
1225
1226         ret = smu_disable_thermal_alert(smu);
1227         if (ret) {
1228                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1229                 return ret;
1230         }
1231
1232         ret = smu_disable_dpms(smu);
1233         if (ret) {
1234                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1235                 return ret;
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int smu_hw_fini(void *handle)
1242 {
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244         struct smu_context *smu = &adev->smu;
1245
1246         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1247                 return 0;
1248
1249         if (smu->is_apu) {
1250                 smu_powergate_sdma(&adev->smu, true);
1251                 smu_dpm_set_vcn_enable(smu, false);
1252                 smu_dpm_set_jpeg_enable(smu, false);
1253         }
1254
1255         if (!smu->pm_enabled)
1256                 return 0;
1257
1258         adev->pm.dpm_enabled = false;
1259
1260         return smu_smc_hw_cleanup(smu);
1261 }
1262
1263 int smu_reset(struct smu_context *smu)
1264 {
1265         struct amdgpu_device *adev = smu->adev;
1266         int ret;
1267
1268         amdgpu_gfx_off_ctrl(smu->adev, false);
1269
1270         ret = smu_hw_fini(adev);
1271         if (ret)
1272                 return ret;
1273
1274         ret = smu_hw_init(adev);
1275         if (ret)
1276                 return ret;
1277
1278         ret = smu_late_init(adev);
1279         if (ret)
1280                 return ret;
1281
1282         amdgpu_gfx_off_ctrl(smu->adev, true);
1283
1284         return 0;
1285 }
1286
1287 static int smu_suspend(void *handle)
1288 {
1289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290         struct smu_context *smu = &adev->smu;
1291         int ret;
1292
1293         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1294                 return 0;
1295
1296         if (!smu->pm_enabled)
1297                 return 0;
1298
1299         adev->pm.dpm_enabled = false;
1300
1301         ret = smu_smc_hw_cleanup(smu);
1302         if (ret)
1303                 return ret;
1304
1305         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1306
1307         if (smu->is_apu)
1308                 smu_set_gfx_cgpg(&adev->smu, false);
1309
1310         return 0;
1311 }
1312
1313 static int smu_resume(void *handle)
1314 {
1315         int ret;
1316         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317         struct smu_context *smu = &adev->smu;
1318
1319         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1320                 return 0;
1321
1322         if (!smu->pm_enabled)
1323                 return 0;
1324
1325         dev_info(adev->dev, "SMU is resuming...\n");
1326
1327         ret = smu_start_smc_engine(smu);
1328         if (ret) {
1329                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1330                 return ret;
1331         }
1332
1333         ret = smu_smc_hw_setup(smu);
1334         if (ret) {
1335                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1336                 return ret;
1337         }
1338
1339         if (smu->is_apu)
1340                 smu_set_gfx_cgpg(&adev->smu, true);
1341
1342         smu->disable_uclk_switch = 0;
1343
1344         adev->pm.dpm_enabled = true;
1345
1346         dev_info(adev->dev, "SMU is resumed successfully!\n");
1347
1348         return 0;
1349 }
1350
1351 int smu_display_configuration_change(struct smu_context *smu,
1352                                      const struct amd_pp_display_configuration *display_config)
1353 {
1354         int index = 0;
1355         int num_of_active_display = 0;
1356
1357         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1358                 return -EOPNOTSUPP;
1359
1360         if (!display_config)
1361                 return -EINVAL;
1362
1363         mutex_lock(&smu->mutex);
1364
1365         smu_set_min_dcef_deep_sleep(smu,
1366                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1367
1368         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1369                 if (display_config->displays[index].controller_id != 0)
1370                         num_of_active_display++;
1371         }
1372
1373         smu_set_active_display_count(smu, num_of_active_display);
1374
1375         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1376                            display_config->cpu_cc6_disable,
1377                            display_config->cpu_pstate_disable,
1378                            display_config->nb_pstate_switch_disable);
1379
1380         mutex_unlock(&smu->mutex);
1381
1382         return 0;
1383 }
1384
1385 static int smu_get_clock_info(struct smu_context *smu,
1386                               struct smu_clock_info *clk_info,
1387                               enum smu_perf_level_designation designation)
1388 {
1389         int ret;
1390         struct smu_performance_level level = {0};
1391
1392         if (!clk_info)
1393                 return -EINVAL;
1394
1395         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1396         if (ret)
1397                 return -EINVAL;
1398
1399         clk_info->min_mem_clk = level.memory_clock;
1400         clk_info->min_eng_clk = level.core_clock;
1401         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1402
1403         ret = smu_get_perf_level(smu, designation, &level);
1404         if (ret)
1405                 return -EINVAL;
1406
1407         clk_info->min_mem_clk = level.memory_clock;
1408         clk_info->min_eng_clk = level.core_clock;
1409         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1410
1411         return 0;
1412 }
1413
1414 int smu_get_current_clocks(struct smu_context *smu,
1415                            struct amd_pp_clock_info *clocks)
1416 {
1417         struct amd_pp_simple_clock_info simple_clocks = {0};
1418         struct smu_clock_info hw_clocks;
1419         int ret = 0;
1420
1421         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1422                 return -EOPNOTSUPP;
1423
1424         mutex_lock(&smu->mutex);
1425
1426         smu_get_dal_power_level(smu, &simple_clocks);
1427
1428         if (smu->support_power_containment)
1429                 ret = smu_get_clock_info(smu, &hw_clocks,
1430                                          PERF_LEVEL_POWER_CONTAINMENT);
1431         else
1432                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1433
1434         if (ret) {
1435                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1436                 goto failed;
1437         }
1438
1439         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1440         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1441         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1442         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1443         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1444         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1445         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1446         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1447
1448         if (simple_clocks.level == 0)
1449                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1450         else
1451                 clocks->max_clocks_state = simple_clocks.level;
1452
1453         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1454                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1455                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1456         }
1457
1458 failed:
1459         mutex_unlock(&smu->mutex);
1460         return ret;
1461 }
1462
1463 static int smu_set_clockgating_state(void *handle,
1464                                      enum amd_clockgating_state state)
1465 {
1466         return 0;
1467 }
1468
1469 static int smu_set_powergating_state(void *handle,
1470                                      enum amd_powergating_state state)
1471 {
1472         return 0;
1473 }
1474
1475 static int smu_enable_umd_pstate(void *handle,
1476                       enum amd_dpm_forced_level *level)
1477 {
1478         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1479                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1480                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1481                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1482
1483         struct smu_context *smu = (struct smu_context*)(handle);
1484         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1485
1486         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1487                 return -EINVAL;
1488
1489         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1490                 /* enter umd pstate, save current level, disable gfx cg*/
1491                 if (*level & profile_mode_mask) {
1492                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1493                         smu_dpm_ctx->enable_umd_pstate = true;
1494                         amdgpu_device_ip_set_powergating_state(smu->adev,
1495                                                                AMD_IP_BLOCK_TYPE_GFX,
1496                                                                AMD_PG_STATE_UNGATE);
1497                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1498                                                                AMD_IP_BLOCK_TYPE_GFX,
1499                                                                AMD_CG_STATE_UNGATE);
1500                         smu_gfx_ulv_control(smu, false);
1501                         smu_deep_sleep_control(smu, false);
1502                 }
1503         } else {
1504                 /* exit umd pstate, restore level, enable gfx cg*/
1505                 if (!(*level & profile_mode_mask)) {
1506                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1507                                 *level = smu_dpm_ctx->saved_dpm_level;
1508                         smu_dpm_ctx->enable_umd_pstate = false;
1509                         smu_deep_sleep_control(smu, true);
1510                         smu_gfx_ulv_control(smu, true);
1511                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1512                                                                AMD_IP_BLOCK_TYPE_GFX,
1513                                                                AMD_CG_STATE_GATE);
1514                         amdgpu_device_ip_set_powergating_state(smu->adev,
1515                                                                AMD_IP_BLOCK_TYPE_GFX,
1516                                                                AMD_PG_STATE_GATE);
1517                 }
1518         }
1519
1520         return 0;
1521 }
1522
1523 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1524                                    enum amd_dpm_forced_level level,
1525                                    bool skip_display_settings)
1526 {
1527         int ret = 0;
1528         int index = 0;
1529         long workload;
1530         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1531
1532         if (!skip_display_settings) {
1533                 ret = smu_display_config_changed(smu);
1534                 if (ret) {
1535                         dev_err(smu->adev->dev, "Failed to change display config!");
1536                         return ret;
1537                 }
1538         }
1539
1540         ret = smu_apply_clocks_adjust_rules(smu);
1541         if (ret) {
1542                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1543                 return ret;
1544         }
1545
1546         if (!skip_display_settings) {
1547                 ret = smu_notify_smc_display_config(smu);
1548                 if (ret) {
1549                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1550                         return ret;
1551                 }
1552         }
1553
1554         if (smu_dpm_ctx->dpm_level != level) {
1555                 ret = smu_asic_set_performance_level(smu, level);
1556                 if (ret) {
1557                         dev_err(smu->adev->dev, "Failed to set performance level!");
1558                         return ret;
1559                 }
1560
1561                 /* update the saved copy */
1562                 smu_dpm_ctx->dpm_level = level;
1563         }
1564
1565         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1566                 index = fls(smu->workload_mask);
1567                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1568                 workload = smu->workload_setting[index];
1569
1570                 if (smu->power_profile_mode != workload)
1571                         smu_set_power_profile_mode(smu, &workload, 0, false);
1572         }
1573
1574         return ret;
1575 }
1576
1577 int smu_handle_task(struct smu_context *smu,
1578                     enum amd_dpm_forced_level level,
1579                     enum amd_pp_task task_id,
1580                     bool lock_needed)
1581 {
1582         int ret = 0;
1583
1584         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1585                 return -EOPNOTSUPP;
1586
1587         if (lock_needed)
1588                 mutex_lock(&smu->mutex);
1589
1590         switch (task_id) {
1591         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1592                 ret = smu_pre_display_config_changed(smu);
1593                 if (ret)
1594                         goto out;
1595                 ret = smu_set_cpu_power_state(smu);
1596                 if (ret)
1597                         goto out;
1598                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1599                 break;
1600         case AMD_PP_TASK_COMPLETE_INIT:
1601         case AMD_PP_TASK_READJUST_POWER_STATE:
1602                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1603                 break;
1604         default:
1605                 break;
1606         }
1607
1608 out:
1609         if (lock_needed)
1610                 mutex_unlock(&smu->mutex);
1611
1612         return ret;
1613 }
1614
1615 int smu_switch_power_profile(struct smu_context *smu,
1616                              enum PP_SMC_POWER_PROFILE type,
1617                              bool en)
1618 {
1619         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1620         long workload;
1621         uint32_t index;
1622
1623         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1624                 return -EOPNOTSUPP;
1625
1626         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1627                 return -EINVAL;
1628
1629         mutex_lock(&smu->mutex);
1630
1631         if (!en) {
1632                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1633                 index = fls(smu->workload_mask);
1634                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1635                 workload = smu->workload_setting[index];
1636         } else {
1637                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1638                 index = fls(smu->workload_mask);
1639                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1640                 workload = smu->workload_setting[index];
1641         }
1642
1643         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1644                 smu_set_power_profile_mode(smu, &workload, 0, false);
1645
1646         mutex_unlock(&smu->mutex);
1647
1648         return 0;
1649 }
1650
1651 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1652 {
1653         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1654         enum amd_dpm_forced_level level;
1655
1656         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1657                 return -EOPNOTSUPP;
1658
1659         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1660                 return -EINVAL;
1661
1662         mutex_lock(&(smu->mutex));
1663         level = smu_dpm_ctx->dpm_level;
1664         mutex_unlock(&(smu->mutex));
1665
1666         return level;
1667 }
1668
1669 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1670 {
1671         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1672         int ret = 0;
1673
1674         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1675                 return -EOPNOTSUPP;
1676
1677         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1678                 return -EINVAL;
1679
1680         mutex_lock(&smu->mutex);
1681
1682         ret = smu_enable_umd_pstate(smu, &level);
1683         if (ret) {
1684                 mutex_unlock(&smu->mutex);
1685                 return ret;
1686         }
1687
1688         ret = smu_handle_task(smu, level,
1689                               AMD_PP_TASK_READJUST_POWER_STATE,
1690                               false);
1691
1692         mutex_unlock(&smu->mutex);
1693
1694         return ret;
1695 }
1696
1697 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1698 {
1699         int ret = 0;
1700
1701         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1702                 return -EOPNOTSUPP;
1703
1704         mutex_lock(&smu->mutex);
1705         ret = smu_init_display_count(smu, count);
1706         mutex_unlock(&smu->mutex);
1707
1708         return ret;
1709 }
1710
1711 int smu_force_clk_levels(struct smu_context *smu,
1712                          enum smu_clk_type clk_type,
1713                          uint32_t mask)
1714 {
1715         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1716         int ret = 0;
1717
1718         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1719                 return -EOPNOTSUPP;
1720
1721         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1722                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1723                 return -EINVAL;
1724         }
1725
1726         mutex_lock(&smu->mutex);
1727
1728         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1729                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1730
1731         mutex_unlock(&smu->mutex);
1732
1733         return ret;
1734 }
1735
1736 /*
1737  * On system suspending or resetting, the dpm_enabled
1738  * flag will be cleared. So that those SMU services which
1739  * are not supported will be gated.
1740  * However, the mp1 state setting should still be granted
1741  * even if the dpm_enabled cleared.
1742  */
1743 int smu_set_mp1_state(struct smu_context *smu,
1744                       enum pp_mp1_state mp1_state)
1745 {
1746         uint16_t msg;
1747         int ret;
1748
1749         if (!smu->pm_enabled)
1750                 return -EOPNOTSUPP;
1751
1752         mutex_lock(&smu->mutex);
1753
1754         switch (mp1_state) {
1755         case PP_MP1_STATE_SHUTDOWN:
1756                 msg = SMU_MSG_PrepareMp1ForShutdown;
1757                 break;
1758         case PP_MP1_STATE_UNLOAD:
1759                 msg = SMU_MSG_PrepareMp1ForUnload;
1760                 break;
1761         case PP_MP1_STATE_RESET:
1762                 msg = SMU_MSG_PrepareMp1ForReset;
1763                 break;
1764         case PP_MP1_STATE_NONE:
1765         default:
1766                 mutex_unlock(&smu->mutex);
1767                 return 0;
1768         }
1769
1770         ret = smu_send_smc_msg(smu, msg, NULL);
1771         /* some asics may not support those messages */
1772         if (ret == -EINVAL)
1773                 ret = 0;
1774         if (ret)
1775                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1776
1777         mutex_unlock(&smu->mutex);
1778
1779         return ret;
1780 }
1781
1782 int smu_set_df_cstate(struct smu_context *smu,
1783                       enum pp_df_cstate state)
1784 {
1785         int ret = 0;
1786
1787         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1788                 return -EOPNOTSUPP;
1789
1790         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1791                 return 0;
1792
1793         mutex_lock(&smu->mutex);
1794
1795         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1796         if (ret)
1797                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1798
1799         mutex_unlock(&smu->mutex);
1800
1801         return ret;
1802 }
1803
1804 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1805 {
1806         int ret = 0;
1807
1808         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1809                 return -EOPNOTSUPP;
1810
1811         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1812                 return 0;
1813
1814         mutex_lock(&smu->mutex);
1815
1816         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1817         if (ret)
1818                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1819
1820         mutex_unlock(&smu->mutex);
1821
1822         return ret;
1823 }
1824
1825 int smu_write_watermarks_table(struct smu_context *smu)
1826 {
1827         int ret = 0;
1828
1829         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1830                 return -EOPNOTSUPP;
1831
1832         mutex_lock(&smu->mutex);
1833
1834         ret = smu_set_watermarks_table(smu, NULL);
1835
1836         mutex_unlock(&smu->mutex);
1837
1838         return ret;
1839 }
1840
1841 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1842                 struct pp_smu_wm_range_sets *clock_ranges)
1843 {
1844         int ret = 0;
1845
1846         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1847                 return -EOPNOTSUPP;
1848
1849         if (smu->disable_watermark)
1850                 return 0;
1851
1852         mutex_lock(&smu->mutex);
1853
1854         ret = smu_set_watermarks_table(smu, clock_ranges);
1855
1856         mutex_unlock(&smu->mutex);
1857
1858         return ret;
1859 }
1860
1861 int smu_set_ac_dc(struct smu_context *smu)
1862 {
1863         int ret = 0;
1864
1865         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1866                 return -EOPNOTSUPP;
1867
1868         /* controlled by firmware */
1869         if (smu->dc_controlled_by_gpio)
1870                 return 0;
1871
1872         mutex_lock(&smu->mutex);
1873         ret = smu_set_power_source(smu,
1874                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1875                                    SMU_POWER_SOURCE_DC);
1876         if (ret)
1877                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1878                        smu->adev->pm.ac_power ? "AC" : "DC");
1879         mutex_unlock(&smu->mutex);
1880
1881         return ret;
1882 }
1883
1884 const struct amd_ip_funcs smu_ip_funcs = {
1885         .name = "smu",
1886         .early_init = smu_early_init,
1887         .late_init = smu_late_init,
1888         .sw_init = smu_sw_init,
1889         .sw_fini = smu_sw_fini,
1890         .hw_init = smu_hw_init,
1891         .hw_fini = smu_hw_fini,
1892         .suspend = smu_suspend,
1893         .resume = smu_resume,
1894         .is_idle = NULL,
1895         .check_soft_reset = NULL,
1896         .wait_for_idle = NULL,
1897         .soft_reset = NULL,
1898         .set_clockgating_state = smu_set_clockgating_state,
1899         .set_powergating_state = smu_set_powergating_state,
1900         .enable_umd_pstate = smu_enable_umd_pstate,
1901 };
1902
1903 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1904 {
1905         .type = AMD_IP_BLOCK_TYPE_SMC,
1906         .major = 11,
1907         .minor = 0,
1908         .rev = 0,
1909         .funcs = &smu_ip_funcs,
1910 };
1911
1912 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1913 {
1914         .type = AMD_IP_BLOCK_TYPE_SMC,
1915         .major = 12,
1916         .minor = 0,
1917         .rev = 0,
1918         .funcs = &smu_ip_funcs,
1919 };
1920
1921 int smu_load_microcode(struct smu_context *smu)
1922 {
1923         int ret = 0;
1924
1925         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1926                 return -EOPNOTSUPP;
1927
1928         mutex_lock(&smu->mutex);
1929
1930         if (smu->ppt_funcs->load_microcode)
1931                 ret = smu->ppt_funcs->load_microcode(smu);
1932
1933         mutex_unlock(&smu->mutex);
1934
1935         return ret;
1936 }
1937
1938 int smu_check_fw_status(struct smu_context *smu)
1939 {
1940         int ret = 0;
1941
1942         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1943                 return -EOPNOTSUPP;
1944
1945         mutex_lock(&smu->mutex);
1946
1947         if (smu->ppt_funcs->check_fw_status)
1948                 ret = smu->ppt_funcs->check_fw_status(smu);
1949
1950         mutex_unlock(&smu->mutex);
1951
1952         return ret;
1953 }
1954
1955 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1956 {
1957         int ret = 0;
1958
1959         mutex_lock(&smu->mutex);
1960
1961         if (smu->ppt_funcs->set_gfx_cgpg)
1962                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1963
1964         mutex_unlock(&smu->mutex);
1965
1966         return ret;
1967 }
1968
1969 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1970 {
1971         int ret = 0;
1972
1973         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1974                 return -EOPNOTSUPP;
1975
1976         mutex_lock(&smu->mutex);
1977
1978         if (smu->ppt_funcs->set_fan_speed_rpm)
1979                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1980
1981         mutex_unlock(&smu->mutex);
1982
1983         return ret;
1984 }
1985
1986 int smu_get_power_limit(struct smu_context *smu,
1987                         uint32_t *limit,
1988                         bool max_setting)
1989 {
1990         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1991                 return -EOPNOTSUPP;
1992
1993         mutex_lock(&smu->mutex);
1994
1995         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1996
1997         mutex_unlock(&smu->mutex);
1998
1999         return 0;
2000 }
2001
2002 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2003 {
2004         int ret = 0;
2005
2006         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2007                 return -EOPNOTSUPP;
2008
2009         mutex_lock(&smu->mutex);
2010
2011         if (limit > smu->max_power_limit) {
2012                 dev_err(smu->adev->dev,
2013                         "New power limit (%d) is over the max allowed %d\n",
2014                         limit, smu->max_power_limit);
2015                 goto out;
2016         }
2017
2018         if (!limit)
2019                 limit = smu->current_power_limit;
2020
2021         if (smu->ppt_funcs->set_power_limit)
2022                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2023
2024 out:
2025         mutex_unlock(&smu->mutex);
2026
2027         return ret;
2028 }
2029
2030 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2031 {
2032         int ret = 0;
2033
2034         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2035                 return -EOPNOTSUPP;
2036
2037         mutex_lock(&smu->mutex);
2038
2039         if (smu->ppt_funcs->print_clk_levels)
2040                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2041
2042         mutex_unlock(&smu->mutex);
2043
2044         return ret;
2045 }
2046
2047 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2048 {
2049         int ret = 0;
2050
2051         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2052                 return -EOPNOTSUPP;
2053
2054         mutex_lock(&smu->mutex);
2055
2056         if (smu->ppt_funcs->get_od_percentage)
2057                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2058
2059         mutex_unlock(&smu->mutex);
2060
2061         return ret;
2062 }
2063
2064 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2065 {
2066         int ret = 0;
2067
2068         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2069                 return -EOPNOTSUPP;
2070
2071         mutex_lock(&smu->mutex);
2072
2073         if (smu->ppt_funcs->set_od_percentage)
2074                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2075
2076         mutex_unlock(&smu->mutex);
2077
2078         return ret;
2079 }
2080
2081 int smu_od_edit_dpm_table(struct smu_context *smu,
2082                           enum PP_OD_DPM_TABLE_COMMAND type,
2083                           long *input, uint32_t size)
2084 {
2085         int ret = 0;
2086
2087         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2088                 return -EOPNOTSUPP;
2089
2090         mutex_lock(&smu->mutex);
2091
2092         if (smu->ppt_funcs->od_edit_dpm_table) {
2093                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2094                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2095                         ret = smu_handle_task(smu,
2096                                               smu->smu_dpm.dpm_level,
2097                                               AMD_PP_TASK_READJUST_POWER_STATE,
2098                                               false);
2099         }
2100
2101         mutex_unlock(&smu->mutex);
2102
2103         return ret;
2104 }
2105
2106 int smu_read_sensor(struct smu_context *smu,
2107                     enum amd_pp_sensors sensor,
2108                     void *data, uint32_t *size)
2109 {
2110         struct smu_umd_pstate_table *pstate_table =
2111                                 &smu->pstate_table;
2112         int ret = 0;
2113
2114         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2115                 return -EOPNOTSUPP;
2116
2117         if (!data || !size)
2118                 return -EINVAL;
2119
2120         mutex_lock(&smu->mutex);
2121
2122         if (smu->ppt_funcs->read_sensor)
2123                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2124                         goto unlock;
2125
2126         switch (sensor) {
2127         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2128                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2129                 *size = 4;
2130                 break;
2131         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2132                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2133                 *size = 4;
2134                 break;
2135         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2136                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2137                 *size = 8;
2138                 break;
2139         case AMDGPU_PP_SENSOR_UVD_POWER:
2140                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2141                 *size = 4;
2142                 break;
2143         case AMDGPU_PP_SENSOR_VCE_POWER:
2144                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2145                 *size = 4;
2146                 break;
2147         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2148                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2149                 *size = 4;
2150                 break;
2151         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2152                 *(uint32_t *)data = 0;
2153                 *size = 4;
2154                 break;
2155         default:
2156                 *size = 0;
2157                 ret = -EOPNOTSUPP;
2158                 break;
2159         }
2160
2161 unlock:
2162         mutex_unlock(&smu->mutex);
2163
2164         return ret;
2165 }
2166
2167 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2168 {
2169         int ret = 0;
2170
2171         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2172                 return -EOPNOTSUPP;
2173
2174         mutex_lock(&smu->mutex);
2175
2176         if (smu->ppt_funcs->get_power_profile_mode)
2177                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2178
2179         mutex_unlock(&smu->mutex);
2180
2181         return ret;
2182 }
2183
2184 int smu_set_power_profile_mode(struct smu_context *smu,
2185                                long *param,
2186                                uint32_t param_size,
2187                                bool lock_needed)
2188 {
2189         int ret = 0;
2190
2191         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2192                 return -EOPNOTSUPP;
2193
2194         if (lock_needed)
2195                 mutex_lock(&smu->mutex);
2196
2197         if (smu->ppt_funcs->set_power_profile_mode)
2198                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2199
2200         if (lock_needed)
2201                 mutex_unlock(&smu->mutex);
2202
2203         return ret;
2204 }
2205
2206
2207 int smu_get_fan_control_mode(struct smu_context *smu)
2208 {
2209         int ret = 0;
2210
2211         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2212                 return -EOPNOTSUPP;
2213
2214         mutex_lock(&smu->mutex);
2215
2216         if (smu->ppt_funcs->get_fan_control_mode)
2217                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2218
2219         mutex_unlock(&smu->mutex);
2220
2221         return ret;
2222 }
2223
2224 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2225 {
2226         int ret = 0;
2227
2228         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2229                 return -EOPNOTSUPP;
2230
2231         mutex_lock(&smu->mutex);
2232
2233         if (smu->ppt_funcs->set_fan_control_mode)
2234                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2235
2236         mutex_unlock(&smu->mutex);
2237
2238         return ret;
2239 }
2240
2241 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2242 {
2243         int ret = 0;
2244         uint32_t percent;
2245         uint32_t current_rpm;
2246
2247         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2248                 return -EOPNOTSUPP;
2249
2250         mutex_lock(&smu->mutex);
2251
2252         if (smu->ppt_funcs->get_fan_speed_rpm) {
2253                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, &current_rpm);
2254                 if (!ret) {
2255                         percent = current_rpm * 100 / smu->fan_max_rpm;
2256                         *speed = percent > 100 ? 100 : percent;
2257                 }
2258         }
2259
2260         mutex_unlock(&smu->mutex);
2261
2262
2263         return ret;
2264 }
2265
2266 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2267 {
2268         int ret = 0;
2269         uint32_t rpm;
2270
2271         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2272                 return -EOPNOTSUPP;
2273
2274         mutex_lock(&smu->mutex);
2275
2276         if (smu->ppt_funcs->set_fan_speed_rpm) {
2277                 if (speed > 100)
2278                         speed = 100;
2279                 rpm = speed * smu->fan_max_rpm / 100;
2280                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
2281         }
2282
2283         mutex_unlock(&smu->mutex);
2284
2285         return ret;
2286 }
2287
2288 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2289 {
2290         int ret = 0;
2291
2292         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2293                 return -EOPNOTSUPP;
2294
2295         mutex_lock(&smu->mutex);
2296
2297         if (smu->ppt_funcs->get_fan_speed_rpm)
2298                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2299
2300         mutex_unlock(&smu->mutex);
2301
2302         return ret;
2303 }
2304
2305 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2306 {
2307         int ret = 0;
2308
2309         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2310                 return -EOPNOTSUPP;
2311
2312         mutex_lock(&smu->mutex);
2313
2314         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2315
2316         mutex_unlock(&smu->mutex);
2317
2318         return ret;
2319 }
2320
2321 int smu_get_clock_by_type(struct smu_context *smu,
2322                           enum amd_pp_clock_type type,
2323                           struct amd_pp_clocks *clocks)
2324 {
2325         int ret = 0;
2326
2327         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2328                 return -EOPNOTSUPP;
2329
2330         mutex_lock(&smu->mutex);
2331
2332         if (smu->ppt_funcs->get_clock_by_type)
2333                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2334
2335         mutex_unlock(&smu->mutex);
2336
2337         return ret;
2338 }
2339
2340 int smu_get_max_high_clocks(struct smu_context *smu,
2341                             struct amd_pp_simple_clock_info *clocks)
2342 {
2343         int ret = 0;
2344
2345         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2346                 return -EOPNOTSUPP;
2347
2348         mutex_lock(&smu->mutex);
2349
2350         if (smu->ppt_funcs->get_max_high_clocks)
2351                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2352
2353         mutex_unlock(&smu->mutex);
2354
2355         return ret;
2356 }
2357
2358 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2359                                        enum smu_clk_type clk_type,
2360                                        struct pp_clock_levels_with_latency *clocks)
2361 {
2362         int ret = 0;
2363
2364         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2365                 return -EOPNOTSUPP;
2366
2367         mutex_lock(&smu->mutex);
2368
2369         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2370                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2371
2372         mutex_unlock(&smu->mutex);
2373
2374         return ret;
2375 }
2376
2377 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2378                                        enum amd_pp_clock_type type,
2379                                        struct pp_clock_levels_with_voltage *clocks)
2380 {
2381         int ret = 0;
2382
2383         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2384                 return -EOPNOTSUPP;
2385
2386         mutex_lock(&smu->mutex);
2387
2388         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2389                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2390
2391         mutex_unlock(&smu->mutex);
2392
2393         return ret;
2394 }
2395
2396
2397 int smu_display_clock_voltage_request(struct smu_context *smu,
2398                                       struct pp_display_clock_request *clock_req)
2399 {
2400         int ret = 0;
2401
2402         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2403                 return -EOPNOTSUPP;
2404
2405         mutex_lock(&smu->mutex);
2406
2407         if (smu->ppt_funcs->display_clock_voltage_request)
2408                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2409
2410         mutex_unlock(&smu->mutex);
2411
2412         return ret;
2413 }
2414
2415
2416 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2417 {
2418         int ret = -EINVAL;
2419
2420         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2421                 return -EOPNOTSUPP;
2422
2423         mutex_lock(&smu->mutex);
2424
2425         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2426                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2427
2428         mutex_unlock(&smu->mutex);
2429
2430         return ret;
2431 }
2432
2433 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2434 {
2435         int ret = 0;
2436
2437         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2438                 return -EOPNOTSUPP;
2439
2440         mutex_lock(&smu->mutex);
2441
2442         if (smu->ppt_funcs->notify_smu_enable_pwe)
2443                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2444
2445         mutex_unlock(&smu->mutex);
2446
2447         return ret;
2448 }
2449
2450 int smu_set_xgmi_pstate(struct smu_context *smu,
2451                         uint32_t pstate)
2452 {
2453         int ret = 0;
2454
2455         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2456                 return -EOPNOTSUPP;
2457
2458         mutex_lock(&smu->mutex);
2459
2460         if (smu->ppt_funcs->set_xgmi_pstate)
2461                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2462
2463         mutex_unlock(&smu->mutex);
2464
2465         if(ret)
2466                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2467
2468         return ret;
2469 }
2470
2471 int smu_set_azalia_d3_pme(struct smu_context *smu)
2472 {
2473         int ret = 0;
2474
2475         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2476                 return -EOPNOTSUPP;
2477
2478         mutex_lock(&smu->mutex);
2479
2480         if (smu->ppt_funcs->set_azalia_d3_pme)
2481                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2482
2483         mutex_unlock(&smu->mutex);
2484
2485         return ret;
2486 }
2487
2488 /*
2489  * On system suspending or resetting, the dpm_enabled
2490  * flag will be cleared. So that those SMU services which
2491  * are not supported will be gated.
2492  *
2493  * However, the baco/mode1 reset should still be granted
2494  * as they are still supported and necessary.
2495  */
2496 bool smu_baco_is_support(struct smu_context *smu)
2497 {
2498         bool ret = false;
2499
2500         if (!smu->pm_enabled)
2501                 return false;
2502
2503         mutex_lock(&smu->mutex);
2504
2505         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2506                 ret = smu->ppt_funcs->baco_is_support(smu);
2507
2508         mutex_unlock(&smu->mutex);
2509
2510         return ret;
2511 }
2512
2513 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2514 {
2515         if (smu->ppt_funcs->baco_get_state)
2516                 return -EINVAL;
2517
2518         mutex_lock(&smu->mutex);
2519         *state = smu->ppt_funcs->baco_get_state(smu);
2520         mutex_unlock(&smu->mutex);
2521
2522         return 0;
2523 }
2524
2525 int smu_baco_enter(struct smu_context *smu)
2526 {
2527         int ret = 0;
2528
2529         if (!smu->pm_enabled)
2530                 return -EOPNOTSUPP;
2531
2532         mutex_lock(&smu->mutex);
2533
2534         if (smu->ppt_funcs->baco_enter)
2535                 ret = smu->ppt_funcs->baco_enter(smu);
2536
2537         mutex_unlock(&smu->mutex);
2538
2539         if (ret)
2540                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2541
2542         return ret;
2543 }
2544
2545 int smu_baco_exit(struct smu_context *smu)
2546 {
2547         int ret = 0;
2548
2549         if (!smu->pm_enabled)
2550                 return -EOPNOTSUPP;
2551
2552         mutex_lock(&smu->mutex);
2553
2554         if (smu->ppt_funcs->baco_exit)
2555                 ret = smu->ppt_funcs->baco_exit(smu);
2556
2557         mutex_unlock(&smu->mutex);
2558
2559         if (ret)
2560                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2561
2562         return ret;
2563 }
2564
2565 bool smu_mode1_reset_is_support(struct smu_context *smu)
2566 {
2567         bool ret = false;
2568
2569         if (!smu->pm_enabled)
2570                 return false;
2571
2572         mutex_lock(&smu->mutex);
2573
2574         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2575                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2576
2577         mutex_unlock(&smu->mutex);
2578
2579         return ret;
2580 }
2581
2582 int smu_mode1_reset(struct smu_context *smu)
2583 {
2584         int ret = 0;
2585
2586         if (!smu->pm_enabled)
2587                 return -EOPNOTSUPP;
2588
2589         mutex_lock(&smu->mutex);
2590
2591         if (smu->ppt_funcs->mode1_reset)
2592                 ret = smu->ppt_funcs->mode1_reset(smu);
2593
2594         mutex_unlock(&smu->mutex);
2595
2596         return ret;
2597 }
2598
2599 int smu_mode2_reset(struct smu_context *smu)
2600 {
2601         int ret = 0;
2602
2603         if (!smu->pm_enabled)
2604                 return -EOPNOTSUPP;
2605
2606         mutex_lock(&smu->mutex);
2607
2608         if (smu->ppt_funcs->mode2_reset)
2609                 ret = smu->ppt_funcs->mode2_reset(smu);
2610
2611         mutex_unlock(&smu->mutex);
2612
2613         if (ret)
2614                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2615
2616         return ret;
2617 }
2618
2619 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2620                                          struct pp_smu_nv_clock_table *max_clocks)
2621 {
2622         int ret = 0;
2623
2624         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2625                 return -EOPNOTSUPP;
2626
2627         mutex_lock(&smu->mutex);
2628
2629         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2630                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2631
2632         mutex_unlock(&smu->mutex);
2633
2634         return ret;
2635 }
2636
2637 int smu_get_uclk_dpm_states(struct smu_context *smu,
2638                             unsigned int *clock_values_in_khz,
2639                             unsigned int *num_states)
2640 {
2641         int ret = 0;
2642
2643         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2644                 return -EOPNOTSUPP;
2645
2646         mutex_lock(&smu->mutex);
2647
2648         if (smu->ppt_funcs->get_uclk_dpm_states)
2649                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2650
2651         mutex_unlock(&smu->mutex);
2652
2653         return ret;
2654 }
2655
2656 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2657 {
2658         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2659
2660         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2661                 return -EOPNOTSUPP;
2662
2663         mutex_lock(&smu->mutex);
2664
2665         if (smu->ppt_funcs->get_current_power_state)
2666                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2667
2668         mutex_unlock(&smu->mutex);
2669
2670         return pm_state;
2671 }
2672
2673 int smu_get_dpm_clock_table(struct smu_context *smu,
2674                             struct dpm_clocks *clock_table)
2675 {
2676         int ret = 0;
2677
2678         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2679                 return -EOPNOTSUPP;
2680
2681         mutex_lock(&smu->mutex);
2682
2683         if (smu->ppt_funcs->get_dpm_clock_table)
2684                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2685
2686         mutex_unlock(&smu->mutex);
2687
2688         return ret;
2689 }
2690
2691 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2692                                 void **table)
2693 {
2694         ssize_t size;
2695
2696         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2697                 return -EOPNOTSUPP;
2698
2699         if (!smu->ppt_funcs->get_gpu_metrics)
2700                 return -EOPNOTSUPP;
2701
2702         mutex_lock(&smu->mutex);
2703
2704         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2705
2706         mutex_unlock(&smu->mutex);
2707
2708         return size;
2709 }
2710
2711 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2712 {
2713         int ret = 0;
2714
2715         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2716                 return -EOPNOTSUPP;
2717
2718         mutex_lock(&smu->mutex);
2719
2720         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2721                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2722
2723         mutex_unlock(&smu->mutex);
2724
2725         return ret;
2726 }