drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 365
 366         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 367                                              SMU_FEATURE_MAX/32);
 368         if (ret)
 369                 return ret;
 370
 371         bitmap_or(feature->allowed, feature->allowed,
 372                       (unsigned long *)allowed_feature_mask,
 373                       feature->feature_num);
 374
 375         return ret;
 376 }
 377
 378 static int smu_set_funcs(struct amdgpu_device *adev)
 379 {
 380         struct smu_context *smu = &adev->smu;
 381
 382         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 383                 smu->od_enabled = true;
 384
 385         switch (adev->asic_type) {
 386         case CHIP_NAVI10:
 387         case CHIP_NAVI14:
 388         case CHIP_NAVI12:
 389                 navi10_set_ppt_funcs(smu);
 390                 break;
 391         case CHIP_ARCTURUS:
 392                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 393                 arcturus_set_ppt_funcs(smu);
 394                 /* OD is not supported on Arcturus */
 395                 smu->od_enabled =false;
 396                 break;
 397         case CHIP_SIENNA_CICHLID:
 398         case CHIP_NAVY_FLOUNDER:
 399                 sienna_cichlid_set_ppt_funcs(smu);
 400                 break;
 401         case CHIP_RENOIR:
 402                 renoir_set_ppt_funcs(smu);
 403                 break;
 404         default:
 405                 return -EINVAL;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int smu_early_init(void *handle)
 412 {
 413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 414         struct smu_context *smu = &adev->smu;
 415
 416         smu->adev = adev;
 417         smu->pm_enabled = !!amdgpu_dpm;
 418         smu->is_apu = false;
 419         mutex_init(&smu->mutex);
 420
 421         return smu_set_funcs(adev);
 422 }
 423
 424 static int smu_set_default_dpm_table(struct smu_context *smu)
 425 {
 426         struct smu_power_context *smu_power = &smu->smu_power;
 427         struct smu_power_gate *power_gate = &smu_power->power_gate;
 428         int vcn_gate, jpeg_gate;
 429         int ret = 0;
 430
 431         if (!smu->ppt_funcs->set_default_dpm_table)
 432                 return 0;
 433
 434         mutex_lock(&power_gate->vcn_gate_lock);
 435         mutex_lock(&power_gate->jpeg_gate_lock);
 436
 437         vcn_gate = atomic_read(&power_gate->vcn_gated);
 438         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 439
 440         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 441         if (ret)
 442                 goto err0_out;
 443
 444         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 445         if (ret)
 446                 goto err1_out;
 447
 448         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 449         if (ret)
 450                 dev_err(smu->adev->dev,
 451                         "Failed to setup default dpm clock tables!\n");
 452
 453         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 454 err1_out:
 455         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 456 err0_out:
 457         mutex_unlock(&power_gate->jpeg_gate_lock);
 458         mutex_unlock(&power_gate->vcn_gate_lock);
 459
 460         return ret;
 461 }
 462
 463 static int smu_late_init(void *handle)
 464 {
 465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 466         struct smu_context *smu = &adev->smu;
 467         int ret = 0;
 468
 469         if (!smu->pm_enabled)
 470                 return 0;
 471
 472         ret = smu_post_init(smu);
 473         if (ret) {
 474                 dev_err(adev->dev, "Failed to post smu init!\n");
 475                 return ret;
 476         }
 477
 478         ret = smu_set_default_od_settings(smu);
 479         if (ret) {
 480                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 481                 return ret;
 482         }
 483
 484         /*
 485          * Set initialized values (get from vbios) to dpm tables context such as
 486          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 487          * type of clks.
 488          */
 489         ret = smu_set_default_dpm_table(smu);
 490         if (ret) {
 491                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 492                 return ret;
 493         }
 494
 495         ret = smu_populate_umd_state_clk(smu);
 496         if (ret) {
 497                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 498                 return ret;
 499         }
 500
 501         ret = smu_get_asic_power_limits(smu);
 502         if (ret) {
 503                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 504                 return ret;
 505         }
 506
 507         smu_get_unique_id(smu);
 508
 509         smu_get_fan_parameters(smu);
 510
 511         smu_handle_task(&adev->smu,
 512                         smu->smu_dpm.dpm_level,
 513                         AMD_PP_TASK_COMPLETE_INIT,
 514                         false);
 515
 516         return 0;
 517 }
 518
 519 static int smu_init_fb_allocations(struct smu_context *smu)
 520 {
 521         struct amdgpu_device *adev = smu->adev;
 522         struct smu_table_context *smu_table = &smu->smu_table;
 523         struct smu_table *tables = smu_table->tables;
 524         struct smu_table *driver_table = &(smu_table->driver_table);
 525         uint32_t max_table_size = 0;
 526         int ret, i;
 527
 528         /* VRAM allocation for tool table */
 529         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 530                 ret = amdgpu_bo_create_kernel(adev,
 531                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 532                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 533                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 534                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 535                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 536                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 537                 if (ret) {
 538                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 539                         return ret;
 540                 }
 541         }
 542
 543         /* VRAM allocation for driver table */
 544         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 545                 if (tables[i].size == 0)
 546                         continue;
 547
 548                 if (i == SMU_TABLE_PMSTATUSLOG)
 549                         continue;
 550
 551                 if (max_table_size < tables[i].size)
 552                         max_table_size = tables[i].size;
 553         }
 554
 555         driver_table->size = max_table_size;
 556         driver_table->align = PAGE_SIZE;
 557         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 558
 559         ret = amdgpu_bo_create_kernel(adev,
 560                                       driver_table->size,
 561                                       driver_table->align,
 562                                       driver_table->domain,
 563                                       &driver_table->bo,
 564                                       &driver_table->mc_address,
 565                                       &driver_table->cpu_addr);
 566         if (ret) {
 567                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 568                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 569                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 570                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 571                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int smu_fini_fb_allocations(struct smu_context *smu)
 578 {
 579         struct smu_table_context *smu_table = &smu->smu_table;
 580         struct smu_table *tables = smu_table->tables;
 581         struct smu_table *driver_table = &(smu_table->driver_table);
 582
 583         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 584                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 585                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 586                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 587
 588         amdgpu_bo_free_kernel(&driver_table->bo,
 589                               &driver_table->mc_address,
 590                               &driver_table->cpu_addr);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * smu_alloc_memory_pool - allocate memory pool in the system memory
 597  *
 598  * @smu: amdgpu_device pointer
 599  *
 600  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 601  * and DramLogSetDramAddr can notify it changed.
 602  *
 603  * Returns 0 on success, error on failure.
 604  */
 605 static int smu_alloc_memory_pool(struct smu_context *smu)
 606 {
 607         struct amdgpu_device *adev = smu->adev;
 608         struct smu_table_context *smu_table = &smu->smu_table;
 609         struct smu_table *memory_pool = &smu_table->memory_pool;
 610         uint64_t pool_size = smu->pool_size;
 611         int ret = 0;
 612
 613         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 614                 return ret;
 615
 616         memory_pool->size = pool_size;
 617         memory_pool->align = PAGE_SIZE;
 618         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 619
 620         switch (pool_size) {
 621         case SMU_MEMORY_POOL_SIZE_256_MB:
 622         case SMU_MEMORY_POOL_SIZE_512_MB:
 623         case SMU_MEMORY_POOL_SIZE_1_GB:
 624         case SMU_MEMORY_POOL_SIZE_2_GB:
 625                 ret = amdgpu_bo_create_kernel(adev,
 626                                               memory_pool->size,
 627                                               memory_pool->align,
 628                                               memory_pool->domain,
 629                                               &memory_pool->bo,
 630                                               &memory_pool->mc_address,
 631                                               &memory_pool->cpu_addr);
 632                 if (ret)
 633                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 634                 break;
 635         default:
 636                 break;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static int smu_free_memory_pool(struct smu_context *smu)
 643 {
 644         struct smu_table_context *smu_table = &smu->smu_table;
 645         struct smu_table *memory_pool = &smu_table->memory_pool;
 646
 647         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 648                 return 0;
 649
 650         amdgpu_bo_free_kernel(&memory_pool->bo,
 651                               &memory_pool->mc_address,
 652                               &memory_pool->cpu_addr);
 653
 654         memset(memory_pool, 0, sizeof(struct smu_table));
 655
 656         return 0;
 657 }
 658
 659 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 660 {
 661         struct smu_table_context *smu_table = &smu->smu_table;
 662         struct smu_table *dummy_read_1_table =
 663                         &smu_table->dummy_read_1_table;
 664         struct amdgpu_device *adev = smu->adev;
 665         int ret = 0;
 666
 667         dummy_read_1_table->size = 0x40000;
 668         dummy_read_1_table->align = PAGE_SIZE;
 669         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 670
 671         ret = amdgpu_bo_create_kernel(adev,
 672                                       dummy_read_1_table->size,
 673                                       dummy_read_1_table->align,
 674                                       dummy_read_1_table->domain,
 675                                       &dummy_read_1_table->bo,
 676                                       &dummy_read_1_table->mc_address,
 677                                       &dummy_read_1_table->cpu_addr);
 678         if (ret)
 679                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 680
 681         return ret;
 682 }
 683
 684 static void smu_free_dummy_read_table(struct smu_context *smu)
 685 {
 686         struct smu_table_context *smu_table = &smu->smu_table;
 687         struct smu_table *dummy_read_1_table =
 688                         &smu_table->dummy_read_1_table;
 689
 690
 691         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 692                               &dummy_read_1_table->mc_address,
 693                               &dummy_read_1_table->cpu_addr);
 694
 695         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 696 }
 697
 698 static int smu_smc_table_sw_init(struct smu_context *smu)
 699 {
 700         int ret;
 701
 702         /**
 703          * Create smu_table structure, and init smc tables such as
 704          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 705          */
 706         ret = smu_init_smc_tables(smu);
 707         if (ret) {
 708                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 709                 return ret;
 710         }
 711
 712         /**
 713          * Create smu_power_context structure, and allocate smu_dpm_context and
 714          * context size to fill the smu_power_context data.
 715          */
 716         ret = smu_init_power(smu);
 717         if (ret) {
 718                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 719                 return ret;
 720         }
 721
 722         /*
 723          * allocate vram bos to store smc table contents.
 724          */
 725         ret = smu_init_fb_allocations(smu);
 726         if (ret)
 727                 return ret;
 728
 729         ret = smu_alloc_memory_pool(smu);
 730         if (ret)
 731                 return ret;
 732
 733         ret = smu_alloc_dummy_read_table(smu);
 734         if (ret)
 735                 return ret;
 736
 737         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 738         if (ret)
 739                 return ret;
 740
 741         return 0;
 742 }
 743
 744 static int smu_smc_table_sw_fini(struct smu_context *smu)
 745 {
 746         int ret;
 747
 748         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 749
 750         smu_free_dummy_read_table(smu);
 751
 752         ret = smu_free_memory_pool(smu);
 753         if (ret)
 754                 return ret;
 755
 756         ret = smu_fini_fb_allocations(smu);
 757         if (ret)
 758                 return ret;
 759
 760         ret = smu_fini_power(smu);
 761         if (ret) {
 762                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 763                 return ret;
 764         }
 765
 766         ret = smu_fini_smc_tables(smu);
 767         if (ret) {
 768                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 769                 return ret;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void smu_throttling_logging_work_fn(struct work_struct *work)
 776 {
 777         struct smu_context *smu = container_of(work, struct smu_context,
 778                                                throttling_logging_work);
 779
 780         smu_log_thermal_throttling(smu);
 781 }
 782
 783 static int smu_sw_init(void *handle)
 784 {
 785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 786         struct smu_context *smu = &adev->smu;
 787         int ret;
 788
 789         smu->pool_size = adev->pm.smu_prv_buffer_size;
 790         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 791         mutex_init(&smu->smu_feature.mutex);
 792         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 793         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 794         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 795
 796         mutex_init(&smu->smu_baco.mutex);
 797         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 798         smu->smu_baco.platform_support = false;
 799
 800         mutex_init(&smu->sensor_lock);
 801         mutex_init(&smu->metrics_lock);
 802         mutex_init(&smu->message_lock);
 803
 804         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 805         atomic64_set(&smu->throttle_int_counter, 0);
 806         smu->watermarks_bitmap = 0;
 807         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 808         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 809
 810         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 811         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 812         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 813         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 814
 815         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 816         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 817         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 818         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 819         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 820         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 821         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 822         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 823
 824         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 825         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 826         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 827         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 828         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 829         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 830         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 831         smu->display_config = &adev->pm.pm_display_cfg;
 832
 833         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 834         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 835         ret = smu_init_microcode(smu);
 836         if (ret) {
 837                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 838                 return ret;
 839         }
 840
 841         ret = smu_smc_table_sw_init(smu);
 842         if (ret) {
 843                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 844                 return ret;
 845         }
 846
 847         ret = smu_register_irq_handler(smu);
 848         if (ret) {
 849                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 850                 return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int smu_sw_fini(void *handle)
 857 {
 858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 859         struct smu_context *smu = &adev->smu;
 860         int ret;
 861
 862         ret = smu_smc_table_sw_fini(smu);
 863         if (ret) {
 864                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 865                 return ret;
 866         }
 867
 868         smu_fini_microcode(smu);
 869
 870         return 0;
 871 }
 872
 873 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 874 {
 875         struct amdgpu_device *adev = smu->adev;
 876         struct smu_temperature_range *range =
 877                                 &smu->thermal_range;
 878         int ret = 0;
 879
 880         if (!smu->ppt_funcs->get_thermal_temperature_range)
 881                 return 0;
 882
 883         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 884         if (ret)
 885                 return ret;
 886
 887         adev->pm.dpm.thermal.min_temp = range->min;
 888         adev->pm.dpm.thermal.max_temp = range->max;
 889         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 890         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 891         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 892         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 893         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 894         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 895         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 896
 897         return ret;
 898 }
 899
 900 static int smu_smc_hw_setup(struct smu_context *smu)
 901 {
 902         struct amdgpu_device *adev = smu->adev;
 903         uint32_t pcie_gen = 0, pcie_width = 0;
 904         int ret;
 905
 906         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 907                 dev_info(adev->dev, "dpm has been enabled\n");
 908                 return 0;
 909         }
 910
 911         ret = smu_init_display_count(smu, 0);
 912         if (ret) {
 913                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 914                 return ret;
 915         }
 916
 917         ret = smu_set_driver_table_location(smu);
 918         if (ret) {
 919                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 920                 return ret;
 921         }
 922
 923         /*
 924          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 925          */
 926         ret = smu_set_tool_table_location(smu);
 927         if (ret) {
 928                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 929                 return ret;
 930         }
 931
 932         /*
 933          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 934          * pool location.
 935          */
 936         ret = smu_notify_memory_pool_location(smu);
 937         if (ret) {
 938                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 939                 return ret;
 940         }
 941
 942         /* smu_dump_pptable(smu); */
 943         /*
 944          * Copy pptable bo in the vram to smc with SMU MSGs such as
 945          * SetDriverDramAddr and TransferTableDram2Smu.
 946          */
 947         ret = smu_write_pptable(smu);
 948         if (ret) {
 949                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 950                 return ret;
 951         }
 952
 953         /* issue Run*Btc msg */
 954         ret = smu_run_btc(smu);
 955         if (ret)
 956                 return ret;
 957
 958         ret = smu_feature_set_allowed_mask(smu);
 959         if (ret) {
 960                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 961                 return ret;
 962         }
 963
 964         ret = smu_system_features_control(smu, true);
 965         if (ret) {
 966                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 967                 return ret;
 968         }
 969
 970         if (!smu_is_dpm_running(smu))
 971                 dev_info(adev->dev, "dpm has been disabled\n");
 972
 973         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 974                 pcie_gen = 3;
 975         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 976                 pcie_gen = 2;
 977         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 978                 pcie_gen = 1;
 979         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 980                 pcie_gen = 0;
 981
 982         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 983          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 984          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 985          */
 986         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 987                 pcie_width = 6;
 988         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 989                 pcie_width = 5;
 990         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 991                 pcie_width = 4;
 992         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 993                 pcie_width = 3;
 994         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 995                 pcie_width = 2;
 996         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 997                 pcie_width = 1;
 998         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 999         if (ret) {
1000                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1001                 return ret;
1002         }
1003
1004         ret = smu_get_thermal_temperature_range(smu);
1005         if (ret) {
1006                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1007                 return ret;
1008         }
1009
1010         ret = smu_enable_thermal_alert(smu);
1011         if (ret) {
1012                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1013                 return ret;
1014         }
1015
1016         if (!smu->dc_controlled_by_gpio) {
1017                 /*
1018                  * For Navi1X, manually switch it to AC mode as PMFW
1019                  * may boot it with DC mode.
1020                  */
1021                 ret = smu_set_power_source(smu,
1022                                            adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1023                                            SMU_POWER_SOURCE_DC);
1024                 if (ret) {
1025                         dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1026                         return ret;
1027                 }
1028         }
1029
1030         ret = smu_notify_display_change(smu);
1031         if (ret)
1032                 return ret;
1033
1034         /*
1035          * Set min deep sleep dce fclk with bootup value from vbios via
1036          * SetMinDeepSleepDcefclk MSG.
1037          */
1038         ret = smu_set_min_dcef_deep_sleep(smu,
1039                                           smu->smu_table.boot_values.dcefclk / 100);
1040         if (ret)
1041                 return ret;
1042
1043         return ret;
1044 }
1045
1046 static int smu_start_smc_engine(struct smu_context *smu)
1047 {
1048         struct amdgpu_device *adev = smu->adev;
1049         int ret = 0;
1050
1051         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1052                 if (adev->asic_type < CHIP_NAVI10) {
1053                         if (smu->ppt_funcs->load_microcode) {
1054                                 ret = smu->ppt_funcs->load_microcode(smu);
1055                                 if (ret)
1056                                         return ret;
1057                         }
1058                 }
1059         }
1060
1061         if (smu->ppt_funcs->check_fw_status) {
1062                 ret = smu->ppt_funcs->check_fw_status(smu);
1063                 if (ret) {
1064                         dev_err(adev->dev, "SMC is not ready\n");
1065                         return ret;
1066                 }
1067         }
1068
1069         /*
1070          * Send msg GetDriverIfVersion to check if the return value is equal
1071          * with DRIVER_IF_VERSION of smc header.
1072          */
1073         ret = smu_check_fw_version(smu);
1074         if (ret)
1075                 return ret;
1076
1077         return ret;
1078 }
1079
1080 static int smu_hw_init(void *handle)
1081 {
1082         int ret;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084         struct smu_context *smu = &adev->smu;
1085
1086         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1087                 smu->pm_enabled = false;
1088                 return 0;
1089         }
1090
1091         ret = smu_start_smc_engine(smu);
1092         if (ret) {
1093                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1094                 return ret;
1095         }
1096
1097         if (smu->is_apu) {
1098                 smu_powergate_sdma(&adev->smu, false);
1099                 smu_dpm_set_vcn_enable(smu, true);
1100                 smu_dpm_set_jpeg_enable(smu, true);
1101                 smu_set_gfx_cgpg(&adev->smu, true);
1102         }
1103
1104         if (!smu->pm_enabled)
1105                 return 0;
1106
1107         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1108         ret = smu_get_vbios_bootup_values(smu);
1109         if (ret) {
1110                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1111                 return ret;
1112         }
1113
1114         ret = smu_setup_pptable(smu);
1115         if (ret) {
1116                 dev_err(adev->dev, "Failed to setup pptable!\n");
1117                 return ret;
1118         }
1119
1120         ret = smu_get_driver_allowed_feature_mask(smu);
1121         if (ret)
1122                 return ret;
1123
1124         ret = smu_smc_hw_setup(smu);
1125         if (ret) {
1126                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1127                 return ret;
1128         }
1129
1130         /*
1131          * Move maximum sustainable clock retrieving here considering
1132          * 1. It is not needed on resume(from S3).
1133          * 2. DAL settings come between .hw_init and .late_init of SMU.
1134          *    And DAL needs to know the maximum sustainable clocks. Thus
1135          *    it cannot be put in .late_init().
1136          */
1137         ret = smu_init_max_sustainable_clocks(smu);
1138         if (ret) {
1139                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1140                 return ret;
1141         }
1142
1143         adev->pm.dpm_enabled = true;
1144
1145         dev_info(adev->dev, "SMU is initialized successfully!\n");
1146
1147         return 0;
1148 }
1149
1150 static int smu_disable_dpms(struct smu_context *smu)
1151 {
1152         struct amdgpu_device *adev = smu->adev;
1153         int ret = 0;
1154         bool use_baco = !smu->is_apu &&
1155                 ((amdgpu_in_reset(adev) &&
1156                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1157                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1158
1159         /*
1160          * For custom pptable uploading, skip the DPM features
1161          * disable process on Navi1x ASICs.
1162          *   - As the gfx related features are under control of
1163          *     RLC on those ASICs. RLC reinitialization will be
1164          *     needed to reenable them. That will cost much more
1165          *     efforts.
1166          *
1167          *   - SMU firmware can handle the DPM reenablement
1168          *     properly.
1169          */
1170         if (smu->uploading_custom_pp_table &&
1171             (adev->asic_type >= CHIP_NAVI10) &&
1172             (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1173                 return 0;
1174
1175         /*
1176          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1177          * on BACO in. Driver involvement is unnecessary.
1178          */
1179         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1180              use_baco)
1181                 return 0;
1182
1183         /*
1184          * For gpu reset, runpm and hibernation through BACO,
1185          * BACO feature has to be kept enabled.
1186          */
1187         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1188                 ret = smu_disable_all_features_with_exception(smu,
1189                                                               SMU_FEATURE_BACO_BIT);
1190                 if (ret)
1191                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1192         } else {
1193                 ret = smu_system_features_control(smu, false);
1194                 if (ret)
1195                         dev_err(adev->dev, "Failed to disable smu features.\n");
1196         }
1197
1198         if (adev->asic_type >= CHIP_NAVI10 &&
1199             adev->gfx.rlc.funcs->stop)
1200                 adev->gfx.rlc.funcs->stop(adev);
1201
1202         return ret;
1203 }
1204
1205 static int smu_smc_hw_cleanup(struct smu_context *smu)
1206 {
1207         struct amdgpu_device *adev = smu->adev;
1208         int ret = 0;
1209
1210         cancel_work_sync(&smu->throttling_logging_work);
1211
1212         ret = smu_disable_thermal_alert(smu);
1213         if (ret) {
1214                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1215                 return ret;
1216         }
1217
1218         ret = smu_disable_dpms(smu);
1219         if (ret) {
1220                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1221                 return ret;
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int smu_hw_fini(void *handle)
1228 {
1229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230         struct smu_context *smu = &adev->smu;
1231         int ret = 0;
1232
1233         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1234                 return 0;
1235
1236         if (smu->is_apu) {
1237                 smu_powergate_sdma(&adev->smu, true);
1238                 smu_dpm_set_vcn_enable(smu, false);
1239                 smu_dpm_set_jpeg_enable(smu, false);
1240         }
1241
1242         if (!smu->pm_enabled)
1243                 return 0;
1244
1245         adev->pm.dpm_enabled = false;
1246
1247         ret = smu_smc_hw_cleanup(smu);
1248         if (ret)
1249                 return ret;
1250
1251         return 0;
1252 }
1253
1254 int smu_reset(struct smu_context *smu)
1255 {
1256         struct amdgpu_device *adev = smu->adev;
1257         int ret;
1258
1259         amdgpu_gfx_off_ctrl(smu->adev, false);
1260
1261         ret = smu_hw_fini(adev);
1262         if (ret)
1263                 return ret;
1264
1265         ret = smu_hw_init(adev);
1266         if (ret)
1267                 return ret;
1268
1269         ret = smu_late_init(adev);
1270         if (ret)
1271                 return ret;
1272
1273         amdgpu_gfx_off_ctrl(smu->adev, true);
1274
1275         return 0;
1276 }
1277
1278 static int smu_suspend(void *handle)
1279 {
1280         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281         struct smu_context *smu = &adev->smu;
1282         int ret;
1283
1284         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1285                 return 0;
1286
1287         if (!smu->pm_enabled)
1288                 return 0;
1289
1290         adev->pm.dpm_enabled = false;
1291
1292         ret = smu_smc_hw_cleanup(smu);
1293         if (ret)
1294                 return ret;
1295
1296         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1297
1298         if (smu->is_apu)
1299                 smu_set_gfx_cgpg(&adev->smu, false);
1300
1301         return 0;
1302 }
1303
1304 static int smu_resume(void *handle)
1305 {
1306         int ret;
1307         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308         struct smu_context *smu = &adev->smu;
1309
1310         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1311                 return 0;
1312
1313         if (!smu->pm_enabled)
1314                 return 0;
1315
1316         dev_info(adev->dev, "SMU is resuming...\n");
1317
1318         ret = smu_start_smc_engine(smu);
1319         if (ret) {
1320                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1321                 return ret;
1322         }
1323
1324         ret = smu_smc_hw_setup(smu);
1325         if (ret) {
1326                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1327                 return ret;
1328         }
1329
1330         if (smu->is_apu)
1331                 smu_set_gfx_cgpg(&adev->smu, true);
1332
1333         smu->disable_uclk_switch = 0;
1334
1335         adev->pm.dpm_enabled = true;
1336
1337         dev_info(adev->dev, "SMU is resumed successfully!\n");
1338
1339         return 0;
1340 }
1341
1342 int smu_display_configuration_change(struct smu_context *smu,
1343                                      const struct amd_pp_display_configuration *display_config)
1344 {
1345         int index = 0;
1346         int num_of_active_display = 0;
1347
1348         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1349                 return -EOPNOTSUPP;
1350
1351         if (!display_config)
1352                 return -EINVAL;
1353
1354         mutex_lock(&smu->mutex);
1355
1356         smu_set_min_dcef_deep_sleep(smu,
1357                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1358
1359         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1360                 if (display_config->displays[index].controller_id != 0)
1361                         num_of_active_display++;
1362         }
1363
1364         smu_set_active_display_count(smu, num_of_active_display);
1365
1366         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1367                            display_config->cpu_cc6_disable,
1368                            display_config->cpu_pstate_disable,
1369                            display_config->nb_pstate_switch_disable);
1370
1371         mutex_unlock(&smu->mutex);
1372
1373         return 0;
1374 }
1375
1376 static int smu_get_clock_info(struct smu_context *smu,
1377                               struct smu_clock_info *clk_info,
1378                               enum smu_perf_level_designation designation)
1379 {
1380         int ret;
1381         struct smu_performance_level level = {0};
1382
1383         if (!clk_info)
1384                 return -EINVAL;
1385
1386         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1387         if (ret)
1388                 return -EINVAL;
1389
1390         clk_info->min_mem_clk = level.memory_clock;
1391         clk_info->min_eng_clk = level.core_clock;
1392         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1393
1394         ret = smu_get_perf_level(smu, designation, &level);
1395         if (ret)
1396                 return -EINVAL;
1397
1398         clk_info->min_mem_clk = level.memory_clock;
1399         clk_info->min_eng_clk = level.core_clock;
1400         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1401
1402         return 0;
1403 }
1404
1405 int smu_get_current_clocks(struct smu_context *smu,
1406                            struct amd_pp_clock_info *clocks)
1407 {
1408         struct amd_pp_simple_clock_info simple_clocks = {0};
1409         struct smu_clock_info hw_clocks;
1410         int ret = 0;
1411
1412         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1413                 return -EOPNOTSUPP;
1414
1415         mutex_lock(&smu->mutex);
1416
1417         smu_get_dal_power_level(smu, &simple_clocks);
1418
1419         if (smu->support_power_containment)
1420                 ret = smu_get_clock_info(smu, &hw_clocks,
1421                                          PERF_LEVEL_POWER_CONTAINMENT);
1422         else
1423                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1424
1425         if (ret) {
1426                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1427                 goto failed;
1428         }
1429
1430         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1431         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1432         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1433         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1434         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1435         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1436         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1437         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1438
1439         if (simple_clocks.level == 0)
1440                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1441         else
1442                 clocks->max_clocks_state = simple_clocks.level;
1443
1444         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1445                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1446                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1447         }
1448
1449 failed:
1450         mutex_unlock(&smu->mutex);
1451         return ret;
1452 }
1453
1454 static int smu_set_clockgating_state(void *handle,
1455                                      enum amd_clockgating_state state)
1456 {
1457         return 0;
1458 }
1459
1460 static int smu_set_powergating_state(void *handle,
1461                                      enum amd_powergating_state state)
1462 {
1463         return 0;
1464 }
1465
1466 static int smu_enable_umd_pstate(void *handle,
1467                       enum amd_dpm_forced_level *level)
1468 {
1469         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1470                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1471                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1472                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1473
1474         struct smu_context *smu = (struct smu_context*)(handle);
1475         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1476
1477         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1478                 return -EINVAL;
1479
1480         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1481                 /* enter umd pstate, save current level, disable gfx cg*/
1482                 if (*level & profile_mode_mask) {
1483                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1484                         smu_dpm_ctx->enable_umd_pstate = true;
1485                         amdgpu_device_ip_set_powergating_state(smu->adev,
1486                                                                AMD_IP_BLOCK_TYPE_GFX,
1487                                                                AMD_PG_STATE_UNGATE);
1488                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1489                                                                AMD_IP_BLOCK_TYPE_GFX,
1490                                                                AMD_CG_STATE_UNGATE);
1491                         smu_gfx_ulv_control(smu, false);
1492                         smu_deep_sleep_control(smu, false);
1493                 }
1494         } else {
1495                 /* exit umd pstate, restore level, enable gfx cg*/
1496                 if (!(*level & profile_mode_mask)) {
1497                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1498                                 *level = smu_dpm_ctx->saved_dpm_level;
1499                         smu_dpm_ctx->enable_umd_pstate = false;
1500                         smu_deep_sleep_control(smu, true);
1501                         smu_gfx_ulv_control(smu, true);
1502                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1503                                                                AMD_IP_BLOCK_TYPE_GFX,
1504                                                                AMD_CG_STATE_GATE);
1505                         amdgpu_device_ip_set_powergating_state(smu->adev,
1506                                                                AMD_IP_BLOCK_TYPE_GFX,
1507                                                                AMD_PG_STATE_GATE);
1508                 }
1509         }
1510
1511         return 0;
1512 }
1513
1514 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1515                                    enum amd_dpm_forced_level level,
1516                                    bool skip_display_settings)
1517 {
1518         int ret = 0;
1519         int index = 0;
1520         long workload;
1521         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1522
1523         if (!skip_display_settings) {
1524                 ret = smu_display_config_changed(smu);
1525                 if (ret) {
1526                         dev_err(smu->adev->dev, "Failed to change display config!");
1527                         return ret;
1528                 }
1529         }
1530
1531         ret = smu_apply_clocks_adjust_rules(smu);
1532         if (ret) {
1533                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1534                 return ret;
1535         }
1536
1537         if (!skip_display_settings) {
1538                 ret = smu_notify_smc_display_config(smu);
1539                 if (ret) {
1540                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1541                         return ret;
1542                 }
1543         }
1544
1545         if (smu_dpm_ctx->dpm_level != level) {
1546                 ret = smu_asic_set_performance_level(smu, level);
1547                 if (ret) {
1548                         dev_err(smu->adev->dev, "Failed to set performance level!");
1549                         return ret;
1550                 }
1551
1552                 /* update the saved copy */
1553                 smu_dpm_ctx->dpm_level = level;
1554         }
1555
1556         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1557                 index = fls(smu->workload_mask);
1558                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1559                 workload = smu->workload_setting[index];
1560
1561                 if (smu->power_profile_mode != workload)
1562                         smu_set_power_profile_mode(smu, &workload, 0, false);
1563         }
1564
1565         return ret;
1566 }
1567
1568 int smu_handle_task(struct smu_context *smu,
1569                     enum amd_dpm_forced_level level,
1570                     enum amd_pp_task task_id,
1571                     bool lock_needed)
1572 {
1573         int ret = 0;
1574
1575         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1576                 return -EOPNOTSUPP;
1577
1578         if (lock_needed)
1579                 mutex_lock(&smu->mutex);
1580
1581         switch (task_id) {
1582         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1583                 ret = smu_pre_display_config_changed(smu);
1584                 if (ret)
1585                         goto out;
1586                 ret = smu_set_cpu_power_state(smu);
1587                 if (ret)
1588                         goto out;
1589                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1590                 break;
1591         case AMD_PP_TASK_COMPLETE_INIT:
1592         case AMD_PP_TASK_READJUST_POWER_STATE:
1593                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1594                 break;
1595         default:
1596                 break;
1597         }
1598
1599 out:
1600         if (lock_needed)
1601                 mutex_unlock(&smu->mutex);
1602
1603         return ret;
1604 }
1605
1606 int smu_switch_power_profile(struct smu_context *smu,
1607                              enum PP_SMC_POWER_PROFILE type,
1608                              bool en)
1609 {
1610         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1611         long workload;
1612         uint32_t index;
1613
1614         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1615                 return -EOPNOTSUPP;
1616
1617         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1618                 return -EINVAL;
1619
1620         mutex_lock(&smu->mutex);
1621
1622         if (!en) {
1623                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1624                 index = fls(smu->workload_mask);
1625                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1626                 workload = smu->workload_setting[index];
1627         } else {
1628                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1629                 index = fls(smu->workload_mask);
1630                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1631                 workload = smu->workload_setting[index];
1632         }
1633
1634         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1635                 smu_set_power_profile_mode(smu, &workload, 0, false);
1636
1637         mutex_unlock(&smu->mutex);
1638
1639         return 0;
1640 }
1641
1642 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1643 {
1644         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1645         enum amd_dpm_forced_level level;
1646
1647         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1648                 return -EOPNOTSUPP;
1649
1650         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1651                 return -EINVAL;
1652
1653         mutex_lock(&(smu->mutex));
1654         level = smu_dpm_ctx->dpm_level;
1655         mutex_unlock(&(smu->mutex));
1656
1657         return level;
1658 }
1659
1660 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1661 {
1662         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1663         int ret = 0;
1664
1665         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1666                 return -EOPNOTSUPP;
1667
1668         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1669                 return -EINVAL;
1670
1671         mutex_lock(&smu->mutex);
1672
1673         ret = smu_enable_umd_pstate(smu, &level);
1674         if (ret) {
1675                 mutex_unlock(&smu->mutex);
1676                 return ret;
1677         }
1678
1679         ret = smu_handle_task(smu, level,
1680                               AMD_PP_TASK_READJUST_POWER_STATE,
1681                               false);
1682
1683         mutex_unlock(&smu->mutex);
1684
1685         return ret;
1686 }
1687
1688 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1689 {
1690         int ret = 0;
1691
1692         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1693                 return -EOPNOTSUPP;
1694
1695         mutex_lock(&smu->mutex);
1696         ret = smu_init_display_count(smu, count);
1697         mutex_unlock(&smu->mutex);
1698
1699         return ret;
1700 }
1701
1702 int smu_force_clk_levels(struct smu_context *smu,
1703                          enum smu_clk_type clk_type,
1704                          uint32_t mask)
1705 {
1706         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1707         int ret = 0;
1708
1709         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1710                 return -EOPNOTSUPP;
1711
1712         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1713                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1714                 return -EINVAL;
1715         }
1716
1717         mutex_lock(&smu->mutex);
1718
1719         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1720                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1721
1722         mutex_unlock(&smu->mutex);
1723
1724         return ret;
1725 }
1726
1727 /*
1728  * On system suspending or resetting, the dpm_enabled
1729  * flag will be cleared. So that those SMU services which
1730  * are not supported will be gated.
1731  * However, the mp1 state setting should still be granted
1732  * even if the dpm_enabled cleared.
1733  */
1734 int smu_set_mp1_state(struct smu_context *smu,
1735                       enum pp_mp1_state mp1_state)
1736 {
1737         uint16_t msg;
1738         int ret;
1739
1740         if (!smu->pm_enabled)
1741                 return -EOPNOTSUPP;
1742
1743         mutex_lock(&smu->mutex);
1744
1745         switch (mp1_state) {
1746         case PP_MP1_STATE_SHUTDOWN:
1747                 msg = SMU_MSG_PrepareMp1ForShutdown;
1748                 break;
1749         case PP_MP1_STATE_UNLOAD:
1750                 msg = SMU_MSG_PrepareMp1ForUnload;
1751                 break;
1752         case PP_MP1_STATE_RESET:
1753                 msg = SMU_MSG_PrepareMp1ForReset;
1754                 break;
1755         case PP_MP1_STATE_NONE:
1756         default:
1757                 mutex_unlock(&smu->mutex);
1758                 return 0;
1759         }
1760
1761         ret = smu_send_smc_msg(smu, msg, NULL);
1762         /* some asics may not support those messages */
1763         if (ret == -EINVAL)
1764                 ret = 0;
1765         if (ret)
1766                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1767
1768         mutex_unlock(&smu->mutex);
1769
1770         return ret;
1771 }
1772
1773 int smu_set_df_cstate(struct smu_context *smu,
1774                       enum pp_df_cstate state)
1775 {
1776         int ret = 0;
1777
1778         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1779                 return -EOPNOTSUPP;
1780
1781         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1782                 return 0;
1783
1784         mutex_lock(&smu->mutex);
1785
1786         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1787         if (ret)
1788                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1789
1790         mutex_unlock(&smu->mutex);
1791
1792         return ret;
1793 }
1794
1795 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1796 {
1797         int ret = 0;
1798
1799         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1800                 return -EOPNOTSUPP;
1801
1802         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1803                 return 0;
1804
1805         mutex_lock(&smu->mutex);
1806
1807         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1808         if (ret)
1809                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1810
1811         mutex_unlock(&smu->mutex);
1812
1813         return ret;
1814 }
1815
1816 int smu_write_watermarks_table(struct smu_context *smu)
1817 {
1818         int ret = 0;
1819
1820         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1821                 return -EOPNOTSUPP;
1822
1823         mutex_lock(&smu->mutex);
1824
1825         ret = smu_set_watermarks_table(smu, NULL);
1826
1827         mutex_unlock(&smu->mutex);
1828
1829         return ret;
1830 }
1831
1832 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1833                 struct pp_smu_wm_range_sets *clock_ranges)
1834 {
1835         int ret = 0;
1836
1837         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1838                 return -EOPNOTSUPP;
1839
1840         mutex_lock(&smu->mutex);
1841
1842         if (!smu->disable_watermark &&
1843                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1844                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1845                 ret = smu_set_watermarks_table(smu, clock_ranges);
1846
1847                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1848                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1849                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1850                 }
1851         }
1852
1853         mutex_unlock(&smu->mutex);
1854
1855         return ret;
1856 }
1857
1858 int smu_set_ac_dc(struct smu_context *smu)
1859 {
1860         int ret = 0;
1861
1862         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1863                 return -EOPNOTSUPP;
1864
1865         /* controlled by firmware */
1866         if (smu->dc_controlled_by_gpio)
1867                 return 0;
1868
1869         mutex_lock(&smu->mutex);
1870         ret = smu_set_power_source(smu,
1871                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1872                                    SMU_POWER_SOURCE_DC);
1873         if (ret)
1874                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1875                        smu->adev->pm.ac_power ? "AC" : "DC");
1876         mutex_unlock(&smu->mutex);
1877
1878         return ret;
1879 }
1880
1881 const struct amd_ip_funcs smu_ip_funcs = {
1882         .name = "smu",
1883         .early_init = smu_early_init,
1884         .late_init = smu_late_init,
1885         .sw_init = smu_sw_init,
1886         .sw_fini = smu_sw_fini,
1887         .hw_init = smu_hw_init,
1888         .hw_fini = smu_hw_fini,
1889         .suspend = smu_suspend,
1890         .resume = smu_resume,
1891         .is_idle = NULL,
1892         .check_soft_reset = NULL,
1893         .wait_for_idle = NULL,
1894         .soft_reset = NULL,
1895         .set_clockgating_state = smu_set_clockgating_state,
1896         .set_powergating_state = smu_set_powergating_state,
1897         .enable_umd_pstate = smu_enable_umd_pstate,
1898 };
1899
1900 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1901 {
1902         .type = AMD_IP_BLOCK_TYPE_SMC,
1903         .major = 11,
1904         .minor = 0,
1905         .rev = 0,
1906         .funcs = &smu_ip_funcs,
1907 };
1908
1909 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1910 {
1911         .type = AMD_IP_BLOCK_TYPE_SMC,
1912         .major = 12,
1913         .minor = 0,
1914         .rev = 0,
1915         .funcs = &smu_ip_funcs,
1916 };
1917
1918 int smu_load_microcode(struct smu_context *smu)
1919 {
1920         int ret = 0;
1921
1922         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1923                 return -EOPNOTSUPP;
1924
1925         mutex_lock(&smu->mutex);
1926
1927         if (smu->ppt_funcs->load_microcode)
1928                 ret = smu->ppt_funcs->load_microcode(smu);
1929
1930         mutex_unlock(&smu->mutex);
1931
1932         return ret;
1933 }
1934
1935 int smu_check_fw_status(struct smu_context *smu)
1936 {
1937         int ret = 0;
1938
1939         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1940                 return -EOPNOTSUPP;
1941
1942         mutex_lock(&smu->mutex);
1943
1944         if (smu->ppt_funcs->check_fw_status)
1945                 ret = smu->ppt_funcs->check_fw_status(smu);
1946
1947         mutex_unlock(&smu->mutex);
1948
1949         return ret;
1950 }
1951
1952 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1953 {
1954         int ret = 0;
1955
1956         mutex_lock(&smu->mutex);
1957
1958         if (smu->ppt_funcs->set_gfx_cgpg)
1959                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1960
1961         mutex_unlock(&smu->mutex);
1962
1963         return ret;
1964 }
1965
1966 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1967 {
1968         int ret = 0;
1969
1970         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1971                 return -EOPNOTSUPP;
1972
1973         mutex_lock(&smu->mutex);
1974
1975         if (smu->ppt_funcs->set_fan_speed_rpm)
1976                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1977
1978         mutex_unlock(&smu->mutex);
1979
1980         return ret;
1981 }
1982
1983 int smu_get_power_limit(struct smu_context *smu,
1984                         uint32_t *limit,
1985                         bool max_setting)
1986 {
1987         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1988                 return -EOPNOTSUPP;
1989
1990         mutex_lock(&smu->mutex);
1991
1992         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1993
1994         mutex_unlock(&smu->mutex);
1995
1996         return 0;
1997 }
1998
1999 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2000 {
2001         int ret = 0;
2002
2003         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2004                 return -EOPNOTSUPP;
2005
2006         mutex_lock(&smu->mutex);
2007
2008         if (limit > smu->max_power_limit) {
2009                 dev_err(smu->adev->dev,
2010                         "New power limit (%d) is over the max allowed %d\n",
2011                         limit, smu->max_power_limit);
2012                 goto out;
2013         }
2014
2015         if (!limit)
2016                 limit = smu->current_power_limit;
2017
2018         if (smu->ppt_funcs->set_power_limit)
2019                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2020
2021 out:
2022         mutex_unlock(&smu->mutex);
2023
2024         return ret;
2025 }
2026
2027 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2028 {
2029         int ret = 0;
2030
2031         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2032                 return -EOPNOTSUPP;
2033
2034         mutex_lock(&smu->mutex);
2035
2036         if (smu->ppt_funcs->print_clk_levels)
2037                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2038
2039         mutex_unlock(&smu->mutex);
2040
2041         return ret;
2042 }
2043
2044 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2045 {
2046         int ret = 0;
2047
2048         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2049                 return -EOPNOTSUPP;
2050
2051         mutex_lock(&smu->mutex);
2052
2053         if (smu->ppt_funcs->get_od_percentage)
2054                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2055
2056         mutex_unlock(&smu->mutex);
2057
2058         return ret;
2059 }
2060
2061 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2062 {
2063         int ret = 0;
2064
2065         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2066                 return -EOPNOTSUPP;
2067
2068         mutex_lock(&smu->mutex);
2069
2070         if (smu->ppt_funcs->set_od_percentage)
2071                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2072
2073         mutex_unlock(&smu->mutex);
2074
2075         return ret;
2076 }
2077
2078 int smu_od_edit_dpm_table(struct smu_context *smu,
2079                           enum PP_OD_DPM_TABLE_COMMAND type,
2080                           long *input, uint32_t size)
2081 {
2082         int ret = 0;
2083
2084         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2085                 return -EOPNOTSUPP;
2086
2087         mutex_lock(&smu->mutex);
2088
2089         if (smu->ppt_funcs->od_edit_dpm_table) {
2090                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2091                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2092                         ret = smu_handle_task(smu,
2093                                               smu->smu_dpm.dpm_level,
2094                                               AMD_PP_TASK_READJUST_POWER_STATE,
2095                                               false);
2096         }
2097
2098         mutex_unlock(&smu->mutex);
2099
2100         return ret;
2101 }
2102
2103 int smu_read_sensor(struct smu_context *smu,
2104                     enum amd_pp_sensors sensor,
2105                     void *data, uint32_t *size)
2106 {
2107         struct smu_umd_pstate_table *pstate_table =
2108                                 &smu->pstate_table;
2109         int ret = 0;
2110
2111         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2112                 return -EOPNOTSUPP;
2113
2114         if (!data || !size)
2115                 return -EINVAL;
2116
2117         mutex_lock(&smu->mutex);
2118
2119         if (smu->ppt_funcs->read_sensor)
2120                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2121                         goto unlock;
2122
2123         switch (sensor) {
2124         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2125                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2126                 *size = 4;
2127                 break;
2128         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2129                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2130                 *size = 4;
2131                 break;
2132         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2133                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2134                 *size = 8;
2135                 break;
2136         case AMDGPU_PP_SENSOR_UVD_POWER:
2137                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2138                 *size = 4;
2139                 break;
2140         case AMDGPU_PP_SENSOR_VCE_POWER:
2141                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2142                 *size = 4;
2143                 break;
2144         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2145                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2146                 *size = 4;
2147                 break;
2148         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2149                 *(uint32_t *)data = 0;
2150                 *size = 4;
2151                 break;
2152         default:
2153                 *size = 0;
2154                 ret = -EOPNOTSUPP;
2155                 break;
2156         }
2157
2158 unlock:
2159         mutex_unlock(&smu->mutex);
2160
2161         return ret;
2162 }
2163
2164 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2165 {
2166         int ret = 0;
2167
2168         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2169                 return -EOPNOTSUPP;
2170
2171         mutex_lock(&smu->mutex);
2172
2173         if (smu->ppt_funcs->get_power_profile_mode)
2174                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2175
2176         mutex_unlock(&smu->mutex);
2177
2178         return ret;
2179 }
2180
2181 int smu_set_power_profile_mode(struct smu_context *smu,
2182                                long *param,
2183                                uint32_t param_size,
2184                                bool lock_needed)
2185 {
2186         int ret = 0;
2187
2188         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2189                 return -EOPNOTSUPP;
2190
2191         if (lock_needed)
2192                 mutex_lock(&smu->mutex);
2193
2194         if (smu->ppt_funcs->set_power_profile_mode)
2195                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2196
2197         if (lock_needed)
2198                 mutex_unlock(&smu->mutex);
2199
2200         return ret;
2201 }
2202
2203
2204 int smu_get_fan_control_mode(struct smu_context *smu)
2205 {
2206         int ret = 0;
2207
2208         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2209                 return -EOPNOTSUPP;
2210
2211         mutex_lock(&smu->mutex);
2212
2213         if (smu->ppt_funcs->get_fan_control_mode)
2214                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2215
2216         mutex_unlock(&smu->mutex);
2217
2218         return ret;
2219 }
2220
2221 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2222 {
2223         int ret = 0;
2224
2225         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2226                 return -EOPNOTSUPP;
2227
2228         mutex_lock(&smu->mutex);
2229
2230         if (smu->ppt_funcs->set_fan_control_mode)
2231                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2232
2233         mutex_unlock(&smu->mutex);
2234
2235         return ret;
2236 }
2237
2238 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2239 {
2240         int ret = 0;
2241         uint32_t percent;
2242         uint32_t current_rpm;
2243
2244         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2245                 return -EOPNOTSUPP;
2246
2247         mutex_lock(&smu->mutex);
2248
2249         if (smu->ppt_funcs->get_fan_speed_rpm) {
2250                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, &current_rpm);
2251                 if (!ret) {
2252                         percent = current_rpm * 100 / smu->fan_max_rpm;
2253                         *speed = percent > 100 ? 100 : percent;
2254                 }
2255         }
2256
2257         mutex_unlock(&smu->mutex);
2258
2259
2260         return ret;
2261 }
2262
2263 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2264 {
2265         int ret = 0;
2266         uint32_t rpm;
2267
2268         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2269                 return -EOPNOTSUPP;
2270
2271         mutex_lock(&smu->mutex);
2272
2273         if (smu->ppt_funcs->set_fan_speed_rpm) {
2274                 if (speed > 100)
2275                         speed = 100;
2276                 rpm = speed * smu->fan_max_rpm / 100;
2277                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
2278         }
2279
2280         mutex_unlock(&smu->mutex);
2281
2282         return ret;
2283 }
2284
2285 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2286 {
2287         int ret = 0;
2288
2289         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2290                 return -EOPNOTSUPP;
2291
2292         mutex_lock(&smu->mutex);
2293
2294         if (smu->ppt_funcs->get_fan_speed_rpm)
2295                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2296
2297         mutex_unlock(&smu->mutex);
2298
2299         return ret;
2300 }
2301
2302 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2303 {
2304         int ret = 0;
2305
2306         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2307                 return -EOPNOTSUPP;
2308
2309         mutex_lock(&smu->mutex);
2310
2311         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2312
2313         mutex_unlock(&smu->mutex);
2314
2315         return ret;
2316 }
2317
2318 int smu_get_clock_by_type(struct smu_context *smu,
2319                           enum amd_pp_clock_type type,
2320                           struct amd_pp_clocks *clocks)
2321 {
2322         int ret = 0;
2323
2324         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2325                 return -EOPNOTSUPP;
2326
2327         mutex_lock(&smu->mutex);
2328
2329         if (smu->ppt_funcs->get_clock_by_type)
2330                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2331
2332         mutex_unlock(&smu->mutex);
2333
2334         return ret;
2335 }
2336
2337 int smu_get_max_high_clocks(struct smu_context *smu,
2338                             struct amd_pp_simple_clock_info *clocks)
2339 {
2340         int ret = 0;
2341
2342         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2343                 return -EOPNOTSUPP;
2344
2345         mutex_lock(&smu->mutex);
2346
2347         if (smu->ppt_funcs->get_max_high_clocks)
2348                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2349
2350         mutex_unlock(&smu->mutex);
2351
2352         return ret;
2353 }
2354
2355 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2356                                        enum smu_clk_type clk_type,
2357                                        struct pp_clock_levels_with_latency *clocks)
2358 {
2359         int ret = 0;
2360
2361         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2362                 return -EOPNOTSUPP;
2363
2364         mutex_lock(&smu->mutex);
2365
2366         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2367                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2368
2369         mutex_unlock(&smu->mutex);
2370
2371         return ret;
2372 }
2373
2374 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2375                                        enum amd_pp_clock_type type,
2376                                        struct pp_clock_levels_with_voltage *clocks)
2377 {
2378         int ret = 0;
2379
2380         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2381                 return -EOPNOTSUPP;
2382
2383         mutex_lock(&smu->mutex);
2384
2385         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2386                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2387
2388         mutex_unlock(&smu->mutex);
2389
2390         return ret;
2391 }
2392
2393
2394 int smu_display_clock_voltage_request(struct smu_context *smu,
2395                                       struct pp_display_clock_request *clock_req)
2396 {
2397         int ret = 0;
2398
2399         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2400                 return -EOPNOTSUPP;
2401
2402         mutex_lock(&smu->mutex);
2403
2404         if (smu->ppt_funcs->display_clock_voltage_request)
2405                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2406
2407         mutex_unlock(&smu->mutex);
2408
2409         return ret;
2410 }
2411
2412
2413 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2414 {
2415         int ret = -EINVAL;
2416
2417         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2418                 return -EOPNOTSUPP;
2419
2420         mutex_lock(&smu->mutex);
2421
2422         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2423                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2424
2425         mutex_unlock(&smu->mutex);
2426
2427         return ret;
2428 }
2429
2430 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2431 {
2432         int ret = 0;
2433
2434         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2435                 return -EOPNOTSUPP;
2436
2437         mutex_lock(&smu->mutex);
2438
2439         if (smu->ppt_funcs->notify_smu_enable_pwe)
2440                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2441
2442         mutex_unlock(&smu->mutex);
2443
2444         return ret;
2445 }
2446
2447 int smu_set_xgmi_pstate(struct smu_context *smu,
2448                         uint32_t pstate)
2449 {
2450         int ret = 0;
2451
2452         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2453                 return -EOPNOTSUPP;
2454
2455         mutex_lock(&smu->mutex);
2456
2457         if (smu->ppt_funcs->set_xgmi_pstate)
2458                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2459
2460         mutex_unlock(&smu->mutex);
2461
2462         if(ret)
2463                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2464
2465         return ret;
2466 }
2467
2468 int smu_set_azalia_d3_pme(struct smu_context *smu)
2469 {
2470         int ret = 0;
2471
2472         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2473                 return -EOPNOTSUPP;
2474
2475         mutex_lock(&smu->mutex);
2476
2477         if (smu->ppt_funcs->set_azalia_d3_pme)
2478                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2479
2480         mutex_unlock(&smu->mutex);
2481
2482         return ret;
2483 }
2484
2485 /*
2486  * On system suspending or resetting, the dpm_enabled
2487  * flag will be cleared. So that those SMU services which
2488  * are not supported will be gated.
2489  *
2490  * However, the baco/mode1 reset should still be granted
2491  * as they are still supported and necessary.
2492  */
2493 bool smu_baco_is_support(struct smu_context *smu)
2494 {
2495         bool ret = false;
2496
2497         if (!smu->pm_enabled)
2498                 return false;
2499
2500         mutex_lock(&smu->mutex);
2501
2502         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2503                 ret = smu->ppt_funcs->baco_is_support(smu);
2504
2505         mutex_unlock(&smu->mutex);
2506
2507         return ret;
2508 }
2509
2510 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2511 {
2512         if (smu->ppt_funcs->baco_get_state)
2513                 return -EINVAL;
2514
2515         mutex_lock(&smu->mutex);
2516         *state = smu->ppt_funcs->baco_get_state(smu);
2517         mutex_unlock(&smu->mutex);
2518
2519         return 0;
2520 }
2521
2522 int smu_baco_enter(struct smu_context *smu)
2523 {
2524         int ret = 0;
2525
2526         if (!smu->pm_enabled)
2527                 return -EOPNOTSUPP;
2528
2529         mutex_lock(&smu->mutex);
2530
2531         if (smu->ppt_funcs->baco_enter)
2532                 ret = smu->ppt_funcs->baco_enter(smu);
2533
2534         mutex_unlock(&smu->mutex);
2535
2536         if (ret)
2537                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2538
2539         return ret;
2540 }
2541
2542 int smu_baco_exit(struct smu_context *smu)
2543 {
2544         int ret = 0;
2545
2546         if (!smu->pm_enabled)
2547                 return -EOPNOTSUPP;
2548
2549         mutex_lock(&smu->mutex);
2550
2551         if (smu->ppt_funcs->baco_exit)
2552                 ret = smu->ppt_funcs->baco_exit(smu);
2553
2554         mutex_unlock(&smu->mutex);
2555
2556         if (ret)
2557                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2558
2559         return ret;
2560 }
2561
2562 bool smu_mode1_reset_is_support(struct smu_context *smu)
2563 {
2564         bool ret = false;
2565
2566         if (!smu->pm_enabled)
2567                 return false;
2568
2569         mutex_lock(&smu->mutex);
2570
2571         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2572                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2573
2574         mutex_unlock(&smu->mutex);
2575
2576         return ret;
2577 }
2578
2579 int smu_mode1_reset(struct smu_context *smu)
2580 {
2581         int ret = 0;
2582
2583         if (!smu->pm_enabled)
2584                 return -EOPNOTSUPP;
2585
2586         mutex_lock(&smu->mutex);
2587
2588         if (smu->ppt_funcs->mode1_reset)
2589                 ret = smu->ppt_funcs->mode1_reset(smu);
2590
2591         mutex_unlock(&smu->mutex);
2592
2593         return ret;
2594 }
2595
2596 int smu_mode2_reset(struct smu_context *smu)
2597 {
2598         int ret = 0;
2599
2600         if (!smu->pm_enabled)
2601                 return -EOPNOTSUPP;
2602
2603         mutex_lock(&smu->mutex);
2604
2605         if (smu->ppt_funcs->mode2_reset)
2606                 ret = smu->ppt_funcs->mode2_reset(smu);
2607
2608         mutex_unlock(&smu->mutex);
2609
2610         if (ret)
2611                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2612
2613         return ret;
2614 }
2615
2616 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2617                                          struct pp_smu_nv_clock_table *max_clocks)
2618 {
2619         int ret = 0;
2620
2621         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2622                 return -EOPNOTSUPP;
2623
2624         mutex_lock(&smu->mutex);
2625
2626         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2627                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2628
2629         mutex_unlock(&smu->mutex);
2630
2631         return ret;
2632 }
2633
2634 int smu_get_uclk_dpm_states(struct smu_context *smu,
2635                             unsigned int *clock_values_in_khz,
2636                             unsigned int *num_states)
2637 {
2638         int ret = 0;
2639
2640         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2641                 return -EOPNOTSUPP;
2642
2643         mutex_lock(&smu->mutex);
2644
2645         if (smu->ppt_funcs->get_uclk_dpm_states)
2646                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2647
2648         mutex_unlock(&smu->mutex);
2649
2650         return ret;
2651 }
2652
2653 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2654 {
2655         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2656
2657         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2658                 return -EOPNOTSUPP;
2659
2660         mutex_lock(&smu->mutex);
2661
2662         if (smu->ppt_funcs->get_current_power_state)
2663                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2664
2665         mutex_unlock(&smu->mutex);
2666
2667         return pm_state;
2668 }
2669
2670 int smu_get_dpm_clock_table(struct smu_context *smu,
2671                             struct dpm_clocks *clock_table)
2672 {
2673         int ret = 0;
2674
2675         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2676                 return -EOPNOTSUPP;
2677
2678         mutex_lock(&smu->mutex);
2679
2680         if (smu->ppt_funcs->get_dpm_clock_table)
2681                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2682
2683         mutex_unlock(&smu->mutex);
2684
2685         return ret;
2686 }
2687
2688 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2689                                 void **table)
2690 {
2691         ssize_t size;
2692
2693         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2694                 return -EOPNOTSUPP;
2695
2696         if (!smu->ppt_funcs->get_gpu_metrics)
2697                 return -EOPNOTSUPP;
2698
2699         mutex_lock(&smu->mutex);
2700
2701         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2702
2703         mutex_unlock(&smu->mutex);
2704
2705         return size;
2706 }
2707
2708 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2709 {
2710         int ret = 0;
2711
2712         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2713                 return -EOPNOTSUPP;
2714
2715         mutex_lock(&smu->mutex);
2716
2717         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2718                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2719
2720         mutex_unlock(&smu->mutex);
2721
2722         return ret;
2723 }