2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define SWSMU_CODE_LAYER_L1
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
39 * DO NOT use these for err/warn/info/debug messages.
40 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
41 * They are more MGPU friendly.
48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
52 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
55 mutex_lock(&smu->mutex);
57 size = smu_get_pp_feature_mask(smu, buf);
59 mutex_unlock(&smu->mutex);
64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
68 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
71 mutex_lock(&smu->mutex);
73 ret = smu_set_pp_feature_mask(smu, new_mask);
75 mutex_unlock(&smu->mutex);
80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
83 struct smu_context *smu = &adev->smu;
85 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
86 *value = smu_get_gfx_off_status(smu);
93 int smu_set_soft_freq_range(struct smu_context *smu,
94 enum smu_clk_type clk_type,
100 mutex_lock(&smu->mutex);
102 if (smu->ppt_funcs->set_soft_freq_limited_range)
103 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
108 mutex_unlock(&smu->mutex);
113 int smu_get_dpm_freq_range(struct smu_context *smu,
114 enum smu_clk_type clk_type,
123 mutex_lock(&smu->mutex);
125 if (smu->ppt_funcs->get_dpm_ultimate_freq)
126 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
131 mutex_unlock(&smu->mutex);
136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
139 struct smu_power_context *smu_power = &smu->smu_power;
140 struct smu_power_gate *power_gate = &smu_power->power_gate;
143 if (!smu->ppt_funcs->dpm_set_vcn_enable)
146 if (atomic_read(&power_gate->vcn_gated) ^ enable)
149 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
151 atomic_set(&power_gate->vcn_gated, !enable);
156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
159 struct smu_power_context *smu_power = &smu->smu_power;
160 struct smu_power_gate *power_gate = &smu_power->power_gate;
163 mutex_lock(&power_gate->vcn_gate_lock);
165 ret = smu_dpm_set_vcn_enable_locked(smu, enable);
167 mutex_unlock(&power_gate->vcn_gate_lock);
172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
175 struct smu_power_context *smu_power = &smu->smu_power;
176 struct smu_power_gate *power_gate = &smu_power->power_gate;
179 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
182 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
185 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
187 atomic_set(&power_gate->jpeg_gated, !enable);
192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
195 struct smu_power_context *smu_power = &smu->smu_power;
196 struct smu_power_gate *power_gate = &smu_power->power_gate;
199 mutex_lock(&power_gate->jpeg_gate_lock);
201 ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
203 mutex_unlock(&power_gate->jpeg_gate_lock);
209 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
211 * @smu: smu_context pointer
212 * @block_type: the IP block to power gate/ungate
213 * @gate: to power gate if true, ungate otherwise
215 * This API uses no smu->mutex lock protection due to:
216 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
217 * This is guarded to be race condition free by the caller.
218 * 2. Or get called on user setting request of power_dpm_force_performance_level.
219 * Under this case, the smu->mutex lock protection is already enforced on
220 * the parent API smu_force_performance_level of the call path.
222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
227 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
230 switch (block_type) {
232 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
233 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
235 case AMD_IP_BLOCK_TYPE_UVD:
236 case AMD_IP_BLOCK_TYPE_VCN:
237 ret = smu_dpm_set_vcn_enable(smu, !gate);
239 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
240 gate ? "gate" : "ungate");
242 case AMD_IP_BLOCK_TYPE_GFX:
243 ret = smu_gfx_off_control(smu, gate);
245 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
246 gate ? "enable" : "disable");
248 case AMD_IP_BLOCK_TYPE_SDMA:
249 ret = smu_powergate_sdma(smu, gate);
251 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
252 gate ? "gate" : "ungate");
254 case AMD_IP_BLOCK_TYPE_JPEG:
255 ret = smu_dpm_set_jpeg_enable(smu, !gate);
257 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
258 gate ? "gate" : "ungate");
261 dev_err(smu->adev->dev, "Unsupported block type!\n");
268 int smu_get_power_num_states(struct smu_context *smu,
269 struct pp_states_info *state_info)
274 /* not support power state */
275 memset(state_info, 0, sizeof(struct pp_states_info));
276 state_info->nums = 1;
277 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
282 bool is_support_sw_smu(struct amdgpu_device *adev)
284 if (adev->asic_type >= CHIP_ARCTURUS)
290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
292 struct smu_table_context *smu_table = &smu->smu_table;
293 uint32_t powerplay_table_size;
295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
298 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
301 mutex_lock(&smu->mutex);
303 if (smu_table->hardcode_pptable)
304 *table = smu_table->hardcode_pptable;
306 *table = smu_table->power_play_table;
308 powerplay_table_size = smu_table->power_play_table_size;
310 mutex_unlock(&smu->mutex);
312 return powerplay_table_size;
315 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
317 struct smu_table_context *smu_table = &smu->smu_table;
318 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
324 if (header->usStructureSize != size) {
325 dev_err(smu->adev->dev, "pp table size not matched !\n");
329 mutex_lock(&smu->mutex);
330 if (!smu_table->hardcode_pptable)
331 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
332 if (!smu_table->hardcode_pptable) {
337 memcpy(smu_table->hardcode_pptable, buf, size);
338 smu_table->power_play_table = smu_table->hardcode_pptable;
339 smu_table->power_play_table_size = size;
342 * Special hw_fini action(for Navi1x, the DPMs disablement will be
343 * skipped) may be needed for custom pptable uploading.
345 smu->uploading_custom_pp_table = true;
347 ret = smu_reset(smu);
349 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
351 smu->uploading_custom_pp_table = false;
354 mutex_unlock(&smu->mutex);
358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
360 struct smu_feature *feature = &smu->smu_feature;
362 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
364 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
366 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
371 bitmap_or(feature->allowed, feature->allowed,
372 (unsigned long *)allowed_feature_mask,
373 feature->feature_num);
378 static int smu_set_funcs(struct amdgpu_device *adev)
380 struct smu_context *smu = &adev->smu;
382 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
383 smu->od_enabled = true;
385 switch (adev->asic_type) {
389 navi10_set_ppt_funcs(smu);
392 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
393 arcturus_set_ppt_funcs(smu);
394 /* OD is not supported on Arcturus */
395 smu->od_enabled =false;
397 case CHIP_SIENNA_CICHLID:
398 case CHIP_NAVY_FLOUNDER:
399 sienna_cichlid_set_ppt_funcs(smu);
402 renoir_set_ppt_funcs(smu);
411 static int smu_early_init(void *handle)
413 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
414 struct smu_context *smu = &adev->smu;
417 smu->pm_enabled = !!amdgpu_dpm;
419 mutex_init(&smu->mutex);
420 mutex_init(&smu->smu_baco.mutex);
421 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
422 smu->smu_baco.platform_support = false;
424 return smu_set_funcs(adev);
427 static int smu_set_default_dpm_table(struct smu_context *smu)
429 struct smu_power_context *smu_power = &smu->smu_power;
430 struct smu_power_gate *power_gate = &smu_power->power_gate;
431 int vcn_gate, jpeg_gate;
434 if (!smu->ppt_funcs->set_default_dpm_table)
437 mutex_lock(&power_gate->vcn_gate_lock);
438 mutex_lock(&power_gate->jpeg_gate_lock);
440 vcn_gate = atomic_read(&power_gate->vcn_gated);
441 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
443 ret = smu_dpm_set_vcn_enable_locked(smu, true);
447 ret = smu_dpm_set_jpeg_enable_locked(smu, true);
451 ret = smu->ppt_funcs->set_default_dpm_table(smu);
453 dev_err(smu->adev->dev,
454 "Failed to setup default dpm clock tables!\n");
456 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
458 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
460 mutex_unlock(&power_gate->jpeg_gate_lock);
461 mutex_unlock(&power_gate->vcn_gate_lock);
466 static int smu_late_init(void *handle)
468 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
469 struct smu_context *smu = &adev->smu;
472 if (!smu->pm_enabled)
475 ret = smu_post_init(smu);
477 dev_err(adev->dev, "Failed to post smu init!\n");
481 ret = smu_set_default_od_settings(smu);
483 dev_err(adev->dev, "Failed to setup default OD settings!\n");
487 ret = smu_populate_umd_state_clk(smu);
489 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
493 ret = smu_get_asic_power_limits(smu);
495 dev_err(adev->dev, "Failed to get asic power limits!\n");
499 smu_get_unique_id(smu);
501 smu_get_fan_parameters(smu);
503 smu_handle_task(&adev->smu,
504 smu->smu_dpm.dpm_level,
505 AMD_PP_TASK_COMPLETE_INIT,
511 static int smu_init_fb_allocations(struct smu_context *smu)
513 struct amdgpu_device *adev = smu->adev;
514 struct smu_table_context *smu_table = &smu->smu_table;
515 struct smu_table *tables = smu_table->tables;
516 struct smu_table *driver_table = &(smu_table->driver_table);
517 uint32_t max_table_size = 0;
520 /* VRAM allocation for tool table */
521 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
522 ret = amdgpu_bo_create_kernel(adev,
523 tables[SMU_TABLE_PMSTATUSLOG].size,
524 tables[SMU_TABLE_PMSTATUSLOG].align,
525 tables[SMU_TABLE_PMSTATUSLOG].domain,
526 &tables[SMU_TABLE_PMSTATUSLOG].bo,
527 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
528 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
530 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
535 /* VRAM allocation for driver table */
536 for (i = 0; i < SMU_TABLE_COUNT; i++) {
537 if (tables[i].size == 0)
540 if (i == SMU_TABLE_PMSTATUSLOG)
543 if (max_table_size < tables[i].size)
544 max_table_size = tables[i].size;
547 driver_table->size = max_table_size;
548 driver_table->align = PAGE_SIZE;
549 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
551 ret = amdgpu_bo_create_kernel(adev,
554 driver_table->domain,
556 &driver_table->mc_address,
557 &driver_table->cpu_addr);
559 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
560 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
561 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
562 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
563 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
569 static int smu_fini_fb_allocations(struct smu_context *smu)
571 struct smu_table_context *smu_table = &smu->smu_table;
572 struct smu_table *tables = smu_table->tables;
573 struct smu_table *driver_table = &(smu_table->driver_table);
575 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
576 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
577 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
578 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
580 amdgpu_bo_free_kernel(&driver_table->bo,
581 &driver_table->mc_address,
582 &driver_table->cpu_addr);
588 * smu_alloc_memory_pool - allocate memory pool in the system memory
590 * @smu: amdgpu_device pointer
592 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
593 * and DramLogSetDramAddr can notify it changed.
595 * Returns 0 on success, error on failure.
597 static int smu_alloc_memory_pool(struct smu_context *smu)
599 struct amdgpu_device *adev = smu->adev;
600 struct smu_table_context *smu_table = &smu->smu_table;
601 struct smu_table *memory_pool = &smu_table->memory_pool;
602 uint64_t pool_size = smu->pool_size;
605 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
608 memory_pool->size = pool_size;
609 memory_pool->align = PAGE_SIZE;
610 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
613 case SMU_MEMORY_POOL_SIZE_256_MB:
614 case SMU_MEMORY_POOL_SIZE_512_MB:
615 case SMU_MEMORY_POOL_SIZE_1_GB:
616 case SMU_MEMORY_POOL_SIZE_2_GB:
617 ret = amdgpu_bo_create_kernel(adev,
622 &memory_pool->mc_address,
623 &memory_pool->cpu_addr);
625 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
634 static int smu_free_memory_pool(struct smu_context *smu)
636 struct smu_table_context *smu_table = &smu->smu_table;
637 struct smu_table *memory_pool = &smu_table->memory_pool;
639 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
642 amdgpu_bo_free_kernel(&memory_pool->bo,
643 &memory_pool->mc_address,
644 &memory_pool->cpu_addr);
646 memset(memory_pool, 0, sizeof(struct smu_table));
651 static int smu_alloc_dummy_read_table(struct smu_context *smu)
653 struct smu_table_context *smu_table = &smu->smu_table;
654 struct smu_table *dummy_read_1_table =
655 &smu_table->dummy_read_1_table;
656 struct amdgpu_device *adev = smu->adev;
659 dummy_read_1_table->size = 0x40000;
660 dummy_read_1_table->align = PAGE_SIZE;
661 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
663 ret = amdgpu_bo_create_kernel(adev,
664 dummy_read_1_table->size,
665 dummy_read_1_table->align,
666 dummy_read_1_table->domain,
667 &dummy_read_1_table->bo,
668 &dummy_read_1_table->mc_address,
669 &dummy_read_1_table->cpu_addr);
671 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
676 static void smu_free_dummy_read_table(struct smu_context *smu)
678 struct smu_table_context *smu_table = &smu->smu_table;
679 struct smu_table *dummy_read_1_table =
680 &smu_table->dummy_read_1_table;
683 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
684 &dummy_read_1_table->mc_address,
685 &dummy_read_1_table->cpu_addr);
687 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
690 static int smu_smc_table_sw_init(struct smu_context *smu)
695 * Create smu_table structure, and init smc tables such as
696 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
698 ret = smu_init_smc_tables(smu);
700 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
705 * Create smu_power_context structure, and allocate smu_dpm_context and
706 * context size to fill the smu_power_context data.
708 ret = smu_init_power(smu);
710 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
715 * allocate vram bos to store smc table contents.
717 ret = smu_init_fb_allocations(smu);
721 ret = smu_alloc_memory_pool(smu);
725 ret = smu_alloc_dummy_read_table(smu);
729 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
736 static int smu_smc_table_sw_fini(struct smu_context *smu)
740 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
742 smu_free_dummy_read_table(smu);
744 ret = smu_free_memory_pool(smu);
748 ret = smu_fini_fb_allocations(smu);
752 ret = smu_fini_power(smu);
754 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
758 ret = smu_fini_smc_tables(smu);
760 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
767 static void smu_throttling_logging_work_fn(struct work_struct *work)
769 struct smu_context *smu = container_of(work, struct smu_context,
770 throttling_logging_work);
772 smu_log_thermal_throttling(smu);
775 static void smu_interrupt_work_fn(struct work_struct *work)
777 struct smu_context *smu = container_of(work, struct smu_context,
780 mutex_lock(&smu->mutex);
782 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
783 smu->ppt_funcs->interrupt_work(smu);
785 mutex_unlock(&smu->mutex);
788 static int smu_sw_init(void *handle)
790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791 struct smu_context *smu = &adev->smu;
794 smu->pool_size = adev->pm.smu_prv_buffer_size;
795 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
796 mutex_init(&smu->smu_feature.mutex);
797 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
798 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
799 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
801 mutex_init(&smu->sensor_lock);
802 mutex_init(&smu->metrics_lock);
803 mutex_init(&smu->message_lock);
805 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
806 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
807 atomic64_set(&smu->throttle_int_counter, 0);
808 smu->watermarks_bitmap = 0;
809 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
810 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
812 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
813 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
814 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
815 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
817 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
818 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
819 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
820 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
821 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
822 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
823 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
824 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
826 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
827 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
828 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
829 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
830 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
831 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
832 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
833 smu->display_config = &adev->pm.pm_display_cfg;
835 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
836 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
838 if (!amdgpu_sriov_vf(adev)) {
839 ret = smu_init_microcode(smu);
841 dev_err(adev->dev, "Failed to load smu firmware!\n");
846 ret = smu_smc_table_sw_init(smu);
848 dev_err(adev->dev, "Failed to sw init smc table!\n");
852 ret = smu_register_irq_handler(smu);
854 dev_err(adev->dev, "Failed to register smc irq handler!\n");
861 static int smu_sw_fini(void *handle)
863 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
864 struct smu_context *smu = &adev->smu;
867 ret = smu_smc_table_sw_fini(smu);
869 dev_err(adev->dev, "Failed to sw fini smc table!\n");
873 smu_fini_microcode(smu);
878 static int smu_get_thermal_temperature_range(struct smu_context *smu)
880 struct amdgpu_device *adev = smu->adev;
881 struct smu_temperature_range *range =
885 if (!smu->ppt_funcs->get_thermal_temperature_range)
888 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
892 adev->pm.dpm.thermal.min_temp = range->min;
893 adev->pm.dpm.thermal.max_temp = range->max;
894 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
895 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
896 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
897 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
898 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
899 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
900 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
905 static int smu_smc_hw_setup(struct smu_context *smu)
907 struct amdgpu_device *adev = smu->adev;
908 uint32_t pcie_gen = 0, pcie_width = 0;
911 if (adev->in_suspend && smu_is_dpm_running(smu)) {
912 dev_info(adev->dev, "dpm has been enabled\n");
916 ret = smu_init_display_count(smu, 0);
918 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
922 ret = smu_set_driver_table_location(smu);
924 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
929 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
931 ret = smu_set_tool_table_location(smu);
933 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
938 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
941 ret = smu_notify_memory_pool_location(smu);
943 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
947 /* smu_dump_pptable(smu); */
949 * Copy pptable bo in the vram to smc with SMU MSGs such as
950 * SetDriverDramAddr and TransferTableDram2Smu.
952 ret = smu_write_pptable(smu);
954 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
958 /* issue Run*Btc msg */
959 ret = smu_run_btc(smu);
963 ret = smu_feature_set_allowed_mask(smu);
965 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
969 ret = smu_system_features_control(smu, true);
971 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
975 if (!smu_is_dpm_running(smu))
976 dev_info(adev->dev, "dpm has been disabled\n");
978 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
980 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
982 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
984 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
987 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
988 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
989 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
991 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
993 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
995 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
997 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
999 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1001 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1003 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1005 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1009 ret = smu_get_thermal_temperature_range(smu);
1011 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1015 ret = smu_enable_thermal_alert(smu);
1017 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1022 * Set initialized values (get from vbios) to dpm tables context such as
1023 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1026 ret = smu_set_default_dpm_table(smu);
1028 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1032 ret = smu_notify_display_change(smu);
1037 * Set min deep sleep dce fclk with bootup value from vbios via
1038 * SetMinDeepSleepDcefclk MSG.
1040 ret = smu_set_min_dcef_deep_sleep(smu,
1041 smu->smu_table.boot_values.dcefclk / 100);
1048 static int smu_start_smc_engine(struct smu_context *smu)
1050 struct amdgpu_device *adev = smu->adev;
1053 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1054 if (adev->asic_type < CHIP_NAVI10) {
1055 if (smu->ppt_funcs->load_microcode) {
1056 ret = smu->ppt_funcs->load_microcode(smu);
1063 if (smu->ppt_funcs->check_fw_status) {
1064 ret = smu->ppt_funcs->check_fw_status(smu);
1066 dev_err(adev->dev, "SMC is not ready\n");
1072 * Send msg GetDriverIfVersion to check if the return value is equal
1073 * with DRIVER_IF_VERSION of smc header.
1075 ret = smu_check_fw_version(smu);
1082 static int smu_hw_init(void *handle)
1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086 struct smu_context *smu = &adev->smu;
1088 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1089 smu->pm_enabled = false;
1093 ret = smu_start_smc_engine(smu);
1095 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1100 smu_powergate_sdma(&adev->smu, false);
1101 smu_dpm_set_vcn_enable(smu, true);
1102 smu_dpm_set_jpeg_enable(smu, true);
1103 smu_set_gfx_cgpg(&adev->smu, true);
1106 if (!smu->pm_enabled)
1109 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1110 ret = smu_get_vbios_bootup_values(smu);
1112 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1116 ret = smu_setup_pptable(smu);
1118 dev_err(adev->dev, "Failed to setup pptable!\n");
1122 ret = smu_get_driver_allowed_feature_mask(smu);
1126 ret = smu_smc_hw_setup(smu);
1128 dev_err(adev->dev, "Failed to setup smc hw!\n");
1133 * Move maximum sustainable clock retrieving here considering
1134 * 1. It is not needed on resume(from S3).
1135 * 2. DAL settings come between .hw_init and .late_init of SMU.
1136 * And DAL needs to know the maximum sustainable clocks. Thus
1137 * it cannot be put in .late_init().
1139 ret = smu_init_max_sustainable_clocks(smu);
1141 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1145 adev->pm.dpm_enabled = true;
1147 dev_info(adev->dev, "SMU is initialized successfully!\n");
1152 static int smu_disable_dpms(struct smu_context *smu)
1154 struct amdgpu_device *adev = smu->adev;
1156 bool use_baco = !smu->is_apu &&
1157 ((amdgpu_in_reset(adev) &&
1158 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1159 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1162 * For custom pptable uploading, skip the DPM features
1163 * disable process on Navi1x ASICs.
1164 * - As the gfx related features are under control of
1165 * RLC on those ASICs. RLC reinitialization will be
1166 * needed to reenable them. That will cost much more
1169 * - SMU firmware can handle the DPM reenablement
1172 if (smu->uploading_custom_pp_table &&
1173 (adev->asic_type >= CHIP_NAVI10) &&
1174 (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1178 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1179 * on BACO in. Driver involvement is unnecessary.
1181 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1186 * For gpu reset, runpm and hibernation through BACO,
1187 * BACO feature has to be kept enabled.
1189 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1190 ret = smu_disable_all_features_with_exception(smu,
1191 SMU_FEATURE_BACO_BIT);
1193 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1195 ret = smu_system_features_control(smu, false);
1197 dev_err(adev->dev, "Failed to disable smu features.\n");
1200 if (adev->asic_type >= CHIP_NAVI10 &&
1201 adev->gfx.rlc.funcs->stop)
1202 adev->gfx.rlc.funcs->stop(adev);
1207 static int smu_smc_hw_cleanup(struct smu_context *smu)
1209 struct amdgpu_device *adev = smu->adev;
1212 cancel_work_sync(&smu->throttling_logging_work);
1213 cancel_work_sync(&smu->interrupt_work);
1215 ret = smu_disable_thermal_alert(smu);
1217 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1221 ret = smu_disable_dpms(smu);
1223 dev_err(adev->dev, "Fail to disable dpm features!\n");
1230 static int smu_hw_fini(void *handle)
1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233 struct smu_context *smu = &adev->smu;
1235 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1239 smu_powergate_sdma(&adev->smu, true);
1240 smu_dpm_set_vcn_enable(smu, false);
1241 smu_dpm_set_jpeg_enable(smu, false);
1244 if (!smu->pm_enabled)
1247 adev->pm.dpm_enabled = false;
1249 return smu_smc_hw_cleanup(smu);
1252 int smu_reset(struct smu_context *smu)
1254 struct amdgpu_device *adev = smu->adev;
1257 amdgpu_gfx_off_ctrl(smu->adev, false);
1259 ret = smu_hw_fini(adev);
1263 ret = smu_hw_init(adev);
1267 ret = smu_late_init(adev);
1271 amdgpu_gfx_off_ctrl(smu->adev, true);
1276 static int smu_suspend(void *handle)
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279 struct smu_context *smu = &adev->smu;
1282 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1285 if (!smu->pm_enabled)
1288 adev->pm.dpm_enabled = false;
1290 ret = smu_smc_hw_cleanup(smu);
1294 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1297 smu_set_gfx_cgpg(&adev->smu, false);
1302 static int smu_resume(void *handle)
1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306 struct smu_context *smu = &adev->smu;
1308 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1311 if (!smu->pm_enabled)
1314 dev_info(adev->dev, "SMU is resuming...\n");
1316 ret = smu_start_smc_engine(smu);
1318 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1322 ret = smu_smc_hw_setup(smu);
1324 dev_err(adev->dev, "Failed to setup smc hw!\n");
1329 smu_set_gfx_cgpg(&adev->smu, true);
1331 smu->disable_uclk_switch = 0;
1333 adev->pm.dpm_enabled = true;
1335 dev_info(adev->dev, "SMU is resumed successfully!\n");
1340 int smu_display_configuration_change(struct smu_context *smu,
1341 const struct amd_pp_display_configuration *display_config)
1344 int num_of_active_display = 0;
1346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1349 if (!display_config)
1352 mutex_lock(&smu->mutex);
1354 smu_set_min_dcef_deep_sleep(smu,
1355 display_config->min_dcef_deep_sleep_set_clk / 100);
1357 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1358 if (display_config->displays[index].controller_id != 0)
1359 num_of_active_display++;
1362 smu_set_active_display_count(smu, num_of_active_display);
1364 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1365 display_config->cpu_cc6_disable,
1366 display_config->cpu_pstate_disable,
1367 display_config->nb_pstate_switch_disable);
1369 mutex_unlock(&smu->mutex);
1374 static int smu_get_clock_info(struct smu_context *smu,
1375 struct smu_clock_info *clk_info,
1376 enum smu_perf_level_designation designation)
1379 struct smu_performance_level level = {0};
1384 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1388 clk_info->min_mem_clk = level.memory_clock;
1389 clk_info->min_eng_clk = level.core_clock;
1390 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1392 ret = smu_get_perf_level(smu, designation, &level);
1396 clk_info->min_mem_clk = level.memory_clock;
1397 clk_info->min_eng_clk = level.core_clock;
1398 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1403 int smu_get_current_clocks(struct smu_context *smu,
1404 struct amd_pp_clock_info *clocks)
1406 struct amd_pp_simple_clock_info simple_clocks = {0};
1407 struct smu_clock_info hw_clocks;
1410 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1413 mutex_lock(&smu->mutex);
1415 smu_get_dal_power_level(smu, &simple_clocks);
1417 if (smu->support_power_containment)
1418 ret = smu_get_clock_info(smu, &hw_clocks,
1419 PERF_LEVEL_POWER_CONTAINMENT);
1421 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1424 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1428 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1429 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1430 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1431 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1432 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1433 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1434 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1435 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1437 if (simple_clocks.level == 0)
1438 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1440 clocks->max_clocks_state = simple_clocks.level;
1442 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1443 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1444 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1448 mutex_unlock(&smu->mutex);
1452 static int smu_set_clockgating_state(void *handle,
1453 enum amd_clockgating_state state)
1458 static int smu_set_powergating_state(void *handle,
1459 enum amd_powergating_state state)
1464 static int smu_enable_umd_pstate(void *handle,
1465 enum amd_dpm_forced_level *level)
1467 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1468 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1469 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1470 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1472 struct smu_context *smu = (struct smu_context*)(handle);
1473 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1475 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1478 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1479 /* enter umd pstate, save current level, disable gfx cg*/
1480 if (*level & profile_mode_mask) {
1481 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1482 smu_dpm_ctx->enable_umd_pstate = true;
1483 amdgpu_device_ip_set_powergating_state(smu->adev,
1484 AMD_IP_BLOCK_TYPE_GFX,
1485 AMD_PG_STATE_UNGATE);
1486 amdgpu_device_ip_set_clockgating_state(smu->adev,
1487 AMD_IP_BLOCK_TYPE_GFX,
1488 AMD_CG_STATE_UNGATE);
1489 smu_gfx_ulv_control(smu, false);
1490 smu_deep_sleep_control(smu, false);
1493 /* exit umd pstate, restore level, enable gfx cg*/
1494 if (!(*level & profile_mode_mask)) {
1495 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1496 *level = smu_dpm_ctx->saved_dpm_level;
1497 smu_dpm_ctx->enable_umd_pstate = false;
1498 smu_deep_sleep_control(smu, true);
1499 smu_gfx_ulv_control(smu, true);
1500 amdgpu_device_ip_set_clockgating_state(smu->adev,
1501 AMD_IP_BLOCK_TYPE_GFX,
1503 amdgpu_device_ip_set_powergating_state(smu->adev,
1504 AMD_IP_BLOCK_TYPE_GFX,
1512 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1513 enum amd_dpm_forced_level level,
1514 bool skip_display_settings)
1519 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1521 if (!skip_display_settings) {
1522 ret = smu_display_config_changed(smu);
1524 dev_err(smu->adev->dev, "Failed to change display config!");
1529 ret = smu_apply_clocks_adjust_rules(smu);
1531 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1535 if (!skip_display_settings) {
1536 ret = smu_notify_smc_display_config(smu);
1538 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1543 if (smu_dpm_ctx->dpm_level != level) {
1544 ret = smu_asic_set_performance_level(smu, level);
1546 dev_err(smu->adev->dev, "Failed to set performance level!");
1550 /* update the saved copy */
1551 smu_dpm_ctx->dpm_level = level;
1554 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1555 index = fls(smu->workload_mask);
1556 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1557 workload = smu->workload_setting[index];
1559 if (smu->power_profile_mode != workload)
1560 smu_set_power_profile_mode(smu, &workload, 0, false);
1566 int smu_handle_task(struct smu_context *smu,
1567 enum amd_dpm_forced_level level,
1568 enum amd_pp_task task_id,
1573 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1577 mutex_lock(&smu->mutex);
1580 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1581 ret = smu_pre_display_config_changed(smu);
1584 ret = smu_set_cpu_power_state(smu);
1587 ret = smu_adjust_power_state_dynamic(smu, level, false);
1589 case AMD_PP_TASK_COMPLETE_INIT:
1590 case AMD_PP_TASK_READJUST_POWER_STATE:
1591 ret = smu_adjust_power_state_dynamic(smu, level, true);
1599 mutex_unlock(&smu->mutex);
1604 int smu_switch_power_profile(struct smu_context *smu,
1605 enum PP_SMC_POWER_PROFILE type,
1608 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1615 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1618 mutex_lock(&smu->mutex);
1621 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1622 index = fls(smu->workload_mask);
1623 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1624 workload = smu->workload_setting[index];
1626 smu->workload_mask |= (1 << smu->workload_prority[type]);
1627 index = fls(smu->workload_mask);
1628 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1629 workload = smu->workload_setting[index];
1632 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1633 smu_set_power_profile_mode(smu, &workload, 0, false);
1635 mutex_unlock(&smu->mutex);
1640 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1642 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1643 enum amd_dpm_forced_level level;
1645 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1648 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1651 mutex_lock(&(smu->mutex));
1652 level = smu_dpm_ctx->dpm_level;
1653 mutex_unlock(&(smu->mutex));
1658 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1660 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1663 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1666 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1669 mutex_lock(&smu->mutex);
1671 ret = smu_enable_umd_pstate(smu, &level);
1673 mutex_unlock(&smu->mutex);
1677 ret = smu_handle_task(smu, level,
1678 AMD_PP_TASK_READJUST_POWER_STATE,
1681 mutex_unlock(&smu->mutex);
1686 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1690 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1693 mutex_lock(&smu->mutex);
1694 ret = smu_init_display_count(smu, count);
1695 mutex_unlock(&smu->mutex);
1700 int smu_force_clk_levels(struct smu_context *smu,
1701 enum smu_clk_type clk_type,
1704 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1710 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1711 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1715 mutex_lock(&smu->mutex);
1717 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1718 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1720 mutex_unlock(&smu->mutex);
1726 * On system suspending or resetting, the dpm_enabled
1727 * flag will be cleared. So that those SMU services which
1728 * are not supported will be gated.
1729 * However, the mp1 state setting should still be granted
1730 * even if the dpm_enabled cleared.
1732 int smu_set_mp1_state(struct smu_context *smu,
1733 enum pp_mp1_state mp1_state)
1738 if (!smu->pm_enabled)
1741 mutex_lock(&smu->mutex);
1743 switch (mp1_state) {
1744 case PP_MP1_STATE_SHUTDOWN:
1745 msg = SMU_MSG_PrepareMp1ForShutdown;
1747 case PP_MP1_STATE_UNLOAD:
1748 msg = SMU_MSG_PrepareMp1ForUnload;
1750 case PP_MP1_STATE_RESET:
1751 msg = SMU_MSG_PrepareMp1ForReset;
1753 case PP_MP1_STATE_NONE:
1755 mutex_unlock(&smu->mutex);
1759 ret = smu_send_smc_msg(smu, msg, NULL);
1760 /* some asics may not support those messages */
1764 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1766 mutex_unlock(&smu->mutex);
1771 int smu_set_df_cstate(struct smu_context *smu,
1772 enum pp_df_cstate state)
1776 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1779 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1782 mutex_lock(&smu->mutex);
1784 ret = smu->ppt_funcs->set_df_cstate(smu, state);
1786 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1788 mutex_unlock(&smu->mutex);
1793 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1800 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1803 mutex_lock(&smu->mutex);
1805 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1807 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1809 mutex_unlock(&smu->mutex);
1814 int smu_write_watermarks_table(struct smu_context *smu)
1818 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1821 mutex_lock(&smu->mutex);
1823 ret = smu_set_watermarks_table(smu, NULL);
1825 mutex_unlock(&smu->mutex);
1830 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1831 struct pp_smu_wm_range_sets *clock_ranges)
1835 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1838 if (smu->disable_watermark)
1841 mutex_lock(&smu->mutex);
1843 ret = smu_set_watermarks_table(smu, clock_ranges);
1845 mutex_unlock(&smu->mutex);
1850 int smu_set_ac_dc(struct smu_context *smu)
1854 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1857 /* controlled by firmware */
1858 if (smu->dc_controlled_by_gpio)
1861 mutex_lock(&smu->mutex);
1862 ret = smu_set_power_source(smu,
1863 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1864 SMU_POWER_SOURCE_DC);
1866 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1867 smu->adev->pm.ac_power ? "AC" : "DC");
1868 mutex_unlock(&smu->mutex);
1873 const struct amd_ip_funcs smu_ip_funcs = {
1875 .early_init = smu_early_init,
1876 .late_init = smu_late_init,
1877 .sw_init = smu_sw_init,
1878 .sw_fini = smu_sw_fini,
1879 .hw_init = smu_hw_init,
1880 .hw_fini = smu_hw_fini,
1881 .suspend = smu_suspend,
1882 .resume = smu_resume,
1884 .check_soft_reset = NULL,
1885 .wait_for_idle = NULL,
1887 .set_clockgating_state = smu_set_clockgating_state,
1888 .set_powergating_state = smu_set_powergating_state,
1889 .enable_umd_pstate = smu_enable_umd_pstate,
1892 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1894 .type = AMD_IP_BLOCK_TYPE_SMC,
1898 .funcs = &smu_ip_funcs,
1901 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1903 .type = AMD_IP_BLOCK_TYPE_SMC,
1907 .funcs = &smu_ip_funcs,
1910 int smu_load_microcode(struct smu_context *smu)
1914 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1917 mutex_lock(&smu->mutex);
1919 if (smu->ppt_funcs->load_microcode)
1920 ret = smu->ppt_funcs->load_microcode(smu);
1922 mutex_unlock(&smu->mutex);
1927 int smu_check_fw_status(struct smu_context *smu)
1931 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1934 mutex_lock(&smu->mutex);
1936 if (smu->ppt_funcs->check_fw_status)
1937 ret = smu->ppt_funcs->check_fw_status(smu);
1939 mutex_unlock(&smu->mutex);
1944 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1948 mutex_lock(&smu->mutex);
1950 if (smu->ppt_funcs->set_gfx_cgpg)
1951 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1953 mutex_unlock(&smu->mutex);
1958 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1962 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1965 mutex_lock(&smu->mutex);
1967 if (smu->ppt_funcs->set_fan_speed_rpm)
1968 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1970 mutex_unlock(&smu->mutex);
1975 int smu_get_power_limit(struct smu_context *smu,
1979 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1982 mutex_lock(&smu->mutex);
1984 *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1986 mutex_unlock(&smu->mutex);
1991 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1995 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1998 mutex_lock(&smu->mutex);
2000 if (limit > smu->max_power_limit) {
2001 dev_err(smu->adev->dev,
2002 "New power limit (%d) is over the max allowed %d\n",
2003 limit, smu->max_power_limit);
2008 limit = smu->current_power_limit;
2010 if (smu->ppt_funcs->set_power_limit)
2011 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2014 mutex_unlock(&smu->mutex);
2019 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2026 mutex_lock(&smu->mutex);
2028 if (smu->ppt_funcs->print_clk_levels)
2029 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2031 mutex_unlock(&smu->mutex);
2036 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2040 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2043 mutex_lock(&smu->mutex);
2045 if (smu->ppt_funcs->get_od_percentage)
2046 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2048 mutex_unlock(&smu->mutex);
2053 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2057 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2060 mutex_lock(&smu->mutex);
2062 if (smu->ppt_funcs->set_od_percentage)
2063 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2065 mutex_unlock(&smu->mutex);
2070 int smu_od_edit_dpm_table(struct smu_context *smu,
2071 enum PP_OD_DPM_TABLE_COMMAND type,
2072 long *input, uint32_t size)
2076 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2079 mutex_lock(&smu->mutex);
2081 if (smu->ppt_funcs->od_edit_dpm_table) {
2082 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2083 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2084 ret = smu_handle_task(smu,
2085 smu->smu_dpm.dpm_level,
2086 AMD_PP_TASK_READJUST_POWER_STATE,
2090 mutex_unlock(&smu->mutex);
2095 int smu_read_sensor(struct smu_context *smu,
2096 enum amd_pp_sensors sensor,
2097 void *data, uint32_t *size)
2099 struct smu_umd_pstate_table *pstate_table =
2103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2109 mutex_lock(&smu->mutex);
2111 if (smu->ppt_funcs->read_sensor)
2112 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2116 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2117 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2120 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2121 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2124 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2125 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2128 case AMDGPU_PP_SENSOR_UVD_POWER:
2129 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2132 case AMDGPU_PP_SENSOR_VCE_POWER:
2133 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2136 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2137 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2140 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2141 *(uint32_t *)data = 0;
2151 mutex_unlock(&smu->mutex);
2156 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2160 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2163 mutex_lock(&smu->mutex);
2165 if (smu->ppt_funcs->get_power_profile_mode)
2166 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2168 mutex_unlock(&smu->mutex);
2173 int smu_set_power_profile_mode(struct smu_context *smu,
2175 uint32_t param_size,
2180 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2184 mutex_lock(&smu->mutex);
2186 if (smu->ppt_funcs->set_power_profile_mode)
2187 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2190 mutex_unlock(&smu->mutex);
2196 int smu_get_fan_control_mode(struct smu_context *smu)
2200 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2203 mutex_lock(&smu->mutex);
2205 if (smu->ppt_funcs->get_fan_control_mode)
2206 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2208 mutex_unlock(&smu->mutex);
2213 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2217 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2220 mutex_lock(&smu->mutex);
2222 if (smu->ppt_funcs->set_fan_control_mode)
2223 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2225 mutex_unlock(&smu->mutex);
2230 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2234 uint32_t current_rpm;
2236 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2239 mutex_lock(&smu->mutex);
2241 if (smu->ppt_funcs->get_fan_speed_rpm) {
2242 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, ¤t_rpm);
2244 percent = current_rpm * 100 / smu->fan_max_rpm;
2245 *speed = percent > 100 ? 100 : percent;
2249 mutex_unlock(&smu->mutex);
2255 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2263 mutex_lock(&smu->mutex);
2265 if (smu->ppt_funcs->set_fan_speed_rpm) {
2268 rpm = speed * smu->fan_max_rpm / 100;
2269 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
2272 mutex_unlock(&smu->mutex);
2277 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2281 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2284 mutex_lock(&smu->mutex);
2286 if (smu->ppt_funcs->get_fan_speed_rpm)
2287 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2289 mutex_unlock(&smu->mutex);
2294 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2298 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2301 mutex_lock(&smu->mutex);
2303 ret = smu_set_min_dcef_deep_sleep(smu, clk);
2305 mutex_unlock(&smu->mutex);
2310 int smu_get_clock_by_type(struct smu_context *smu,
2311 enum amd_pp_clock_type type,
2312 struct amd_pp_clocks *clocks)
2316 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2319 mutex_lock(&smu->mutex);
2321 if (smu->ppt_funcs->get_clock_by_type)
2322 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2324 mutex_unlock(&smu->mutex);
2329 int smu_get_max_high_clocks(struct smu_context *smu,
2330 struct amd_pp_simple_clock_info *clocks)
2334 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2337 mutex_lock(&smu->mutex);
2339 if (smu->ppt_funcs->get_max_high_clocks)
2340 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2342 mutex_unlock(&smu->mutex);
2347 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2348 enum smu_clk_type clk_type,
2349 struct pp_clock_levels_with_latency *clocks)
2353 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2356 mutex_lock(&smu->mutex);
2358 if (smu->ppt_funcs->get_clock_by_type_with_latency)
2359 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2361 mutex_unlock(&smu->mutex);
2366 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2367 enum amd_pp_clock_type type,
2368 struct pp_clock_levels_with_voltage *clocks)
2372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2375 mutex_lock(&smu->mutex);
2377 if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2378 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2380 mutex_unlock(&smu->mutex);
2386 int smu_display_clock_voltage_request(struct smu_context *smu,
2387 struct pp_display_clock_request *clock_req)
2391 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2394 mutex_lock(&smu->mutex);
2396 if (smu->ppt_funcs->display_clock_voltage_request)
2397 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2399 mutex_unlock(&smu->mutex);
2405 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2412 mutex_lock(&smu->mutex);
2414 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2415 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2417 mutex_unlock(&smu->mutex);
2422 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2426 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2429 mutex_lock(&smu->mutex);
2431 if (smu->ppt_funcs->notify_smu_enable_pwe)
2432 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2434 mutex_unlock(&smu->mutex);
2439 int smu_set_xgmi_pstate(struct smu_context *smu,
2444 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2447 mutex_lock(&smu->mutex);
2449 if (smu->ppt_funcs->set_xgmi_pstate)
2450 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2452 mutex_unlock(&smu->mutex);
2455 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2460 int smu_set_azalia_d3_pme(struct smu_context *smu)
2464 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2467 mutex_lock(&smu->mutex);
2469 if (smu->ppt_funcs->set_azalia_d3_pme)
2470 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2472 mutex_unlock(&smu->mutex);
2478 * On system suspending or resetting, the dpm_enabled
2479 * flag will be cleared. So that those SMU services which
2480 * are not supported will be gated.
2482 * However, the baco/mode1 reset should still be granted
2483 * as they are still supported and necessary.
2485 bool smu_baco_is_support(struct smu_context *smu)
2489 if (!smu->pm_enabled)
2492 mutex_lock(&smu->mutex);
2494 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2495 ret = smu->ppt_funcs->baco_is_support(smu);
2497 mutex_unlock(&smu->mutex);
2502 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2504 if (smu->ppt_funcs->baco_get_state)
2507 mutex_lock(&smu->mutex);
2508 *state = smu->ppt_funcs->baco_get_state(smu);
2509 mutex_unlock(&smu->mutex);
2514 int smu_baco_enter(struct smu_context *smu)
2518 if (!smu->pm_enabled)
2521 mutex_lock(&smu->mutex);
2523 if (smu->ppt_funcs->baco_enter)
2524 ret = smu->ppt_funcs->baco_enter(smu);
2526 mutex_unlock(&smu->mutex);
2529 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2534 int smu_baco_exit(struct smu_context *smu)
2538 if (!smu->pm_enabled)
2541 mutex_lock(&smu->mutex);
2543 if (smu->ppt_funcs->baco_exit)
2544 ret = smu->ppt_funcs->baco_exit(smu);
2546 mutex_unlock(&smu->mutex);
2549 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2554 bool smu_mode1_reset_is_support(struct smu_context *smu)
2558 if (!smu->pm_enabled)
2561 mutex_lock(&smu->mutex);
2563 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2564 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2566 mutex_unlock(&smu->mutex);
2571 int smu_mode1_reset(struct smu_context *smu)
2575 if (!smu->pm_enabled)
2578 mutex_lock(&smu->mutex);
2580 if (smu->ppt_funcs->mode1_reset)
2581 ret = smu->ppt_funcs->mode1_reset(smu);
2583 mutex_unlock(&smu->mutex);
2588 int smu_mode2_reset(struct smu_context *smu)
2592 if (!smu->pm_enabled)
2595 mutex_lock(&smu->mutex);
2597 if (smu->ppt_funcs->mode2_reset)
2598 ret = smu->ppt_funcs->mode2_reset(smu);
2600 mutex_unlock(&smu->mutex);
2603 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2608 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2609 struct pp_smu_nv_clock_table *max_clocks)
2613 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2616 mutex_lock(&smu->mutex);
2618 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2619 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2621 mutex_unlock(&smu->mutex);
2626 int smu_get_uclk_dpm_states(struct smu_context *smu,
2627 unsigned int *clock_values_in_khz,
2628 unsigned int *num_states)
2632 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2635 mutex_lock(&smu->mutex);
2637 if (smu->ppt_funcs->get_uclk_dpm_states)
2638 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2640 mutex_unlock(&smu->mutex);
2645 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2647 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2649 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2652 mutex_lock(&smu->mutex);
2654 if (smu->ppt_funcs->get_current_power_state)
2655 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2657 mutex_unlock(&smu->mutex);
2662 int smu_get_dpm_clock_table(struct smu_context *smu,
2663 struct dpm_clocks *clock_table)
2667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2670 mutex_lock(&smu->mutex);
2672 if (smu->ppt_funcs->get_dpm_clock_table)
2673 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2675 mutex_unlock(&smu->mutex);
2680 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2685 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2688 if (!smu->ppt_funcs->get_gpu_metrics)
2691 mutex_lock(&smu->mutex);
2693 size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2695 mutex_unlock(&smu->mutex);
2700 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2704 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2707 mutex_lock(&smu->mutex);
2709 if (smu->ppt_funcs->enable_mgpu_fan_boost)
2710 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2712 mutex_unlock(&smu->mutex);